AKM AK4620A 24 bit 192khz audio codec with ipga Datasheet

ASAHI KASEI
[AK4620A]
AK4620A
24-Bit 192kHz Audio CODEC with IPGA
GENERAL DESCRIPTION
The AK4620A is a high performance 24-bit CODEC that supports up to 192kHz record and playback. The
on-board analog-to-digital converter has a high dynamic range due to AKM’s Enhanced Dual-Bit
architecture. The DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise
and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology. The AK4620A has
an input Programmable Gain Amplifier and is ideal for Pro Audio sound cards, Digital Audio Workstations,
DVD-R, hard disk, CD-R recording/playback systems, and musical instrument recording.
FEATURES
• 24-bit 2-channel ADC
- Selectable Single-ended or Differential Input
- High Performance Linear Phase Digital Anti-Alias Filter
Passband: 0 ~ 20.25kHz (@fs=44.1kHz)
Ripple: ± 0.005dB
Stopband Attenuation: 100dB
- S/(N+D): 92dB (single-ended)
100dB (differential)
- S/N: 110dB (single-ended)
113dB (differential)
- Digital High-pass Filter for Offset Cancellation
- Input PGA: 0dB to +18dB, 0.5dB/step (for single-ended input)
- Input Digital Attenuator: 0dB to – 63dB, 0.5dB/step
- Overflow Flag
2
- Audio Interface Format: MSB justified or I S
• 24-bit 2-channel DAC
- 24-bit 8 times Oversampling Linear Phase Digital Filter
Ripple: ±0.005dB
Stopband Attenuation: 75dB
- Switched-cap Low Pass Filter
- Differential Outputs
- S/(N+D): 100dB
- S/N: 115dB
- De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling
- Output Digital Attenuator: Linear 255 steps
- Soft Mute
- Zero Detection Function
2
- Audio interface format: MSB justified, LSB justified, I S, or DSD
• High Jitter Tolerance
• Sampling Rate: Up to 216kHz
• µP Interface: 3-wire Serial Interface
• Master Clock
- 128fs/192fs/256fs/384fs/512fs/768fs/1024fs
• Power Supply: 5V ± 5%(Analog), 3V~3.6V with 5V tolerant I/O(Digital)
• Small 30-pin VSOP package
• Ta: -10 to 70 °C
MS0368-E-00
2004/12
-1-
ASAHI KASEI
[AK4620A]
„ Block Diagram
ADMODE
VD
VT
DGND
AINL+
AINL-/NC
ADC
DATT
HPF
PDN
AINR+
AINR-/NC
OVF
OVFL/DZFL
Audio I/F
Controller
OVFR/DZFR
LRCK
BICK
SDTO
SDTI
MCLK
DFS0
AOUTL+
AOUTLAOUTR+
AOUTR-
DATT
SMUTE
DAC
Control Register I/F
VCOM
VREF
VA
AGND
DEM0
CSN/
DIF
CCLK/
CKS1
P/S
CDTI/
CKS0
Figure 1. Block Diagram
• Compatibility with AK4528 / AK4524
Function
Max fs
ADC Inputs
Input analog PGA
Input digital ATT
ADC S/(N+D)
ADC DR, S/N
ADC Digital Filter SA
ADC Overflow detection
DAC S/(N+D)
DAC DR, S/N
Output digital Attenuator
DAC DSD mode
DAC Zero-data detection
X’tal Oscillating Circuit
Master Mode
Parallel Mode
AK4524
96kHz
Single-ended
0dB ~ +18dB
0.5dB/step
Mute, -72dB ~ 0dB
Pseudo-log step
90dB
100dB
75dB
94dB
110dB
Mute, -72dB ~ 0dB
Pseudo-log step
X
X
-
AK4528
108kHz
Differential
Mute, -72dB ~ 0dB
Pseudo-log step
94dB
108dB
75dB
94dB
110dB
Mute, -72dB ~ 0dB
Pseudo-log step
X
MS0368-E-00
AK4620A
216kHz
Single-ended
Differential
0 ~ +18dB
0.5dB/step
Mute,-63.5dB ~ 0dB Mute,-63.5dB ~ 0dB
0.5dB/step
0.5dB/step
92dB
100dB
110dB
113dB
100dB
X
100dB
115dB
Mute, -48dB ~ 0dB Mute, -48dB ~ 0dB
Linear 256 steps
Linear 256 steps
X
X
X
X: Available, -: NOT available
2004/12
-2-
ASAHI KASEI
[AK4620A]
„ Ordering Guide
AK4620AVF
AKD4620A
-10∼+70°C
Evaluation Board
30pin VSOP (0.65mm pitch)
„ Pin Layout
VCOM
1
30
AOUTR+
AINR+
2
29
AOUTR-
AINR-/NC
3
28
AOUTL+
AINL+
4
27
AOUTL-
AINL-/NC
5
26
DGND
VREF
6
25
VD
AGND
7
24
VT
VA
8
23
ADMODE
P/S
9
22
DEM0
MCLK
10
21
PDN
LRCK/DSDR
11
20
DFS0
BICK/DCLK
12
19
CSN/DIF
SDTO
13
18
CCLK/CKS1
SDTI/DSDL
14
17
CDTI/CKS0
OVFR/DZFR
15
16
OVFL/DZFL
Top
View
MS0368-E-00
2004/12
-3-
ASAHI KASEI
[AK4620A]
PIN/FUNCTION
No.
Pin Name
I/O
Function
Common Voltage Output Pin, VA/2
Bias voltage of ADC inputs and DAC outputs.
Rch Positive Input Pin
Rch Negative Input Pin (when ADMODE pin=“H”)
1
VCOM
O
2
AINR+
I
I
3
AINR-
4
AINL+
5
AINL-
6
VREF
I
7
8
AGND
VA
-
9
P/S
I
10
MCLK
LRCK
DSDR
BICK
I
I
I
I
No Connect pin (when ADMODE pin=“L”)
No internal bonding. This pin should be open.
Lch Positive Input Pin
Lch Negative Input Pin (when ADMODE pin=“H”)
No Connect pin (when ADMODE pin=“L”)
No internal bonding. This pin should be open.
Voltage Reference Input Pin, VA
Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered
VA.
Analog Ground Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Parallel/Serial Mode Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
Master Clock Input Pin
Input/Output Channel Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSD Rch Data Input Pin (when D/P bit=“1” in Serial Mode)
Audio Serial Data Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DCLK
SDTO
SDTI
I
O
I
DSD Clock Pin (when D/P bit=“1” in Serial Mode)
Audio Serial Data Output Pin
Audio Serial Data Input Pin (in Parallel mode or when D/P bit=“0” in Serial Mode)
DSDL
OVFR
DZFR
OVFL
DZFL
I
O
O
O
O
DSD Lch Data Input Pin (when D/P bit=“1” in Serial Mode)
Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
CDTI
CKS0
CCLK
CKS1
I
I
I
I
Control Data Input Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
Control Data Clock Pin (in Serial Mode)
Master Clock Select Pin (in Parallel Mode)
CSN
I
Chip Select Pin in Serial Mode (in Serial Mode)
DIF
I
20
DFS0
I
21
PDN
I
22
DEM0
I
23
ADMODE
I
11
12
13
14
15
16
17
18
19
I
I
I
I
Digital Audio Interface Select Pin (in Parallel Mode)
“L”: 24bit MSB justified, “H”: I2S compatible
Double Speed Sampling Mode Pin
Power-Down Mode Pin
“L”: Power down reset and initialize the control register, “H”: Power up
De-emphasis Control Pin
Analog Input Mode Select Pin
“L”: Single-ended Input & IPGA Enable
“H”: Differential Input & IPGA Bypass
MS0368-E-00
2004/12
-4-
ASAHI KASEI
[AK4620A]
PIN/FUNCTION (Continued)
24
25
26
27
28
29
30
VT
VD
DGND
AOUTLAOUTL+
AOUTRAOUTR+
O
O
O
O
Input Buffer Tolerant Pin, 3.0 ∼ 5.25V
Digital Power Supply Pin, 3.0 ∼ 3.6V
Digital Ground Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Note. Do not allow digital input pins (P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0,
CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and ADMODE pins) to float.
„ Handling of Unused Pin
The unused I/O pin should be processed appropriately as below.
Classification
Pin Name
AINL+, AINL-/NC, AINR+, AINR+NC
Analog Input
AINL+, AINL-/NC
AINR+, AINR-/NC
Analog Output
Digital Input
Digital Output
AOUTL+, AOUTL-, AOUTR+,
AOUTRDEM0
OVFL/DZFL, OVFR/DZFR
Setting
These pins should be open when ADMODE pin = “L”.
AINL+ pin is connected to AINL-/NC pin when
ADMODE pin = “H”.
AINR+ pin is connected to AINR-/NC pin when
ADMODE pin = “H”.
These pins should be open.
This pin should be connected to DVSS.
These pins should be open.
MS0368-E-00
2004/12
-5-
ASAHI KASEI
[AK4620A]
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND=0V;Note 1)
Parameter
Symbol
min
Power Supplies:
Analog
VA
-0.3
Digital
VD
-0.3
Input Tolerant
VT
-0.3
|AGND – DGND|
(Note 2)
∆GND
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage
(Note 3)
VINA
-0.3
Digital Input Voltage
(Note 4)
VIND
-0.3
Ambient Temperature (powered applied)
Ta
-10
Storage Temperature
Tstg
-65
max
6.0
6.0
6.0
0.3
±10
VA+0.3
VT+0.3
70
150
Units
V
V
V
V
mA
V
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AGND and DGND must be connected to the same analog ground plane.
Note 3. AINL+, AINL-/NC, AINR+ and AINR-/NC pins
Note 4. P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN,
DEM0 and ADMODE pins.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND=0V;Note 1)
Parameter
Symbol
min
typ
Power Supplies
Analog
VA
4.75
5.0
(Note 5) Digital
VD
3.0
3.3
Input Tolerant
VT
VD
5.0
Voltage Reference
VREF
3.0
-
max
5.25
3.6
5.25
VA
Units
V
V
V
V
Note 5. The power up sequence among VA, VD and VT is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0368-E-00
2004/12
-6-
ASAHI KASEI
[AK4620A]
ANALOG CHARACTERISTICS (ADC: Single-ended Input)
(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit
Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz;
unless otherwise specified)
Parameter
min
typ
max
Units
Input PGA Characteristics:
Input Voltage
(Note 6)
2.77
3.07
3.37
Vpp
Input Resistance
(Note 7)
0.7
5.1
kΩ
Step Size
0.2
0.5
0.8
dB
Gain Control Range
0
18
dB
ADC Analog Input Characteristics: IPGA=0dB
Resolution
24
Bits
S/(N+D)
fs=44.1kHz
-1dBFS
82
92
dB
BW=20kHz
-60dBFS
47
dB
fs=96kHz
-1dBFS
92
dB
BW=40kHz
-60dBFS
44
dB
fs=192kHz
-1dBFS
92
dB
BW=40kHz
-60dBFS
44
dB
Dynamic Range
(-60dBFS with A-weighted)
110
dB
S/N
(A-weighted)
101
110
dB
Interchannel Isolation
90
105
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
150
ppm/°C
Power Supply Rejection
(Note 8)
50
dB
ANALOG CHARACTERISTICS (ADC: Differential Input)
(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit
Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz;
unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics:
Resolution
24
Bits
Input Voltage
(Note 9)
±2.62
±2.82
±3.02
Vpp
Input Resistance
fs=44.1kHz
8
14
kΩ
fs=48kHz
13
kΩ
fs=96kHz
13
kΩ
fs=192kHz
13
kΩ
S/(N+D)
fs=44.1kHz
-1dBFS
90
100
dB
BW=20kHz
-60dBFS
50
dB
fs=96kHz
-1dBFS
100
dB
BW=40kHz
-60dBFS
46
dB
fs=192kHz
-1dBFS
100
dB
BW=40kHz
-60dBFS
46
dB
Dynamic Range
(-60dBFS with A-weighted)
113
dB
S/N
(A-weighted)
103
113
dB
Interchannel Isolation
90
120
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
20
ppm/°C
Power Supply Rejection
(Note 8)
50
dB
MS0368-E-00
2004/12
-7-
ASAHI KASEI
[AK4620A]
Note 6. Full scale (0dB) of the input voltage at PGA=0dB.
This voltage is proportional to VREF. Vin(typ) = 3.07Vpp x VREF/5.
Note 7. These values become smaller when a gain of IPGA is large.
IPGA=0dB; typ. 5.1kΩ, IPGA=+18dB; typ. 1.18kΩ
Note 8. PSR is applied to VA, VD, VT with 1kHz, 50mVpp. VREF pin is held a constant voltage.
Note 9. Full scale (0dB) of the input voltage at 0dB. This voltage is proportional to VREF.
Vin (typ) = ±2.82Vpp x VREF/5.
ANALOG CHARACTERISTICS (DAC)
(Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit
Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz;
unless otherwise specified)
DAC Analog Output Characteristics:
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
0dBFS
S/(N+D)
90
100
dB
fs=44.1kHz
BW=20kHz
52
dB
−60dBFS
0dBFS
97
dB
fs=96kHz
BW=40kHz
49
dB
−60dBFS
0dBFS
97
dB
fs=192kHz
BW=40kHz
49
dB
−60dBFS
Dynamic Range (−60dBFS with A-weighted) (Note 10, Note 11)
115
dB
S/N
(A-weighted) (Note 11, Note 12)
107
115
dB
Interchannel Isolation (1kHz)
90
110
dB
DC Accuracy
Interchannel Gain Mismatch
0.15
0.3
dB
Gain Drift
(Note 13)
20
ppm/°C
Output Voltage
(Note 14)
±2.6
±2.8
±3.0
Vpp
Load Capacitance
25
pF
Load Resistance
(Note 15)
3
kΩ
Note 10. 100dB at 16bit data and 114dB at 20bit data.
Note 11. By Figure 19. External LPF Circuit Example 2 for PCM.
Note 12. S/N does not depend on input bit length.
Note 13. The voltage on VREF is held +5V externally.
Note 14. Full-scale voltage(0dB). Output voltage scales with the voltage of VREF.
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 5.6Vpp x VREF/5.
Note 15. For AC-load.
Parameter
Power Supplies
min
Power Supply Current
Normal Operation (PDN pin = “H”)
VA: ADC Single-ended Mode
ADC Differential Mode
VD+VT (fs=44.1kHz)
(fs=96kHz)
(fs=192kHz)
Power-down mode (PDN pin = “L”)
(Note 16)
VA
VD+VT
Note 16. All digital input pins are held VT or DGND.
MS0368-E-00
typ
max
Units
60
51
10
18
22
90
77
33
mA
mA
mA
mA
mA
10
10
100
100
µA
µA
2004/12
-8-
ASAHI KASEI
[AK4620A]
ADC FILTER CHARACTERISTICS (fs=44.1kHz)
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Normal Speed Mode)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 17) −0.005dB
PB
0
−0.02dB
20.25
−0.06dB
20.4
−6.0dB
22.05
Stopband
(Note 17)
SB
24.3
Passband Ripple
PR
Stopband Attenuation
SA
100
Group Delay
(Note 18)
GD
43.2
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 17) −3dB
FR
0.9
−0.1dB
6.0
ADC FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Double Speed Mode)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 17) −0.005dB
PB
0
−0.02dB
44.08
−0.06dB
44.5
−6.0dB
48.0
Stopband
(Note 17)
SB
53.0
Passband Ripple
PR
Stopband Attenuation
SA
100
Group Delay
(Note 18)
GD
43.1
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 17) −3dB
FR
2.0
−0.1dB
13.0
FILTER CHARACTERISTICS (fs=192kHz)
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; Quad Speed Mode)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 17) −0.005dB
PB
0
−0.02dB
88.18
89.0
−0.06dB
96.0
−6.0dB
Stopband
(Note 17)
SB
106.0
Passband Ripple
PR
Stopband Attenuation
SA
100
Group Delay
(Note 18)
GD
38.2
Group Delay Distortion
∆GD
0
ADC Digital Filter (HPF):
Frequency Response (Note 17) −3dB
FR
4.0
−0.1dB
26.0
max
Units
19.8
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.005
Hz
Hz
max
Units
43.0
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.005
Hz
Hz
max
Units
86.0
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.005
Hz
Hz
Note 17. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
Note 18. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC.
MS0368-E-00
2004/12
-9-
ASAHI KASEI
[AK4620A]
DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF;
SLOW = “0”)
Parameter
Symbol
min
typ
max
Units
PB
0
24.1
22.05
20.0
-
Digital Filter
Passband
±0.01dB
-6.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 19)
(Note 19)
(Note 20)
SB
PR
SA
GD
75
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
± 0.2
-
dB
± 0.005
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF; SLOW
= “0”)
Parameter
Symbol
min
(Note 19)
PB
(Note 19)
SB
PR
SA
GD
0
52.5
typ
max
Units
48.0
43.5
-
Digital Filter
Passband
±0.01dB
-6.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 20)
75
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
± 0.3
-
dB
± 0.005
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 192kHz; Quad Speed Mode; DEM = OFF; SLOW
= “0”)
Parameter
symbol
min
typ
max
Units
Digital Filter
Passband
±0.01dB
(Note 19)
PB
0
87.0
kHz
-6.0dB
96.0
kHz
Stopband
(Note 19)
SB
105
kHz
Passband Ripple
PR
± 0.005
dB
Stopband Attenuation
SA
75
dB
Group Delay
(Note 20)
GD
28
1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
+0/-1
dB
Note 19. The passband and stopband frequencies scale with fs.
For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs.
Note 20. Delay time caused by digital filtering. This time is from setting the 16/20/24bit data of both channels to input
register to the output of analog signal.
MS0368-E-00
2004/12
- 10 -
ASAHI KASEI
[AK4620A]
DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 44.1kHz; Normal Speed Mode; DEM = OFF;
SLOW = “1”)
Parameter
Symbol
min
typ
max
Units
PB
0
39.2
18.2
8.1
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 21)
(Note 21)
(Note 20)
SB
PR
SA
GD
72
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-5
-
dB
± 0.005
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz
DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 96kHz; Double Speed Mode; DEM = OFF; SLOW
= “1”)
Parameter
Symbol
min
(Note 21)
PB
(Note 21)
SB
PR
SA
GD
0
85.3
typ
max
Units
39.6
17.7
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 20)
72
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-4
-
dB
± 0.005
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz
DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta = 25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; fs = 192kHz; Quad Speed Mode; DEM = OFF; SLOW
= “1”)
Parameter
Symbol
min
typ
max
Units
PB
0
171
79.1
35.5
-
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 21)
(Note 21)
(Note 20)
SB
PR
SA
GD
72
-
28
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0/-5
-
dB
± 0.005
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz
Note 21. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
MS0368-E-00
2004/12
- 11 -
ASAHI KASEI
[AK4620A]
DIGITAL CHARACTERISTICS
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%VD
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout=-100µA)
VOH
VD-0.5
Low-Level Output Voltage (Iout=100µA)
VOL
Input Leakage Current
Iin
-
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=4.75 ∼ 5.25V; VD=3.0 ∼ 3.6V, VT=3.0 ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
8.192
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK Frequency
(Note 22)
Normal Speed Mode (DFS0=“0”, DFS1=”0”)
Double Speed Mode (DFS0=“1”, DFS1=”0”)
Quad Speed Mode (DFS0=“0”, DFS1=”1”)
Duty Cycle
typ
-
typ
max
VT
30%VD
0.5
±10
Units
V
V
V
V
µA
max
Units
55.296
MHz
ns
ns
54
108
216
55
kHz
kHz
kHz
%
fsn
fsd
fsq
32
54
108
45
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 23)
BICK “↑” to LRCK Edge
(Note 23)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
33
33
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DSD Audio Interface Timing
DCLK Period
DCLK Pulse Width Low
Pulse Width High
DCLK Edge to DSDL/R
tDCK
tDCKL
tDCKH
tDDD
1/64fs
160
160
-20
ns
ns
ns
ns
(Note 24)
20
20
20
Note 22. When the normal/double/quad speed modes are switched, the AK4620A should be reset by PDN pin or RSTN
bit.
Note 23. BICK rising edge must not occur at the same time as LRCK edge.
Note 24. DSD data transmitting device must meet this time.
MS0368-E-00
2004/12
- 12 -
ASAHI KASEI
[AK4620A]
Parameter
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
RSTAD “↑” to SDTO valid
(Note 25)
(Note 26)
Symbol
min
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
tPD
tPDV
150
typ
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
516
ns
1/fs
Note 25. The AK4620A can be reset by bringing PDN pin “L”.
Note 26. These cycles are the number of LRCK rising from RSTAD bit.
MS0368-E-00
2004/12
- 13 -
ASAHI KASEI
[AK4620A]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BICK
tLRS
tBSD
50%VD
SDTO
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (PCM mode)
MS0368-E-00
2004/12
- 14 -
ASAHI KASEI
[AK4620A]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
MS0368-E-00
2004/12
- 15 -
ASAHI KASEI
[AK4620A]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power Down & Reset Timing
MS0368-E-00
2004/12
- 16 -
ASAHI KASEI
[AK4620A]
OPERATION OVERVIEW
„ D/A Conversion Mode
In serial mode, the AK4620A can digitize either PCM data or DSD data. The P/D bit controls PCM/DSD mode. When
DSD mode, DSD data input occurs on DCLK, DSDL and DSDR pins. The ADC and IPGA are in power down mode. In
PCM mode, PCM data input occurs on BICK, SDTI and LRCK pins. When PCM/DSD mode changes (D/P bit), the
AK4620A should be reset by setting RSTAD and RSTDA bits to “0” or by grounding the PDN pin. It takes from 2/fs to
3/fs to change the mode. In parallel mode, AK4620A can only process PCM data.
D/P bit
DAC mode
ADC mode
0
PCM
PCM
1
DSD
Power down
Table 1. DSD/PCM Mode Control
„ System Clock Input
1. PCM Mode
AK4620A requires MCLK, BICK and LRCK external clocks. MCLK should be synchronized with LRCK but the phase
is not critical. External clocks (MCLK, BICK and LRCK) should always be present whenever the AK4620A is in normal
operation mode (PDN pin = “H” and either the ADC and DAC is in normal operation mode). If these clocks are not
provided, the AK4620A may draw excess current due to dynamic refresh of internal logic. If the external clocks are not
present, the AK4620A should be in the power-down mode (PDN pin = “L” or power down both the ADC and DAC by the
register). After exiting reset (PDN pin = “L” Æ “H”) at power-up etc., the AK4620A is in power-down mode until MCLK
and LRCK are provided.
As the AK4620A includes the phase detect circuit for LRCK, the AK4620A is reset automatically when the
synchronization is out of phase by changing the clock frequencies.
1-1. Serial mode (P/S pin= “L”)
As shown in Table 2, Table 3 and Table 4, select the MCLK frequency by setting CMODE, CKS0-1 and DFS0-1
(DFS0 bit and DFS0 pin are internally ORd). These registers are changed when RSTAD bit = RSTDA bit = “0”.
DFS1 bit
0
0
1
1
OR of DFS0 bit /
DFS0 pin
Mode
Sampling Rate
0
Normal speed
32kHz-54kHz
1
Double speed
54kHz-108kHz
0
Quad speed
108kHz-216kHz
1
N/A
Table 2. Sampling speed in serial mode
MS0368-E-00
Default
2004/12
- 17 -
ASAHI KASEI
[AK4620A]
CMODE bit
CKS1 bit
0
0
0
0
1
1
0
0
1
1
0
0
MCLK
Normal Speed
(DFS1-0 = “00”)
CKS0 bit
MCLK
Double Speed
(DFS1-0 = “01”)
MCLK
Quad Speed
(DFS1-0 = “10”)
0
256fs
N/A
N/A
1
512fs
256fs
128fs
0
1024fs
512fs
256fs
1
N/A
Auto Setting Mode (*)
N/A
0
384fs
N/A
N/A
1
768fs
384fs
192fs
Table 3. Master clock frequency in serial mode (“*”: refer to Table 4)
Default
The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically.
MCLK/LRCK ratio
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 4. Auto Setting Mode in serial mode (DFS1-0 = “01”, CMODE bit = “1”, CKS1-0 bit = “11”)
1-2. Parallel mode (P/S pin= “H”)
As shown in Table 5, Table 6 and Table 7, select the MCLK frequency with the CKS0-1 and DFS0 pins. These
pins should be changed when the PDN pin = “L”.
DFS0 pin
L
H
CKS1 pin
Mode
Sampling Rate
Normal speed
32kHz-54kHz
Double speed
54kHz-108kHz
Table 5. Sampling speed in parallel mode
CKS0 pin
MCLK
Normal Speed
(DFS0 pin = “L”)
MCLK
Double Speed
(DFS0 pin = “H”)
L
L
256fs
N/A
L
H
512fs
256fs
H
L
384fs
Auto Setting Mode (*)
H
H
1024fs
512fs
Table 6. Master clock frequency in parallel mode (“*”; refer to Table 7.)
The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically.
MCLK/LRCK ratio
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 7. Auto Setting Mode in parallel mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”)
MS0368-E-00
2004/12
- 18 -
ASAHI KASEI
[AK4620A]
MCLK (Normal speed)
256fs
512fs
1024fs
384fs
768fs
fs=44.1kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
MCLK (Quad speed)
128fs
256fs
192fs
fs=176.4kHz
22.5792MHz
45.1584MHz
33.8688MHz
fs=48kHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
MCLK (Double speed)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz
N/A
22.5792MHz
45.1584MHz
N/A
33.8688MHz
fs=96kHz
N/A
24.576MHz
49.152MHz
N/A
36.864MHz
fs=192kHz
24.576MHz
49.152MHz
36.864MHz
Table 8. Master clock frequency example
2. DSD Mode
The external clocks, which are required to operate the AK4620A, are MCLK and DCLK. The master clock (MCLK)
should be synchronized with DSD clock (DCLK) but the phase is not critical. The frequency of MCLK is set by DCKS
bit.
All external clocks (MCLK, DCLK) must be present whenever the AK4620A is in the normal operation mode (PDN pin
= “H”). If these clocks are not provided, the AK4620A may draw excess current because the device utilizes dynamically
refreshed logic. The AK4620A should be reset by PDN pin = “L” after these clocks are provided. If the external clocks
are not present, the AK4620A should be in the power-down mode (PDN pin = “L”). After exiting reset (PDN pin = “↑”)
at power-up etc., the AK4620A is in the power-down mode until MCLK is provided.
„ Audio Serial Interface Format
1. PCM Mode
Five serial modes are supported and selected by the DIF2-0 bits in Serial Mode (two modes by DIF pin in Parallel Mode)
as shown in Table 9 and Table 10. In all modes the serial data has MSB first, 2’s complement format. The SDTO is
clocked out on the falling edge of BICK and the SDTI is latched on the rising edge. Mode2 can be used for 20 and 16
MSB justified formats by zeroing the unused LSBs.
Mode
DIF2
DIF1
DIF0
0
1
2
3
4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Mode
DIF pin
2
3
L
H
LRCK
BICK
24bit, MSB justified
16bit, LSB justified
24bit, MSB justified
20bit, LSB justified
24bit, MSB justified
24bit, MSB justified
24bit, I2S
24bit, I2S
24bit, MSB justified
24bit, LSB justified
Table 9. Audio data format (Serial Mode)
SDTO
SDTI
H/L
H/L
H/L
L/H
H/L
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
SDTO
BICK
SDTI
LRCK
24bit, MSB justified
24bit, MSB justified
H/L
24bit, I2S
24bit, I2S
L/H
Table 10. Audio data format (Parallel Mode)
MS0368-E-00
Default
≥ 48fs
≥ 48fs
2004/12
- 19 -
ASAHI KASEI
[AK4620A]
LRCK
0
1
2
3
17
18
19
20
30
31
0
1
2
3
17
18
19
20
31
0
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
7
Don’t Care
6
5
4
3
23 22 21
15 14 13 12 11
2
1
7
Don’t Care
0
6
5
4
3
23
15 14 13 12 11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
2
1
0
Rch Data
Figure 2. Mode 0 Timing
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
Don’t Care
0
19 18
23 22
8
7
1
12 11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 3. Mode 1 Timing
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
23
Rch Data
Figure 4. Mode 2 Timing
LRCK
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 3 Timing
MS0368-E-00
2004/12
- 20 -
ASAHI KASEI
[AK4620A]
LRCK
0
1
2
8
9
10
20
21
31
0
1
2
8
9
10
20
21
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15 14
Don’t Care
23:MSB, 0:LSB
23 22
0
12 11
23 22
1
0
16 15 14
Don’t Care
Lch Data
23 22
0
12 11
23
1
0
Rch Data
Figure 6. Mode 4 Timing
MS0368-E-00
2004/12
- 21 -
ASAHI KASEI
[AK4620A]
2. DSD Mode
In DSD mode, DIF0-2 is ignored. The frequency of DCLK is fixed at 64fs. The DCKB bit inverts the polarity of DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D3
D2
Figure 7. DSD Mode Timing
„ D/A conversion mode switching timing
RSTDA bit
≥4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 8. D/A Mode Switching Timing (PCM to DSD)
RSTDA bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 9. D/A Mode Switching Mode Timing (DSD to PCM)
Caution: In DSD mode, the signal level ranges from 25% to 75%. Peak levels of DSD signal above this range are not
recommended by the SACD format book (Scarlet Book).
MS0368-E-00
2004/12
- 22 -
ASAHI KASEI
[AK4620A]
„ Input Volume
The AK4620A includes two channel-independent analog volumes (IPGA), each with 32 levels in 0.5dB increments.
These are located in front of the ADC while digital volume controls (IATT) with 128 levels (including MUTE) are
located after the ADC. Control of both of these volume settings is handled by the same register address. When the MSB of
the register is “1”, the IPGA changes and when the MSB = “0” the IATT changes.
The IPGA is an analog volume control that improves the S/N ratio compared with digital volume controls (Table 11).
Level changes only occur during zero-crossings to minimize switching noise. Channel independent zero-crossing
detection is used. If there are no zero-crossings, then the level will change after a time-out. The time-out period scales
with fs. The periods of 256/fs, 512/fs, 1024/fs and 2048/fs are selected by ZTM1-0 bits in normal speed mode. If a new
value is written to the IPGA register before the IPGA changes at the zero crossing or time-out, the previous value
becomes invalid. The timer (channel independent) for time-out is reset and the timer restarts for the new IPGA value.
ZCEI bits in the control register enable zero-crossing detection.
The IATT is a log volume that is linear-interpolated internally. When changing the level, the transition between ATT
values has 29 levels and is done by soft changes, eliminating any switching noise.
Input Gain Setting
0dB
+6dB
fs=44.1kHz, A-weight
110dB
108dB
Table 11. IPGA+ADC S/N (typ.)
ZTM1
0
0
1
1
ZTM0
Normal speed Double speed
0
256/fs
512/fs
1
512/fs
1024/fs
0
1024/fs
2048/fs
1
2048/fs
4096/fs
Table 12. LRCK cycles for timeout period
+18dB
101dB
Quad speed
1024/fs
2048/fs
4096/fs
8192/fs
Default
„ Output Volume
The AK4620A includes channel independent digital output volumes (ATT) with 256 levels at linear steps including
MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to −48dB and mute. When
changing levels, transitions are executed via soft changes, eliminating any switching noise. The transition time of 1 level
and all 256 levels is shown in Table 13.
Transition Time
1 Level
255 to 0
Normal Speed Mode
4LRCK
1020LRCK
Double Speed Mode
8LRCK
2040LRCK
Quad Speed Mode
16LRCK
4080LRCK
Table 13. ATT Transition Time
Sampling Speed
MS0368-E-00
2004/12
- 23 -
ASAHI KASEI
[AK4620A]
„ Overflow Detection
The ADC has a channel independent overflow detection function. This function is enabled in the parallel control mode, or
when the ZOS bit = ZOE bit = “0”in serial control mode. OVFL/R pins go to “H” if each Lch/Rch analog input overflows
(exceeds -0.3dBFS). The output of each OVFL/R pin has same group delay as ADC against analog input. OVFL/R pin is
“L” for 516/fs (=10.8ms @fs=48kHz) after PDN pin = “↑”, and then overflow detection is enabled.
„ Zero detection
The DAC has a channel-independent zero detect function. The zero detect function is enabled when the ZOS bit = “1” and
the ZOE bit = “0”in serial control mode. When the input data at both channels is continuously zero for 8192 LRCK cycles,
the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately goes to “L” if the input data of each
channel is not zero after DZF “H”. If the RSTDA bit is “0”, the DZF pins of both channels go to “H”. DZF pins of both
channels go to “L” at 4~5/fs after the RSTDA bit becomes “1”. Zero detect function can be disabled by the ZOE bit. In
this case, the DZF pins of both channels are always “L”. The DZFB bit can invert the polarity of the DZF pin.
„ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz at
fs=44.1kHz. The digital high pass filter cutoff frequency scales with the sampling rate (fs). In parallel mode, the HPF is
always enabled. In serial mode, the HPF can control each channel by HPLN/HPRN bits.
„ De-emphasis Filter
The DAC includes a digital de-emphasis filter (tc=50/15µs) via an integrated IIR filter. This filter corresponds to three
frequencies (32kHz, 44.1kHz, 48kHz). This setting is done via control register (DEM1-0 bits). This filter is always OFF
in double and quad speed modes. The DEM0 pin and DEM0 bit are OR’d in serial control mode. In parallel control mode,
the DEM1 bit is fixed to “0” and only the DEM0 pin can be controlled (44.1kHz or OFF). When in DSD mode, DEM1-0
bits are ignored. The setting value is held even if PCM mode and DSD mode are switched.
No
DEM1
DEM0
Mode
0
0
0
44.1kHz
1
0
1
OFF
2
1
0
48kHz
3
1
1
32kHz
Table 14. De-emphasis control (Normal Speed Mode)
MS0368-E-00
Default
2004/12
- 24 -
ASAHI KASEI
[AK4620A]
„ ADC Single-ended/Differential Input Mode
The ADC has a selectable single-ended or differential input mode. This mode can be selected by ADMODE pin, AML bit
and AMR bit. (See Table 15 and Table 16) In differential input mode, the IPGA is powered-down and bypassed. IATT
can be controlled in differential mode.
ADMODE pin
Lch
Rch
L
Single-ended
Single-ended
H
Differential
Differential
Table 15. ADC Input Mode in parallel mode
ADMODE pin
L
H
AML bit
AMR bit
Lch
Rch
0
0
Single-ended
Single-ended
0
1
Single-ended
Differential
1
0
Differential
Single-ended
1
1
Differential
Differential
X
X
Differential
Differential
Table 16. ADC Input Mode in serial mode (X: Don’t care)
„ Soft Mute Operation
Soft mute operation is performed in the digital domain of the DAC input. When the SMUTE bit goes to “1”, the output
signal is attenuated by −∞ during ATT_DATA × ATT transition time (Table 12) from the current ATT level. When
SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during
ATT_DATA × ATT transition time. If soft mute is cancelled before attenuating to −∞ after starting the operation, the
attenuation is discontinued and returns to ATT level by the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
SM U T E bit
(1)
(1)
AT T _Level
(3)
Attenuation
-∞
GD
(2)
GD
(2)
AO U T
D ZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA × ATT transition time (Table 12). For example, this time is 1020LRCK cycles (1020/fs)
at ATT_DATA=255 in Normal Speed Mode.
(2) Analog output corresponding to digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zero for 8192 LRCK cycles, DZF pin of each channel goes
to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”.
Figure 10. Soft Mute and Zero Detection
MS0368-E-00
2004/12
- 25 -
ASAHI KASEI
[AK4620A]
„ Power Down & Reset
The ADC and DAC of AK4620A are placed in power-down mode by bringing the PDN pin = “L”. Each digital filter is
also reset at the same time. The internal register values are initialized by bringing PDN pin to “L”. This reset should
always be done after power-up. As both control registers of the ADC and the DAC go to the reset state (RSTAD bit =
RSTDA bit = “0”), each register should be cleared after performing the reset. In the case of the ADC, an analog
initialization cycle starts after exiting the power-down or reset state. The output data (SDTO) is available after 516 cycles
of LRCK clock. This initialization cycle does not affect the DAC operation. Power down mode can be also controlled by
the registers (PWAD bit, PWDA bit).
Pow er Supply
PDN pin
RSTAD(register)
RSTDA(register)
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
PD
IATT
Reset INITA
00H → XXH
00H
SDTO
“0”
PD
Reset
OATT
FFH
FFH (1)
AOUT
Hi-z
External clocks
INITA
Normal
00H 00H → XXH
Output
“0”
XXH
FI
Output
Normal
VCOM
*
PD
XXH
FI
DAC Internal State
External Mute
Example
Normal
PD
FFH → XXH
XXH
FADE
Output
*
Normal
XXH(2 )
Hi-z
*
XXH → YYH YYH
FADE
*
MCLK, LRCK, BICK
The clocks can be stopped.
• INITA:
Initializing period of ADC analog section (516/fs).
• PD:
Power down state. The contents of all registers are held.
• XXH, YYH: The current value in ATT registers.
• FI:
Fade in. After exiting power down and reset state, ATT value fades in.
• FADE:
After exiting power down and reset state, ATT value fades in/out.
(1) When RSTDA is “L” and OATT value is written to “XXH”, OATT value changes from FFH
to XXH according to fade operation.
(2) When PWDA is “L” and OATT value is written to “YYH”, OATT value changes from XXH
to YYH according to fade operation.
• AOUT: Some pop noise may occur at “*”.
Figure 11. Reset & Power down sequence in serial mode
MS0368-E-00
2004/12
- 26 -
ASAHI KASEI
[AK4620A]
In parallel mode, both ADC and DAC are powered up with releasing internal reset state when PDN pin is set to “H”.
When PDN pin is “L”, IATT is set to “00H (Mute)”. After exiting power down mode, IATTs fade in to “80H (0dB)”. At
that time, ADC s output “0” during first 516/fs cycles. DAC does not have the initialization cycle and the operation of
fade-in.
Power Supply
PDN pin
ADC Internal State
PD
INITA
IATT
00H
00HÆ80H
SDTO
DAC Internal State
AOUT
External Mute
Example
External clocks
“0”
PD
FI
Normal
PD
INITA
80H
00H
00HÆ80H
Output
Hi-Z
PD
Output
*
FI
“0”
Normal
80H
Output
Normal
Output
Hi-Z
*
Normal
*
MCLK, LRCK, BICK
MCLK, LRCK, BICK
The clocks can be stopped.
• INITA:
• PD:
• FI:
• AOUT:
Initializing period of ADC analog section (516/fs).
Power down state.
Fade in. After exiting power down and reset state, ATT value fades in.
Some pop noise may occur at “*”.
Figure 12. Reset & Power Down Sequence in parallel mode
MS0368-E-00
2004/12
- 27 -
ASAHI KASEI
[AK4620A]
„ Serial Control Interface
The internal registers may be written to the 3-wire µP interface pins: CSN, CCLK, CDTI. The data on this interface
consists of Chip address (2bits, C0/1) Read/Write (1 bit), Register address (MSB first, 5 bits) and Control data (MSB first,
8 bits). Address and data is clocked in on the rising edge of CCLK. Data is latched out after the 16th rising edge of CCLK,
following a high-to-low transition of CSN. Operation of the control serial port may be completely asynchronous with the
audio sample rate. The maximum clock speed of the CCLK is 5MHz. The chip address is fixed to “10”. The access to the
chip address except for “10” is invalid. PDN pin = “L” resets the registers to their default values.
Function
Parallel mode
Serial mode
ADC Single-ended/Differential Input mode
X
X
Overflow detection
X
X
Zero detection
X
Soft Mute
X
Input Volume
X
Output Volume
X
HPF OFF
X
DSD mode
X
16/20/24 bit LSB justified format of DAC
X
MCLK = 256fs @ Quad Speed
X
De-emphasis: 32kHz, 48kHz
X
Table 17. Function List (X: available, -: not available)
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip A ddress (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE)
Register Address
Cont rol data
Figure 13. Control I/F Timing
* READ command is not supported.
* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.
MS0368-E-00
2004/12
- 28 -
ASAHI KASEI
[AK4620A]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
Register Name
Power Down Control
Reset Control
Clock and Format Control
D7
SLOW
D/P
DIF2
Deem and Volume Control
SMUTE
Lch IPGA Control
Rch IPGA Control
Lch ATT Control
Rch ATT Control
IPGL7
IPGR7
ATTL7
ATTR7
D6
DZFB
DCKS
DIF1
HPRN
IPGL6
IPGR6
ATTL6
ATTR6
D5
ZOE
DCKB
DIF0
HPLN
IPGL5
IPGR5
ATTL5
ATTR5
D4
ZOS
0
CMODE
ZCEI
IPGL4
IPGR4
ATTL4
ATTR4
D3
0
AML
CKS1
ZTM1
IPGL3
IPGR3
ATTL3
ATTR3
D2
PWVR
AMR
CKS0
ZTM0
IPGL2
IPGR2
ATTL2
ATTR2
D1
PWAD
RSTAD
DFS1
DEM1
IPGL1
IPGR1
ATTL1
ATTR1
D0
PWDA
RSTDA
DFS0
DEM0
IPGL0
IPGR0
ATTL0
ATTR0
Note: Data should not be written to addresses 08H through 1FH.
PDN pin = “L” resets the registers to their default values.
„ Control Register Setup Sequence
When the PDN pin goes “L” to “H” upon power-up etc., the AK4620A will be ready for normal operation by the next
sequence. In this case, all control registers are set to default values and the AK4620A is in the reset state.
(1) Set the clock mode and the audio data interface mode.
(2) Cancel the reset state by setting RSTAD bit or RSTDA bit to “1”. Refer to Reset Contorl Register (01H).
(3) ADC output and DAC output should be muted externally until canceling each reset state.
The clock mode should be changed after setting RSTAD bit and RSTDA bit to “0”. At that time, ADC outputs and DAC
outputs should be muted externally.
MS0368-E-00
2004/12
- 29 -
ASAHI KASEI
[AK4620A]
„ Register Definitions
Addr
00H
Register Name
Power Down Control
DEFAULT
D7
SLOW
0
D6
DZFB
0
D5
ZOE
0
D4
ZOS
0
D3
0
0
D2
PWVR
1
D1
PWAD
1
D0
PWDA
1
PWDA: DAC power down
0: Power down
1: Power up (Default)
“0” powers down only the DAC section and then the AOUTs go to Hi-Z immediately. The contents of all
registers are not initialized and enabled to write to the registers. After exiting power down mode, the OATTs
fade in/out the setting value of the control register (06H & 07H). The analog output should be muted externally
as some pop noise may occur when entering and exiting this mode.
PWAD: ADC power down
0: Power down
1: Power up (Default)
“0” powers down only the ADC and then the SDTO goes “L” immediately. The IPGAs also go “00H”, but the
contents of all registers are not initialized and enabled to write to the registers. After exiting power down
mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, the ADCs output
“0” during first 516 LRCK cycles.
PWVR: Vref power down
0: Power down
1: Power up (Default)
“0” powers all sections down and then both ADC and DAC do not operate. The contents of all register values
are not initialized and enabled to write to the registers. When PWAD and PWDA bits go to “0” and PWVR bit
goes to “1”, only the VREF section can be powered up.
ZOS: Zero-detection/ Overflow-detection control for #15 and 16 pins.
0: Overflow detection for ADC input (Default)
1: Zero detection for DAC input.
ZOE: Zero-detection / Overflow-detection Disable
0: Enable (Default)
1: Disable. Outputs “L”.
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection (Default)
1: DZF goes “L” at Zero Detection
SLOW: DAC Slow Roll-off Filter Enable
0: Sharp Roll-off Filter (Default)
1: Slow Roll-off Filter
MS0368-E-00
2004/12
- 30 -
ASAHI KASEI
Addr
01H
Register Name
Reset Control
DEFAULT
[AK4620A]
D7
D/P
0
D6
DCKS
0
D5
DCKB
0
D4
0
0
D3
AML
0
D2
AMR
0
D1
RSTAD
0
D0
RSTDA
0
RSTDA: DAC reset
0: Reset (Default)
1: Normal Operation
“0” resets the internal timing and the AOUTs go to VCOM voltage immediately. The contents of all registers
are not initialized and enabled to write to the registers. After exiting the power down mode, the OATTs fade in
the setting values of the control register (06H & 07H). The analog outputs should be muted externally since
pop noise may occur when entering to and exiting from this mode.
RSTAD: ADC reset
0: Reset (Default)
1: Normal Operation
“0” resets the internal timing and then SDTO goes to “L” immediately. The IPGAs also go “00H”, but the
contents of all registers are not initialized and enabled to write to the register. After exiting the power down
mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, the ADCs output
“0” during first 516 LRCK cycles.
AML, AMR: default “0” (see Table 16)
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is available upon DCLK falling edge. (Default)
1: DSD data is available upon DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (Default)
1: 768fs
D/P: DSD/PCM Mode Select
0: PCM mode (Default)
1: DSD mode
Addr
02H
Register Name
Clock and Format Control
DEFAULT
D7
DIF2
0
D6
DIF1
1
D5
DIF0
0
D4
CMODE
0
D3
CKS1
0
D2
CKS0
0
D1
DFS1
0
D0
DFS0
0
DFS1-0: Sampling Speed Control (see Table 2)
Default: Normal speed
CMODE, CKS1-0: Master Clock Frequency Select (see Table 3)
Default: 256fs
DIF2-0: Audio data interface modes (see Table 9)
000: Mode 0
001: Mode 1
010: Mode 2
011: Mode 3
100: Mode 4
Default: 24bit MSB justified for both ADC and DAC
MS0368-E-00
2004/12
- 31 -
ASAHI KASEI
Addr
03H
Register Name
Deem and Volume Control
DEFAULT
[AK4620A]
D7
D6
D5
SMUTE
HPRN
HPLN
0
0
0
D4
ZCEI
1
D3
ZTM1
1
D2
ZTM0
0
D1
DEM1
0
D0
DEM0
1
DEM1-0: De-emphasis response (see Table 3)
00: 44.1kHz
01: OFF (Default)
10: 48kHz
11: 32kHz
ZTM1-0: Zero-crossing timeout period select (see Table 11)
Default: 1024fs
ZCEI: ADC IPGA Zero crossing enable
0: Input PGA gain changes occur immediately
1: Input PGA gain changes occur only on zero-crossing or after timeout. (Default)
HPLN/RN: Left/Right channel Digital High Pass Filter Disable
0: Enable (Default)
1: Disable
SMUTE: DAC Input Soft Mute control
0: Normal operation (Default)
1: DAC outputs soft-muted
The soft mute is independent of the output ATT and performed digitally.
MS0368-E-00
2004/12
- 32 -
ASAHI KASEI
Addr
04H
05H
[AK4620A]
Register Name
Lch IPGA Control
Rch IPGA Control
DEFAULT
D7
IPGL7
IPGR7
1
D6
IPGL6
IPGR6
0
D5
IPGL5
IPGR5
0
D4
IPGL4
IPGR4
0
D3
IPGL3
IPGR3
0
D2
IPGL2
IPGR2
0
D1
IPGL1
IPGR1
0
D0
IPGL0
IPGR0
0
IPGL/R7-0: ADC Input Gain Level
Refer to Table 10
Default: 80H (0dB)
The AK4620A includes two channel-independent analog volumes (IPGA), each with 32 levels in 0.5dB increments.
These are located in front of the ADC while digital volume controls (IATT) with 128 levels (including MUTE) are
located after the ADC. Control of both of these volume settings is handled by the same register address (04H for L-ch,
05H for R-ch). When the MSB of the register is “1”, the IPGA changes and when the MSB= “0” the IATT changes. 80H
is the crossover point of the IPGA and DATT, and both IPGA/IATT are set to 0dB.
The IPGAs are set to “00H” when the PDN pin goes “L”. After returning to “H”, the IPGAs fade in the default value,
“80H” by 531(1/fs) cycles. The IPGAs are set to “00H” when PWAD goes “0”. After returning to “1”, the IPGAs fade in
the current value, but the ADC output is “0” during the first 516(1/fs) cycles. The IPAGs are set to “00H” when RSTAD
goes “0”. After returning to “1”, the IPGAs fade in to the current value, but the ADC outputs “0” during the first 516(1/fs)
cycles. IATTs can be controlled in differential mode.
Data
FFH ~ A5H
A4H
A3H
:
82H
81H
80H
7FH
7EH
:
02H
01H
00H
Addr
06H
07H
Analog
Volume (dB)
+18
+18
+17.5
:
+1.0
+0.5
0
0
0
:
0
0
0
Register Name
Lch OATT Control
Rch OATT Control
DEFAULT
Step width
Digital
Total Gain (dB)
(dB)
ATT (dB)
0
+18
0
+18
0
+17.5
0.5
:
:
:
0
+1.0
0.5
0
+0.5
0.5
0
0
0.5
-0.5
-0.5
0.5
-1.0
-1.0
0.5
:
:
:
-63.0
-63.0
0.5
-63.5
-63.5
0.5
MUTE
MUTE
Table 10. IPGA code table
D7
ATTL7
ATTR7
1
D6
ATTL6
ATTR6
1
D5
ATTL5
ATTR5
1
D4
ATTL4
ATTR4
1
D3
ATTL3
ATTR3
1
IPGA
Analog volume with 0.5dB/step
IATT
Digital volume with 0.5dB/step.
Soft-changes between each level.
D2
ATTL2
ATTR2
1
D1
ATTL1
ATTR1
1
D0
ATTL0
ATTR0
1
ATT7-0: Attenuation Level
ATT = 20 log10 (ATT_DATA / 255) [dB]
FFH : 0dB (Default)
00H : Mute
MS0368-E-00
2004/12
- 33 -
ASAHI KASEI
[AK4620A]
SYSTEM DESIGN
Figure 14 & Figure 15 shows the system connection diagram. An evaluation board (AKD4620A) is available, which
demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
0.1u
10u
+
1
VCOM
AOUTR+
30
Rch
Input
Buffer
2
AINR+
AOUTR-
29
3
AINR-
AOUTL+
28
Lch
Input
Buffer
4
AINL+
AOUTL-
27
5
AINL-
DGND
26
6
VREF
VD
25
7
AGND
VT
24
8
VA
ADMODE
23
9
P/S
DEM0
22
10 MCLK
PDN
21
11 LRCK
DFS0
20
CSN/DIF
19
13 SDTO
CCLK/CKS1
18
14 SDTI
CDTI/CKS0
17
15 OVFR/DZFR
OVFL/DZFL
16
4.75 ∼ 5.25V
Analog Supply +
10u
AK4620A
0.1u
Rch
LPF
Rch Out
Lch
LPF
Lch Out
0.1u
3.0 ∼ 3.6V
Digital Supply
3.0 ∼ 5.25V
Digital Supply
0.1u
Audio
DSP
12 BICK
Mode
Setting/
uP
330
330
33p
33p
Notes:
- AGND and DGND must be connected to the same analog ground plane.
- When AOUT+/- drives some capacitive load, some resistance should be added in series between AOUT+/- and
capacitive load.
- All digital input pins must not be left floating.
- When OVFR/DZFR pin and OVFL/DZFL pin are used, a 330Ω resistor and a 33pF capacitor should be added to
OVFR/DZFR pin and OVFL/DZFL pin to avoid the coupling from SDTO pin.
Figure 14. Typical Connection Diagram (Differential mode)
MS0368-E-00
2004/12
- 34 -
ASAHI KASEI
[AK4620A]
0.1u
4.75 ∼ 5.25V
Analog Supply
+
10u
10u
+
1
VCOM
AOUTR+
30
2
AINR+
AOUTR-
29
3
NC
AOUTL+
28
4
AINL+
AOUTL-
27
5
NC
DGND
26
6
VREF
VD
25
7
AGND
VT
24
8
VA
ADMODE
23
9
P/S
DEM0
22
10 MCLK
PDN
21
11 LRCK
DFS0
20
CSN/DIF
19
13 SDTO
CCLK/CKS1
18
14 SDTI
CDTI/CKS0
17
15 OVFR/DZFR
OVFL/DZFL
16
AK4620A
0.1u
Rch
LPF
Rch Out
Lch
LPF
Lch Out
0.1u
3.0 ∼ 3.6V
Digital Supply
3.0 ∼ 5.25V
Digital Supply
0.1u
Audio
DSP
12 BICK
Mode
Setting/
uP
330
330
33p
33p
Notes:
- AGND and DGND must be connected to the same analog ground plane.
- When AOUT+/- drives some capacitive load, some resistor should be added in series between AOUT+/- and
capacitive load.
- All digital input pins must not be left floating.
- When OVFR/DZFR pin and OVFL/DZFL pin are used, a 330Ω resistor and a 33pF capacitor should be added to
OVFR/DZFR pin and OVFL/DZFL pin to avoid the coupling from SDTO pin.
Figure 15. Typical Connection Diagram (Single-ended mode)
MS0368-E-00
2004/12
- 35 -
ASAHI KASEI
[AK4620A]
Digital Ground
Analog Ground
System
Controller
1
VCOM
AOUTR+
30
2
AINR+
AOUTR-
29
3
AINR-/NC
AOUTL+
28
4
AINL+
AOUTL-
27
5
AINL-/NC
DGND
26
6
VREF
VD
25
7
AGND
VT
24
8
VA
ADMODE
23
9
P/S
DEM0
22
10
MCLK
PDN
21
11
LRCK
DFS0
20
12
BICK
CSN/DIF
19
13
SDTO
CCLK/CKS1
18
14
SDTI
CDTI/CKS0
17
15
OVFR/DZFR
OVFL/DZFL
16
AK4620A
Figure 16. Ground Layout
1. Grounding and Power Supply Decoupling
The AK4620A requires careful attention to power supply and grounding layout. To minimize coupling from digital noise,
decoupling capacitors should be connected to VA, VD and VT respectively. VA is supplied from the analog supply in the
system, and VD and VT are supplied from the digital supply in the system. Power lines of VA, VD and VT should be
distributed separately from the point with low impedance of regulator etc. The power up sequence is not critical among
VA, VD and VT. AGND and DGND must be connected to one analog ground plane. Decoupling capacitors
should be as near to the AK4620A as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
The differential voltage between VREF and AGND sets the analog input/output range. VREF pin is normally connected
to VA with a 0.1µF ceramic capacitor. VCOM is the signal ground of this chip. A 10µF electrolytic capacitor in parallel
with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may
be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order
to avoid unwanted coupling into the AK4620A.
3. ADC Output
The ADC output data format is 2’s complement. The DC offset, including the ADC’s own DC offset, is removed by the
internal HPF. The AK4620A samples the analog inputs at 128fs. The digital filter rejects noise above the stopband except
for multiples of 128fs.
MS0368-E-00
2004/12
- 36 -
ASAHI KASEI
[AK4620A]
4. Analog Inputs
4-1. Single-ended Input (ADMODE pin = “L”)
The IPGA inputs are single-ended. The input resistance of IPGA is typically 5.1kΩ at IPGA=0dB and typically
1.18kΩ at IPGA=+18dB. The input signal is typically AC coupled through a capacitor. The cut-off frequency is fc =
(1/2πRC). The input signal range scales with the VREF voltage and is nominally 3.07Vpp (VREF=5V) centered
around the internal common voltage (about VA/2). In single-ended mode, the AK4620A includes an anti-aliasing
filter (RC filter) to attenuate noise around 128fs.
4-2. Full-Differential Input (ADMODE pin = “H”)
The AK4620A can accept input voltages from AGND to VA. The input signal range scales with the VREF voltage
and is nominally 2.82Vpp (VREF = 5V), centered around the internal common voltage (about VA/2). Figure 17 shows
an input buffer circuit example. This is a fully differential input buffer circuit with an inverted amplifier (gain:
−10dB). The capacitor of 10nF between AINL+/− (AINR+/−) decreases the clock feedthrough noise of the modulator,
and composes a 1st order LPF (fc=360kHz) with a 22Ω resistor before the capacitor. This circuit also has a 1st order
LPF (fc=370kHz) composed of op-amp. The evaluation board should be referred about the detail.
910
4.7k
4.7k
470p
VP+
Analog In
47µ
3k
22
2.82Vpp
AIN+
VP9.3Vpp
Bias
NJM5532
910
VA
10k
47µ
22
AIN-
0.1µ 10µ
Bias
10k
3k
AK4620A
10n
470p
VA = 5V
VP+ = 15V
VP- = -15V
Bias
2.82Vpp
Figure 17. Input Buffer example in differential mode
MS0368-E-00
2004/12
- 37 -
ASAHI KASEI
[AK4620A]
5. Analog Outputs
The analog outputs are fully differential and 2.8Vpp (typ. VREF = 5V), centered around VCOM. The differential outputs
are summed externally: Vout = (AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output
range is 5.6Vpp (typ. VREF = 5V). The bias voltage of the external summing circuit is supplied externally. The input data
format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for
800000H(@24bit). The ideal AOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filter and the external LPF attenuate the noise generated by the delta-sigma modulator
beyond the audio passband. Figure 18 shows an example of external LPF circuit summing the differential outputs by an
op-amp. Figure 19 shows an example of differential outputs and LPF circuit example by three op-amps.
AK4620A
4.7k
4.7k
AOUT200
330p
+Vop
AOUT+
2.2n
4.7k
4.7k
Analog
Out
200
330p
-Vop
Figure 18. External LPF Circuit Example 1 for PCM (fc = 136kHz, Q=0.694)
Frequency Response
Gain
20kHz
−0.01dB
40kHz
−0.06dB
80kHz
−0.59dB
Table 18. Filter Response of External LPF Circuit Example 1 for PCM
MS0368-E-00
2004/12
- 38 -
ASAHI KASEI
[AK4620A]
+15
3.3n
+
180
AOUTL- +
0.1u
7
3
2 +
4
3.9n
10k
330
-15
10u
6
NJM5534D
+
10u
0.1u
620
620
3.3n
+
100u
180
3
+
2 -
AOUTL+ +
3.9n
10k
330
7
6
1.2k
2
- 4
3 + 7
Lch
1.0n NJM5534D
10u
0.1u
680
100
6
0.1u
4
NJM5534D
+10u
1.0n
1.2k
680
0.1u
560
560
100u
+
+
10u
10u
0.1u
Figure 19. External LPF Circuit Example 2 for PCM
1st Stage
2nd Stage
Total
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 19. Filter Response of External LPF Circuit Example 2 for PCM
MS0368-E-00
2004/12
- 39 -
ASAHI KASEI
[AK4620A]
It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass
filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4620A can achieve this
filter response by combination of the internal filter (Table 20) and an external filter (Figure 20).
Frequency
Gain
20kHz
−0.4dB
50kHz
−2.8dB
100kHz
−15.5dB
Table 20. Internal Filter Response at DSD mode
2.0k
1.8k
4.3k
AOUT1.0k
270p
2.8Vpp
2200p
+Vop
3300p
2.0k
1.8k
1.0k
AOUT+
+
2.8Vpp
4.3k
270p
Analog
Out
6.34Vpp
-Vop
Figure 20. External 3rd order LPF Circuit Example for DSD
Frequency
Gain
20kHz
−0.05dB
50kHz
−0.51dB
100kHz
−16.8dB
DC gain = 1.07dB
Table 21. 3rd order LPF (Figure 20) Response
MS0368-E-00
2004/12
- 40 -
ASAHI KASEI
[AK4620A]
PACKAGE
30pin VSOP (Unit: mm)
1.5MAX
*9.7±0.1
0.3
30
16
15
1
0.22±0.1
7.6±0.2
5.6±0.1
A
0.15 +0.10
-0.05
0.65
0.12 M
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
„ Material & Lead finish
Package molding compound: Epoxy
Lead frame material:
Cu
Lead frame surface treatment: Solder plate (Pb Free)
MS0368-E-00
2004/12
- 41 -
ASAHI KASEI
[AK4620A]
MARKING
AKM
AK4620AVF
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB : Lot number (X : Digit number, B : Alpha character)
YYYYC : Assembly date (Y : Digit number, C : Alpha character)
Revision History
Date (YY/MM/DD)
04/12/14
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or
use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or
other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with
the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any
and all claims arising from the use of said product in the absence of such notification.
MS0368-E-00
2004/12
- 42 -