ASAHI KASEI [AKD4528] AKD4528 AK4528 Evaluation Board Rev.C GENERAL DESCRIPTION The AKD4528 is an evaluation board for the AK4528, the 24Bit A/D & D/A converter. The AKD4528 can evaluate A/D converter and D/A converter separately in addition to Loopback mode (A/D→D/A). The AKD4528 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD4528 --- AK4528 Evaluation Board (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This Control software does not operate on Windows NT.) FUNCTION Digital interface - DIT (AK4353), DIR (AK4112B) with optical output/input. 10pin header for serial control interface -15V +15V LIN RIN Regulator AGND DGND AK4112B (DIT) Input Buffer AK4528 LOUT ROUT AK4353 (DIT) Opt In Opt Out Output Buffer 10pin Header Control Data Figure 1. AKD4528 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM063101> 2005/11 -1- ASAHI KASEI [AKD4528] 1. Analog Input Buffer Circuit The ADC inputs are full differential and the input resistance is 27kΩ (typ. @fs=44.1kHz). The input signal range scales with the VREF voltage and nominally 0.56 x VREF Vpp. It is recommended that the input DC bias voltage is 2.9V(The bias is a voltage divided by resistors (3.3k and 4.7k) from VA in figure 2. The ADC output data format is 2’s complement. The DC offset including ADC own DC offset removed by the internal HPF (fc=0.9Hz@fs=44.1kHz). The AK4528 samples the analog inputs at 64fs. The digital filter rejects noise above the stopband except for multiples of 64fs. A simple RC filter may be used to attenuate any noise around 64fs though most audio signals do not have significant energy at 64fs. Figure 2 is an example of differential input circuit. 5.96Vpp 4.7k 4.7k 2.8Vpp AK4528 1.5nF 330 AINR+ 2 330 AINR- Vop+ 10k 4.7k + NJM5532 22u + Signal VA Vop- 3 3.3k Vop+/-=+/-15V 2.8Vpp AINL+ 4 0.1u BIAS VA=5V AINL- 5 Same circuit Input RC filter response : fc = 160kHz, + 10u 4.7k g = -0.07dB at 20kHz, -0.26dB at 40kHz. Figure 2. Differential Input Buffer Example 2.Analog Output Buffer Circuit The 2nd-order LPF (fc=93.2kHz, Q=0.712) which adds differential output of AK4528 is implemented on the board. When the further attenuation of the out-band noise is needed, some additional LPF is required. NJM5532D is used for op-amp. Analog signal is output through BNC connectors (AOUTL, AOUTR) on board, and the output level of AK4528 is about 5.4Vp-p. 4.7k 4.7k AOUT200 +Vop 3300p 4.7k 200 AOUT+ 4.7k 470p 470p + Analog Out -Vop fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz Figure 3. External 2nd order LPF Example (using dual supply op-amp) <KM063101> 2005/11 -2- ASAHI KASEI [AKD4528] 1. Evaluation Board Manual Operation sequence 1) Set up the power supply line [+15V] (Orange) = +15V [-15V] (Green) = -15V [AGND] (Black) = 0V [DGND] (Black) = 0V Note: Power should be supplied after jumpers are set-ups properly. Each supply line should be distributed from the power supply unit. 2) Set up the evaluation modes, jumper pins and DIP switch. (See the followings.) 3) Power on The AK4528, AK4112B and AK4353 should be reset once bringing SW3 (PDN) “L” upon power-up. Evaluation modes Applicable evaluation modes (1) Loopback mode (Default) (2) Evaluation of ADC (3) Evaluation of DAC (1) Loopback mode (Default) Clock mode of the AK4112B should be set to X’tal mode. (2) Evaluation of ADC TOTX176 is used for digital output. Clock mode of the AK4112B should be set to X’tal mode. (3) Evaluation of DAC TORX176 or COAX is used for digital input. Clock mode of the AK4112B should be set to PLL mode. <KM063101> 2005/11 -3- ASAHI KASEI [AKD4528] Set-up SW2 [SW2]: Set-up AK4112B. Upper is “ON”(“H”), Lower is “OFF”(“L”) (For further details, refer to the datasheet.) No. 1 2 3 4 5 6 7 Name OCKS0 OCKS1 CM0 CM1 DIF0 DIF1 DIF2 Default OFF OFF ON OFF ON OFF ON OFF ON Set-up the master clock frequency (Default: 256fs) (Refer to the datasheet.) Set-up the clock source (Default: X’tal) (Refer to the datasheet.) Set–up the audio format (Default: 24bit, I2S ) (Refer to the datasheet.) Table 1. Set up SW2 1. Set-up Master clock frequency This master clock is generated by the AK4112B, and is supplied from MCKO1 pin of the AK4112B. OCKS1 OCKS0 pin pin (SW2-2) (SW2-1) MCKO1 fs (kHz) 0 0 256fs 32, 44.1, 48, 96 0 1 256fs 32, 44.1, 48, 96 1 0 512fs 32, 44.1, 48 Table 2. Set up Master clock frequency (Default) 2. Set-up Clock source CM1 pin (SW2-4) CM0 pin (SW2-3) 0 0 0 1 PLL X'tal Clock source Input data of DAC ON OFF PLL Optical (Default) OFF ON X'tal Output of ADC Table 3. Set up Clock source (Note) ON: Oscillation (Power-up), OFF: STOP (Power-down) 3. Set–up Audio interface format DIF2 pin (SW2-7) 0 0 0 0 1 1 DIF1 pin (SW2-6) 0 0 1 1 0 0 DIF0 pin ADC format Input format (SW2-5) at Loopback of DAC 0 24bit, Left justified 16bit, Right justified 1 24bit, Left justified 18bit, Right justified 0 24bit, Left justified 20bit, Right justified 1 24bit, Left justified 24bit, Right justified 0 24bit, Left justified 24bit, Left justified 1 24bit, I2S 24bit, I2S Table 4. Set up Audio interface format <KM063101> LRCK H/L H/L H/L H/L H/L L/H BICK 64fs 64fs 64fs 64fs 64fs 64fs (Default) 2005/11 -4- ASAHI KASEI [AKD4528] Set-up SW1 [SW1]: Set-up AK4528. Upper is “ON”(“H”), Lower is “OFF”(“L”) (For further details, refer to the datasheet.) No. 1 2 3 4 5 6 7 Name P/S DEM1 DEM0 DFS DIF CKS1 CKS0 Default ON OFF ON OFF ON OFF OFF OFF ON Serial mode Parallel mode (Default) Set up de-emphasis (Default: OFF) (Refer to the datasheet.) Normal speed (Default) Double speed MSB justified I2S (Default) Set up Master clock frequency in case of the parallel mode (Default: 256fs) (Refer to the datasheet.) Table 5. Set up SW1 Set up Registers and Device pins of AK4528 The register setting uses the control software. (For further details, refer to the datasheet.) 1. Set up Parallel/Serial mode control When P/S= “H”, the AK4528 becomes to the parallel mode. DIF pin selects the audio interface format, and DFS, CKS1, and CKS0 pins select the master clock frequency. When P/S= “L”, the AK4528 becomes to the serial mode. The CKS1, CKS0 and DIF pins are changed to CDTI, CCLK and CSN pins respectively. The DEM1, DEM0 and DFS are ORed between pins and register respectively, so those are able to control by pins even in serial mode. When all the functions are controlled by register, DEM1, DEM0 and DFS pins should be set to “L”. 2. Set up Master clock frequency (a) In case of serial mode CMODE bit 0 0 0 1 1 CKS1 bit CKS0 bit MCLK Normal Speed (DFS bit = “0”) MCLK Double Speed (DFS bit = “1”) 0 0 256fs N/A (Default) 0 1 512fs 256fs 1 0 1024fs 512fs 0 0 384fs N/A 0 1 768fs 384fs Table 6. Set up Master clock frequency in case of serial mode (b) In case of parallel mode CKS1 Pin (SW1-6) CKS0 Pin (SW1-7) MCLK Normal Speed (DFS pin = “L”) MCLK Double Speed (DFS pin = “H”) L L 256fs N/A (Default) L H 512fs 256fs H L 384fs N/A H H 1024fs 512fs Table 7. Set up Master clock frequency in case of parallel mode <KM063101> 2005/11 -5- ASAHI KASEI [AKD4528] 3. Set up Audio interface format (a) In case of the serial mode Mode DIF2 bit DIF1 bit 0 1 2 3 4 0 0 0 0 1 0 0 1 1 0 DIF0 bit SDTO SDTI LRCK 0 24bit, MSB justified 16bit, LSB justified H/L 1 24bit, MSB justified 20bit, LSB justified H/L 0 24bit, MSB justified 24bit, MSB justified H/L 1 24bit, I2S 24bit, I2S L/H 0 24bit, MSB justified 24bit, LSB justified H/L Table 8. Set up Audio interface format in case of serial mode BICK ≥ 32fs ≥ 40fs ≥ 48fs ≥ 48fs ≥ 48fs (Default) (b) In case of parallel mode Mode DIF Pin (SW1-5) 2 3 0 1 SDTO SDTI LRCK BICK 24bit, MSB justified 24bit, MSB justified H/L ≥ 48fs 2 2 ≥ 48fs 24bit, I S 24bit, I S L/H Table 9. Set up Audio interface format in case of parallel mode (Default) Set up Registers of AK4353 (DIT). The register setting uses the control software. (For further details, refer to the datasheet) 1. Set up Master clock frequency CKS2 bit 0 0 0 0 1 1 1 1 DFS1, DFS0 bit “0”, “0” “0”, ”1” (Normal speed) (Double speed) 256fs 128fs (Default) 0 1 256fs 256fs 256fs 1 0 768fs 384fs 192fs 1 1 384fs 384fs 384fs 0 0 1024fs 512fs 256fs 0 1 512fs 512fs N/A 1 0 1536fs 768fs 384fs 1 1 768fs 768fs N/A Table 10. Set up Master clock frequency (Note) DFS1, DFS0=“1”, “0”: Reserved (Not defined) CKS1 bit 0 CKS0 bit 0 “1”, ”1” (Half speed) 512fs <KM063101> 2005/11 -6- ASAHI KASEI [AKD4528] 2. Set up Audio interface format Mode 0 1 2 3 4 5 6 7 DIF2 bit 0 0 0 0 1 1 1 1 DIF1 DIF0 bit bit SDTI 0 0 16bit, LSB justified 0 1 18bit, LSB justified 1 0 20bit, LSB justified 1 1 24bit, LSB justified 0 0 24bit, MSB justified 0 1 I2S 1 0 Reserved 1 1 Reserved Table 11. Set up Audio interface format L/R H/L H/L H/L H/L H/L L/H BICK ≥32fs ≥36fs ≥40fs ≥48fs ≥48fs ≥48fs (Default) Set up Jumper pins JP1 (RX): Selection of Optical connector or BNC connector TORX176 (Default): Biphase signal is supplied to AK4112B by optical connector. COAX : Biphase signal is supplied to AK4112B by BNC connector. JP2 (GND): Separate/Connect AGND and DGND Open : Separate AGND and DGND. Short (Default) : Connect AGND and DGND. The indication content for LED [LE1] (ERF) : AK4112B unlock and parity error output. [LE2] (FS96) : AK4112B 96kHz sampling detect. [LE3] (AUTO): AK4112B AC-3/MPEG detects. [LE4] (V) : Validity. The function of the toggle SW [SW3]: Resets the AK4528, AK4112B and AK4353. Keep “H” during normal operation. Serial control mode The AK4528 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (CR-I/F) with PC by 10-wire flat cable packed with the AKD4528. 10 PORT2 CR-I/F 9 CSN CCLK CDTI Take care of the direction of connector. There is a mark at pin#1. The pin layout of PORT1 is as Figure 4. 2 1 Figure 4. PORT2 pin layout *AKM assumes no responsibility for the trouble when using the circuit examples. <KM063101> 2005/11 -7- ASAHI KASEI [AKD4528] Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4528 according to previous term. 2. Connect IBM-AT compatible PC with AKD4528 by 10-line type flat cable (packed with AKD4528). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AKD4528 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive, and double-click the icon of “akd4528.exe”and “akd4528_dit.exe”, and set up the control program. akd4528.exe: AK4528 control program akd4528_dit.exe: AK4353 (DIT) control program 5. Then evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. Explanation of each buttons 1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A). Initialize the registers. Write all registers data that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM063101> 2005/11 -8- ASAHI KASEI [AKD4528] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. When writing the input data to register, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog]: Dialog to write data by keyboard operation Address Box: Input registers address in 2 figures of hexadecimal. Data Box: Input registers data in 2 figures of hexadecimal. When writing the input data to register, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog]: Dialog to evaluate ATT This is a dialog corresponding to address: 04H, 05H of AK4528, and address: 03H, 04H of AK4353. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to register by this interval. Step Box: Data changes by this step. Mode Select Box: With checking this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 Without checking this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 When writing the input data to register, click [OK] button. If not, click [Cancel] button. <KM063101> 2005/11 -9- ASAHI KASEI [AKD4528] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data to the file. The extension of file name is “akr”. (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is “akr”. 4-2. [Open] The register setting data saved to the file by [Save] is written to register. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button. <KM063101> 2005/11 - 10 - ASAHI KASEI [AKD4528] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the [Function3] window. The extension of file name is “aks”. Figure 1. Window of [F3] <KM063101> 2005/11 - 11 - ASAHI KASEI [AKD4528] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 2 opens. Figure 2. [F4] window <KM063101> 2005/11 - 12 - ASAHI KASEI [AKD4528] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 3. Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The sequence file names can assign be saved. The file name is *.ak4. [OPEN]: The sequence file names assign that are saved in *.ak4 are loaded. <KM063101> 2005/11 - 13 - ASAHI KASEI [AKD4528] 6-3. Note (1) [Function4] doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change. <KM063101> 2005/11 - 14 - ASAHI KASEI [AKD4528] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 4opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). (2) Click [WRITE] button, then the register setting is executed. 7-2. [SAVE] and [OPEN] buttons on right side [SAVE]: The register setting file names assign can be saved. The file name is *.ak5. [OPEN]: The register setting file names assign that are saved in *.ak5 are loaded. <KM063101> 2005/11 - 15 - ASAHI KASEI [AKD4528] 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change. <KM063101> 2005/11 - 16 - ASAHI KASEI [AKD4528] AK4528 Measurement Results Conditions: Measurement unit: Audio Precision System Two Cascade MCLK: 256fs BICK: 64fs LRCK: 44.1kHz(DIR or DIT), or 96kHz(DIR or DIT) Power supply: VA=VD=VT=5.0V Interface: DIT or DIR Temperature: Room Temp. 1. ADC 1-1. fs = 44.1kHz Parameter Input signal BW, filter S/(N+D) 1kHz, -0.5dB 20kHz Dynamic range 1kHz, -60dB 20kHz 20kHz, A-weighted S/N off 20kHz 20kHz, A-weighted Results Lch Rch 98.4 98.2 102.6 102.6 107.4 107.5 102.8 102.8 107.5 107.5 unit dB dB dB dB dB 1-2. fs=96kHz Parameter Input signal BW, filter S/(N+D) 1kHz, -0.5dB fs/2 Dynamic range 1kHz, -60dB fs/2 fs/2, A-weighted S/N off fs/2 fs/2, A-weighted <KM063101> Results Lch Rch 91.4 92.8 99.8 99.9 108.3 108.5 100.0 100.8 108.9 109.0 unit dB dB dB dB dB 2005/11 - 17 - ASAHI KASEI [AKD4528] DAC 2-1. fs=44.1kHz Parameter Input signal BW, filter S/(D+N) 1kHz, 0dBFS 20kHz Dynamic range 1kHz, -60dBFS 20kHz 22kHz, A-weighted S/N "0" data 20kHz 22kHz, A-weighted Results Lch Rch 93.7 94.5 108.0 108.0 110.7 110.6 108.2 108.0 110.9 110.7 unit dB dB dB dB dB 2-2. fs=96kHz Parameter Input signal BW, filter S/(N+D) 1kHz, 0dBFS 40kHz Dynamic range 1kHz, -60dBFS 40kHz 80kHz, A-weighted S/N "0" data 40kHz 80kHz, A-weighted <KM063101> Results Lch Rch 91.2 91.8 104.8 104.9 110.0 110.0 104.9 104.8 110.2 109.9 unit dB dB dB dB dB 2005/11 - 18 - ASAHI KASEI [AKD4528] 1. ADC (fs=44.1kHz) AK M A K4528 ADC FFT (Input Level=-0.5dBFS , fin=1kHz) +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz FFT (Input Level = -0.5dBFS, fin=1kHz) AK M AK 4528 A DC FFT (Input Level=-60dBFS, fin=1kHz) +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz FFT (Input Level = -60dBFS, fin=1kHz) <KM063101> 2005/11 - 19 - ASAHI KASEI [AKD4528] (fs=44.1kHz) AK M AK4528 ADC FFT (noise floor) +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz FFT (noise floor) <KM063101> 2005/11 - 20 - ASAHI KASEI [AKD4528] (fs=44.1kHz) AK M AK4528 ADC THD + N vs Am plitude(fin=1kHz) -80 -82 -84 -86 -88 -90 -92 d B F S -94 -96 -98 -100 -102 -104 -106 -108 -110 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr THD + N vs Amplitude (fin=1kHz) AK M A K4528 ADC THD + N vs Input Frequency(Input Level=0dB FS ) -80 -82 -84 -86 -88 -90 -92 d B F S -94 -96 -98 -100 -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k Hz THD + N vs Input Frequency (Input Level = -0.5dBFS) <KM063101> 2005/11 - 21 - ASAHI KASEI [AKD4528] (fs=44.1kHz) AK M AK4528 ADC Linearity +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Linearity (fin=1kHz) AK M AK 4528 A DC C rosstalk +0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 d B F S -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 -0.75 -0.8 -0.85 -0.9 -0.95 -1 20 50 100 200 500 1k 2k 5k 10k 20k Hz Frequency Response (Input Level=1kHz) <KM063101> 2005/11 - 22 - ASAHI KASEI [AKD4528] (fs=44.1kHz) AK M AK 4528 A DC C rosstalk -100 -102 -104 -106 -108 -110 -112 -114 -116 d B F S -118 -120 -122 -124 -126 -128 -130 -132 -134 -136 -138 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Crosstalk <KM063101> 2005/11 - 23 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M AK 4528 A DC FFT(Input Level=-0.5dBFS, fin=1kHz) +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k 5k 10k 20k 40k 10k 20k 40k Hz FFT (Input Level = -0.5dBFS, fin=1kHz) AK M AK 4528 A DC FFT(Input Level=-60dB FS, fin=1kHz) +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k 5k Hz FFT (Input Level = -60dBFS, fin=1kHz) <KM063101> 2005/11 - 24 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M AK 4528 A DC FFT(noise floor) +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz FFT (noise floor) <KM063101> 2005/11 - 25 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M AK4528 ADC THD + N vs Am plitude(fin=1kHz) -80 -82 -84 -86 -88 -90 -92 d B F S -94 -96 -98 -100 -102 -104 -106 -108 -110 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr THD + N vs Amplitude (fin=1kHz) AK M AK 4528 A DC THD + N vs Input Frequency (Input Level=-0.5dB FS) -70 -72 -74 -76 -78 -80 -82 -84 -86 d B F S -88 -90 -92 -94 -96 -98 -100 -102 -104 -106 -108 -110 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz THD + N vs Input Frequency (input Level=-0.5dBFS) <KM063101> 2005/11 - 26 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M AK4528 ADC Linearity +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Linearity (fin=1kHz) AK M A K4528 ADC Frequency Response +0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 d B F S -0.45 -0.5 -0.55 -0.6 -0.65 -0.7 -0.75 -0.8 -0.85 -0.9 -0.95 -1 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Frequency Response (Input Level=-0.5dBFS) <KM063101> 2005/11 - 27 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M A K4528 ADC Crosstalk(Upper=Lch, Lower=Rch) -100 -102 -104 -106 -108 -110 -112 d B F S -114 -116 -118 -120 -122 -124 -126 -128 -130 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Crosstalk <KM063101> 2005/11 - 28 - ASAHI KASEI [AKD4528] 2. DAC (fs=44.1kHz) AK M A K4528 DAC FFT (Input Level=0dBFS , fin=1kHz) +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz FFT (Input Level=0dBFS, fin=1kHz) AK M A K4528 DAC FFT (Input Level=0dBFS , fin=1kHz) +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz FFT (Input Level=-60dBFS, fin=1kHz) <KM063101> 2005/11 - 29 - ASAHI KASEI [AKD4528] (fs=44.1kHz) AK M A K4528 D AC FFT (Input=0data) +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k Hz FFT (Input = “0”data) AK M A K4528 DAC FFT (O ut-of-band noise) +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k 5k 10k 20k 50k 100k Hz FFT (out-of-band noise) <KM063101> 2005/11 - 30 - ASAHI KASEI [AKD4528] (fs=44.1kHz) AK M AK4528 DAC THD + N vs Am plitude(fin=1kHz) -80 -82 -84 -86 -88 -90 -92 -94 -96 d B r A -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS THD + N vs Amplitude (fin=1kHz) AK M AK 4528 DA C THD + N vs Input Frequency (Input Level=0dBFS) -80 -82 -84 -86 -88 -90 -92 d B r -94 -96 A -98 -100 -102 -104 -106 -108 -110 20 50 100 200 500 1k 2k 5k 10k 20k Hz THD + N vs Input Frequency (Input Level=0dBFS) <KM063101> 2005/11 - 31 - ASAHI KASEI [AKD4528] (fs=44.1kHz) AK M AK4528 DAC Linearity +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Linearity (fin=1kHz) AK M A K4528 DAC Frequency Response + 0.5 + 0.45 + 0.4 + 0.35 + 0.3 + 0.25 + 0.2 + 0.15 + 0.1 d B r A + 0.05 +0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Hz Frequency Response (Input Level = 0dBFS) <KM063101> 2005/11 - 32 - ASAHI KASEI [AKD4528] (fs=44.1kHz) AK M A K4528 DAC Crosstalk(Upper=Rch, Lower=Lch) -100 -102 -104 -106 -108 -110 -112 d B r -114 -116 A -118 -120 -122 -124 -126 -128 -130 20 50 100 200 500 1k 2k 5k 10k 20k Hz Crosstalk <KM063101> 2005/11 - 33 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M A K4528 DAC FFT ( Input Level=0dBFS, fin=1kHz, notch O N) +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k 5k 10k 20k 40k 10k 20k 40k Hz FFT (Input Level=0dBFS, fin=1kHz) AK M A K4528 DAC FFT ( Input Level=-60dBFS , fin=1kHz) +0 -10 -20 -30 -40 -50 -60 d B r -70 A -90 -80 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k 5k Hz FFT (Input Level=-60dBFS, fin=1kHz) <KM063101> 2005/11 - 34 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M AK 4528 DA C FFT ( Input 0data) +0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz FFT (Input = “0”data) <KM063101> 2005/11 - 35 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M AK4528 DAC THD + N vs Am plitude(fin=1kHz) -80 -82 -84 -86 -88 -90 -92 d B r -94 -96 A -98 -100 -102 -104 -106 -108 -110 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS THD + N vs Amplitude (fin=1kHz) AK M AK 4528 DA C THD + N vs Input Frequency (Input Level=0dBFS) -80 -82 -84 -86 -88 -90 -92 d B r -94 -96 A -98 -100 -102 -104 -106 -108 -110 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz THD + N vs Input Frequency (Input Level=0dBFS) <KM063101> 2005/11 - 36 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M AK4528 DAC Linearity +0 -10 -20 -30 -40 -50 -60 d B r -70 -80 A -90 -100 -110 -120 -130 -140 -150 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Linearity (fin=1kHz) AK M A K4528 DAC Frequency Response + 0.5 + 0.45 + 0.4 + 0.35 + 0.3 + 0.25 + 0.2 + 0.15 + 0.1 d B r A + 0.05 +0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k Hz Frequency Response (Input Level=0dBFS) <KM063101> 2005/11 - 37 - ASAHI KASEI [AKD4528] (fs=96kHz) AK M AK 4528 DA C C rosstalk -100 -102 -104 -106 -108 -110 -112 d B r -114 -116 A -118 -120 -122 -124 -126 -128 -130 40 50 100 200 500 1k 2k 5k 10k 20k 40k Hz Crosstalk <KM063101> 2005/11 - 38 - ASAHI KASEI [AKD4528] Revision History Date (YY/MM/DD) 00/06/01 Manual Revision KM063100 05/11/01 KM063101 Board Reason Revision 0 First Edition 1 Circuit Change Manual Change Contents (1) AK4112AÆAK4112B (2) C6, C7: 22pFÆ5pF (3) C36, C37, C47, C48ÆDelete (4) L2: shortÆResistance: 5.1 Ohm (1) Change DOS base program to Windows base program. (2) Change the description about control program. (3) Add register / pin settings of AK4528 and AK4353. IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM063101> 2005/11 - 39 - 5 PORT3 5 IN VCC IF 6 6 GND TOTX176 5 TX 4 3 2 1 4 3 2 1 R59 +5V C66 0.1u 1k R60 5.1 D R12 5.1 C68 0.1u U2 +3.3V U4 R1 100 4353_MCLK R2 100 4353_BICK R3 100 4528_SDTO R4 100 PDN 4353_LRCK 4353_CSN 4353_CCLK 4353_CDTI 1 2 3 4 5 6 7 8 9 10 11 12 MCKO DZF TX NC DVDD AVDD DVSS AVSS MCKI VCOM BICK AOUTL SDTI AOUTR LRCK CAD0 PDN CAD1 CSN I2C SCL/CCLK TTL SDA/CDTI TST 24 23 22 21 20 19 18 17 16 15 14 13 C2 10u +5V C69 0.1u + C3 0.1u +C70 10u C71 0.1u + + C4 10u C50 10u C5 0.1u + C67 10u D +5V V/TX C6 5p 2 AK4353 X1 11.2896MHz DVDD CM0/CDTO 28 CM0 2 DVSS CM1/CDTI 27 CM1 3 TVDD OCKS1/CCLK 26 OCKS1 4 V/TX OCKS0/CSN 25 OCKS0 5 XTI MCKO1 24 4112_MCLK 6 XTO MCKO2 23 7 PDN DAUX 22 +5V 1 (DIT) 1 C7 5p C PDN for 74HCT14, 74HCT157 R17 8 +5V R BICK 21 + C27 0.1u 6 RX 5 PORT1 6 GND VCC GND 5 OUT +5V 10u 4 3 2 1 + C9 0.1u AVDD SDTO 20 4112_SDTO 10 AVSS LRCK 19 4112_LRCK ERF 18 C10 0.1u +C11 10u TORX176 RX2/DIF0 FS96 17 1 +3.3V JP1 2 RX COAX RX1 4112_DIF0 12 4112_DIF1 13 RX3/DIF1 P/SN 16 4112_DIF2 14 RX4/DIF2 AUTO 15 3 C12 0.1u RX R11 75 U3B 5 U3C R5 LE1 1k ERF R7 LE2 1k FS96 R8 LE3 1k AUTO R10 LE4 1k V 2 4 74HCT14 6 74HCT14 +5V D2 1S1588 U3A 74HCT14 9 11 R9 470 3 J2 COAX C8 L1 10u TORX176 B +3.3V 2 C26 0.1u 1 18k 1 4112_BICK R6 C25 47u C 4528_SDTO 100 9 V V/TX U3D 8 74HCT14 B AK4112B (DIR) +5V T2 LP2950A 14 13 12 11 10 9 8 1 +3.3V C13 0.1u C14 47u RP2 7 6 5 4 3 2 1 OCKS0 OCKS1 CM0 CM1 DIF0 DIF1 DIF2 OUT + IN 3 C1 47u +5V + C15 0.1u 4112_DIP A GND SW2 2 1 2 3 4 5 6 7 A OCKS0 OCKS1 CM0 CM1 4112_DIF0 4112_DIF1 4112_DIF2 Title 47k Size A3 Date: 5 4 3 2 AKD4528 Document Number AK4112B AK4353 DIR1 DIT Sheet of Monday, October 03, 2005 1 Rev C 3 5 +15V 4 Bias T1 GND NJM78M05FA 1 IN L2 3 2 1 JP2 GND +5V Digital Ground Analog Ground 5.1 AK4528_+5V +C18 47u C17 0.1u 2 C16 0.1u OUT 3 L6 10u 1 2 D D 1 C19 2.2u C20 0.1u + L3 (short) 2 U1 1 VCOM AOUTR+ 28 AOUTR+ AINR+ 2 AINR+ AOUTR- 27 AOUTR- AINR- 3 AINR- AOUTL+ 26 AOUTL+ AINL+ 4 AINL+ AOUTL- 25 AOUTL- AINL- 5 AINL- DGND 24 6 VREF VD 23 7 AGND VT 22 8 VA DEM1 21 DEM1 9 P/S DEM0 20 DEM0 +5V R13 10k 1S1588 C23 10u 11 H L U3E 10 13 74HCT14 C29 0.1u U3F 12 74HCT14 SW3 C24 0.1u + D1 C21 0.1u + C C22 10u C AK4528_+5V PDN 4353_MCLK 4353_LRCK 4353_BICK P/S R14 PDN 10 MCLK PDN 19 PDN 11 LRCK DFS 18 DFS CSN / DIF 17 CSN/DIF CCLK / CKS1 16 CCLK/CKS1 CDTI/CKS0 15 CDTI/CKS0 100 4112_MCLK 4112_LRCK 4112_BICK 4112_SDTO R15 100 R16 12 BICK 13 SDTO 14 SDTI 1 2 3 4 5 6 7 100 B 4528_SDTO R18 +5V SW1 14 13 12 11 10 9 8 B AK4528_DIP 100 AK4528 RP1 +5V R19 2.2k 1 2 3 4 5 A PORT2 10 CSN 9 CCLK 8 CDTI 7 6 R20 2.2k R21 2.2k CKS1 R23 470 P/S DEM1 DEM0 DFS DIF CKS1 CKS0 R22 470 CKS0 CR-I/F 4353_CSN 4353_CCLK 4353_CDTI P/S 2 3 5 6 11 10 14 13 1 15 U5 1A 1B 2A 2B 3A 3B 4A 4B 1Y 4 CSN/DIF 2Y 7 CCLK/CKS1 3Y 9 CDTI/CKS0 4Y 12 A A/B G 74HCT157 Title Size A3 Date: 5 P/S DEM1 DEM0 DFS DIF CKS1 CKS0 47K DIF R24 470 7 6 5 4 3 2 1 4 3 2 Document Number AKD4528 Rev AK4528 Monday, October 03, 2005 Sheet 1 C 2 of 3 5 4 R25 4.7k 3 2 1 R26 4.7k R27 4.7k D D VOP- 4 5 8 U6A NJM5532 VOP+ R31 330 7 R32 4.7k AINL+ R33 200 U6B VOP- NJM5532 VOP+ C33 1.5n C34 3300p R37 4.7k R39 330 + 3 1 U8A NJM5532 J4 AOUTL R34 220 C35 22u R36 10k R38 200 VOP+ AOUTL+ AINL- C39 10u 2 8 Bias R40 3.3k C38 0.1u C32 470p AOUTL- + 6 4 4 8 R29 4.7k 1 + 3 - 2 + 22u + R30 560 VOP- R28 10k - + C30 - J3 LIN R41 4.7k R35 4.7k C40 470p C C R42 4.7k R43 4.7k R44 4.7k VOP- 4 3 NJM5532 VOP+ 8 R48 330 1 R49 4.7k AINR+ R52 200 C43 470p AOUTRVOP- NJM5532 B VOP+ 4 8 2 C44 1.5n C45 3300p 5 8 Bias R57 3.3k 6 + B 7 U7B U7A R54 4.7k R56 330 + 4 VOPR46 4.7k - 5 + 22u 6 + R47 560 R45 10k - + C41 - J5 RIN 7 U8B NJM5532 C46 22u J1 AOUTR R51 220 R53 10k R55 200 VOP+ AOUTR+ AINR- C42 0.1u C49 10u + R50 4.7k R58 4.7k C51 470p -15V +15V A for NJM5532 2 + + C53 10u C54 0.1u C55 10u C56 0.1u C57 10u C59 47u C58 0.1u A 1 VOP+ (short) + 1 C52 47u L4 + L5 for NJM5532 2 (short) VOP+ + + + Title C60 10u C61 0.1u C62 10u C63 0.1u C64 10u C65 0.1u Size A3 Date: 5 4 3 2 Document Number AKD4528 Rev Analog_I/O Monday, October 03, 2005 Sheet 1 C 3 of 3