ALD ALD110900 Quad/dual n-channel zero threshold Datasheet

e
ADVANCED
LINEAR
DEVICES, INC.
EN
FEATURES
ALD110800A/ALD110800/ALD110900A/ALD110900 are high precision
monolithic quad/dual N-Channel MOSFETs matched at the factory using
ALD’s proven EPAD CMOS technology. These devices are members of
the EPAD® Matched Pair MOSFET Family.
• Precision zero threshold voltage mode
• Nominal RDS(ON) @ VGS = 0.00V of 104KΩ
• Matched MOSFET-to-MOSFET characteristics
• Tight lot-to-lot parametric control
• VGS(th) match (VOS) to 2mV and 10mV max.
• Positive, zero, and negative VGS(th) tempco
• Low input capacitance
• Low input/output leakage currents
Intended for low voltage small signal applications, the ALD110800/
ALD110900 features Zero-Threshold™ voltage, which reduces or eliminates input to output voltage level shift, including circuits where the signal
is referenced to GND or V+. This feature greatly reduces output signal
voltage level shift and enhances signal operating range, especially for
very low operating voltage environments. With these zero threshold devices, an analog circuit with multiple stages can be constructed to operate at extremely low supply or bias voltage levels. For example, an input
amplifier stage operating at 0.2V supply voltage has been demonstrated.
ALD110800A/ALD110800/ALD110900A/ALD110900 matched pair
MOSFETs are designed for exceptional device electrical characteristics
matching with the threshold voltage set precisely at +0.00V +/-0.01V, featuring a typical offset voltage of only +/-0.001V (1mV). As these devices
are on the same monolithic chip, they also exhibit excellent tempco tracking characteristics. They are versatile as design components for a broad
range of analog applications such as basic building blocks for current
sources, differential amplifier input stages, transmission gates, and multiplexer applications.
Besides matched pair electrical characteristics, each individual MOSFET
also exhibits well controlled parameters, enabling the user to depend on
tight design limits. Even units from different batches and different date
of manufacture have correspondingly well matched characteristics.
D
• Energy harvesting circuits
• Very low voltage analog and digital circuits
• Zero power fail safe circuits
• Backup battery circuits & power failure detector
• Low level voltage clamp & zero crossing detector
• Source followers and buffers
• Precision current mirrors and current sources
• Capacitives probes and sensor interfaces
• Charge detectors and charge integrators
• Differential amplifier input stage
• High side switches
• Peak detectors and level shifters
• Sample and Hold
• Current multipliers
• Analog switches / multiplexers
• Voltage comparators and level shifters
PIN CONFIGURATIONS
The ALD110800A/ALD110800/ALD110900A/ALD110900 feature high input impedance (1012Ω) and high DC current gain (>108). A sample calculation of the DC current gain at a drain current of 3mA and input leakage
current of 30pA at 25°C is 3mA/30pA = 100,000,000. For most applications, connect the V+ pin to the most positive voltage and the V- and IC
pins to the most negative voltage in the system. All other pins must have
voltages within these voltage limits at all times.
ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS))
Operating Temperature Range*
0°C to +70°C
0°C to +70°C
ALD110800APCL
ALD110800PCL
LE
APPLICATIONS
These devices are built for minimum offset voltage and differential thermal response, and they are designed for switching and amplifying applications in +0.2V to +10V systems where low input bias current, low input
capacitance, and fast switching speed are desired. The VGS(th) of these
devices is set at +0.00V, which classifies them as both enhancement mode
and depletion mode devices. When the gate is set at 0.00V, the drain
current is +1µA @ VDS = 0.1V, which allows a class of circuits with output
voltage level biased at or near input voltage level without voltage level
shift. These devices exhibit well controlled turn-off and sub-threshold
characteristics of standard enhancement mode MOSFETs.
ALD110800ASCL
ALD110800SCL
AB
VGS(th)= +0.00V
GENERAL DESCRIPTION
16-Pin
Plastic Dip
Package
®
ALD110800A/ALD110800/ALD110900A/ALD110900
QUAD/DUAL N-CHANNEL ZERO THRESHOLD™ EPAD®
PRECISION MATCHED PAIR MOSFET ARRAY
16-Pin
SOIC
Package
TM
EPAD
8-Pin
SOIC
Package
ALD110900ASAL
ALD110900SAL
8-Pin
Plastic Dip
Package
ALD110900APAL
ALD110900PAL
* Contact factory for industrial temp. range or user-specified threshold voltage values.
©2017 Advanced Linear Devices, Inc., Vers. 2.4
www.aldinc.com
ALD110800
IC*
1
GN1
2
DN1
V-
V-
M1
3
S12
4
V-
5
DN4
6
GN4
7
IC*
8
M2
V+
VM4
M3
V-
V-
16
IC*
15
GN2
14
DN2
13
V+
12
S34
11
DN3
10
GN3
9
IC*
8
IC*
7
GN2
6
DN2
5
V-
SCL, PCL PACKAGES
ALD110900
IC*
1
GN1
2
DN1
3
S12
4
V-
V-
M1
M2
VSAL, PAL PACKAGES
*IC pins are internally connected, connect to V-
1 of 12
ABSOLUTE MAXIMUM RATINGS
Drain-Source voltage, VDS
10.6V
Gate-Source voltage, VGS
10.6V
Power dissipation
500 mW
Operating temperature range SCL, PCL, SAL, PAL
0°C to +70°C
Storage temperature range
-65°C to +150°C
Lead temperature, 10 seconds
+260°C
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
OPERATING ELECTRICAL CHARACTERISTICS
V+ = +5V V- = GND TA = 25°C unless otherwise specified
ALD110800A/ALD110900A
Parameter
Symbol
Gate Threshold Voltage
VGS(th)
Offset Voltage
VGS(th)1-VGS(th)2
Min
-0.02
Typ
Max
ALD110800/ALD110900
Min
Max
Unit
0.00
0.02
V
2
10
Test Conditions
0.00
0.02
VOS
1
2
Offset Voltage Tempco
TCVOS
5
5
µV/°C
VDS1 = VDS2
Gate Threshold Voltage
Tempco
TCVGS(th)
-1.7
0.0
+1.6
-1.7
0.0
+1.6
mV/°C
IDS = 1µA, VDS = 0.1V
IDS = 20µA, VDS = 0.1V
IDS = 40µA, VDS = 0.1V
Drain Source On Current
IDS(ON)
12.0
3.0
12.0
3.0
mA
VGS = +9.5V, VDS = +5V
VGS = +4.0V, VDS = +5V
Forward Transconductance
GFS
1.4
1.4
mmho
VGS = +4.0V
VDS = +9.0V
Transconductance Mismatch
∆GFS
1.8
1.8
%
Output Conductance
GOS
68
68
µmho
VGS = +4.0V
VDS = +9.0V
Drain Source On Resistance
RDS(ON)
500
500
Ω
VGS = +4.0V
VDS = +0.1V
Drain Source On Resistance
RDS(ON)
104
104
KΩ
VGS = +0.0V
VDS = +0.1V
Drain Source On Resistance
Tolerance
∆RDS(ON)
5
5
%
VGS = +4.0V
VDS = +0.1V
Drain Source On Resistance
Mismatch
∆RDS(ON)
0.5
0.5
%
Drain Source Breakdown
Voltage
BVDSX
Drain Source Leakage Current1
IDS(OFF)
10
-0.02
Typ
400
10
4
mV
V
V- = VGS = -1.0V
IDS = 1.0µA
400
pA
4
nA
VGS = -1.0V, VDS =+5V
V- = -5V
TA = 125°C
200
1
pA
nA
VGS = +5V, VDS = 0V
TA =125°C
10
10
IDS =1µA, VDS = 0.1V
Gate Leakage Current1
IGSS
5
Input Capacitance
CISS
2.5
2.5
pF
Transfer Reverse Capacitance
CRSS
0.1
0.1
pF
Turn-on Delay Time
ton
10
10
ns
V+ = 5V, RL= 5KΩ
Turn-off Delay Time
toff
10
10
ns
V+ = 5V, RL= 5KΩ
60
60
dB
f = 100KHz
Crosstalk
Notes:
1
200
1
5
Consists of junction leakage currents
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
Advanced Linear Devices
2 of 12
PERFORMANCE CHARACTERISTICS OF EPAD®
PRECISION MATCHED PAIR MOSFET FAMILY
ALD1108xx/ALD1109xx/ALD1148xx/ALD1149xx are monolithic
quad/dual N-Channel MOSFETs matched at the factory using ALD’s
proven EPAD® CMOS technology. These devices are intended for
low voltage, small signal applications.
ALD’s Electrically Programmable Analog Device (EPAD) technology provides a family of matched transistors with a range of precision threshold values. All members of this family are designed and
actively programmed for exceptional matching of device electrical
characteristics. Threshold values range from -3.50V Depletion to
+3.50V Enhancement devices, including standard products specified at -3.50V, -1.30V, -0.40V, +0.00V, +0.20V, +0.40V, +0.80V,
+1.40V, and +3.30V. ALD can also provide any customer desired
value between -3.50V and +3.50V. For all these devices, even the
depletion and zero threshold transistors, ALD EPAD technology
enables the same well controlled turn-off, subthreshold, and low
leakage characteristics as standard enhancement mode MOSFETs.
With the design and active programming, even units from different
batches and different dates of manufacture have well matched characteristics. As these devices are on the same monolithic chip, they
also exhibit excellent tempco tracking.
This EPAD MOSFET Array product family (EPAD MOSFET) is available in the three separate categories, each providing a distinctly
different set of electrical specifications and characteristics. The first
category is the ALD110800/ALD110900 Zero-Threshold™ mode
EPAD MOSFETs. The second category is the ALD1108xx/
ALD1109xx enhancement mode EPAD MOSFETs. The third category is the ALD1148xx/ALD1149xx depletion mode EPAD
MOSFETs. (The suffix “xx” denotes threshold voltage in 0.1V steps,
for example, xx = 08 denotes 0.80V).
The ALD110800/ALD110900 (quad/dual) are EPAD MOSFETs in
which the individual threshold voltage of each MOSFET is fixed at
zero. The threshold voltage is defined as IDS = 1µA @ VDS = 0.1V
when the gate voltage VGS = 0.00V. Zero threshold devices operate in the enhancement region when operated above threshold voltage and current level (VGS > 0.00V and IDS > 1µA) and subthreshold region when operated at or below threshold voltage and current level (VGS <= 0.00V and IDS < 1µA). This device, along with
other very low threshold voltage members of the product family,
constitute a class of EPAD MOSFETs that enable ultra low supply
voltage operation and nanopower type of circuit designs, applicable
in either analog or digital circuits.
The ALD1108xx/ALD1109xx (quad/dual) product family features
precision matched enhancement mode EPAD MOSFET devices,
which require a positive bias voltage to turn on. Precision threshold
values such as +1.40V, +0.80V, +0.20V are offered. No conductive
channel exists between the source and drain at zero applied gate
voltage for these devices, except that the +0.20V version has a
subthreshold current at about 20nA.
The ALD1148xx/ALD1149xx (quad/dual) features depletion mode
EPAD MOSFETs, which are normally-on devices when the gate
bias voltage is at zero volts. The depletion mode threshold voltage
is at a negative voltage level at which the EPAD MOSFET turns off.
Without a supply voltage and/or with VGS = 0.0V the EPAD MOSFET
device is already turned on and exhibits a defined and controlled
on-resistance between the source and drain terminals.
The ALD1148xx/ALD1149xx depletion mode EPAD MOSFETs are
different from most other types of depletion mode MOSFETs and
certain types of JFETs in that they do not exhibit high gate leakage
currents and channel/junction leakage currents. When negative
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
signal voltages are applied to the gate terminal, the designer/user
can depend on the EPAD MOSFET device to be controlled, modulated and turned off precisely. The device can be modulated and
turned-off under the control of the gate voltage in the same manner
as the enhancement mode EPAD MOSFET and the same device
equations apply.
EPAD MOSFETs are ideal for minimum offset voltage and differential thermal response, and they are used for switching and amplifying applications in low voltage (1V to 10V or +/-0.5V to +/-5V) or
ultra low voltage (less than 1V or +/-0.5V) systems. They feature
low input bias current (less than 30pA max.), ultra low power
(microWatt) or Nanopower (power measured in nanoWatt) operation, low input capacitance and fast switching speed. These devices can be used where a combination of these characteristics
are desired.
KEY APPLICATION ENVIRONMENT
EPAD MOSFET Array products are for circuit applications in one or
more of the following operating environments:
* Low voltage: 1V to 10V or +/-0.5V to +/-5V
* Ultra low voltage: less than 1V or +/-0.5V
* Low power: voltage x current = power measured in microwatt
* Nanopower: voltage x current = power measured in nanowatt
* Precision matching and tracking of two or more MOSFETs
ELECTRICAL CHARACTERISTICS
The turn-on and turn-off electrical characteristics of the EPAD
MOSFET products are shown in the Drain-Source On Current vs
Drain-Source On Voltage and Drain-Source On Current vs GateSource Voltage graphs. Each graph shows the Drain-Source On
Current versus Drain-Source On Voltage characteristics as a function of Gate-Source voltage in a different operating region under
different bias conditions. As the threshold voltage is tightly specified, the Drain-Source On Current at a given gate input voltage is
better controlled and more predictable when compared to many
other types of MOSFETs.
EPAD MOSFETs behave similarly to a standard MOSFET, therefore classic equations for a n-channel MOSFET applies to EPAD
MOSFET as well. The Drain current in the linear region (VDS <
VGS - VGS(th)) is given by:
IDS = u . COX . W/L . [VGS - VGS(th) - VDS/2] . VDS
where:
u = Mobility
COX = Capacitance / unit area of Gate electrode
VGS = Gate to Source voltage
VGS(th) = Turn-on threshold voltage
VDS = Drain to Source voltage
W = Channel width
L = Channel length
In this region of operation the IDS value is proportional to VDS value
and the device can be used as a gate-voltage controlled resistor.
For higher values of VDS where VDS >= VGS - VGS(th), the saturation current IDS is now given by (approx.):
IDS = u . COX . W/L . [VGS - VGS(th)]2
Advanced Linear Devices
3 of 12
PERFORMANCE CHARACTERISTICS OF EPAD®
PRECISION MATCHED PAIR MOSFET FAMILY (cont.)
SUB-THRESHOLD REGION OF OPERATION
ZERO TEMPERATURE COEFFICIENT (ZTC) OPERATION
Low voltage systems, namely those operating at 5V, 3.3V or less,
typically require MOSFETs that have threshold voltage of 1V or
less. The threshold, or turn-on, voltage of the MOSFET is a voltage
below which the MOSFET conduction channel rapidly turns off. For
analog designs, this threshold voltage directly affects the operating
signal voltage range and the operating bias current levels.
For an EPAD MOSFET in this product family, there exist operating
points where the various factors that cause the current to increase
as a function of temperature balance out those that cause the current to decrease, thereby canceling each other, and resulting in net
temperature coefficient of near zero. One of these temperature
stable operating points is obtained by a ZTC voltage bias condition, which is 0.55V above a threshold voltage when VGS = VDS,
resulting in a temperature stable current level of about 68µA. For
other ZTC operating points, see ZTC characteristics.
At or below threshold voltage, an EPAD MOSFET exhibits a turnoff characteristic in an operating region called the subthreshold region. This is when the EPAD MOSFET conduction channel rapidly
turns off as a function of decreasing applied gate voltage. The conduction channel induced by the gate voltage on the gate electrode
decreases exponentially and causes the drain current to decrease
exponentially. However, the conduction channel does not shut off
abruptly with decreasing gate voltage. Rather, it decreases at a
fixed rate of approximately 116mV per decade of drain current decrease. Thus, if the threshold voltage is +0.20V, for example, the
drain current is 1µA at VGS = +0.20V. At VGS = +0.09V, the drain
current would decrease to 0.1µA. Extrapolating from this, the drain
current is 0.01µA (10nA) at VGS = -0.03V, 1nA at VGS = -0.14V,
and so forth. This subthreshold characteristic extends all the way
down to current levels below 1nA and is limited by other currents
such as junction leakage currents.
PERFORMANCE CHARACTERISTICS
Performance characteristics of the EPAD MOSFET product family
are shown in the following graphs. In general, the threshold voltage
shift for each member of the product family causes other affected
electrical characteristics to shift with an equivalent linear shift in
VGS(th) bias voltage. This linear shift in VGS causes the subthreshold I-V curves to shift linearly as well. Accordingly, the subthreshold
operating current can be determined by calculating the gate voltage drop relative to its threshold voltage, VGS(th).
RDS(ON) AT VGS = GROUND
At a drain current to be declared “zero current” by the user, the
VGS voltage at that zero current can now be estimated. Note that
using the above example, with VGS(th) = +0.20V, the drain current
still hovers around 20nA when the gate is at zero volts, or ground.
LOW POWER AND NANOPOWER
When supply voltages decrease, the power consumption of a given
load resistor decreases as the square of the supply voltage. So
one of the benefits in reducing supply voltage is to reduce power
consumption. While decreasing power supply voltages and power
consumption go hand-in-hand with decreasing useful AC bandwidth
and at the same time increases noise effects in the circuit, a circuit
designer can make the necessary tradeoffs and adjustments in any
given circuit design and bias the circuit accordingly.
With EPAD MOSFETs, a circuit that performs a specific function
can be designed so that power consumption can be minimized. In
some cases, these circuits operate in low power mode where the
power consumed is measure in micro-watts. In other cases, power
dissipation can be reduced to the nano-watt region and still provide
a useful and controlled circuit function operation.
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
Several of the EPAD MOSFETs produce a fixed resistance when
their gate is grounded. For ALD110800, the drain current is 1µA at
VDS = 0.1V and VGS = 0.0V. Thus, just by grounding the gate of
the ALD110800, a resistor with RDS(ON) = ~100KΩ is produced.
When an ALD114804 gate is grounded, the drain current IDS =
18.5µA @ VDS = 0.1V, producing RDS(ON) = 5.4KΩ. Similarly,
ALD114813 and ALD114835 produce drain currents of 77µA and
185µA, respectively, at VGS = 0.0V, and RDS(ON) values of 1.3KΩ
and 540Ω, respectively.
MATCHING CHARACTERISTICS
A key benefit of using a matched pair EPAD MOSFET is to maintain temperature tracking. In general, for EPAD MOSFET matched
pair devices, one device of the matched pair has gate leakage currents, junction temperature effects, and drain current temperature
coefficient as a function of bias voltage that cancel out similar effects of the other device, resulting in a temperature stable circuit.
As mentioned earlier, this temperature stability can be further enhanced by biasing the matched-pairs at Zero Tempco (ZTC) point,
even though that could require special circuit configuration and
power consumption design consideration.
Advanced Linear Devices
4 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT CHARACTERISTICS
DRAIN-SOURCE ON RESISTANCE
vs. DRAIN-SOURCE ON CURRENT
TA = +25°C
VGS - VGS(th) = +5V
4
VGS - VGS(th) = +4V
3
VGS - VGS(th) = +3V
2
VGS - VGS(th) = +2V
1
VGS - VGS(th) = +1V
0
0
2
4
6
8
2500
DRAIN-SOURCE ON RESISTANCE
(Ω)
DRAIN-SOURCE ON CURRENT
(mA)
5
TA = +25°C
2000
1500
VGS = VGS(th) + 4V
1000
500
VGS = VGS(th) + 6V
0
10
100
10
DRAIN-SOURCE ON VOLTAGE (V)
2.5
20
VGS(th) = -3.5V
TA = +25°C
VDS = +10V
15
TRANSCONDUCTANCE
( m A/V)
DRAIN-SOURCE ON CURRENT
(mA)
10000
TRANSCONDUCTANCE vs.
AMBIENT TEMPERATURE
FORWARD TRANSFER CHARACTERISTICS
VGS(th) = -1.3V
VGS(th) = -0.4V
10
VGS(th) = 0.0V
VGS(th) = +0.2V
5
VGS(th) = +0.8V
2.0
1.5
1.0
0.5
VGS(th) = +1.4V
0
-4
-2
0
2
6
4
0
-50
10
8
-25
DRAIN-SOURCE ON CURRENT
(nA)
100000
TA = +25°C
VDS = +0.1V
VGS
(th) = +1.4V
VGS
(th) = +0.8V
VGS
(th) = +0.2V
VGS
(th) = 0.0V
1
VGS
(th) = -0.4V
10
VGS
(th) = -1.3V
VGS
(th) = -3.5V
1000
100
25
50
75
100
125
SUBTHRESHOLD FORWARD TRANSFER
CHARACTERISTICS
SUBTHRESHOLD FORWARD TRANSFER
CHARACTERISTICS
10000
0
AMBIENT TEMPERATURE (°C)
GATE-SOURCE VOLTAGE (V)
DRAIN-SOURCE ON CURRENT
(nA)
1000
DRAIN-SOURCE ON CURRENT (µA)
0.1
10000
0.01
1000
100
VDS = +0.1V
~ 110mV/decade
Slope =
10
1
0.1
0.01
-4
-3
-2
-1
0
1
2
GATE-SOURCE VOLTAGE (V)
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
VGS(th)-0.5
VGS(th)-0.4
VGS(th)-0.3
VGS(th)-0.2
VGS(th)-0.1
VGS(th)
GATE-SOURCE VOLTAGE (V)
Advanced Linear Devices
5 of 12
TYPICAL PERFORMANCE CHARACTERISTICS (cont.)
DRAIN-SOURCE ON CURRENT, BIAS
CURRENT vs. AMBIENT TEMPERATURE
DRAIN-SOURCE ON CURRENT, BIAS
CURRENT vs. AMBIENT TEMPERATURE
100
-55°C
4
-25°C
3
0°C
2
1
+70°C
0
VGS(th)-1
VGS(th)
VGS(th)+1
+125°C
+125°C
50
-25°C
0
VGS(th)+3 VGS(th)+4
VGS(th)+2
VGS(th)
VGS(th)+0.2
VGS(th)+0.6
VGS(th)+0.8
GATE- AND DRAIN-SOURCE VOLTAGE
(VGS = VDS) (V)
DRAIN-SOURCE ON CURRENT vs.
DRAIN-SOURCE ON RESISTANCE
GATE-SOURCE VOLTAGE vs.
DRAIN-SOURCE ON CURRENT
VGS(th)+1.0
1000
100
VDS = +10V
10
VDS = +0.1V
1
VDS = +5V
VDS = +1V
0.1
GATE-SOURCE VOLTAGE (V)
VGS(th)+4
TA = +25°C
VGS = -4.0V to +5.4V
10000
VDS = RON • IDS(ON)
VGS(th)+3
D
VGS(th)+2
VDS
VGS
VDS = +0.5V
TA = +125°C
VDS = +0.5V
TA = +25°C
IDS(ON)
S
VDS = +5V
TA = +125°C
VGS(th)+1
VDS = +5V
TA = +25°C
VGS(th)
VGS(th)-1
0.01
0.1
1
10
100
1000
1
0.1
10000
10
100
1000
10000
DRAIN-SOURCE ON CURRENT (µA)
DRAIN-SOURCE ON RESISTANCE (KΩ)
OFFSET VOLTAGE vs.
AMBIENT TEMPERATURE
DRAIN-SOURCE ON CURRENT
vs. OUTPUT VOLTAGE
5
4
3
VDS = +10V
4
TA = +25°C
3
VDS = +5V
2
1
OFFSET VOLTAGE
(mV)
DRAIN-SOURCE ON CURRENT
(mA)
VGS(th)+0.4
GATE- AND DRAIN-SOURCE VOLTAGE
(VGS = VDS) (V)
100000
DRAIN-SOURCE ON CURRENT
(µA)
Zero Temperature
Coefficient (ZTC)
DRAIN-SOURCE ON CURRENT
(µA)
DRAIN-SOURCE ON CURRENT
(mA)
5
REPRESENTATIVE UNITS
2
1
0
-1
-2
VDS = +1V
-3
0
-4
VGS(th)
VGS(th)+1
VGS(th)+2
VGS(th)+3
VGS(th)+4 VGS(th)+5
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
-50
Advanced Linear Devices
6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS (cont.)
GATE SOURCE VOLTAGE vs.
DRAIN-SOURCE ON RESISTANCE
GATE LEAKAGE CURRENT
vs. AMBIENT TEMPERATURE
VGS(th)+4
GATE-SOURCE VOLTAGE (V)
GATE LEAKAGE CURRENT
(pA)
10000
1000
100
10
1
IGSS
0.1
0.0V ≤ VDS ≤ 5.0V
VGS(th)+3
+125°C
D
VGS(th)+2
-50
S
VGS(th)+1
-25
0
25
50
75
100
0
125
2
4
6
8
DRAIN-GATE DIODE CONNECTED VOLTAGE
TEMPCO vs. DRAIN-SOURCE ON CURRENT
TRANSFER CHARACTERISTICS
1.6
5
TRANSCONDUCTANCE
(mΩ-1)
-55°C ≤ TA ≤ +125°C
2.5
0
-2.5
VGS(th) = -3.5V
TA = +25°C
VDS = +10V
VGS(th) = -1.3V
1.2
VGS(th) = -0.4V
0.8
VGS(th) = 0.0V
VGS(th) = +0.2V
0.4
VGS(th) = +0.8V
VGS(th) = +1.4V
0.0
-5
1
100
10
10
DRAIN-SOURCE ON RESISTANCE (KΩ)
AMBIENT TEMPERATURE (°C)
DRAIN-GATE DIODE CONNECTED
VOLTAGE TEMPCO (mV/°C)
IDS(ON)
VGS
+25°C
VGS(th)
0.01
1000
-4
2
0
-2
4
6
8
DRAIN-SOURCE ON CURRENT (µA)
GATE-SOURCE VOLTAGE (V)
ZERO TEMPERATURE
COEFFICIENT CHARACTERISTICS
SUBTHRESHOLD CHARACTERISTICS
0.6
10
2.5
VGS(th) = -3.5V
GATE-SOURCE VOLTAGE
(V)
GATE-SOURCE VOLTAGE
(V)
VDS
0.5
VGS(th) = -1.3V, -0.4V, 0.0V, +0.2V, +0.8V, +1.4V
0.3
0.2
0.0
2.0
1.5
0.2
0.5
1.0
2.0
5.0
DRAIN-SOURCE ON VOLTAGE (V)
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
Advanced Linear Devices
VGS(th) = +0.4V
TA = +55°C
0.5
0.0
-0.5
0.1
VGS(th) = +0.4V
TA = +25°C
1.0
VGS(th) = +0.2V
TA = +25°C
100000 10000
VGS(th) = +0.2V
TA = +55°C
1000
100
10
1
0.1
DRAIN-SOURCE ON CURRENT (nA)
7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS (cont.)
THRESHOLD VOLTAGE vs.
AMBIENT TEMPERATURE
TRANCONDUCTANCE vs.
DRAIN-SOURCE ON CURRENT
4.0
TA = +25°C
VDS = +10V
THRESHOLD VOTAGE
(V)
TARNCONDUCTANCE
(mΩ-1)
1.2
0.9
0.6
0.3
IDS = +1µA
VDS = +0.1V
3.0
2.0
Vt = +1.4V
1.0
Vt = 0.0V
Vt = +0.8V
Vt = +0.2V
Vt = +0.4V
0.0
0.0
0
2
4
6
8
-50
10
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
NORMALIZED SUBTHRESHOLD
CHARACTERISTICS RELATIVE TO
GATE THRESHOLD VOLTAGE
SUBTHRESHOLD FORWARD
TRANSFER CHARACTERISTICS
125
2.0
0.3
0.2
THRESHOLD VOLTAGE
(V)
GATE-SOURCE VOLTAGE
VGS - VGS(th) (V)
-25
DRAIN-SOURCE ON CURRENT (mA)
VDS = +0.1V
0.1
0
-0.1
+25°C
-0.2
+55°C
-0.3
IDS = +1µA
VDS = +0.1V
1.0
VGS(th) = 0.0V
0.0
VGS(th) = -0.4V
-1.0
VGS(th) = -1.3V
-2.0
-3.0
VGS(th) = -3.5V
-4.0
-0.4
10000
1000
100
10
1
0.1
DRAIN-SOURCE ON CURRENT (nA)
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
Advanced Linear Devices
-25
25
75
125
AMBIENT TEMPERATURE (°C)
8 of 12
SOIC-16 PACKAGE DRAWING
16 Pin Plastic SOIC Package
E
Millimeters
S (45°)
D
Dim
Min
A
1.35
Max
1.75
Min
0.053
Max
0.069
A1
0.10
0.25
0.004
0.010
b
0.35
0.45
0.014
0.018
C
0.18
0.25
0.007
0.010
D-16
9.80
10.00
0.385
0.394
E
3.50
4.05
0.140
0.160
1.27 BSC
e
A
A1
e
Inches
0.050 BSC
H
5.70
6.30
0.224
0.248
L
0.60
0.937
0.024
0.037
ø
0°
8°
0°
8°
S
0.25
0.50
0.010
0.020
b
S (45°)
H
L
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
C
ø
Advanced Linear Devices
9 of 12
PDIP-16 PACKAGE DRAWING
16 Pin Plastic DIP Package
E
E1
Millimeters
Dim
D
S
A2
A1
e
b
A
L
Inches
A
Min
3.81
Max
5.08
Min
0.105
Max
0.200
A1
0.38
1.27
0.015
0.050
A2
1.27
2.03
0.050
0.080
b
0.89
1.65
0.035
0.065
b1
0.38
0.51
0.015
0.020
c
0.20
0.30
0.008
0.012
D-16
18.93
21.33
0.745
0.840
E
5.59
7.11
0.220
0.280
E1
7.62
8.26
0.300
0.325
e
2.29
2.79
0.090
0.110
e1
L
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
S-16
0.38
1.52
0.015
0.060
ø
0°
15°
0°
15°
b1
c
e1
ø
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
Advanced Linear Devices
10 of 12
SOIC-8 PACKAGE DRAWING
8 Pin Plastic SOIC Package
E
Millimeters
Dim
S (45°)
D
A
Min
1.35
Max
1.75
Min
0.053
Max
0.069
A1
0.10
0.25
0.004
0.010
b
0.35
0.45
0.014
0.018
C
0.18
0.25
0.007
0.010
D-8
4.69
5.00
0.185
0.196
E
3.50
4.05
0.140
0.160
1.27 BSC
e
A
A1
e
b
Inches
0.050 BSC
H
5.70
6.30
0.224
0.248
L
0.60
0.937
0.024
0.037
ø
0°
8°
0°
8°
S
0.25
0.50
0.010
0.020
S (45°)
H
L
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
C
ø
Advanced Linear Devices
11 of 12
PDIP-8 PACKAGE DRAWING
8 Pin Plastic DIP Package
E
E1
Millimeters
D
S
A2
A1
e
b
b1
A
L
Inches
Dim
Min
Max
Min
Max
A
3.81
5.08
0.105
0.200
A1
0.38
1.27
0.015
0.050
A2
1.27
2.03
0.050
0.080
b
0.89
1.65
0.035
0.065
b1
0.38
0.51
0.015
0.020
c
0.20
0.30
0.008
0.012
D-8
9.40
11.68
0.370
0.460
E
5.59
7.11
0.220
0.280
E1
7.62
8.26
0.300
0.325
e
2.29
2.79
0.090
0.110
e1
L
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
S-8
1.02
2.03
0.040
0.080
0°
15°
0°
15°
ø
c
e1
ø
ALD110800A/ALD110800/
ALD110900A/ALD110900, Vers. 2.4
Advanced Linear Devices
12 of 12