PRELIMINARY Am186TMES/ESLV and Am188TM ES/ESLV High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers DISTINCTIVE CHARACTERISTICS n E86 family 80C186-/188- and 80L186-/188compatible microcontrollers with enhanced bus interface — Lower system cost with higher performance — 3.3-V ±0.3-V operation (Am186ESLV and Am188ESLV microcontrollers) n High performance — 20-, 25-, 33-, and 40-MHz operating frequencies — Supports zero-wait-state operation at 25 MHz with 100-ns static memory (Am186ESLV and Am188ESLV microcontrollers) and 40 MHz with 70-ns static memory (Am186ES and Am188ES microcontrollers) — 1-Mbyte memory address space — 64-Kbyte I/O space n Enhanced features provide improved memory access and remove the requirement for a 2x clock input — Nonmultiplexed address bus — Processor operates at the clock input frequency — On the Am186ES/ESLV microcontroller, 8-bit or 16-bit memory and I/O static bus option n Enhanced integrated peripherals provide increased functionality, while reducing system cost — Thirty-two programmable I/O (PIO) pins — Two full-featured asynchronous serial ports allow full-duplex, 7-bit, 8-bit, or 9-bit data transfers — Serial port hardware handshaking with CTS, RTS, ENRX, and RTR selectable for each port — — — — — — Multidrop 9-bit serial port protocol Independent serial port baud rate generators DMA to and from the serial ports Watchdog timer can generate NMI or reset A pulse-width demodulation option A data strobe, true asynchronous bus interface option included for DEN — Pseudo static RAM (PSRAM) controller includes auto refresh capability — Reset configuration register n Familiar 80C186/80L186 peripherals — Two independent DMA channels — Programmable interrupt controller with up to eight external and eight internal interrupts — Three programmable 16-bit timers — Programmable memory and peripheral chip-select logic — Programmable wait state generator — Power-save clock divider n Software-compatible with the 80C186/80L186 and 80C188/80L188 microcontrollers with widely available native development tools, applications, and system software n A compatible evolution of the Am186EM and Am188EM microcontrollers n Available in the following packages: — 100-pin, thin quad flat pack (TQFP) — 100-pin, plastic quad flat pack (PQFP) GENERAL DESCRIPTION T h e A m 1 8 6 ES/ESLV and Am188ES /ESLV microcontrollers are an ideal upgrade for 80C186/188 and 80L186/188 microcontroller designs requiring 80C186/188 and 80L186/188 compatibility, increased performance, serial communications, and a direct bus interface. The Am186ES/ESLV and Am188ES/ESLV microcontrollers ar e p ar t o f th e A MD E 8 6 fa mi l y o f em be dd e d microcontrollers and microprocessors based on the x86 architecture. The E86 family includes the 16- and 32-bit microcontrollers and microprocessors described on page 8. The Am186ES/ESLV and Am188ES/ESLV microcontrollers have been designed to meet the most c om mo n r eq ui r e me nt s of e mb ed de d pr o du c ts developed for the office automation, mass storage, and communications markets. Specific applications include disk drives, hand-held and desktop terminals, set-top controllers, fax machines, printers, photocopiers, feature phones, cellular phones, PBXs, multiplexers, modems, and industrial controls. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 20002 Rev: B Amendment/0 Issue Date: February 1997 P R E L I M I N A R Y Am186ES MICROCONTROLLER BLOCK DIAGRAM INT2/INTA0** INT3/INTA1/IRQ CLKOUTA INT1/SELECT TMROUT0 TMROUT1 PWD** TMRIN0 TMRIN1 DRQ0** NMI INT6–INT4** INT0 CLKOUTB X2 X1 VCC GND Clock and Power Management Unit Interrupt Control Unit Watchdog Timer (WDT) Control Registers Pulse Width Demodulator (PWD) DMA Unit 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers Control Registers Timer Control Unit 0 1 2 Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers RES ARDY DRQ1** Control Registers SRDY Refresh Control Unit PSRAM Control Unit Control Registers S2–S0 DT/R Bus Interface Unit DEN/DS HOLD HLDA S6/LOCK/ CLKDIV2 UZI PIO Unit Control Registers Asynchronous Serial Port 0 TXD0 RXD0 RTS0/RTR0 CTS0/ENRX0 Asynchronous Serial Port 1 TXD1 RXD1 RTS1/RTR1** CTS1/ENRX1** Chip-Select Unit Execution Unit PIO31– PIO0* RD WHB A19–A0 WLB AD15–AD0 LCS/ONCE0 PCS6/A2 PCS5/A1 MCS3/RFSH MCS2–MCS0 WR BHE/ADEN PCS3–PCS0** UCS/ONCE1 ALE Notes: *All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 27 and Table 2 on page 34 for information on shared functions. ** PWD, INT5, INT6, RTS1/RTR1, and CTS1/ENRX1 are multiplexed with INT2/INTA0, DRQ0, DRQ1, PCS3, and PCS2 respectively. See the pin descriptions beginning on page 27. 2 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Am188ES MICROCONTROLLER BLOCK DIAGRAM INT2/INTA0** INT3/INTA1/IRQ INT1/SELECT CLKOUTA TMROUT0 TMROUT1 PWD** TMRIN0 TMRIN1 DRQ0** NMI INT6–INT4** INT0 CLKOUTB X2 X1 Clock and Power Management Unit VCC GND Interrupt Control Unit Watchdog Timer (WDT) Control Registers Pulse Width Demodulator (PWD) DMA Unit 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers Control Registers Timer Control Unit 0 1 2 Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers DRQ1** RES Control Registers Refresh Control Unit ARDY SRDY PSRAM Control Unit Control Registers S2–S0 DT/R Bus Interface Unit DEN/DS HOLD HLDA S6/LOCK/ CLKDIV2 UZI PIO Unit Control Registers Asynchronous Serial Port 0 TXD0 RXD0 RTS0/RTR0 CTS0/ENRX0 Asynchronous Serial Port 1 TXD1 RXD1 RTS1/RTR1** CTS1/ENRX1** Chip-Select Unit Execution Unit PIO31– PIO0* RD WB LCS/ONCE0 PCS6/A2 A19–A0 PCS5/A1 MCS3/RFSH AO15–AO8 WR AD7–AD0 RFSH2/ADEN MCS2–MCS0 PCS3–PCS0** UCS/ONCE1 ALE Notes: *All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 27 and Table 2 on page 34 for information on shared functions. ** PWD, INT5, INT6, RTS1/RTR1, and CTS1/ENRX1 are multiplexed with INT2/INTA0, DRQ0, DRQ1, PCS3, and PCS2 respectively. See the pin descriptions beginning on page 27. Am186/188ES and Am186/188ESLV Microcontrollers 3 P R E L I M I N A R Y ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. Am186ES -40 V C \W LEAD FORMING \W=Trimmed and Formed TEMPERATURE RANGE C=ES Commercial (TC =0°C to +100°C) C=ESLV Commercial (TA =0°C to +70°C) I=ES Industrial (TA =–40°C to +85°C) where: TC = case temperature TA = ambient temperature PACKAGE TYPE V=100-Pin Thin Quad Flat Pack (TQFP) K=100-Pin Plastic Quad Flat Pack (PQFP) SPEED OPTION –20 = 20 MHz –25 = 25 MHz –33 = 33 MHz –40 = 40 MHz DEVICE NUMBER/DESCRIPTION Am186ES High-Performance, 80C186-Compatible, 16-Bit Embedded Microcontroller Am188ES High-Performance, 80C188-Compatible, 16-Bit Embedded Microcontroller Am186ESLV High-Performance, 80L186-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller Am188ESLV High-Performance, 80L188-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller Valid Combinations 4 Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am186ES–20 Am186ES–25 Am186ES–33 Am186ES–40 VC\W or KC\W Am188ES–20 Am188ES–25 Am188ES–33 Am188ES–40 VC\W or KC\W Note: The industrial version of the Am186ES and Am188ES microcontrollers, as well as the Am186ESLV and Am188ESLV, are available in 20 and 25 MHz operating frequencies only. Am186ES–20 Am186ES–25 KI\W Am188ES–20 Am188ES–25 KI\W The Am186ES, Am188ES, Am186ESLV, and Am188ESLV microcontrollers are all functionally the same except for their DC characteristics and available frequencies. Am186ESLV–20 Am186ESLV–25 VC\W or KC\W Am188ESLV–20 Am188ESLV–25 VC\W or KC\W Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 1 Am186ES Microcontroller Block Diagram..................................................................................... 2 Am188ES Microcontroller Block Diagram..................................................................................... 3 Ordering Information .................................................................................................................... 4 Related AMD Products ................................................................................................................ 8 Key Features and Benefits ........................................................................................................ 10 Comparing the ES to the 80C186 .............................................................................................. 11 Comparing the ES to the EM ..................................................................................................... 11 TQFP Connection Diagrams and Pinouts .................................................................................. 13 PQFP Connection Diagrams and Pinouts ................................................................................. 19 Logic Symbol—Am186ES Microcontroller ................................................................................. 25 Logic Symbol—Am188ES Microcontroller ................................................................................. 26 Pin Descriptions ......................................................................................................................... 27 Pins That Are Used by Emulators .................................................................................. 27 Pin Terminology ............................................................................................................. 27 A19–A0 .......................................................................................................................... 27 AD15–AD8 (Am186ES Microcontroller) .......................................................................... 27 AO15–AO8 (Am188ES Microcontroller) ........................................................................ 27 AD7–AD0 ....................................................................................................................... 27 ALE ................................................................................................................................ 27 ARDY ............................................................................................................................. 27 BHE/ADEN (Am186ES Microcontroller Only) ................................................................ 28 CLKOUTA ...................................................................................................................... 28 CLKOUTB ...................................................................................................................... 28 CTS0/ENRX0/PIO21 ...................................................................................................... 28 DEN/DS/PIO5 ................................................................................................................ 29 DRQ0/INT5/PIO12 ......................................................................................................... 29 DRQ1/INT6/PIO13 ......................................................................................................... 29 DT/R/PIO4 ..................................................................................................................... 29 GND ............................................................................................................................... 29 HLDA ............................................................................................................................. 29 HOLD ............................................................................................................................. 29 INT0 ............................................................................................................................... 30 INT1/SELECT ................................................................................................................ 30 INT2/INTA0/PWD/PIO31 ............................................................................................... 30 INT3/INTA1/IRQ ............................................................................................................. 30 INT4/PIO30 .................................................................................................................... 31 LCS/ONCE0 ................................................................................................................... 31 MCS0 (MCS0/PIO14) .................................................................................................... 31 MCS2–MCS1 (MCS2/PIO24, MCS1/PIO15) ................................................................. 31 MCS3/RFSH/PIO25 ....................................................................................................... 31 NMI ................................................................................................................................ 32 PCS1–PCS0 (PCS1/PIO17, PCS0/PIO16) .................................................................... 32 PCS2/CTS1/ENRX1/PIO18 ........................................................................................... 32 PCS3/RTS1/RTR1/PIO19 .............................................................................................. 32 PCS5/A1/PIO3 ............................................................................................................... 33 PCS6/A2/PIO2 ............................................................................................................... 33 PIO31–PIO0 (Shared) .................................................................................................... 33 RD .................................................................................................................................. 35 RES ................................................................................................................................ 35 RFSH2/ADEN (Am188ES Microcontroller Only) ............................................................ 35 Am186/188ES and Am186/188ESLV Microcontrollers 5 P R E L I M I N A R Y RTS0/RTR0/PIO20 ........................................................................................................ 35 RXD0/PIO23 .................................................................................................................. 35 RXD1/PIO28 .................................................................................................................. 35 S2–S0 ............................................................................................................................ 35 S6/LOCK/CLKDIV2/PIO29 ............................................................................................. 36 SRDY/PIO6 .................................................................................................................... 36 TMRIN0/PIO11 .............................................................................................................. 36 TMRIN1/PIO0 ................................................................................................................ 36 TMROUT0/PIO10 .......................................................................................................... 36 TMROUT1/PIO1 ............................................................................................................ 36 TXD0/PIO22 ................................................................................................................... 36 TXD1/PIO27 ................................................................................................................... 36 UCS/ONCE1 .................................................................................................................. 36 UZI/PIO26 ...................................................................................................................... 37 VCC ................................................................................................................................ 37 WHB (Am186ES Microcontroller Only) .......................................................................... 37 WLB (Am186ES Microcontroller Only) ........................................................................... 37 WB (Am188ES Microcontroller Only) ............................................................................. 37 WR ................................................................................................................................. 37 X1 ................................................................................................................................... 37 X2 ................................................................................................................................... 37 Functional Description ................................................................................................................ 38 Bus Operation ............................................................................................................................ 39 Bus Interface Unit ...................................................................................................................... 41 Peripheral Control Block (PCB) ................................................................................................. 42 Clock and Power Management .................................................................................................. 44 Chip-Select Unit ......................................................................................................................... 46 Refresh Control Unit .................................................................................................................. 47 Interrupt Control Unit ................................................................................................................. 48 Timer Control Unit ...................................................................................................................... 48 Direct Memory Access (DMA) ................................................................................................... 49 Pulse Width Demodulation ........................................................................................................ 51 Asynchronous Serial Ports ........................................................................................................ 51 Programmable I/O (PIO) Pins .................................................................................................... 52 Absolute Maximum Ratings ....................................................................................................... 53 Operating Ranges ...................................................................................................................... 53 DC Characteristics Over Commercial Operating Ranges .......................................................... 53 Commercial Switching Characteristics and Waveforms ............................................................ 61 TQFP Physical Dimensions ........................................................................................................ 98 PQFP Physical Dimensions ...................................................................................................... 100 6 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Am186ES Microcontroller Example System Design .............................................. 10 80C186 Microcontroller Example System Design ................................................. 11 Two-Component Address ...................................................................................... 38 Am186ES Microcontroller Address Bus — Normal Operation................................ 39 Am186ES Microcontroller—Address Bus Disable In Effect ................................... 40 Am188ES Microcontroller Address Bus — Normal Operation ............................... 40 Am188ES Microcontroller— Address Bus Disable In Effect................................... 41 Am186ES and Am188ES Microcontrollers Oscillator Configurations .................... 44 Clock Organization ................................................................................................ 45 DMA Unit Block Diagram ....................................................................................... 50 Typical Icc Versus Frequency for the Am186ESLV and Am188ESLV ................... 54 Typical Icc Versus Frequency for the Am186ES and Am188ES............................. 54 Thermal Resistance(°C/Watt) ................................................................................ 55 Thermal Characteristics Equations ........................................................................ 55 Typical Ambient Temperatures for PQFP with a 2-Layer Board ............................ 57 Typical Ambient Temperatures for TQFP with a 2-Layer Board ............................ 58 Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board .......... 59 Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board ........... 60 LIST OF TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Data Byte Encoding ............................................................................................... 28 Numeric PIO Pin Designations .............................................................................. 34 Alphabetic PIO Pin Designations ........................................................................... 34 Bus Cycle Encoding ............................................................................................... 35 Segment Register Selection Rules ........................................................................ 38 Programming Am186ES Microcontroller Bus Width .............................................. 42 Peripheral Control Block Register Map .................................................................. 43 Am186ES Microcontroller Maximum DMA Transfer Rates .................................... 49 Typical Power Consumption for the Am186ESLV and Am188ESLV...................... 54 Thermal Characteristics (°C/Watt) ......................................................................... 55 Typical Power Consumption Calculation ............................................................... 56 Junction Temperature Calculation ......................................................................... 56 Typical Ambient Temperatures for PQFP with a 2-Layer Board ............................ 57 Typical Ambient Temperatures for TQFP with a 2-Layer Board ............................ 58 Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board .......... 59 Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board ........... 60 Am186/188ES and Am186/188ESLV Microcontrollers 7 P R E L I M I N A R Y K86™ Future Microprocessors AMD-K5™ Microprocessor AT Peripheral Microcontrollers Am486DX Microprocessor 186 Peripheral Microcontrollers 32-bit Future ÉlanSC400 Microcontroller Am386SX/DX Microprocessors Am186ER and Am188ER Microcontrollers ÉlanSC310 Microcontroller Am186 and Am188 Future Am186ES and Am188ES Microcontrollers ÉlanSC300 Microcontroller 80C186 and 80C188 Microcontrollers Am486 Future Am186EM and Am188EM Microcontrollers Am186ESLV & Am188ESLV Microcontrollers Am186EMLV & Am188EMLV Microcontrollers 80L186 and 80L188 Microcontrollers Time The E86 Family of Embedded Microprocessors and Microcontrollers RELATED AMD PRODUCTS E86 Family Devices Device 80C186 80C188 80L186 80L188 Am186EM Am188EM Am186EMLV Am188EMLV Description 16-bit microcontroller 16-bit microcontroller with 8-bit external data bus Low-voltage, 16-bit microcontroller Low-voltage, 16-bit microcontroller with 8-bit external data bus High-performance, 80C186-compatible, 16-bit embedded microcontroller High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ES High-performance, 80C186-compatible, 16-bit embedded microcontroller Am188ES High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal RAM Am188ER High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 Kbyte of internal RAM Élan™SC300 ÉlanSC310 ÉlanSC400 Am386®DX Am386®SX Am486®DX 8 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller High-performance, single-chip, 32-bit embedded PC/AT microcontroller Single-chip, low-power, PC/AT-compatible microcontroller High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 16-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Related Documents Corporate Applications Hotline The following documents provide additional information regarding the Am186ES and Am188ES microcontrollers: (800) 222-9323 Toll-free for U.S. and Canada 44-(0) 1276-803-299 U.K. and Europe hotline n The Am186ES and Am188ES Microcontrollers User’s Manual, order# 21096 World Wide Web Home Page and FTP Site n The FusionE86 SM Catalog, order# 19255 Third-Party Development Support Products The FusionE86 S M Program of Partnerships for Application Solutions provides the customer with an array of products designed to meet critical time-tomarket needs. Products and solutions available from the AMD FusionE86 partners include emulators, hardware and software debuggers, board-level products, and software development tools, among others. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. Customer Service The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff who can answer E86 family hardware and software development questions. Hotline and World Wide Web Support To a c c e s s t h e A M D h o m e pa g e g o t o h tt p : / / www.amd.com. To downl oad d ocu ments and s oftwar e, ftp t o ftp.amd.com and log on as anonymous using your E-mail address as a password. Or via your web browser, go to ftp://ftp.amd.com. Questions, requests, and input concerning AMD’s WWW pages can be sent via E-mail to [email protected]. Documentation and Literature Free E86 family information such as data books, user’s man ual s , data sh eets , ap pl ic ati on n otes , th e FusionE86 Partner Solutions Catalog, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for complete E86 family literature. Literature Ordering (800) 222-9323 Toll-free for U.S. and Canada (512) 602-5651 Direct dial worldwide (800) 222-9323 AMD Facts-On-Demand™ fax information service, toll-free for U.S. and Canada For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information, including technical information and data on upcoming product releases. For technical support questions on all E86 products, send E-mail to [email protected]. Am186/188ES and Am186/188ESLV Microcontrollers 9 P R E L I M I N A R Y KEY FEATURES AND BENEFITS The Am186ES and Am188ES microcontrollers extend the AMD family of microcontrollers based on the industry-standard x86 architecture. The Am186ES and Am188ES microcontrollers are higher-performance, mo r e i n te g r a te d v e r s i on s of t he 8 0 C1 8 6/ 1 88 microprocessors, offering an attractive migration path. In addition, the Am186ES and Am188ES microcontrollers offer application-specific features that can enhance the system functionality of the Am186EM and Am188EM microcontrollers. Upgrading to the Am186ES and Am188ES microcontrollers is an attractive solution for several reasons: n Minimized total system cost—New peripherals and on-chip system interface logic on the Am186ES and Am188ES microcontrollers reduce the cost of existing 80C186/188 designs. n x86 software compatibility—80C186/188-compatible and upward-compatible with the other members of the AMD E86 family. The x86 architecture is the most widely used and supported computer architecture in the world. n Enhanced performance—The Am186ES and Am188ES microcontrollers increase the performance of 80C186/188 systems, and the nonmultiplexed address bus offers faster, unbuffered access to memory. n Enhanced functionality—The new and enhanced on-chip peripherals of the Am186ES and Am188ES microcontrollers include two asynchronous serial ports, 32 PIOs, a watchdog timer, additional interrupt pins, a pulse width demodulation option, DMA directly to and from the serial ports, 8-bit and 16-bit static bus sizing, a PSRAM controller, a 16-bit reset configuration register, and enhanced chip-select functionality. Application Considerations The integration enhancements of the Am186ES and Am188ES microcontrollers provide a highperformance, low-system-cost solution for 16-bit embedded microcontroller designs. The nonmultiplexed address bus eliminates the need for system-support logic to interface memory devices, while the multiplexed address/data bus maintains the value of previously engineered, customer-specific peripherals and circuits within the upgraded design. Figure 1 illustrates an example system design that uses the integrated peripheral set to achieve high performance with reduced system cost. Clock Generation The integrated clock generation circuitry of the Am186ES and Am188ES microcontrollers allows the use of a times-one crystal frequency. The design 10 shown in Figure 1 achieves 40-MHz CPU operation, while using a 40-MHz crystal. Memory Interface The integrated memory controller logic of the Am186ES and Am188ES microcontrollers provides a direct address bus interface to memory devices. It is not necessary to use an external address latch controlled by the address latch enable (ALE) signal. Individual byte-write-enable signals eliminate the need for external high/low byte-write-enable circuitry. The maximum bank size that is programmable for the memory chip-select signals has been increased to facilitate the use of high-density memory devices. The improved memory timing specifications for the Am186ES and Am188ES microcontrollers allow nowait-state operation with 70-ns memory access times at a 40-MHz CPU clock speed. This reduces overall system cost significantly by allowing the use of a more commonly available memory speed and technology. Figure 1 also shows an implementation of an RS-232 console or modem communications port. The RS-232to-CMOS voltage-level converter is required for the electrical interface with the external device. Am186ES Microcontroller X2 WHB WLB 40-MHz Crystal X1 A19–A0 AD15–AD0 PWD Input Flash PROM WE WE Address Data RD OE UCS CS Static RAM PW WE WE RS-232 Level Converter Serial Port 0 Serial Port 1 Address Data OE LCS CS Figure 1. Am186ES Microcontroller Example System Design Direct Memory Interface Example Figure 1 illustrates the Am186ES microcontroller’s direct memory interface. The processor A19–A0 bus connects to the memory address inputs, the AD bus Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y The RD output connects to the SRAM Output Enable (OE) pin for read operations. Write operations use the byte-write enables connected to the SRAM Write Enable (WE) pins. The example design uses 2-Mbit memory technology (256 Kbytes) to fully populate the available address space. Two flash PROM devices provide 512 Kbytes of nonvolatile program storage, and two static RAM devices provide 512 Kbytes of data storage area. 40-MHz Crystal X2 BHE A0 COMPARING THE ES TO THE 80C186 Figure 1 shows an example system using a 40-MHz A m1 86 ES m i cr o c on tr o ll er . Fi gu r e 2 s ho ws a comparable system implementation with an 80C186. Because of its superior integration, the Am186ES microcontroller system does not require the support devices that are required on the 80C186 example system. In addition, the Am186ES microcontroller provides significantly better performance with its 40MHz clock rate. PAL connects to the data inputs and outputs, and the chip selects connect to the memory chip-select inputs. X1 SRAM Am29F200 Flash WE WE WE Address Address Data Data RD OE OE UCS CS CS AD15–AD0 LATCH WR ALE LCS LATCH PCS0 Timer 0–2 PIOs Serial Port RS-232 Level Converter INT3 INT2–INT0 DMA 0–1 CLKOUT 20 MHz Figure 2. 80C186 Microcontroller Example System Design COMPARING THE ES TO THE EMTABLE1 Compared to the Am186EM and Am188EM microcontrollers, the Am186ES and Am188ES microcontrollers have the following additional features: n Two full-featured asynchronous serial ports n The ability to use DMA to and from the serial ports n Two additional external interrupt signals n Enhancements to the watchdog timer to improve its security and functionality n A pulse width demodulation option n A data strobe bus interface option for DEN n ARDY functionality is changed to allow both edges of ARDY to be asynchronous to the clock n An option to have all MCS space asserted through MCS0 n On the Am186ES microcontroller, static bus sizing allows UCS space to use a 16-bit data bus, while LCS space can be either 8-bit or 16-bit. All nonUCS and non-LCS memory and I/O accesses can be 8-bit or 16-bit. This capability is available only on the Am186ES microcontroller; the Am188ES microcontroller has a uniform 8-bit access width. n The synchronous serial interface is removed n On the ES, row addresses are not driven on DRAM refreshes Two Asynchronous Serial Ports The Am186ES and Am188ES microcontrollers have two identical asynchronous serial ports. Each serial Am186/188ES and Am186/188ESLV Microcontrollers 11 P R E L I M I N A R Y port operates independently and has the following features: n Full-duplex operation n 7-bit, 8-bit, or 9-bit operation n Even, odd, or no parity n One stop bit n Long or short break character recognition n Parity error, framing error, overrun error, and break character detection n Configurable hardware handshaking with CTS, RTS, ENRX, and RTR n DMA to and from the serial ports n Separate maskable interrupts for each port n Multiprocessor 9-bit protocol n Independent baud rates for each port n Maximum baud rate of 1/16th of the CPU clock rate n Double-buffered transmit and receive n Programmable interrupt generation for transmit, receive, and/or error detection DMA and the Serial Ports The Am186ES and Am188ES microcontrollers can DMA directly to and from the serial ports. DMA and serial port transfer is accomplished by programming the DMA controller to perform transfers between a data source in memory or I/O space and a serial port transmit or receive register. The two DMA channels can support one serial port in full-duplex mode or two serial ports in half-duplex mode. Two Additional External Interrupts Two new interrupts, INT5 and INT6, are multiplexed with the DMA request signals, DRQ0 and DRQ1. If a DMA channel is not enabled, or if it is not using external synchronization, then the associated pin can be used as an external interrupt. INT5 and INT6 can also be used in conjunction with the DMA terminal count interrupts. Enhanced Watchdog Timer The Am186ES and Am188ES microcontrollers provide a true watchdog timer that can be configured to generate either an NMI interrupt or a system reset upon timeout. The watchdog timer supports up to a 1.67-second timeout period in a 40-MHz system. After reset, the watchdog timer defaults to enabled and can be modified or disabled only one time. If the timer is not disabled, the application program must periodically reset the timer by writing a specific key sequence to the watchdog timer control register. If the timer is not reset before it counts down, either an NMI or a system reset is issued, depending on the configuration of the timer. 12 Pulse Width Demodulation Option The Am186ES and Am188ES microcontrollers provide pulse width demodulation by adding a Schmitt trigger buffer to the INT2 pin. If pulse width demodulation mode is enabled, timer 0 and timer 1 are used to determine the pulse width of the signal period. Separate maskable interrupts are generated on the rising and falling edge of the pulse input. In pulse width demodulation mode, the external pins INT4, TIMERIN0, and TIMERIN1 are available as PIOs, but not as their normal functionality. Data Strobe Bus Interface Option The Am186ES and Am188ES microcontrollers provide a truly asynchronous bus interface that allows the use of 68K-type peripher als . This implementation combines a new DS data strobe signal (multiplexed with DEN) with a truly asynchronous ARDY ready input. When DS is asserted, the data and address signals are valid. A chip-select signal, ARDY, DS, and other control signals (RD/WR) can control the interface of 68K-type external peripherals to the AD bus. MCS0 Asserted for All MCS Option When the MCS0- onl y mode is enabl ed in the Am186ES and Am188ES microcontrollers, the entire middle chip-select range is selected through MCS0. The remaining MCS pins are available as PIOs or alternate functions. ARDY Functionality Change In the Am186ES and Am188ES microcontrollers, the ARDY signal is changed to allow both edges of ARDY to be asynchronous to the clock. On the Am186EM and Am188EM microcontrollers, proper operation was not guaranteed if ARDY did not meet the specification relative to the clock for all edges except the falling edge of a normally-ready system (relative to the rising edge of CLKOUTA). To guarantee the number of wait states inserted, ARDY or SRDY must be synchronized to CLKOUTA. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an additional clock period can be added. 8-Bit and 16-Bit Bus Sizing Option The Am186ES microcontroller allows switchable 8-bit and 16-bit bus sizing based on chip selects for three chip-select regions. The Am188ES microcontroller supports only 8-bit data widths. On the Am186ES microcontroller, the upper chip select (UCS) region is always 16 bits, so memory used for boot code at power-on reset must be 16-bit memory. However, the LCS memory region, memory that is not UCS or LCS (including memory mapped to MCS and PCS), and I/O space can be independently configured as 8-bit or 16-bit. Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y PCS2/CTS1/ENRX1 PCS3 /RTS1/RTR1 VCC PCS 5/A1 PCS 6/A2 LCS / ONCE 0 UCS / ONCE1 INT0 INT1/ SELECT INT2/INTA0/PWD INT3/INTA1/IRQ 84 83 82 81 80 79 78 77 76 MCS3/ RFSH MCS2/PIO24 VCC 92 91 86 85 RES GND 94 93 PCS1 GND TMROUT1 TMRIN1/PIO0 96 95 88 87 TMRIN0 TMROUT0 98 97 PCS0 DRQ0/INT5 DRQ1/INT6 100 99 90 89 TQFP CONNECTION DIAGRAMS AND PINOUTS Am186ES Microcontroller Top Side View—100-Pin Thin Quad Flat Pack (TQFP) AD0 AD8 1 2 75 74 AD1 AD9 3 4 73 72 AD2 AD10 5 6 71 70 AD3 AD11 7 8 69 68 SRDY HOLD AD4 AD12 9 10 67 66 AD5 GND 11 12 65 64 HLDA WLB WHB AD13 AD6 13 14 V CC AD14 AD7 AD15 S6/LOCK/CLKDIV2 Am186ES Microcontroller INT4 MCS1 MCS0 DEN/DS DT/R NMI GND 23 24 53 52 A9 A10 TXD0 25 51 A11 30 31 32 33 34 35 S2 S1 S0 28 29 WR RD ALE ARDY BHE/ADEN 26 27 RTS0/RTR0 50 RXD0 A12 A7 A8 48 49 55 54 A14 A13 21 22 TXD1 RXD1 CTS0/ENRX0 46 47 A5 A6 A16 A15 57 56 44 45 19 20 UZI VCC A17 A3 A4 42 43 59 58 40 41 17 18 CLKOUTB GND A19 A18 VCC A2 38 39 61 60 VCC CLKOUTA 15 16 36 37 A0 A1 GND X1 X2 63 62 Note: Pin 1 is marked for orientation. Am186/188ES and Am186/188ESLV Microcontrollers 13 P R E L I M I N A R Y TQFP PIN ASSIGNMENTS—Am186ES Microcontroller (Sorted by Pin Number) Pin No. 14 Name Pin No. Name Pin No. Name Pin No. Name 1 AD0 26 RTS0/RTR0/ PIO20 51 A11 76 INT3/INTA1/IRQ 2 AD8 27 BHE/ADEN 52 A10 77 INT2/INTA0/PWD/ PIO31 3 AD1 28 WR 53 A9 78 INT1/SELECT 4 AD9 29 RD 54 A8 79 INT0 5 AD2 30 ALE 55 A7 80 UCS/ONCE1 6 AD10 31 ARDY 56 A6 81 LCS/ONCE0 7 AD3 32 S2 57 A5 82 PCS6/A2/PIO2 8 AD11 33 S1 58 A4 83 PCS5/A1/PIO3 9 AD4 34 S0 59 A3 84 VCC 10 AD12 35 GND 60 A2 85 PCS3/RTS1/ RTR1/ PIO19 11 AD5 36 X1 61 VCC 86 PCS2/CTS1/ ENRX1/PIO18 12 GND 37 X2 62 A1 87 GND 13 AD13 38 VCC 63 A0 88 PCS1/PIO17 14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16 15 VCC 40 CLKOUTB 65 WHB 90 VCC 16 AD14 41 GND 66 WLB 91 MCS2/PIO24 17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH/ PIO25 18 AD15 43 A18/PIO8 68 HOLD 93 GND 19 S6/LOCK/CLKDIV2/ PIO29 44 VCC 69 SRDY/PIO6 94 RES 20 UZI/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0 21 TXD1/PIO27 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1 22 RXD1/PIO28 47 A15 72 DEN/DS/PIO5 97 TMROUT0/PIO10 23 CTS0/ENRX0/PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11 24 RXD0/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/INT6/PIO13 25 TXD0/PIO22 50 A12 75 INT4/PIO30 100 DRQ0/INT5/PIO12 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y TQFP PIN DESIGNATIONS—Am186ES Microcontroller (Sorted by Pin Name) Pin Name No. Pin Name No. Pin Name No. Pin Name No. A0 63 AD5 11 GND 87 RXD1 22 A1 62 AD6 14 GND 93 S0 34 A2 60 AD7 17 HLDA 67 S1 33 A3 59 AD8 2 HOLD 68 S2 32 A4 58 AD9 4 INT0 79 S6/LOCK/ CLKDIV2/PIO29 19 A5 57 AD10 6 INT1/SELECT 78 SRDY/PIO6 69 A6 56 AD11 8 INT2/INTA0/ PWD/PIO31 77 TMRIN0/PIO11 98 A7 55 AD12 10 INT3/INTA1/IRQ 76 TMRIN1/PIO0 95 A8 54 AD13 13 INT4/PIO30 75 TMROUT0/ PIO10 97 A9 53 AD14 16 LCS/ONCE0 81 TMROUT1/PIO1 96 A10 52 AD15 18 MCS0/PIO14 73 TXD0/PIO22 25 A11 51 ALE 30 MCS1/PIO15 74 TXD1 21 A12 50 ARDY 31 MCS2/PIO24 91 UCS/ONCE1 80 A13 49 BHE/ADEN 27 MCS3/RFSH/PIO25 92 UZI/PIO26 20 A14 48 CLKOUTA 39 NMI 70 VCC 15 A15 47 CLKOUTB 40 PCS0/PIO16 89 VCC 38 A16 46 CTS0/ENRX0/ PIO21 23 PCS1/PIO17 88 VCC 44 A17/PIO7 45 DEN/DS/PIO5 72 PCS2/CTS1/ ENRX1/PIO18 86 VCC 61 A18/PIO8 43 DRQ0/INT5/PIO12 100 PCS3/RTS1/RTR1/ PIO19 85 VCC 84 A19/PIO9 42 DRQ1/INT6/PIO13 99 PCS5/A1/PIO3 83 VCC 90 AD0 1 DT/R/PIO4 71 PCS6/A2/PIO2 82 WHB 65 AD1 3 GND 12 RD 29 WLB 66 AD2 5 GND 35 RES 94 WR 28 AD3 7 GND 41 RTS0/RTR0/PIO20 26 X1 36 AD4 9 GND 64 RXD0/PIO23 24 X2 37 Am186/188ES and Am186/188ESLV Microcontrollers 15 P R E L I M I N A R Y AD0 1 AO8 AD1 2 3 AO9 AD2 4 5 AO10 AD3 6 7 AO11 AD4 8 9 AO12 AD5 GND 10 11 DRQ0/INT5 DRQ1/INT6 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/ RFSH MCS2 VCC PCS 0 PCS 1 GND PCS 2/CTS1/ENRX1 PCS 3 /RTS1/RTR1 VCC PCS 5/A1 PCS 6/A2 LCS / ONCE 0 UCS / ONCE1 INT0 INT1/ SELECT INT2/INTA0/PWD INT3/INTA1/IRQ 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 14 15 16 17 18 19 20 21 22 23 45 46 47 48 49 50 A15 A14 A13 A12 43 44 VCC A17 A16 A18 41 42 CLKOUTB GND A19 VCC CLKOUTA 39 40 35 36 GND X1 X2 37 38 33 34 S1 S0 S2 31 32 ARDY 24 25 29 30 RXD1 CTS0/ENRX0 RXD0 TXD0 Am188ES Microcontroller RD ALE TXD1 12 13 Note: Pin 1 is marked for orientation. 16 Am186/188ES and Am186/188ESLV Microcontrollers INT4 MCS1 MCS0 DEN/DS DT/R NMI 69 68 SRDY HOLD 67 66 HLDA WB GND 65 64 27 28 AO15 S6/LOCK/CLKDIV2 UZI 71 70 RFSH2/ADEN WR VCC AO14 AD7 73 72 26 AD6 75 74 RTS0/RTR0 AO13 100 CONNECTION DIAGRAM Am188ES Microcontroller Top Side View—100-Pin Thin Quad Flat Pack (TQFP) GND 63 62 A0 A1 61 60 VCC A2 59 58 A3 A4 57 56 A5 A6 55 54 A7 A8 53 52 A9 A10 51 A11 P R E L I M I N A R Y TQFP PIN DESIGNATIONS—Am188ES Microcontroller (Sorted by Pin Number) Pin No. Name Pin No. Name Pin No. Name Pin No. Name 1 AD0 26 RTS0/RTR0/ PIO20 51 A11 76 INT3/INTA1/IRQ 2 AO8 27 RFSH2/ADEN 52 A10 77 INT2/INTA0/ PWD/PIO31 3 AD1 28 WR 53 A9 78 INT1/SELECT 4 AO9 29 RD 54 A8 79 INT0 5 AD2 30 ALE 55 A7 80 UCS/ONCE1 6 AO10 31 ARDY 56 A6 81 LCS/ONCE0 7 AD3 32 S2 57 A5 82 PCS6/A2/PIO2 8 AO11 33 S1 58 A4 83 PCS5/A1/PIO3 9 AD4 34 S0 59 A3 84 VCC 10 AO12 35 GND 60 A2 85 PCS3/RTS1/RTR1/ PIO19 11 AD5 36 X1 61 VCC 86 PCS2/CTS1/ENRX1/ PIO18 12 GND 37 X2 62 A1 87 GND 13 AO13 38 VCC 63 A0 88 PCS1/PIO17 14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16 15 VCC 40 CLKOUTB 65 GND 90 VCC 16 AO14 41 GND 66 WB 91 MCS2/PIO24 17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH/PIO25 18 AO15 43 A18/PIO8 68 HOLD 93 GND 19 S6/LOCK/ CLKDIV2/PIO29 44 VCC 69 SRDY/PIO6 94 RES 20 UZI/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0 21 TXD1/PIO27 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1 22 RXD1/PIO28 47 A15 72 DEN/DS/PIO5 97 TMROUT0/PIO10 23 CTS0/ENRX0/ PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11 24 RXD0/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/INT6/PIO13 25 TXD0/PIO22 50 A12 75 INT4/PIO30 100 DRQ0/INT5/PIO12 Am186/188ES and Am186/188ESLV Microcontrollers 17 P R E L I M I N A R Y TQFP PIN DESIGNATIONS—Am188ES Microcontroller (Sorted by Pin Name) Pin Name No. Pin Name No. Pin Name No. Pin Name No. A0 63 AD5 11 GND 87 RXD0/PIO23 24 A1 62 AD6 14 GND 93 RXD1/PIO28 22 A2 60 AD7 17 HLDA 67 S0 34 A3 59 ALE 30 HOLD 68 S1 33 A4 58 AO8 2 INT0 79 S2 32 A5 57 AO9 4 INT1/SELECT 78 S6/LOCK/ CLKDIV2/PIO29 19 A6 56 AO10 6 INT2/INTA0/ PWD/PIO31 77 SRDY/PIO6 69 A7 55 AO11 8 INT3/INTA1/IRQ 76 TMRIN0/PIO11 98 A8 54 AO12 10 INT4/PIO30 75 TMRIN1/PIO0 95 A9 53 AO13 13 LCS/ONCE0 81 TMROUT0/PIO10 97 A10 52 AO14 16 MCS0/PIO14 73 TMROUT1/PIO1 96 A11 51 AO15 18 MCS1/PIO15 74 TXD0/PIO22 25 A12 50 ARDY 31 MCS2/PIO24 91 TXD1/PIO27 21 A13 49 CLKOUTA 39 MCS3/RFSH/ PIO25 92 UCS/ONCE1 80 A14 48 CLKOUTB 40 NMI 70 UZI/PIO26 20 A15 47 CTS0/ENRX0/ PIO21 23 PCS0/PIO16 89 VCC 15 A16 46 DEN/DS/PIO5 72 PCS1/PIO17 88 VCC 38 A17/PIO7 45 DRQ0/INT5/ PIO12 100 PCS2/CTS1/ ENRX1/PIO18 86 VCC 44 A18/PIO8 43 DRQ1/INT6/ PIO13 99 PCS3/RTS1/ RTR1/ PIO19 85 VCC 61 A19/PIO9 42 DT/R/PIO4 71 PCS5/A1/PIO3 83 VCC 84 AD0 1 GND 12 PCS6/A2/PIO2 82 VCC 90 AD1 3 GND 35 RD 29 WB 66 AD2 5 GND 41 RES 94 WR 28 AD3 7 GND 64 RFSH2/ADEN 27 X1 36 AD4 9 GND 65 RTS0/RTR0/ PIO20 26 X2 37 18 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y AD11 AD3 AD10 AD2 AD9 85 83 81 AD12 AD4 87 82 GND AD5 89 84 AD13 90 86 VCC AD6 92 88 AD7 AD14 94 91 AD15 95 93 S6/LOCK/CLKDIV2 96 97 98 47 NMI DT/R 50 46 SRDY 49 45 HOLD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AD1 AD8 AD0 DRQ0/INT5 DRQ1/INT6 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RFSH MCS2 VCC PCS0 PCS1 GND PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1 VCC PCS5/A1 PCS6/A2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PWD INT3/INTA1/IRQ INT4 MCS1 DEN/DS MCS0 44 HLDA 48 43 WHB WLB 42 VCC A1 A0 GND 41 38 A2 40 37 A3 39 36 A4 A9 35 A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 34 CLKOUTB GND Am186ES Microcontroller A5 X1 X2 VCC CLKOUTA 33 S0 GND A6 ARDY S2 S1 32 RD ALE 31 TXD0 RTS0/RTR0 BHE/ADEN WR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A8 A7 RXD0 99 100 CTS0/ENRX0 RXD1 TXD1 UZI PQFP CONNECTION DIAGRAMS AND PINOUTS Am186ES Microcontroller Top Side View—100-Pin Plastic Quad Flat Pack (PQFP) Note: Pin 1 is marked for orientation. Am186/188ES and Am186/188ESLV Microcontrollers 19 P R E L I M I N A R Y PQFP PIN DESIGNATIONS—Am186ES Microcontroller (Sorted by Pin Number) Pin No. 20 Name Pin No. Name Pin No. Name Pin No. Name 1 RXD0/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/INT6/PIO13 2 TXD0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/INT5/PIO12 3 RTS0/RTR0/ PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0 4 BHE/ADEN 29 A10 54 INT2/INTA0/ PWD/PIO31 79 AD8 5 WR 30 A9 55 INT1/SELECT 80 AD1 6 RD 31 A8 56 INT0 81 AD9 7 ALE 32 A7 57 UCS/ONCE1 82 AD2 8 ARDY 33 A6 58 LCS/ONCE0 83 AD10 9 S2 34 A5 59 PCS6/A2/PIO2 84 AD3 10 S1 35 A4 60 PCS5/A1/PIO3 85 AD11 11 S0 36 A3 61 VCC 86 AD4 12 GND 37 A2 62 PCS3/RTS1/RTR1/ PIO19 87 AD12 13 X1 38 VCC 63 PCS2/CTS1/ ENRX1/PIO18 88 AD5 14 X2 39 A1 64 GND 89 GND 15 VCC 40 A0 65 PCS1/PIO17 90 AD13 16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6 17 CLKOUTB 42 WHB 67 VCC 92 VCC 18 GND 43 WLB 68 MCS2/PIO24 93 AD14 19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7 20 A18/PIO8 45 HOLD 70 GND 95 AD15 21 VCC 46 SRDY/PIO6 71 RES 96 S6/LOCK/ CLKDIV2/PIO29 22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/PIO26 23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD1/PIO27 24 A15 49 DEN/DS/PIO5 74 TMROUT0/PIO10 99 RXD1/PIO28 25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 CTS0/ENRX0/PIO21 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y PQFP PIN DESIGNATIONS—Am186ES Microcontroller (Sorted by Pin Name) Pin Name No. Pin Name No. Pin Name No. Pin Name No. A0 40 AD5 88 GND 70 RXD1/PIO28 99 A1 39 AD6 91 GND 89 S0 11 A2 37 AD7 94 HLDA 44 S1 10 A3 36 AD8 79 HOLD 45 S2 9 A4 35 AD9 81 INT0 56 S6/LOCK/ CLKDIV2/PIO29 96 A5 34 AD10 83 INT1/SELECT 55 SRDY/PIO6 46 A6 33 AD11 85 INT2/INTA0/ PWD/PIO31 54 TMRIN0/PIO11 75 A7 32 AD12 87 INT3/INTA1/IRQ 53 TMRIN1/PIO0 72 A8 31 AD13 90 INT4/PIO30 52 TMROUT0/ PIO10 74 A9 30 AD14 93 LCS/ONCE0 58 TMROUT1/PIO1 73 A10 29 AD15 95 MCS0/PIO14 50 TXD0/PIO22 2 A11 28 ALE 7 MCS1/PIO15 51 TXD1/PIO27 98 A12 27 ARDY 8 MCS2/PIO24 68 UCS/ONCE1 57 A13 26 BHE/ADEN 4 MCS3/RFSH/PIO25 69 UZI/PIO26 97 A14 25 CLKOUTA 16 NMI 47 VCC 15 A15 24 CLKOUTB 17 PCS0/PIO16 66 VCC 21 A16 23 CTS0/ENRX0/ PIO21 100 PCS1/PIO17 65 VCC 38 A17/PIO7 22 DEN/DS/PIO5 49 PCS2/CTS1/ENRX1/ PIO18 63 VCC 61 A18/PIO8 20 DRQ0/INT5/PIO12 77 PCS3/RTS1/RTR1/ PIO19 62 VCC 67 A19/PIO9 19 DRQ1/INT6/PIO13 76 PCS5/A1/PIO3 60 VCC 92 AD0 78 DT/R/PIO4 48 PCS6/A2/PIO2 59 WHB 42 AD1 80 GND 12 RD 6 WLB 43 AD2 82 GND 18 RES 71 WR 5 AD3 84 GND 41 RTS0/RTR0/PIO20 3 X1 13 AD4 86 GND 64 RXD0/PIO23 1 X2 14 Am186/188ES and Am186/188ESLV Microcontrollers 21 P R E L I M I N A R Y 81 AO10 AD2 AO9 83 82 AO11 AD3 85 84 AO12 AD4 87 86 GND AD5 89 88 AD6 VCC 92 AO13 AD7 AO14 94 90 AO15 95 91 S6/LOCK/CLKDIV2 96 93 UZI 97 98 50 47 NMI DT/R 49 46 SRDY DEN/DS MCS0 45 48 44 HLDA HOLD 43 42 GND WB 41 40 A0 GND 39 38 A3 A2 VCC A1 36 37 35 A4 A9 Am188ES Microcontroller 34 X1 X2 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 33 S0 GND A5 ALE ARDY S2 S1 A6 RD 32 RFSH2/ADEN WR 31 TXD0 RTS0/RTR0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A8 A7 RXD0 99 100 CTS0/ENRX0 RXD1 TXD1 CONNECTION DIAGRAM Am188ES Microcontroller Top Side View—100-Pin Plastic Quad Flat Pack (PQFP) Note: Pin 1 is marked for orientation. 22 Am186/188ES and Am186/188ESLV Microcontrollers 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AD1 AO8 AD0 DRQ0/INT5 DRQ1/INT6 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RFSH MCS2 VCC PCS0 PCS1 GND PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1 VCC PCS5/A1 PCS6/A2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PWD INT3/INTA1/IRQ INT4 MCS1 P R E L I M I N A R Y PQFP PIN DESIGNATIONS—Am188ES Microcontroller (Sorted by Pin Number) Pin No. Name Pin No. Name Pin No. Name Pin No. Name 1 RXD0/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/INT6/PIO13 2 TXD0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/INT5/PIO12 3 RTS0/RTR0/ PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0 4 RFSH2/ADEN 29 A10 54 INT2/INTA0/ PWD/PIO31 79 AO8 5 WR 30 A9 55 INT1/SELECT 80 AD1 6 RD 31 A8 56 INT0 81 AO9 7 ALE 32 A7 57 UCS/ONCE1 82 AD2 8 ARDY 33 A6 58 LCS/ONCE0 83 AO10 9 S2 34 A5 59 PCS6/A2/PIO2 84 AD3 10 S1 35 A4 60 PCS5/A1/PIO3 85 AO11 11 S0 36 A3 61 VCC 86 AD4 12 GND 37 A2 62 PCS3/RTS1/RTR1/ PIO19 87 AO12 13 X1 38 VCC 63 PCS2/CTS1/ENRX1/ PIO18 88 AD5 14 X2 39 A1 64 GND 89 GND 15 VCC 40 A0 65 PCS1/PIO17 90 AO13 16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6 17 CLKOUTB 42 GND 67 VCC 92 VCC 18 GND 43 WB 68 MCS2/PIO24 93 AO14 19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7 20 A18/PIO8 45 HOLD 70 GND 95 AO15 21 VCC 46 SRDY/PIO6 71 RES 96 S6/LOCK/ CLKDIV2/PIO29 22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/PIO26 23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD1/PIO27 24 A15 49 DEN/DS/PIO5 74 TMROUT0/PIO10 99 RXD1/PIO28 25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 CTS0/ENRX0/PIO21 Am186/188ES and Am186/188ESLV Microcontrollers 23 P R E L I M I N A R Y PQFP PIN DESIGNATIONS—Am188ES Microcontroller (Sorted by Pin Name) Pin Name No. Pin Name No. Pin Name No. Pin Name A0 40 AD5 88 GND 70 RXD0/PIO23 1 A1 39 AD6 91 GND 89 RXD1/PIO28 99 A2 37 AD7 94 HLDA 44 S0 11 A3 36 ALE 7 HOLD 45 S1 10 A4 35 AO8 79 INT0 56 S2 9 A5 34 AO9 81 INT1/SELECT 55 S6/LOCK/ CLKDIV2/PIO29 96 A6 33 AO10 83 INT2/INTA0/ PWD/PIO31 54 SRDY/PIO6 46 A7 32 AO11 85 INT3/INTA1/IRQ 53 TMRIN0/PIO11 75 A8 31 AO12 87 INT4/PIO30 52 TMRIN1/PIO0 72 A9 30 AO13 90 LCS/ONCE0 58 TMROUT0/ PIO10 74 A10 29 AO14 93 MCS0/PIO14 50 TMROUT1/PIO1 73 A11 28 AO15 95 MCS1/PIO15 51 TXD0/PIO22 2 A12 27 ARDY 8 MCS2/PIO24 68 TXD1/PIO27 98 A13 26 CLKOUTA 16 MCS3/RFSH/PIO25 69 UCS/ONCE1 57 A14 25 CLKOUTB 17 NMI 47 UZI/PIO26 97 A15 24 CTS0/ENRX0/ PIO21 100 PCS0/PIO16 66 VCC 15 A16 23 DEN/DS/PIO5 49 PCS1/PIO17 65 VCC 21 A17/PIO7 22 DRQ0/INT5/PIO12 77 PCS2/CTS1/ENRX1/ PIO18 63 VCC 38 A18/PIO8 20 DRQ1/INT6/PIO13 76 PCS3/RTS1/RTR1/ PIO19 62 VCC 61 A19/PIO9 19 DT/R/PIO4 48 PCS5/A1/PIO3 60 VCC 67 AD0 78 GND 12 PCS6/A2/PIO2 59 VCC 92 AD1 80 GND 18 RD 6 WB 43 AD2 82 GND 41 RES 71 WR 5 AD3 84 GND 42 RFSH2/ADEN 4 X1 13 AD4 86 GND 64 RTS0/RTR0/PIO20 3 X2 14 24 Am186/188ES and Am186/188ESLV Microcontrollers No. P R E L I M I N A R Y LOGIC SYMBOL—Am186ES MICROCONTROLLER X1 X2 Clocks CLKOUTA CLKOUTB RES DRQ1/INT6 DRQ0/INT5 INT4 * INT3/INTA1/IRQ INT2/INTA0/PWD * 20 A19–A0 16 AD15–AD0 * Reset Control and Interrupt Service INT1/SELECT INT0 Address and Address/Data Buses * S6/LOCK/CLKDIV2 * UZI ALE 3 S2–S0 HOLD HLDA RD WR Bus Control * DT/R * DEN/DS NMI PCS6/A2 * PCS5/A1 * PCS3/RTS1/RTR1 * PCS2/CTS1/ENRX1 * PCS1–PCS0 2 * LCS/ONCE0 * MCS3/RFSH MCS2–MCS0 Memory and Peripheral Control 3 * UCS/ONCE1 ARDY * SRDY BHE/ADEN DRQ1/INT6 * DRQ0/INT5 * TXD0 * RXD0 * CTS0/ENRX0 * RTS0/RTR0 * TXD1 * RXD1 * PCS2/CTS1/ENRX1 * PCS3/RTS1/RTR1 * DMA Control WHB WLB Timer Control Programmable I/O Control * TMRIN0 * TMROUT0 * TMRIN1 * TMROUT1 32 shared ** PIO32–PIO0 Asynchronous Serial Port Control Notes: * These signals are the normal function of a pin that can be used as a PIO. See Pin Descriptions beginning on page 27 and Table 2 on page 34 for information on shared function. ** All PIO signals are shared with other physical pins. Am186/188ES and Am186/188ESLV Microcontrollers 25 P R E L I M I N A R Y LOGIC SYMBOL—Am188ES MICROCONTROLLER X1 X2 Clocks CLKOUTA CLKOUTB RES DRQ1/INT6 DRQ0/INT5 * INT4 INT3/INTA1/IRQ INT2/INTA0/PWD * Address and Address/Data Buses 20 A19–A0 8 AO15–AO8 INT0 8 AD7–AD0 NMI * S6/LOCK/CLKDIV2 * UZI ALE 3 S2–S0 HOLD Bus Control * Reset Control and Interrupt Service INT1/SELECT PCS6/A2 * PCS5/A1 * PCS3/RTS1/RTR1 * PCS2/CTS1/ENRX1 * PCS1–PCS0 HLDA LCS/ONCE0 RD MCS3/RFSH WR MCS2–MCS0 * DT/R UCS/ONCE1 * DEN/DS 2 * Memory and Peripheral Control * 3 * ARDY * SRDY DRQ1/INT6 * DRQ0/INT5 * TXD0 * RXD0 * DMA Control RFSH2/ADEN WB Timer Control Programmable I/O Control * TMRIN0 * TMROUT0 * TMRIN1 * TMROUT1 ** 32 shared PIO32–PIO0 CTS0/ENRX0 RTS0/RTR0 * * TXD1 * RXD1 * PCS2/CTS1/ENRX1 * PCS3/RTS1/RTR1 * Asynchronous Serial Port Control Notes: * These signals are the normal function of a pin that can be used as a PIO. See Pin Descriptions beginning on page 27 and Table 2 on page 34 for information on shared function. ** All PIO signals are shared with other physical pins. 26 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y PIN DESCRIPTIONS Pins That Are Used by Emulators The following pins are used by emulators: A19–A0, AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the 186), CLKOUTA, RFSH2/ADEN (on the 188), RD, S2–S0, S6/LOCK/CLKDIV2, and UZI. Emulators require S6/LOCK/CLKDIV2 and UZI to be configured in their normal functionality as S6 and UZI, not as PIOs. If BHE/ADEN (on the 186) or RFSH2/ ADEN (on the 188) is held Low during the rising edge of RES, S6 and UZI are configured in their normal functionality. During a power-on reset, the address and data bus pins (AD15–AD0 for the 186, AO15–AO8 and AD7– AD0 for the 188) can also be used to load system configuration information into the internal reset configuration register. AO15–AO8—When the address bus is enabled on the Am188ES microcontroller, via the AD bit in the UMCS and LMCS registers, the address-only bus (AO15– AO8) contains valid high-order address bits from bus cycles t1–t4. These outputs are floated during a bus hold or reset. The following terms are used to describe the pins: On the Am188ES microcontroller, AO15–AO 8 combine with AD7–AD0 to form a complete multiplexed address bus while AD7–AD0 is the 8-bit data bus. Input—An input-only pin. AD7–AD0 Output—An output-only pin. Address and Data Bus (input/output, three-state, synchronous, level-sensitive) Pin Terminology Input/Output—A pin that can be either input or output. Synchronous—Synchronous inputs must meet setup and hold times in relation to CLKOUTA. Synchronous outputs are synchronous to CLKOUTA. Asynchronous—Inputs or outputs that are asynchronous to CLKOUTA. A19–A0 (A19/PIO9, A18/PIO8, A17/PIO7) Address Bus (output, three-state, synchronous) These pins supply nonmultiplexed memory or I/O addresses to the system one half of a CLKOUTA period earlier than the multiplexed address and data bus (AD15–AD0 on the 186 or AO15–AO8 and AD7– AD0 on the 188). During a bus hold or reset condition, the address bus is in a high-impedance state. AD15–AD8 (Am186ES Microcontroller) AO15–AO8 (Am188ES Microcontroller) Address and Data Bus (input/output, three-state, synchronous, level-sensitive) Address-Only Bus (output, three-state, synchronous, level-sensitive) These time-multiplexed pins supply partial memory or I/O addresses, as well as data, to the system. This bus supplies the low-order 8 bits of an address to the system during the first period of a bus cycle (t1), and it supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). In 8-bit mode on the Am188ES microcontroller, AD7–AD0 supplies the data. The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WLB is deasserted, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state. During a power-on reset, the address and data bus pins (AD15–AD0 for the 186, AO15–AO8 and AD7– AD0 for the 188) can also be used to load system configuration information into the internal reset configuration register. ALE Address Latch Enable (output, synchronous) AD15–AD8—On the Am186ES microcontroller, these time-multiplexed pins supply memory or I/O addresses and data to the system. This bus can supply an address to the system during the first period of a bus cycle (t1). It supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). This pin indicates to the system that an address appears on the address and data bus (AD15–AD0 for the 186 or AO15–AO8 and AD7–AD0 for the 188). The address is guaranteed to be valid on the trailing edge of ALE. This pin is three-stated during ONCE mode. This pin is not three-stated during a bus hold or reset. The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WHB is deasserted, these pins are three-stated during t2, t3, and t4. ARDY During a bus hold or reset condition, the address and data bus is in a high-impedance state. Asynchronous Ready (input, asynchronous, level-sensitive) This pin is a true asynchronous ready that indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The ARDY Am186/188ES and Am186/188ESLV Microcontrollers 27 P R E L I M I N A R Y pin is asynchronous to CLKOUTA and is active High. To guarantee the number of wait states inserted, ARDY or SRDY must be synchronized to CLKOUTA. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an additional clock period can be added. To always assert the ready condition to the microcontroller, tie ARDY High. If the system does not use ARDY, tie the pin Low to yield control to SRDY. BHE/ADEN (Am186ES Microcontroller Only) Bus High Enable (three-state, output, synchronous) Address Enable (input, internal pullup) pullup resistor on BHE/ADEN so no external pullup is required. This mode of operation reduces power consumption. If BHE/ADEN is held Low on power-on reset, the AD bus drives both addresses and data, regardless of the DA bit setting. The pin is sampled on the rising edge of RE S . ( S 6 an d U Z I a l s o a s s u me th e i r n o r m al functionality in this instance. See Table 2 on page 34.) Note: On the Am188ES microcontroller, AO15–AO8 are driven during the t2–t4 bus cycle, regardless of the setting of the DA bit in the UMCS and LMCS registers. CLKOUTA Clock Output A (output, synchronous) BHE—During a memory access, this pin and the leastsignificant address bit (AD0 or A0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN and AD0 pins are encoded as shown in Table 1. This pin supplies the internal clock to the system. Depending on the value of the system configuration register (SYSCON), CLKOUTA operates at either the PLL frequency, the power-save frequency, or is threestated. CLKOUTA remains active during reset and bus hold conditions. Table 1. Data Byte Encoding All AC timing specs that use a clock relate to CLKOUTA. BHE AD0 Type of Bus Cycle 0 0 Word Transfer 0 1 High Byte Transfer (Bits 15–8) 1 0 Low Byte Transfer (Bits 7–0) 1 1 Refresh Clock Output B (output, synchronous) BHE is asserted during t 1 and remains asserted through t3 and tW. BHE does not need to be latched. BHE floats during bus hold and reset. On the Am186ES microcontroller, WLB and WHB implement the functionality of BHE and AD0 for high and low byte-write enables. BHE/ADEN also signals DRAM refresh cycles when using the multiplexed address and data (AD) bus. A refresh cycle is indicated when both BHE/ADEN and AD0 are High. During refresh cycles, the A bus and the AD bus are not guaranteed to provide the same address during the address phase of the AD bus cycle. For this reason, the A0 signal cannot be used in place of the AD0 signal to determine refresh cycles. PSRAM refreshes also provide an additional RFSH signal (see the MCS3/RFSH pin description on page 31). ADEN—If BHE/ADEN is held High or left floating during power-on reset, the address portion of the AD bus (AD15–AD0 for the 186 or AO15–AO8 and AD7– AD0 for the 188) is enabled or disabled during LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. In this case, the memory address is accessed on the A19–A0 pins. There is a weak internal 28 CLKOUTB This pin supplies an additional clock with a delayed output compared to CLKOUTA. Depending upon the value of the system configuration register (SYSCON), CLKOUTB operates at either the PLL frequency, the power-save frequency, or is three-stated. CLKOUTB remains active during reset and bus hold conditions. CLKOUTB is not used for AC timing specs. CTS0/ENRX0/PIO21 Clear-to-Send 0 (input, asynchronous) Enable-Receiver-Request 0 (input, asynchronous) CTS0—This pin provides the Clear to Send signal for asynchronous serial port 0 when the ENRX0 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The CTS0 signal gates the transmission of data from the associated serial port transmit register. When CTS0 is asserted, the transmitter begins transmission of a frame of data, if any is available. If CTS0 is deasserted, the transmitter holds the data in the serial port transmit register. The value of CTS0 is checked only at the beginning of the transmission of the frame. ENRX0—This pin provides the Enable Receiver Request for asynchronous serial port 0 when the ENRX0 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The ENRX0 signal enables the receiver for the associated serial port. Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y DEN/DS/PIO5 DT/R/PIO4 Data Enable (output, three-state, synchronous) Data Strobe (output, three-state, synchronous) Data Transmit or Receive (output, three-state, synchronous) DEN—This pin supplies an output enable to an external data-bus transceiver. DEN is asserted during memory, I/O, and interrupt acknowledge cycles. DEN is deasserted when DT/R changes state. DEN floats during a bus hold or reset condition. This pin indicates in which direction data should flow through an external data-bus transceiver. When DT/R is asserted High, the microcontroller transmits data. When this pin is deasserted Low, the microcontroller receives data. DT/R floats during a bus hold or reset condition. DS—The data strobe provides a signal where the write cycle timing is identical to the read cycle timing. When used with other control signals, DS provides an interface for 68K-type peripherals without the need for additional system interface logic. When DS is asserted, addresses are valid. When DS is asserted on writes, data is valid. When DS is asserted on reads, data can be asserted on the AD bus. Note: This pin resets to DEN. DRQ0/INT5/PIO12 DMA Request 0 (input, synchronous, level-sensitive) Maskable Interrupt Request 5 (input, asynchronous, edge-triggered) DRQ0—This pin indicates to the microcontroller that an external device is ready for DMA channel 0 to perform a transfer. DRQ0 is level-triggered and internally synchronized. DRQ0 is not latched and must remain active until serviced. INT5—If DMA 0 is not enabled or DMA 0 is not being used with external synchronization, INT5 can be used as an additional external interrupt request. INT5 shares the DMA 0 interrupt type (0Ah) and register control bits. INT5 is edge-triggered only and must be held until the interrupt is acknowledged. DRQ1/INT6/PIO13 DMA Request 1 (input, synchronous, level-sensitive) Maskable Interrupt Request 6 (input, asynchronous, edge-triggered) DRQ1—This pin indicates to the microcontroller that an external device is ready for DMA channel 1 to perform a transfer. DRQ1 is level-triggered and internally synchronized. DRQ1 is not latched and must remain active until serviced. INT6—If DMA 1 is not enabled or DMA 1 is not being used with external synchronization, INT6 can be used as an additional external interrupt request. INT6 shares the DMA 1 interrupt type (0Bh) and register control bits. INT6 is edge-triggered only and must be held until the interrupt is acknowledged. GND Ground Ground pins connect the microcontroller to the system ground. HLDA Bus Hold Acknowledge (output, synchronous) This pin is asserted High to indicate to an external bus master that the microcontroller has released control of the local bus. When an external bus master requests control of the local bus (by asserting HOLD), the microcontroller completes the bus cycle in progress. It then relinquishes control of the bus to the external bus master by asserting HLDA and floating DEN, RD, WR, S2–S0, AD15–AD0, S6, A19–A0, BHE, WHB, WLB, and DT/R, and then driving the chip selects UCS, LCS, MCS3–MCS0, PCS6–PCS5, and PCS3–PCS0 High. When the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting HOLD. The microcontroller responds by deasserting HLDA. If the microcontroller requires access to the bus (for example, to refresh), it will deassert HLDA before the external bus master deasserts HOLD. The external bus master must be able to deassert HOLD and allow the microcontroller access to the bus. See the timing diagrams for bus hold on page 97. HOLD Bus Hold Request (input, synchronous, level-sensitive) This pin indicates to the microcontroller that an external bus master needs control of the local bus. The Am186ES and Am188ES microcontrollers’ HOLD latency time is a function of the activity occurring in the processor when the HOLD request is received. A DRAM request will delay a HOLD request when both requests are made at the same time. In addition, if locked transfers are performed, the HOLD latency time is increased by the length of the locked transfer. For more information, see the HLDA pin description on page 29. Am186/188ES and Am186/188ESLV Microcontrollers 29 P R E L I M I N A R Y INT0 Maskable Interrupt Request 0 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT0 pin is not masked, the microcontroller transfers program execution to the location specified by the INT0 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT0 until the request is acknowledged. INT1/SELECT Maskable Interrupt Request 1 (input, asynchronous) Slave Select (input, asynchronous) INT1—This pin indicates to the microcontroller that an interrupt request has occurred. If INT1 is not masked, the microcontroller transfers program execution to the location specified by the INT1 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT1 until the request is acknowledged. SELECT—When the microcontroller interrupt control unit is operating as a slave to an external interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. The INT0 pin must indicate to the microcontroller that an interrupt has occurred before the SELECT pin indicates to the microcontroller that the interrupt type appears on the bus. INT2/INTA0/PWD/PIO31 Maskable Interrupt Request 2 (input, asynchronous) Interrupt Acknowledge 0 (output, synchronous) Pulse Width Demodulator (input, Schmitt trigger) INT2—This pin indicates to the microcontroller that an interrupt request has occurred. If the INT2 pin is not masked, the microcontroller transfers program execution to the location specified by the INT2 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT2 until the request is acknowledged. INT2 becomes INTA0 when INT0 is configured in cascade mode. 30 INTA0—When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT0. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. PWD—If pulse width demodulation is enabled, PWD processes a signal through the Schmitt trigger. PWD is used internally to drive TIMERIN0 and INT2, and PWD is inverted internally to drive TIMERIN1 and INT4. If INT2 and INT4 are enabled and timer 0 and timer 1 are properly configured, the pulse width of the alternating PWD signal can be calculated by comparing the values in timer 0 and timer 1. In P WD m ode , the si gna ls TIME RIN0/ PIO 11 , TIMERIN1/PIO0, and INT4/PIO30 can be used as PIOs. If they are not used as PIOs they are ignored internally. The level of INT2/INTA0/PWD/PIO31 is reflected in the PIO data register for PIO 31 as if it was a PIO. INT3/INTA1/IRQ Maskable Interrupt Request 3 (input, asynchronous) Interrupt Acknowledge 1 (output, synchronous) Slave Interrupt Request (output, synchronous) INT3—This pin indicates to the microcontroller that an interrupt request has occurred. If the INT3 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT3 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT3 until the request is acknowledged. INT3 becomes INTA1 when INT1 is configured in cascade mode. INTA1—When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT1. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. IRQ—When the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller. Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y INT4/PIO30 Maskable Interrupt Request 4 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT4 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT4 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT4 until the request is acknowledged. When pulse width demodulation mode is enabled, the INT4 signal is used internally to indicate a High-to-Low transition on the PWD signal. When pulse width demodulation mode is enabled, INT4/PIO30 can be used as a PIO. LCS/ONCE0 Lower Memory Chip Select (output, synchronous, internal pullup) ONCE Mode Request 0 (input) LCS—This pin indicates to the system that a memory access is in progress to the lower memory block. The base address and size of the lower memory block are programmable up to 512 Kbytes. On the Am186ES microcontroller, LCS is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. LCS is held High during a bus hold condition. ONCE0—During reset, this pin and ONCE1 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode; otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode, ONCE0 has a weak internal pullup resistor that is active only during reset. This pin is not three-stated during a bus hold condition. MCS0 (MCS0/PIO14) Midrange Memory Chip Select 0 (output, synchronous, internal pullup) This pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. On the Am186ES microcontroller, MCS0 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. MCS0 is held High during a bus hold condition. In addition, it has weak internal pullup resistors that are active during reset. This signal functions like the corresponding signal in the Am186EM and Am188EM microcontrollers except that MCS0 can be programmed as the chip select for the entire middle chip select address range. MCS2–MCS1 (MCS2/PIO24, MCS1/PIO15) Midrange Memory Chip Selects (output, synchronous, internal pullup) These pins indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. On the Am186ES microcontroller, MCS2–MCS1 are configured for 8-bit or 16-bit bus size by the auxiliary configuration register. MCS2–MCS1 are held High during a bus hold condition. In addition, they have weak internal pullup resistors that are active during reset. These signals function like the signals in the Am186EM and Am188EM microcontrollers except that if MCS0 is programmed to be active for the entire middle chipselect range, then these signals are available as PIOs. If they are not programmed as PIOs and if MCS0 is programmed for the whole middle chip-select range, then these signals operate normally. MCS3/RFSH/PIO25 Midrange Memory Chip Select 3 (output, synchronous, internal pullup) Automatic Refresh (output, synchronous) MCS3—This pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. The base address and size of the midrange memory block are programmable. On the Am186ES microcontroller, MCS3 is configured for 8-bit or 16-bit bus size by the auxiliary configuration register. MCS3 is held High during a bus hold condition. In addition, this pin has a weak internal pullup resistor that is active during reset. This signal functions like the corresponding signal in the Am186EM and Am188EM microcontrollers except that if MCS0 is programmed for the entire middle chipselect range, then this signal is available as a PIO. If MCS3 is not programmed as a PIO and if MCS0 is programmed for the entire middle chip-select range, then this signal operates normally. Depending on the chip configuration, this signal can serve as a memory RFSH. RFSH—This pin provides a signal timed for auto refresh to PSRAM or DRAM devices. It is only enabled to function as a refresh pulse when the PSRAM or DRAM mode bit is set. An active Low pulse is Am186/188ES and Am186/188ESLV Microcontrollers 31 P R E L I M I N A R Y generated for 1.5 clock cycles with an adequate deassertion period to ensure that overall auto refresh cycle time is met. byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. This signal functions like the RFSH signal in the Am186EM and Am188EM microcontrollers except that the DRAM row address is not driven on DRAM refreshes. This pin is not three-stated during a bus hold condition. PCS2/CTS1/ENRX1/PIO18 NMI Nonmaskable Interrupt (input, synchronous, edge-sensitive) This pin indicates to the microcontroller that an interrupt request has occurred. The NMI signal is the highest priority hardware interrupt and, unlike the INT6–INT0 pins, cannot be masked. The microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI is asserted. Although NMI is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. There is no bit associated with NMI in the interrupt in-service or interrupt request registers. This means that a new NMI request can interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the IF (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI interrupt service routine, via the STI instruction for example, the fact that an NMI is currently in service does not have any effect on the priority resolution of maskable interrupt requests. For this reason, it is strongly advised that the interrupt service routine for NMI should not enable the maskable interrupts. An NMI transition from Low to High is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. To guarantee that the interrupt is recognized, the NMI pin must be asserted for at least one CLKOUTA period. PCS1–PCS0 (PCS1/PIO17, PCS0/PIO16) Peripheral Chip Selects (output, synchronous) These pins indicate to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS3–PCS0 are held High during a bus hold condition. They are also held High during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256- 32 Peripheral Chip Select 2 (output, synchronous) Clear-to-Send 1 (input, asynchronous) Enable-Receiver-Request 1 (input, asynchronous) PCS2—This pin provides the Peripheral Chip Select 2 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. The PCS2 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS2 is held High during a bus hold or reset condition. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. CTS1—This pin provides the Clear to Send signal for asynchronous serial port 1 when the ENRX1 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The CTS1 signal gates the transmission of data from the associated serial port transmit register. When CTS1 is asserted, the transmitter begins transmission of a frame of data, if any is available. If CTS1 is deasserted, the transmitter holds the data in the serial port transmit register. The value of CTS1 is checked only at the beginning of the transmission of the frame. ENRX1—This pin provides the Enable Receiver Request for asynchronous serial port 1 when the ENRX1 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The ENRX1 signal enables the receiver for the associated serial port. PCS3/RTS1/RTR1/PIO19 Peripheral Chip Select 3 (output, synchronous) Ready-to-Send 1 (output, asynchronous) Ready-to-Receive 1 (output, asynchronous) PCS3—This pin provides the Peripheral Chip Select 3 signal to the system when hardware flow control is not enabled for asynchronous serial port 1. The PCS3 signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS3 is held High during a bus hold or reset condition. Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. RTS1—This pin provides the Ready to Send signal for asynchronous serial port 1 when the RTS1 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The RTS1 signal is asserted when the associated serial port transmit register contains data which has not been transmitted. RTR1—This pin provides the Ready to Receive signal for asynchronous serial port 1 when the RTS1 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 1 control register is set). The RTR1 signal is asserted when the associated serial port receive register does not contain valid, unread data. PCS5/A1/PIO3 Peripheral Chip Select 5 (output, synchronous) Latched Address Bit 1 (output, synchronous) PCS5—This pin indicates to the system that a memory access is in progress to the sixth region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS5 is held High during a bus hold condition. It is also held High during reset. covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. A2—When the EX bit in the MCS and PCS auxiliary register is 0, this pin supplies an internally latched address bit 2 to the system. During a bus hold condition, A2 retains its previously latched value. PIO31–PIO0 (Shared) Programmable I/O Pins (input/output, asynchronous, open-drain) The Am186ES and Am188ES microcontrollers provide 32 individually programmable I/O pins. Each PIO can be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and weak pullup or pulldown. The pins that are multiplexed with PIO31–PIO0 are listed in Table 2 and Table 3. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 and Table 3 lists the defaults for the PIOs. Most of the PIO pins are configured as PIO inputs with pullup after power-on reset. The system initialization code must reconfigure any PIO pins as required. The A19–A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. A1—When the EX bit in the MCS and PCS auxiliary register is 0, this pin supplies an internally latched address bit 1 to the system. During a bus hold condition, A1 retains its previously latched value. PCS6/A2/PIO2 Peripheral Chip Select 6 (output, synchronous) Latched Address Bit 2 (output, synchronous) PCS6—This pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS6 is held High during a bus hold condition or reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range Am186/188ES and Am186/188ESLV Microcontrollers 33 P R E L I M I N A R Y Table 2. Numeric PIO Pin Designations PIO No Associated Pin Power-On Reset Status Table 3. Alphabetic PIO Pin Designations Associated Pin PIO No Power-On Reset Status (1) 7 Normal operation(3) 0 TMRIN1 Input with pullup A17 1 TMROUT1 Input with pulldown A18(1) 8 Normal operation(3) 2 PCS6/A2 Input with pullup A19(1) 9 Normal operation(3) 3 PCS5/A1 Input with pullup CTS0/ENRX0 21 Input with pullup DEN/DS 5 Normal operation(3) Input with pullup operation(3) 4 DT/R Normal 5 DEN/DS Normal operation(3) DRQ0/INT5 12 operation(4) SRDY Normal DRQ1/INT6 13 Input with pullup 7(1) 6 A17 Normal operation(3) DT/R 4 Normal operation(3) 8(1) A18 Normal operation(3) INT2/INTA0/PWD 31 Input with pullup A19 Normal operation(3) INT4 30 Input with pullup 10 TMROUT0 Input with pulldown MCS0 14 Input with pullup 11 TMRIN0 Input with pullup MCS1 15 Input with pullup 12 DRQ0/INT5 Input with pullup MCS2 24 Input with pullup 13 DRQ1/INT6 Input with pullup MCS3/RFSH 25 Input with pullup 14 MCS0 Input with pullup PCS0 16 Input with pullup 15 MCS1 Input with pullup PCS1 17 Input with pullup 16 PCS0 Input with pullup PCS2/CTS1/ENRX1 18 Input with pullup 17 PCS1 Input with pullup PCS3/RTS1/RTR1 19 Input with pullup 18 PCS2/CTS1/ENRX1 Input with pullup PCS5/A1 3 Input with pullup 19 PCS3/RTS1/RTR1 Input with pullup PCS6/A2 2 Input with pullup 20 RTS0/RTR0 Input with pullup RTS0/RTR0 20 Input with pullup 21 CTS0/ENRX0 Input with pullup RXD0 23 Input with pullup 22 TXD0 Input with pullup RXD1 28 Input with pullup 23 RXD0 Input with pullup S6/LOCK/CLKDIV2(1,2) 29 Input with pullup 24 MCS2 Input with pullup SRDY 6 Normal operation(4) 25 MCS3/RFSH Input with pullup TMRIN0 11 Input with pullup 9(1) (1,2) UZI Input with pullup TMRIN1 0 Input with pullup 27 TXD1 Input with pullup TMROUT0 10 Input with pulldown 28 RXD1 Input with pullup TMROUT1 1 Input with pulldown S6/LOCK/CLKDIV2 Input with pullup TXD0 22 Input with pullup 26 (1,2) 29 30 INT4 Input with pullup TXD1 27 Input with pullup 31 INT2/INTA0/PWD Input with pullup UZI(1,2) 26 Input with pullup Notes: The following notes apply to both tables. 1. These pins are used by emulators. (Emulators also use S2–S0, RES, NMI, CLKOUTA, BHE, ALE, AD15–AD0, and A16–A0.) 2. These pins revert to normal operation if BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during power-on reset. 3. When used as a PIO, input with pullup option available. 4. When used as a PIO, input with pulldown option available. 34 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y RD RTS0/RTR0/PIO20 Read Strobe (output, synchronous, three-state) Ready-to-Send 0 (output, asynchronous) Ready-to-Receive 0 (output, asynchronous) RD—This pin indicates to the system that the microcontroller is performing a memory or I/O read cycle. RD is guaranteed to not be asserted before the address and data bus is floated during the address-todata transition. RD floats during a bus hold condition. RES Reset (input, asynchronous, level-sensitive) This pin requires the microcontroller to perform a reset. When RES is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h. RES must be held Low for at least 1 ms. RES can be asserted asynchronously to CLKOUTA because RES is synchronized internally. For proper initialization, VCC must be within specifications, and CLKO UTA mus t be stab le for m ore th an four CLKOUTA periods during which RES is asserted. The microcontroller begins fetching instructions approximately 6.5 CLKOUTA periods after RES is deasserted. This input is provided with a Schmitt trigger to facilitate power-on RES generation via an RC network. RFSH2/ADEN (Am188ES Microcontroller Only) Refresh 2 (three-state, output, synchronous) Address Enable (input, internal pullup) RFSH2—Asserted Low to signify a DRAM refresh bus cycle. The use of RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is selected. Instead, the MCS3/RFSH signal is provided to the PSRAM. ADEN—If RFSH2/ADEN is held High or left floating on power-on reset, the AD bus (AO15–AO8 and AD7– AD0) is enabled or disabled during the address portion of LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. If the DA bit is set, the memory address is accessed on the A19–A0 pins. This mode of operation reduces power consumption. For more information, see the “Bus Operation” section on page 39. There is a weak internal pullup resistor on RFSH2/ADEN so no external pullup is required. If RFSH2/ADEN is held Low on power-on reset, the AD bus drives both addresses and data, regardless of the DA bit setting. The pin is sampled one crystal clock cycle after the rising edge of RES. RFSH2/ADEN is three-stated during bus holds and ONCE mode. RTS0—This pin provides the Ready to Send signal for asynchronous serial port 0 when the RTS0 bit in the AUXCON register is 1 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The RTS0 signal is asserted when the associated serial port transmit register contains data that has not been transmitted. RTR0—This pin provides the Ready to Receive signal for asynchronous serial port 0 when the RTS0 bit in the AUXCON register is 0 and hardware flow control is enabled for the port (FC bit in the serial port 0 control register is set). The RTR0 signal is asserted when the associated serial port receive register does not contain valid, unread data. RXD0/PIO23 Receive Data 0 (input, asynchronous) This pin supplies asynchronous serial receive data from the system to asynchronous serial port 0. RXD1/PIO28 Receive Data 1 (input, asynchronous) This pin supplies asynchronous serial receive data from the system to asynchronous serial port 1. S2–S0 Bus Cycle Status (output, three-state, synchronous) These pins indicate to the system the type of bus cycle in progress. S2 can be used as a logical memory or I/ O indicator, and S1 can be used as a data transmit or receive indicator. S2–S0 float during bus hold and hold acknowledge conditions. The S2–S0 pins are encoded as shown in Table 4. Table 4. Bus Cycle Encoding S2 S1 S0 0 0 0 Interrupt acknowledge 0 0 1 Read data from I/O 0 1 0 Write data to I/O 0 1 1 Halt 1 0 0 Instruction fetch 1 0 1 Read data from memory 1 1 0 Write data to memory 1 1 1 None (passive) Am186/188ES and Am186/188ESLV Microcontrollers Bus Cycle 35 P R E L I M I N A R Y S6/LOCK/CLKDIV2/PIO29 TMRIN1/PIO0 Bus Cycle Status Bit 6 (output, synchronous) Bus Lock (output, synchronous) Clock Divide by 2 (input, internal pullup) Timer Input 1 (input, synchronous, edge-sensitive) S6—During the second and remaining periods of a cycle (t2, t3, and t4), this pin is asserted High to indicate a DMA-initiated bus cycle. During a bus hold or reset condition, S6 floats. LOCK—This signal is asserted Low to indicate to other system bus masters that they are not to gain control of the system bus. This signal is only available during t1. LOCK on the Am186ES and Am188ES microcontrollers does not conform to the timing of the LOCK signal on the 80C186/188 microcontrollers. This signal is primarily intended for use by emulators. CLKDIV2—If S6/CLKDIV2/PIO29 is held Low during power-on reset, the chip enters clock divided by 2 mode where the processor clock is derived by dividing the external clock input by 2. If this mode is selected, the PLL is disabled. The pin is sampled on the rising edge of RES. If S6 is to be used as PIO29 in input mode, the device driving PIO29 must not drive the pin Low during poweron reset. S6/CLKDIV2/PIO29 defaults to a PIO input with pullup, so the pin does not need to be driven High externally. SRDY/PIO6 Synchronous Ready (input, synchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active High input synchronized to CLKOUTA. Using SRDY instead of ARDY allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ARDY. To always assert the ready condition to the microcontroller, tie SRDY High. If the system does not use SRDY, tie the pin Low to yield control to ARDY. TMRIN0/PIO11 Timer Input 0 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 0. After internally synchronizing a Low-to-High transition on TMRIN0, the microcontroller increments the timer. TMRIN0 must be tied High if not being used. When PIO11 is enabled, TMRIN0 is pulled High internally. TMRIN0 is driven internally by INT2/INTA0/PWD when pulse width demodulation mode is enabled. The TMRIN0/PIO11 pin can be used as a PIO when pulse width demodulation mode is enabled. 36 This pin supplies a clock or control signal to the internal microcontroller timer 1. After internally synchronizing a Low-to-High transition on TMRIN1, the microcontroller increments the timer. TMRIN1 must be tied High if not being used. When PIO0 is enabled, TMRIN1 is pulled High internally. TMRIN1 is driven internally by INT2/INTA0/PWD when pulse width demodulation mode is enabled. The TMRIN1/PIO0 pin can be used as a PIO when pulse width demodulation mode is enabled. TMROUT0/PIO10 Timer Output 0 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT0 is floated during a bus hold or reset. TMROUT1/PIO1 Timer Output 1 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT1 floats during a bus hold or reset. TXD0/PIO22 Transmit Data 0 (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from serial port 0. TXD1/PIO27 Transmit Data 1 (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from serial port 1. UCS/ONCE1 Upper Memory Chip Select (output, synchronous) ONCE Mode Request 1 (input, internal pullup) UCS—This pin indicates to the system that a memory access is in progress to the upper memory block. The base address and size of the upper memory block are programmable up to 512 Kbytes. UCS is held High during a bus hold condition. After reset, UCS is active for the 64 Kbyte memory range from F0000h to FFFFFh, including the reset address of FFFF0h. ONCE1—During reset, this pin and LCS/ONCE0 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode. Otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the micro- Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y controller does not inadvertently enter ONCE mode, ONCE1 has a weak internal pullup resistor that is active only during a reset. This pin is not three-stated during a bus hold condition. UZI/PIO26 Upper Zero Indicate (output, synchronous) This pin lets the designer determine if an access to the interrupt vector table is in progress by ORing it with bits 15–10 of the address and data bus (AD15–AD10 on the 186 and AO15–AO10 on the 188). UZI is the logical OR of the inverted A19–A16 bits. It asserts in the first period of a bus cycle and is held throughout the cycle. This pin should be allowed to float or it should be pulled High at reset. This pin has an internal pullup. If this pin is Low at the negation of reset, the Am186ES and Am188ES microcontrollers will enter a reserved clock test mode. VCC Power Supply (input) These pins supply power (+5 V) to the microcontroller. WHB (Am186ES Microcontroller Only) WR Write Strobe (output, synchronous) WR—This pin indicates to the system that the data on the bus is to be written to a memory or I/O device. WR floats during a bus hold or reset condition. X1 Crystal Input (input) This pin and the X2 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, connect the source to the X1 pin and leave the X2 pin unconnected. X2 Crystal Output (output) This pin and the X1 pin provide connections for a fundamental mode or third-overtone, parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, leave the X2 pin unconnected and connect the source to the X1 pin. Write High Byte (output, three-state, synchronous) This pin and WLB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 microcontroller designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WHB is asserted with AD15–AD8. WHB is the logical OR of BHE and WR. This pin floats during reset. WLB (Am186ES Microcontroller Only) WB (Am188ES Microcontroller Only) Write Low Byte (output, three-state, synchronous) Write Byte (output, three-state, synchronous) WLB—This pin and WHB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 microcontroller designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WLB is asserted with AD7–AD0. WLB is the logical OR of AD0 and WR. This pin floats during reset. WB—On the Am188ES microcontroller, this pin indicates a write to the bus. WB uses the same early timing as the nonmultiplexed address bus. WB is associated with AD7–AD0. This pin floats during reset. Am186/188ES and Am186/188ESLV Microcontrollers 37 P R E L I M I N A R Y FUNCTIONAL DESCRIPTION The Am186ES and Am188ES microcontrollers are based on the architecture of the original Am186 and Am188 microcontrollers—the 80C186 and 80C188 microcontrollers. The Am186ES and Am188ES microcontrollers function in the enhanced mode of earlier generations of Am186 and Am188 microcontrollers. Enhanced mode includes system features such as power-save control. Each of the 8086, 8088, 80186, and 80188 microcontrollers contains the same basic set of registers, instructions, and addressing modes. The Am186ES and Am188ES microcontrollers are backward compatible with the 80C186 and 80C188 microcontrollers. A full description of all the Am186ES and Am188ES microcontroller registers and instructions is included in the Am186ES and Am188ES Microcontrollers User’s Manual, order# 21096. Memory Organization Shift Left 4 Bits 1 2 A 4 19 1 15 2 A 0 15 0 2 4 Segment Logical 0 Base Address 2 Offset 0 0 0 0 0 15 0 1 2 A 2 6 19 2 0 2 Physical Address 0 To Memory Memory is organized in sets of segments. Each segment is a linear contiguous sequence of 64K (216) 8-bit bytes. Memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. The 16-bit segment values are contained in one of four internal segment registers (CS, DS, SS, or ES). The physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 3). This allows for a 1-Mbyte physical address size. All instructions that address operands in memory must specify the segment value and the 16-bit offset value. For speed and compact instruction encoding, the seg- Table 5. 38 ment register used for physical address generation is implied by the addressing mode used (see Table 5). Figure 3. Two-Component Address I/O Space The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions (IN, INS and OUT, OUTS) address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register. Eight-bit port addresses are zero-extended such that A15–A8 are Low. I/O port addresses 00F8h through 00FFh are reserved. Segment Register Selection Rules Memory Reference Needed Segment Register Used Instructions Code (CS) Instructions (including immediate data) Local Data Data (DS) All data references Stack Stack (SS) All stack pushes and pops; any memory references that use BP Register External Data (Global) Extra (ES) All string instruction references that use the DI Register as an index Implicit Segment Selection Rule Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y BUS OPERATION The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t1 clock phase. The Am186ES and Am188ES microcontrollers continue to provide the multiplexed AD bus and, in addition, provide a nonmultiplexed address (A) bus. The A bus provides an address to the system for the complete bus cycle (t1–t4). For systems where power consumption is a concern, it is possible to disable the address from being driven on the AD bus on the Am186ES microcontroller and on the AD and AO buses on the Am188ES microcontroller during the normal address portion of the bus cycle for accesses to UCS and/or LCS address spaces. In this mode, the affected bus is placed in a high-impedance state during the address portion of the bus cycle. This feature is enabled through the DA bits in the UMCS and LMCS registers. When address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, decreasing power consumption and reducing processor switching noise. On the Am188ES microcontroller, the address is driven on A015–A08 during the data portion of the bus cycle regardless of the setting of the DA bits. If the ADEN pin is pulled Low during processor reset, the value of the DA bits in the UMCS and LMCS registers is ignored and the address is driven on the AD bus t1 for all accesses, thus preserving the industry-standard 80C186 and 80C188 microcontrollers’ multiplexed address bus and providing support for existing emulation tools. The following diagrams show the Am186ES and AM188ES microcontroller bus cycles when the address bus disable feature is in effect: n Figure 4 shows the affected signals during a normal read or write operation for an Am186ES microcontroller. The address and data are multiplexed onto the AD bus. n Figure 5 shows an Am186ES microcontroller bus cycle when address bus disable is in effect. This results in the AD bus operating in a nonmultiplexed address/data mode. The A bus has the address during a read or write operation. n Figure 6 shows the affected signals during a normal read or write operation for an Am188ES microcontroller. The multiplexed address/data mode is compatible with the 80C186 and 80C188 microcontrollers and might be used to take advantage of existing logic or peripherals. n Figure 7 shows an Am188ES microcontroller bus cycle when address bus disable is in effect. The address and data is not multiplexed. The AD7–AD0 signals have only data on the bus, while the AO bus has the address during a read or write operation. t2 Address Phase t3 t4 Data Phase CLKOUTA Address A19–A0 AD15–AD0 (Read) Address AD15–AD0 (Write) Address Data Data LCS or UCS MCSx, PCSx Figure 4. Am186ES Microcontroller Address Bus—Normal Read and Write Operation Am186/188ES and Am186/188ESLV Microcontrollers 39 P R E L I M I N A R Y t1 Address Phase t2 t3 Data Phase t4 CLKOUTA A19–A0 Address AD15–AD0 (Read) Data AD15–AD0 (Write) Data LCS, UCS MCSx, PCSx Figure 5. Am186ES Microcontroller—Read and Write with Address Bus Disable In Effect t1 t2 t3 Address Phase t4 Data Phase CLKOUTA Address A19–A0 AD7–AD0 (Read) Address AO15–AO8 (Read or Write) AD7–AD0 (Write) Data Address Address Data LCS or UCS MCSx, PCSx Figure 6. 40 Am188ES Microcontroller Address Bus—Normal Read and Write Operation Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y t1 t2 Address Phase t3 t4 Data Phase CLKOUTA A19–A0 Address AD7–AD0 (Read) Data AO15–AO8 Address AD7–AD0 (Write) Data LCS, UCS MCSx, PCSx Figure 7. Am188ES Microcontroller—Read and Write with Address Bus Disable In Effect BUS INTERFACE UNIT Nonmultiplexed Address Bus The bus interface unit controls all accesses to external peripherals and memory devices. External accesses include those to memory devices, as well as those to memory-mapped and I/O-mapped peripherals and the peripheral control block. The Am186ES and Am188ES microcontrollers provide an enhanced bus interface unit with the following features: The nonmultiplexed address bus (A19–A0) is valid onehalf CLKOUTA cycle in advance of the address on the AD bus. When used in conjunction with the modified UCS and LCS outputs and the byte-write enable signals, the A19–A0 bus provides a seamless interface to SRAM, PSRAM, and Flash EPROM memory systems. n A nonmultiplexed address bus n On the Am186ES microcontroller, a static bus-sizing option for 8-bit and 16-bit memory and I/O n Separate byte write enables for high and low bytes in the Am186ES microcontroller only n Pseudo Static RAM (PSRAM) support The standard 80C186/188 microcontroller multiplexed address and data bus requires system interface logic and an external address latch. On the Am186ES and Am188ES microcontrollers, new byte write enables, PSRAM control logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic. Static Bus Sizing The 80C186 microcontroller provided a 16-bit wide data bus over its entire address range, memory, and I/O, but did not allow accesses to an 8-bit wide bus. The 80C188 microcontroller provided a lower-cost interface by reducing the data bus width to 8 bits, again over the entire address range. The Am188ES microcontroller follows the 80C188 microcontroller in providing an 8-bit data bus to all memory and peripherals. However, the Am186ES microcontroller differs from the 80C186 microcontroller in allowing programmability for data bus widths through fields in the auxiliary configuration (AUXCON) register, as shown in Table 6. The width of the data access should not be modified while the processor is fetching instructions from the associated address space. Am186/188ES and Am186/188ESLV Microcontrollers 41 P R E L I M I N A R Y Table 6. Programming Am186ES Microcontroller Bus Width Space AUXCON Field Value Bus Width UCS – – 16 bits not configurable LCS LSIZ 0 16 bits default 1 8 bits 0 16 bits 1 8 bits 0 16 bits 1 8 bits I/O Other IOSIZ MSIZ Comments default default Byte-Write Enables The Am186ES microcontroller provides the WHB (Write High Byte) and WLB (Write Low Byte) signals, which act as byte-write enables. WHB is the logical OR of BHE and WR. WHB is Low when BHE and WR are both Low. WLB is the logical OR of A0 and WR. WLB is Low when A0 and WR are both Low. WB is Low whenever a byte is written on the Am188ES microcontroller. On the Am188ES microcontroller, the WB (Write Byte) pin indicates a write to the bus. WB uses the same early timing as the nonmulitplexed address bus. WB is associated with AD7–-AD0. This pin floats during reset. The byte-write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common SRAMs. Pseudo Static RAM (PSRAM) Support The Am186ES and Am188ES microcontrollers support the use of PSRAM devices in low memory chip-select (LCS) space only. When PSRAM mode is enabled, the timing for the LCS signal is modified by the chip-select control unit to provide a CS precharge period during PS RA M a cc e ss es . T h e 4 0- MH z t im in g o f the Am186ES and Am188ES microcontrollers is appropriate to allow 70-ns PSRAM to run with one wait state. PSRAM mode is enabled through a bit in the Low Memory Chip-Select (LMCS) register. The PSRAM feature is disabled on CPU reset. In addition to the LCS timing changes for PSRAM precharge, the PSRAM devices also require periodic refresh of all internal row addresses to retain their data. Although refresh of PSRAM can be accomplished several ways, the Am186ES and Am188ES microcontrollers implement auto refresh only. when PSRAM mode and the refresh control unit are enabled. No refresh address is required by the PSRAM when using the auto refresh mechanism. The RFSH signal is multiplexed with the MCS3 signal pin. When PSRAM mode is enabled, MCS3 is not available for use as a chip-select signal. The refresh control unit must be programmed before accessing PSRAM in LCS space. The refresh counter in the clock prescaler (CDRAM) register must be configured with the required refresh interval value. The ending address of LCS space and the ready and waitstate generation in the LMCS register must also be programmed. The refresh counter reload value in the CDRAM register should not be set to less than 18 (12h) in order to provide time for processor cycles within refresh. The refresh address counter must be set to 000000h to prevent another chip select from asserting. LCS is held High during a refresh cycle. The A bus is not used during refresh cycles. The LMCS register must be configured to external ready ignored (R2=1) with one wait state (R1–R0=01b), and the PSRAM mode enable bit (PSE) must be set to 1. PERIPHERAL CONTROL BLOCK (PCB) The integrated peripherals of the Am186ES and Am188ES microcontrollers are controlled by 16-bit read/write registers. The peripheral registers are contained within an internal 256-byte control block. The registers are physically located in the peripheral devices they control, but they are addressed as a single 256-byte block. Table 7 shows a map of these registers. Reading and Writing the PCB Code that is intended to execute on the Am188ES microcontroller should perform all writes to the PCB registers as byte writes. These writes transfer 16 bits of data to the PCB register even if an 8-bit register is named in the instruction. For example, out dx, al results in the value of ax being written to the port address in dx. Reads to the PCB should be done as word reads. Code written in this manner runs correctly on the Am188ES microcontroller and on the Am186ES microcontroller. Unaligned reads and writes to the PCB result in unpredictable behavior on both the Am186ES and Am188ES microcontrollers. For a complete description of all the registers in the PCB, see the Am186ES and Am188ES Microcontrollers User’s Manual, order# 21096. The Am186ES and Am188ES microcontrollers generate a refresh signal, RFSH, to the PSRAM devices 42 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Table 7. Peripheral Control Block Register Map Register Name Register Name Timer 2 max count compare A register 62h Timer 2 count register 60h Offset Processor Control Registers: Offset Peripheral control block relocation register FEh Timer 1 mode/control register 5Eh Reset configuration register F6h Timer 1 max count compare B register 5Ch F4h Timer 1 max count compare A register 5Ah Processor release level register 1 2 F2h Timer 1 count register 58h System configuration register 1 F0h Timer 0 mode/control register 56h Watchdog timer control register 2 E6h Timer 0 max count compare B register 54h E4h Timer 0 max count compare A register 52h Clock prescaler register E2h Timer 0 count register 50h Memory partition register E0h Interrupt Registers: Auxiliary configuration register Enable RCU register 1 DMA Registers: 1 Serial port 0 interrupt control register 1 44h 2 42h DAh Serial port 1 interrupt control register DMA 1 transfer count register D8h INT4 interrupt control register DMA 1 destination address high register D6h INT3 control register 3Eh DMA 1 destination address low register D4h INT2 control register 3Ch DMA 1 source address high register D2h INT1 control register 3Ah DMA 1 source address low register D0h INT0 control register DMA 0 control register 1 CAh DMA1/INT6 interrupt control register 1 36h DMA 0 transfer count register C8h DMA0/INT5 interrupt control register 1 34h DMA 0 destination address high register C6h Timer interrupt control register 32h DMA 0 destination address low register C4h Interrupt status register 30h DMA 0 source address high register C2h Interrupt request register DMA 0 source address low register C0h Interrupt in-service register 1 2Ch Interrupt priority mask register 2Ah DMA 1 control register Chip-Select Registers: 40h 38h 1 2Eh 1 PCS and MCS auxiliary register A8h Interrupt mask register Midrange memory chip-select register A6h Interrupt poll status register 26h Peripheral chip-select register A4h Interrupt poll register 24h 1 A2h End-of-interrupt register 22h Upper memory chip-select register A0h Interrupt vector register 20h Low memory chip-select register Serial Port 0 Registers: Serial Port 1 Registers: Serial port 0 baud rate divisor register 1 Serial port 0 receive register 28h 1 88h 86h 1 Serial port 1 baud rate divisor register 2 Serial port 1 receive register 2 84h Serial port 1 transmit register Serial port 0 status register 1 82h Serial port 1 status register 2 Serial port 0 control register 1 80h Serial port 1 control register 2 Serial port 0 transmit register PIO Registers: 2 18h 16h 14h 12h 10h Notes: PIO data 1 register 7Ah PIO direction 1 register 78h 1. The register has been changed from the Am186EM and Am188EM microcontrollers. PIO mode 1 register 76h 2. The register is new. PIO data 0 register 74h PIO direction 0 register 72h PIO mode 0 register 70h Note: All unused addresses are reserved and should not be accessed. Timer Registers: Timer 2 mode/control register 66h Am186/188ES and Am186/188ESLV Microcontrollers 43 P R E L I M I N A R Y CLOCK AND POWER MANAGEMENT The clock and power management unit of the Am186ES and Am188ES microcontrollers includes a phase-locked loop (PLL) and a second programmable system clock output (CLKOUTB). the output of the amplifier and negatively affects the operation of the clock generator. Values for the loading on X1 and X2 must be chosen to provide the necessary phase shift and crystal operation. Phase-Locked Loop (PLL) Selecting a Crystal In a traditional 80C186/188 microcontroller design, the crystal frequency is twice that of the desired internal clock. Because of the internal PLL on the Am186ES and Am188ES microcontrollers, the internal clock generated by the Am186ES and Am188ES microcontrollers (CLKOUTA) is the same frequency as the crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45–55% (worst case) duty cycle intermediate system clock of the same frequency. This removes the need for an external 2x oscillator, reducing system cost. The PLL is reset during power-on reset by an onchip power-on reset (POR) circuit. When selecting a crystal, the load capacitance should always be specified (CL). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the loading of the feedback network have the following relationship: (C1 ⋅ C2) CL = + CS (C1 + C2) Crystal-Driven Clock Source The internal oscillator circuit of the Am186ES and Am188ES microcontrollers is designed to function with a parallel resonant fundamental or third overtone crystal. Because of the PLL, the crystal frequency should be equal to the processor frequency. Do not replace a crystal with an LC or RC equivalent. where CS is the stray capacitance of the circuit. Placing the crystal and CL in series across the inverting amplifier and tuning these values (C1, C2) allows the crystal to oscillate at resonance. This relationship is true for both fundamental and third-overtone operation. Finally, there is a relationship between C1 and C2. To enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (X2). Equal values of these loads tend to balance the poles of the inverting amplifier. The signals X1 and X2 are connected to an internal inverting amplifier (oscillator) that provides, along with the external feedback loading, the necessary phase shift (Figure 8). In such a positive feedback circuit, the inverting amplifier has an output signal (X2) 180 degrees out of phase of the input signal (X1). The characteristics of the inverting amplifier set limits on the following parameters for crystals: The external feedback network provides an additional 180-degree phase shift. In an ideal system, the input to X1 will have 360 or zero degrees of phase shift. The external feedback network is designed to be as close to ideal as possible. If the feedback network is not providing necessary phase shift, negative feedback dampens C1 ..................................................................15 pF ± 20% C2 ..................................................................22 pF ± 20% ESR (Equivalent Series Resistance) ......40 Ω max Drive Level ..............................................1 mW max The recommended range of values for C1 and C2 are as follows: The specific values for C1 and C2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. C1 X1 Crystal X2 Crystal C1 C2 C2 a. Inverting Amplifier Configuration Note 1 Note 1: Use for Third Overtone Mode XTAL Frequency L1 Value (Max) 20 MHz 12 µH ±20% 25 MHz 8.2 µH ±20% 33 MHz 4.7 µH ±20% 40 MHz 3.0 µH ±20% Am186ES Microcontroller 200 pF b. Crystal Configuration Figure 8. Am186ES and Am188ES Microcontrollers Oscillator Configurations 44 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y External Source Clock Initialization and Processor Reset Alternately, the internal oscillator can be driven from an external clock source. This source should be connected to the input of the inverting amplifier (X1), with the output (X2) not connected. Processor initialization or startup is accomplished by driving the RES input pin Low. RES must be held Low for 1 ms during power-up to ensure proper device initialization. RES forces the Am186ES and Am188ES microcontrollers to terminate all execution and local bus activity. No instruction or bus activity occurs as long as RES is active. After RES becomes inactive and an internal processing interval elapses, the microcontroller begins execution with the instruction at physical location FFFF0h, with UCS asserted with three wait states. RES also sets some registers to predefined values and resets the watchdog timer. System Clocks The base system clock of AMD’s original 80C186 and 80C188 microcontrollers is renamed CLKOUTA and the additional output is called CLKOUTB. CLKOUTA and CLKOUTB operate at either the processor frequency or the PLL frequency. The output drivers for both clocks are individually programmable for disable. Figure 9 shows the organization of the clocks. The second clock output (CLKOUTB) allows one clock to run at the PLL frequency and the other clock to run at the power-save frequency. Individual drive enable bits allow selective enabling of just one or both of these clock outputs. Power-Save Operation The power-save mode of the Am186ES and Am188ES microcontrollers reduces power consumption and heat dissipation, thereby extending battery life in portable systems. In power-save mode, operation of the CPU and internal peripherals continues at a slower clock frequency. When an interrupt occurs, the microcontroller automatically returns to its normal operating frequency on the internal clock’s next rising edge of t3. Note: Power-save operation requires that clock-dependent devices be reprogrammed for clock frequency changes. Software drivers must be aware of clock frequency. The Reset Configuration Register When the RES input is asserted Low, the contents of the address/data bus (AD15–AD0) are written into the reset configuration register. The system can place configuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. The processor does not drive the address/data bus during reset. For example, the reset configuration register could be used to provide the software with the position of a configuration switch in the system. Using weak external pullup and pulldown resistors on the address and data bus, the system can provide the microcontroller with a value corresponding to the position of the jumper during a reset. Processor Internal Clock PLL X1, X2 Power-Save Divisor (/2 to /128) CLKOUTA Mux Drive Enable Mux Time Delay 6 ± 2.5ns CLKOUTB Drive Enable Figure 9. Clock Organization Am186/188ES and Am186/188ESLV Microcontrollers 45 P R E L I M I N A R Y CHIP-SELECT UNIT The Am186ES and Am188ES microcontrollers contain logic that provides programmable chip-select generation for both memories and peripherals. The logic can be programmed to provide ready and wait-state generation and latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit. The Am186ES and Am188ES microcontrollers provide six chip-select outputs for use with memory devices and six more for use with peripherals in either memory space or I/O space. The six memory chip selects can be used to address three memory ranges. Each peripheral chip select addresses a 256-byte block that is offset from a programmable base address. A write to a chip select register will enable the corresponding chip select logic even if the actual pin has another function (e.g., PIO). Chip-Select Timing The timing for the UCS and LCS outputs is modified from the original 80C186 microcontroller. These outputs now assert in conjunction with the nonmultiplexed address bus for normal memory timing. To allow these outputs to be available earlier in the bus cycle, the number of programmable memory size selections has been reduced. Ready and Wait-State Programming The Am186ES and Am188ES microcontrollers can be programmed to sense a ready signal for each of the peripheral or memory chip-select lines. The ready signal can be either the ARDY or SRDY signal. Each chipselect control register (UMCS, LMCS, MMCS, PACS, and MPCS) contains a single-bit field that determines whether the external ready signal is required or ignored. The number of wait states to be inserted for each access to a peripheral or memory region is programmable. The chip-select control registers for UCS, LCS, MCS3–MCS0, PCS6, and PCS5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. PCS3–PCS0 use three bits to provide additional values of 5, 7, 9, and 15 wait states. When external ready is required, internally programmed wait states will always complete before external ready can terminate or extend a bus cycle. For example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. If external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). If external ready is not asserted during the first wait cycle, the access is extended until ready is asserted, and one more wait state occurs followed by t4. 46 The ARDY signal on the Am186ES and Am188ES microcontrollers is a true asynchronous ready signal. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and is active High. If the falling edge of ARDY is not synchronized to CLKOUTA as specified, an additional clock period may be added. Chip-Select Overlap Although programming the various chip selects on the Am186ES microcontroller so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some systems. In such systems, the chip selects whose assertions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. The peripheral control block (PCB) is accessed using internal signals. These internal signals function as chip selects configured with zero wait states and no external ready. Therefore, the PCB can be programmed to addresses that overlap external chip-select signals only if those external chip selects are programmed to zero wait states with no external ready required. When overlapping an additional chip select with either the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS register disables the address from being driven on the AD bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. The MCS and PCS chip-select pins can be configured as either chip selects (normal function) or as PIO inputs or outputs. It should be noted; however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip selects or PIOs. This means that if these chip selects are enabled (by a write to the MMCS and MPCS for the MCS chip selects, or by a write to the PACS and MPCS registers for the PCS chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. Although the PCS4 signal is not available on an external pin, the ready and wait state logic for this signal still exists internal to the part. For this reason, the PCS4 address space must follow the rules for overlapping chip selects. The ready and wait-state logic for PCS6– PCS5 is disabled when these signals are configured as address bits A2–A1. Failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y for a ready signal. This behavior may occur even in a system in which ready is always asserted (ARDY or SRDY tied High). Configuring PCS in I/O space with LCS or any other chip select configured for memory address 0 is not considered overlapping of the chip selects. Overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. Upper Memory Chip Select The Am186ES and Am188ES microcontrollers provide a UCS chip select for the top of memory. On reset the Am186ES and Am188ES microcontrollers begin fetching and executing instructions at memory location FFFF0h. Therefore, upper memory is usually used as instruction memory. To facilitate this usage, UCS defaults to active on reset, with a default memory range of 64 Kbytes from F0000h to FFFFFh, with external ready required and three wait states automatically inserted. The UCS memory range always ends at FFFFFh. The UCS lower boundary is programmable. Low Memory Chip Select The Am186ES and Am188ES microcontrollers provide an LCS chip select for lower memory. The AUXCON register can be used to configure LCS for 8-bit or 16-bit accesses. Since the interrupt vector table is located at the bottom of memory starting at 00000h, the LCS pin is usually used to control data memory. The LCS pin is not active on reset. Midrange Memory Chip Selects The Am186ES and Am188ES microcontrollers provide four chip selects, MCS3–MCS0, for use in a user-locatable memory block. With some exceptions, the base address of the memory block can be located anywhere within the 1-Mbyte memory address space of the Am186ES and Am188ES microcontrollers. The areas associated with the UCS and LCS chip selects are excluded. If they are mapped to memory, the address range of the peripheral chip selects, PCS6, PCS5, and PCS3–PCS0, are also excluded. The MCS address range can overlap the PCS address range if the PCS chip selects are mapped to I/O space. MCS0 can be configured to be asserted for the entire MCS range. When configured in this mode, the MCS3– MCS1 pins can be used as PIOs. The AUXCON register can be used to configure MCS for 8-bit or 16-bit accesses. The bus width of the MCS range is determined by the width of the non-UCS/nonLCS memory range. Peripheral Chip Selects The Am186ES and Am188ES microcontrollers provide six chip selects, PCS6–PCS5 and PCS3–PCS0, for use within a user-configured memory or I/O block. PCS4 is not available on the Am186ES and Am188ES microcontrollers. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS, LCS, and MCS chip selects, or they can be configured to access the 64-Kbyte I/O space. The PCS pins are not active on reset. PCS6–PCS5 can be programmed for zero to three wait states. PCS3– PCS0 can be programmed for four additional wait-state values: 5, 7, 9, and 15. The AUXCON register can be used to configure PCS for 8-bit or 16-bit accesses. The bus width of the PCS range is determined by the width of the non-UCS/nonLCS memory range or by the width of the I/O area. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186/188 microcontrollers. REFRESH CONTROL UNIT The Refresh Control Unit (RCU) automatically generates refresh bus cycles. After a programmable period of time, the RCU generates a memory read request to the bus interface unit. The RCU is fixed to three wait states for the PSRAM auto refresh mode. In the Am186ES and Am188ES microcontrollers, refresh is enabled when the ENA bit is set in the enable RCU register, offset E4h. This is different from the Am186EM and Am188EM microcontrollers where the PSRAM enable bit in the low memory chip-select register, offset A2h, enables refresh. The refresh function is the same as on the Am186EM and Am188EM microcontrollers, except that the DRAM address is not driven on DRAM refreshes. If the HLDA pin is active when a refresh request is generated (indicating a bus hold condition), the Am186ES and Am188ES microcontrollers deactivate the HLDA pin in order to perform a refresh cycle. The external bus master must remove the HOLD signal for at least one clock in order to allow the refresh cycle to execute. Unlike the UCS and LCS chip selects, the MCS outputs assert with the same timing as the multiplexed AD address bus. Am186/188ES and Am186/188ESLV Microcontrollers 47 P R E L I M I N A R Y INTERRUPT CONTROL UNIT TIMER CONTROL UNIT The Am186ES and Am188ES microcontrollers can receive interrupt requests from a variety of sources, both internal and external. The internal interrupt controller arranges these requests by priority and presents them one at a time to the CPU. There are three 16-bit programmable timers and a watchdog timer on the Am186ES and Am188ES microcontrollers. There are up to eight external interrupt sources on the Am186ES and Am188ES microcontrollers—seven maskable interrupt pins and one nonmaskable interrupt (NMI) pin. In addition, there are eight internal interrupt sources (three timers, two DMA channels, the two asynchronous serial ports, and the Watchdog Timer NMI) that are not connected to external pins. INT5 and INT6 are multiplexed with DRQ0 and DRQ1. These two interrupts are available if the associated DMA is not enabled or is being used with internal synchronization. The Am186ES and Am188ES microcontrollers provide up to six interrupt sources not present on the 80C186 and 80C188 microcontrollers. There are up to three additional external interrupt pins—INT4, INT5, and INT6. These pins operate much like the INT3–INT0 interrupt pins on the 80C186 and 80C188 microcontrollers. There are also two internal interrupts from the serial ports and the watchdog timer can generate interrupts. The seven maskable interrupt request pins can be used as direct interrupt requests. INT4–INT0 can be either edge triggered or level triggered. INT6 and INT5 are edge triggered only. In addition, INT0 and INT1 can be configured in cascade mode for use with an external 82C59A-compatible interrupt controller. When INT0 is configured in cascade mode, the INT2 pin is automatically configured in its INTA0 function. When INT1 is configured in cascade mode, the INT3 pin is automatically configured in its INTA1 function. An external interrupt controller can be used as the system master by programming the internal interrupt controller to operate in slave mode. INT6–INT4 are not available in slave mode. Interrupts are automatically disabled when an interrupt is taken. Interrupt-service routines (ISRs) may re-enable interrupts by setting the IF flag. This allows interrupts of greater or equal priority to interrupt the currently executing ISR. Interrupts from the same source are disabled as long as the corresponding bit in the interrupt in-service register is set. INT1 and INT0 provide a special bit to enable special fully nested mode. When configured in special fully nested mode, the interrupt source may generate a new interrupt regardless of the setting of the in-service bit. 48 Timer 0 and timer 1 are connected to four external pins (each one has an input and an output). These two timers can be used to count or time external events, or to generate nonrepetitive or variable-duty-cycle waveforms. When pulse width demodulation is enabled, timer 0 and timer 1 are used to measure the width of the High and Low pulses on the PWD pin. (See the Pulse Width Demodulation section on page 51.) Timer 2 is not connected to any external pins. It can be used for real-time coding and time-delay applications. It can also be used as a prescaler to timers 0 and 1 or to synchronize DMA transfers. The programmable timers are controlled by eleven 16bit registers in the peripheral control block. A timer’s timer-count register contains the current value of that timer. The timer-count register can be read or written with a value at any time, whether the timer is running or not. The microcontroller increments the value of the timer-count register each time a timer event occurs. Each timer also has a maximum-count register that defines the maximum value the timer can reach. When the timer reaches the maximum value, it resets to 0 during the same clock cycle. The value in the maximum-count register is never stored in the timer-count register. Also, timers 0 and 1 have a secondary maximum-count register. Using both the primary and secondary maximum-count registers lets the timer alternate between two maximum values. If the timer is programmed to use only the primary maximum-count register, the timer output pin switches Low for one clock cycle after the maximum value is reached. If the timer is programmed to use both of its maximum-count registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. The duty cycle of the waveform depends on the values in the maximumcount registers. Each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter of the internal clock frequency. A timer can be clocked externally at this same frequency; however, because of internal synchronization and pipelining of the timer circuitry, the timer output can take up to six clock cycles to respond to the clock or gate input. Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Watchdog Timer DIRECT MEMORY ACCESS (DMA) The Am186ES and Am188ES microcontrollers provide a true watchdog timer function. The Watchdog Timer (WDT) can be used to regain control of the system when software fails to respond as expected. The WDT is active after reset. It can only be modified a single time by a keyed sequence of writes to the watchdog timer control register (WDTCON) following reset. This single write can either disable the timer or modify the timeout period and the action taken upon timeout. A keyed sequence is also required to reset the current WDT count. This behavior ensures that randomly executing code will not prevent a WDT event from occurring. Direct memory access (DMA) permits transfer of data between memory and peripherals without CPU involvement. The DMA unit in the Am186ES and Am188ES microcontrollers, shown in Figure 10, provides two high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., memory to I/O) or within the same space (e.g., memory to memory or I/O to I/O). The DMA channels can be directly connected to the asynchronous serial ports. The WDT supports up to a 1.67-second timeout period in a 40-MHz system. After reset, the WDT is enabled and the timeout period is set to its maximum value. The WDT can be configured to cause either an NMI interrupt or a system reset upon timeout. If the WDT is configured for NMI, the NMIFLAG in the WDTCON register is set when the NMI is generated. The NMI interrupt service routine (ISR) should examine this flag to determine if the interrupt was generated by the WDT or by an external source. If the NMIFLAG is set, the ISR should clear the flag by writing the correct keyed sequence to the WDTCON register. If the NMIFLAG is set when a second WDT timeout occurs, a WDT system reset is generated rather than a second NMI event. When the processor takes a WDT reset, either due to a single WDT event with the WDT configured to generate resets or due to a WDT event with the NMIFLAG set, the RSTFLAG in the WDTCON register is set. This allows system initialization code to differentiate between a hardware reset and a WDT reset and take appropriate action. The RSTFLAG is cleared when the WDTCON register is read or written. The processor does not resample external pins during a WDT reset. This means that the clocking, the reset configuration register, and any other features that are user-selectable during reset do not change when a WDT system reset occurs. All other activities are identical to those of a normal system reset. Note: The Watchdog Timer (WDT) is active after reset. Either bytes or words can be transferred to or from even or odd addresses on the Am186ES microcontroller. However, the Am186ES microcontroller does not support word DMA transfers to or from memory configured for 8-bit accesses. The Am188ES microcontroller does not support word transfers. Only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. Each channel accepts a DMA request from one of four sources: the channel request pin (DRQ1–DRQ0), Timer 2, a serial port, or the system software. The channels can be programmed with different priorities in the event of a simultaneous DMA request or if there is a need to interrupt transfers on the other channel. DMA Operation Each channel has six registers in the peripheral control block that define specific channel operations. The DMA registers consist of a 20-bit source address (two registers), a 20-bit destination address (two registers), a 16bit transfer count register, and a 16-bit control register. The DMA transfer count register (DTC) specifies the number of DMA transfers to be performed. Up to 64K of byte or word transfers can be performed with automatic termination. The DMA control registers define the channel operation. All registers can be modified during any DMA activity. Any changes made to the DMA registers are reflected immediately in DMA operation. Table 8. Am186ES Microcontroller Maximum DMA Transfer Rates Maximum DMA Transfer Rate (Mbytes) Type of Synchronization Selected 40 MHz 33 MHz 25 MHz 20 MHz Unsynchronized 10 8.25 6.25 5 Source Synch 10 8.25 6.25 5 Destination Synch (CPU needs bus) 6.6 5.5 4.16 3.3 8 6.6 5 4 Destination Synch (CPU does not need bus) Am186/188ES and Am186/188ESLV Microcontrollers 49 P R E L I M I N A R Y Adder Control Logic 20-bit Adder/Subtractor Timer Request DRQ1/Serial Port 20 Request Selection Logic Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Transfer Counter Ch. 0 Destination Address Ch. 0 Source Address Ch. 0 DRQ0/Serial Port DMA Control Logic Interrupt Request Channel Control Register 1 Channel Control Register 0 20 16 Internal Address/Data Bus Figure 10. DMA Unit Block Diagram DMA Channel Control Registers DMA Priority Each DMA control register determines the mode of operation for the particular DMA channel. The DMA control registers specify the following: The DMA channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have DMA requests pending. DMA cycles always have priority over internal CPU cycles except between locked memory accesses or word accesses to odd memory locations. However, an external bus hold takes priority over an internal DMA cycle. n The mode of synchronization n Whether bytes or words are transferred n Whether an interrupt is generated after the last transfer n Whether the DRQ pins are configured as INT pins n Whether DMA activity ceases after a programmed number of DMA cycles n The relative priority of the DMA channel with respect to the other DMA channel Because an interrupt request cannot suspend a DMA operation and the CPU cannot access memory during a DMA cycle, interrupt latency time suffers during sequences of continuous DMA cycles. An NMI request, however, causes all internal DMA activity to halt. This allows the CPU to respond quickly to the NMI request. n Whether the source address is incremented, decremented, or maintained constant after each transfer n Whether the source address addresses memory or I/O space n Whether the destination address is incremented, decremented, or maintained constant after transfers n Whether the destination address addresses memory or I/O space 50 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y PULSE WIDTH DEMODULATION ASYNCHRONOUS SERIAL PORTS For many applications, such as bar-code reading, it is necessary to measure the width of a signal in both its High and Low phases. The Am186ES and Am188ES microcontrollers provide a pulse-width demodulation (PWD) option to fulfill this need. The PWD bit in the system configuration register (SYSCON) enables the PWD option. Please note that the Am186ES and Am188ES microcontrollers do not support analog-todigital conversion. The Am186ES and Am188ES microcontrollers provide two independent asynchronous serial ports. These ports provide full-duplex, bidirectional data transfer using several industry-standard communications protocols. The serial ports can be used as sources or destinations of DMA transfers. In PWD mode, TMRIN0, TMRIN1, INT2, and INT4 are configured internal to the microcontroller to support the detection of rising and falling edges on the PWD input pin (INT2/INTA0/PWD) and to enable either timer 0 when the signal is High or timer 1 when the signal is Low. The INT4, TMRIN0, and TMRIN1 pins are not used in PWD mode and so are available for use as PIOs. The following diagram shows the behavior of a system for a typical waveform. The asynchronous serial ports support the following features: n Full-duplex operation n 7-bit, 8-bit, or 9-bit data transfers n Odd, even, or no parity n One stop bit n Two lengths of break characters n Error detection — Parity errors — Framing errors — Overrun errors n Hardware handshaking with the following selectable control signals: — Clear-to-send (CTS) INT2 INT4 INT2 Ints generated TMR1 enabled TMR0 enabled — Enable-receiver-request (ENRX) — Ready-to-send (RTS) — Ready-to-receive (RTR) The interrupt service routine (ISR) for the INT2 and INT4 interrupts should examine the current count of the associated timer, timer 1 for INT2 and timer 0 for INT4, in order to determine the pulse width. The ISR should then reset the timer count register in preparation for the next pulse. n DMA to and from the serial ports Since the timers count at one quarter of the processor clock rate, this determines the maximum resolution that can be obtained. Further, in applications where the pulse width may be short, it may be necessary to poll the INT2 and INT4 request bits in the interrupt request register in order to avoid the overhead involved in taking and returning from an interrupt. Overflow conditions, where the pulse width is greater than the maximum count of the timer, can be detected by monitoring the Maximum Count (MC) bit in the associated timer or by setting the INT bit to enable timer interrupt requests. n Double-buffered transmit and receive n Separate maskable interrupts for each port n Multidrop protocol (9-bit) support n Independent baud rate generators n Maximum baud rate of 1/16th of the CPU clock DMA Transfers through the Serial Port The Am186ES and Am188ES microcontrollers support DMA transfers both to and from the serial port. Either or both DMA channels and either or both serial ports can be used for DMA transmits or receives. See the DMA Control register descriptions in the Am186ES and Am188ES Microcontrollers User’s Manual for more information. Am186/188ES and Am186/188ESLV Microcontrollers 51 P R E L I M I N A R Y PROGRAMMABLE I/O (PIO) PINS There are 32 pins on the Am186ES and Am188ES microcontrollers that are available as user-programmable I/O signals. Table 2 on page 34 and Table 3 on page 34 list the PIO pins. Each of these pins can be used as a user-programmable input or output signal if the normal shared function is not needed. If a pin is enabled to function as a PIO signal, the preassigned signal function is disabled and does not affect the level on the pin. A PIO signal can be configured to operate as an input or output with or without a weak pullup or pulldown, or as an open-drain output. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 on page 34 and Table 3 on page 34 lists 52 the defaults for the PIOs. The system initialization code must reconfigure the PIOs as required. The A19–A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset. Note that emulators use A19, A18, A17, S6, and UZI. In environments where an emulator is needed, these pins must be configured for normal function—not as PIOs. If the AD15–AD0 bus override is enabled on power-on reset, then S6/CLKDIV2 and UZI revert to normal operation instead of PIO input with pullup. If BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during poweron reset, the AD15–AD0 bus override is enabled. Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS the functionality of the device is guaranteed. Storage temperature Am186ES/Am188ES....................... –65°C to +125°C Am186ESLV/Am188ESLV .............. –65°C to +125°C Am186ES/Am188ES Microcontrollers Commercial (TC) .................................0°C to +100°C Industrial* (TA) ..................................–40°C to +85°C VCC up to 33 MHz......................................5 V ± 10% VCC greater than 33 MHz ............................5 V ± 5% Voltage on any pin with respect to ground Am186/188ES ............................ –0.5 V to Vcc +0.5 V Am186/188ESLV ....................... –0.5 V to V cc +0.5 V Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Operating Ranges define those limits between which Am186ESLV/Am188ESLV Microcontrollers Commercial (TA) ................................... 0°C to +70°C VCC up to 25 MHz................................. 3.3 V ± 0.3 V Where: TC = case temperature TA = ambient temperature *Industrial versions of Am186ES and Am188ES microcontrollers are available in 20 and 25 MHz operating frequencies only. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Preliminary Symbol Parameter Description Test Conditions Min Max Unit VIL Input Low Voltage (Except X1) –0.5 0.8 V VIL1 Clock Input Low Voltage (X1) –0.5 0.8 V VIH Input High Voltage (Except RES and X1) 2.0 VCC +0.5 V VIH 1 Input High Voltage (RES) 2.4 VCC +0.5 V VIH 2 Clock Input High Voltage (X1) VCC –0.8 VCC +0.5 V Output Low Voltage Am186ES and Am188ES IOL = 2.5 mA (S2–S0) IOL = 2.0 mA (others) 0.45 V Am186ESLV and Am188ESLV IOL = 1.5 mA (S2–S0) IOL = 1.0 mA (others) 0.45 V 2.4 VCC +0.5 V IOH = –200 µA @ VCC –0.5 VCC –0.5 VCC V IOH = –200 µA @ VCC –0.5 VCC –0.5 VCC V VCC = 5.5 V (b) 5.9 mA/MHz = 3.6 V (b) 2.75 mA/MHz ±10 µA ±10 µA 0.45 V VOL Output High Voltage(a) VOH Am186ES and Am188ES Am186ESLV and Am188ESLV IOH = –2.4 mA @ 2.4 V Power Supply Current @ 0°C ICC Am186ES and Am188ES Am186ESLV and Am188ESLV VCC Input Leakage Current @ 0.5 MHz 0.45 V≤VIN ≤ VCC Output Leakage Current @ 0.5 MHz 0.45 V≤VOUT ≤VCC VCLO Clock Output Low ICLO = 4.0 mA VCHO Clock Output High ICHO = –500 µA ILI ILO (c) VCC –0.5 V Notes: a The LCS/ONCE0, MCS3–MCS0, UCS/ONCE1, and RD pins have weak internal pullup resistors. Loading the LCS/ONCE0 and UCS/ONCE1 pins in excess of IOH = –200 µA during reset can cause the device to go into ONCE mode. b Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open but held High or Low. c Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode. d Power supply current for the Am186ESLV and Am188ESLV microcontrollers, which are available in 20 and 25 MHz operating frequencies only. Am186/188ES and Am186/188ESLV Microcontrollers 53 P R E L I M I N A R Y Capacitance Symbol Parameter Description CIN Input Capacitance CIO Output or I/O Capacitance Preliminary Min Max 10 20 Test Conditions @ 1 MHz @ 1 MHz Unit pF pF Note: Capacitance limits are guaranteed by characterization. Power Supply Current Table 9 shows the variables that are used to calculate the typical power consumption value for each version of the Am186ESLV and Am188ESLV microcontrollers. For the following typical system specification shown in Figure 11, ICC has been measured at 4.0 mA per MHz of system clock. For the following typical system specification shown in Figure 12, I CC has been measured at 5.9 mA per MHz of system clock. The typical system is measured while the system is executing code in a typical application with maximum voltage and maximum case temperature. Actual power supply current is dependent on system design and may be greater or less than the typical ICC figure presented here. Table 9. Typical Power Consumption Calculation for the Am186ESLV and Am188ESLV MHz ⋅ ICC ⋅ Volts / 1000 = P MHz Typical ICC Volts 20 4.0 3.6 25 4.0 3.6 Typical Power in Watts 0.288 0.360 Typical current in Figure 11 is given by: ICC = 4.0 mA ⋅ freq(MHz) Typical current in Figure 12 is given by: ICC = 5.9 mA ⋅ freq(MHz) 140 120 Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were set to the following modes: 100 25 MHz 80 ICC (mA) n No DC loads on the output buffers 20 MHz 60 40 n Output capacitive load set to 35 pF 20 n AD bus set to data only 0 10 n PIOs are disabled 20 Clock Frequency (MHz) n Timer, serial port, refresh, and DMA are enabled Figure 11. Typical ICC Versus Frequency for the Am186ESLV and Am188ESLV 280 240 40 MHz 200 33 MHz 160 ICC (mA) 25 MHz 120 20 MHz 80 40 0 10 20 30 40 50 Clock Frequency (MHz) Figure 12. 54 30 Typical Icc Versus Frequency for Am186ES and Am188ES Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y THERMAL CHARACTERISTICS TQFP Package The Am186ES and Am188ES microcontrollers are specified for operation with case temperature ranges from 0°C to +100°C for a commercial device. Case temperature is measured at the top center of the pack age as shown in Figure 13. The various temperatures and thermal resistances can be determined using the equations in Figure 14 with information given in Table 10. The variable P is power in watts. Typical power supply current (ICC) is TBD mA per MHz of clock frequency. θJA is the total thermal resistance. θJA is the sum of θJC, the internal thermal resistance of the assembly, and θCA, the case to ambient thermal resistance. θJA θCA TC θ JC θJA = θJC + θCA Figure 13. Thermal Resistance(°C/Watt) θJA = θJC + θCA P=ICC ⋅ freq (MHz) ⋅ VCC TJ =TC +( P ⋅ θJC ) TJ =TA + ( P ⋅ θJA ) TC =TJ –( P ⋅ θJC ) TC =TA +( P ⋅ θCA ) TA =TJ –( P ⋅ θJA ) TA =TC –( P ⋅ θCA ) Figure 14. Thermal Characteristics Equations Table 10. Thermal Characteristics (°C/Watt) Package/Board PQFP/2-Layer TQFP/2-Layer PQFP/4-Layer to 6-Layer TQFP/4-Layer to 6-Layer Airflow (Linear Feet per Minute) θJA θJC θCA 0 fpm 45 7 38 200 fpm 39 7 32 400 fpm 35 7 28 600 fpm 33 7 26 0 fpm 56 10 46 200 fpm 46 10 36 400 fpm 40 10 30 600 fpm 38 10 28 0 fpm 23 5 18 200 fpm 21 5 16 400 fpm 19 5 14 600 fpm 17 5 12 0 fpm 30 6 24 200 fpm 28 6 22 400 fpm 26 6 20 600 fpm 24 6 18 Am186/188ES and Am186/188ESLV Microcontrollers 55 P R E L I M I N A R Y Typical Ambient Temperatures The typical ambient temperature specifications are based on the following assumptions and calculations: The commercial operating range of the Am186ES and Am188ES microcontrollers is a case temperature TC of 0 to 100 degrees Centigrade. TC is measured at the top center of the package. An increase in the ambient temperature causes a proportional increase in TC. The 40-MHz microcontroller is specified as 5.0 V plus or minus 5%. Therefore, 5.25 V is used for calculating typical power consumption on the 40-MHz microcontroller. column titled Speed/Pkg/Board in Table 12 indicates the clock speed in MHz, the type of package (P for PQFP and T for TQFP), and the type of board (2 for 2layer and 4-6 for 4-layer to 6-layer). Table 12. Junction Temperature Calculation Speed/ Pkg/ Board TJ = TC + (P ⋅ θJC) TJ TC P θJC 40/P2 108.673 100 1.239 7 40/T2 112.39 100 1.239 10 40/P4-6 106.195 100 1.239 5 40/T4-6 107.434 100 1.239 6 33/P2 107.49595 100 1.07085 7 33/T2 110.7085 100 1.07085 10 33/P4-6 105.35425 100 1.07085 5 33/T4-6 106.4251 100 1.07085 6 Typical power consumption (watts) = (5.9 mA/MHz) times microcontroller clock rate times voltage divided by 1000. 25/P2 105.67875 100 0.81125 7 25/T2 108.1125 100 0.81125 10 25/P4-6 104.05625 100 0.81125 5 Table 11 shows the variables that are used to calculate the typical power consumption value for each version of the Am186ES and Am188ES microcontrollers. 25/T4-6 104.8675 100 0.81125 6 Microcontrollers up to 33 MHz are specified as 5.0 V plus or minus 10%. Therefore, 5.5 V is used for calculating typical power consumption up to 33 MHz. Typical power supply current (ICC) in normal usage is estimated at 5.9 mA per MHz of microcontroller clock rate. Table 11. Typical Power Consumption Calculation P = MHz ⋅ ICC ⋅ Volts / 1000 Typical Power (P) in Watts MHz Typical ICC Volts 40 5.9 5.25 1.239 33 5.9 5.5 1.07085 25 5.9 5.5 0.81125 20 5.9 5.5 0.649 20/P2 104.543 100 0.649 7 20/T2 106.49 100 0.649 10 20/P4-6 103.245 100 0.649 5 20/T4-6 103.894 100 0.649 6 By using T J from Table 12, the typical power consumption value from Table 11, and a θJA value from Table 10, the typical ambient temperature TA can be calculated using the following formula from Figure 14: TA = TJ – (P ⋅ θJA) For example, TA for a 40-MHz PQFP design with a 2layer board and 0 fpm airflow is calculated as follows: TA = 108.673 – (1.239 ⋅ 45) TA = 52.918 Thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. A safe operating range for the device can be calculated using the formulas from Figure 14 and the variables in Table 10. In this calculation, TJ comes from Table 12, P comes from Table 11, and θJA comes from Table 10. See Table 13. By using the maximum case rating T C , the typical power consumption value from Table 11, and θJC from Table 10, the junction temperature T J can be calculated by using the following formula from Figure 14. TA = 106.4251 – (1.07085 ⋅ 28) TA = 76.4413 TJ = TC + (P ⋅ θJC) Table 12 shows TJ values for the various versions of the Am186ES and Am188ES microcontrollers. The 56 TA for a 33-MHz TQFP design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: See Table 16 for the result of this calculation. Table 13 through Table 16 and Figure 15 through Figure 18 show TA based on the preceding assumptions and calculations for a range of θJA values with airflow from 0 linear feet per minute to 600 linear feet per minute. Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Table 13 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used on a 2layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 15 graphically illustrates the typical temperatures in Table 13. Table 13. Typical Ambient Temperatures for PQFP with a 2-Layer Board Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 52.918 59.3077 69.1725 75.338 200 fpm 60.352 65.7328 74.04 79.232 400 fpm 65.308 70.0162 77.285 81.828 600 fpm 67.786 72.1579 78.9075 83.126 Typical Ambient Temperature (Degrees C) 90 Legend: ● 40 MHz ✵ 33 MHz ■ 80 ■ ■ ◆ ◆ ■ ◆ ✶ 70 ✶ ◆ ● ✶ 60 ● ● ✶ ● 50 ◆ 25 Mhz ■ 20 MHz 40 0 fpm 200 fpm 400 fpm 600 fpm Airflow (Linear Feet Per Minute) Figure 15. Typical Ambient Temperatures for PQFP with a 2-Layer Board Am186/188ES and Am186/188ESLV Microcontrollers 57 P R E L I M I N A R Y Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used on a 2layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 16 graphically illustrates the typical temperatures in Table 14. Table 14. Typical Ambient Temperatures for TQFP with a 2-Layer Board Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 43.006 50.7409 62.6825 70.146 200 fpm 55.396 61.4494 70.795 76.636 400 fpm 62.83 67.8745 75.6625 80.53 600 fpm 65.308 70.0162 77.285 81.828 Typical Ambient Temperature (Degrees C) 90 ■ ■ 80 ◆ ■ 70 ◆ ◆ ■ ✶ ✶ ● ✶ ◆ ● 60 ● ✶ Legend: 50 ● 40 MHz ✵ 33 MHz ● ◆ 25 Mhz ■ 20 MHz 40 0 fpm 200 fpm 400 fpm Airflow (Linear Feet Per Minute) Figure 16. 58 Typical Ambient Temperatures for TQFP with a 2-Layer Board Am186/188ES and Am186/188ESLV Microcontrollers 600 fpm P R E L I M I N A R Y Table 15 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used on a 4layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 17 graphically illustrates the typical temperatures in Table 15. Table 15. Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 77.698 80.7247 85.3975 88.318 200 fpm 80.176 82.8664 87.02 89.616 400 fpm 82.654 85.0081 88.6425 90.914 600 fpm 85.132 87.1498 90.265 92.212 95 Typical Ambient Temperature (Degrees C) ■ Legend: ● 40 MHz ✵ 33 MHz ■ 90 ■ ◆ ■ ✶ ◆ 85 ◆ ✶ ✶ ✶ ◆ ● ● ● 80 ● 75 ◆ 25 Mhz ■ 20 MHz 70 0 fpm 200 fpm 400 fpm 600 fpm Airflow (Linear Feet Per Minute) Figure 17. Typical Ambient Temperatures for PQFP with a 4-Layer to 6-Layer Board Am186/188ES and Am186/188ESLV Microcontrollers 59 P R E L I M I N A R Y Table 16 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used on a 4layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 18 graphically illustrates the typical temperatures in Table 16. Table 16. Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board Linear Feet per Minute Airflow Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 70.264 74.2996 80.53 84.424 200 fpm 72.742 76.4413 82.1525 85.722 400 fpm 75.22 78.583 83.775 87.02 600 fpm 77.698 80.7247 85.3975 88.318 Typical Ambient Temperature (Degrees C) 95 Legend: ● 40 MHz ✵ 33 MHz 90 ■ ■ ■ 85 ◆ ■ ◆ ◆ ✶ ◆ 80 ✶ ● ✶ ● 75 ✶ ● ◆ 25 Mhz ■ 20 MHz 70 ● 0 fpm 200 fpm 400 fpm 600 fpm Airflow (Linear Feet Per Minute) Figure 18. 60 Typical Ambient Temperatures for TQFP with a 4-Layer to 6-Layer Board Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y COMMERCIAL SWITCHING CHARACTERISTICS AND WAVEFORMS In the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. These periods are referred to as time states. A typical bus cycle is composed of four consecutive time states: t1, t2, t3, and t4. Wait states, which represent multiple t3 states, are referred to as tw states. When no bus cycle is pending, an idle (ti) state occurs. In t h e s w i tc h i n g pa r a m e te r de s c r i p t i on s , t h e multiplexed address is referred to as the AD address bus; the demultiplexed address is referred to as the A address bus. Key to Switching Waveforms WAVEFORM INPUT OUTPUT Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance Off State Invalid Invalid Am186/188ES and Am186/188ESLV Microcontrollers 61 P R E L I M I N A R Y Alphabetical Key to Switching Parameter Symbols 62 Parameter Symbol No. Description tARYCH 49 ARDY Resolution Transition Setup Time tARYCHL 51 ARDY Inactive Holding Time tARYHDSH 95 ARDY High to DS High tARYHDV 89 ARDY Assert to Data Valid tARYLCL 52 ARDY Setup Time tARYLDSH 96 ARDY Low to DS High tAVBL 87 A Address Valid to WHB, WLB Low tAVCH 14 AD Address Valid to Clock High tAVLL 12 AD Address Valid to ALE Low tAVRL 66 A Address Valid to RD Low tAVWL 65 A Address Valid to WR Low tAZRL 24 AD Address Float to RD Active tCH1CH2 45 CLKOUTA Rise Time tCHAV 68 CLKOUTA High to A Address Valid tCHCK 38 X1 High Time tCHCL 44 CLKOUTA High Time tCHCSV 67 CLKOUTA High to LCS/UCS Valid tCHCSX 18 MCS/PCS Inactive Delay tCHCTV 22 Control Active Delay 2 tCHCV 64 Command Lines Valid Delay (after Float) tCHCZ 63 Command Lines Float Delay tCHDX 8 Status Hold Time tCHLH 9 ALE Active Delay tCHLL 11 ALE Inactive Delay tCHRFD 79 CLKOUTA High to RFSH Valid tCHSV 3 Status Active Delay tCICOA 69 X1 to CLKOUTA Skew tCICOB 70 X1 to CLKOUTB Skew tCKHL 39 X1 Fall Time tCKIN 36 X1 Period tCKLH 40 X1 Rise Time tCL2CL1 46 CLKOUTA Fall Time tCLARX 50 ARDY Active Hold Time tCLAV 5 AD Address Valid Delay tCLAX 6 Address Hold tCLAZ 15 AD Address Float Delay tCLCH 43 CLKOUTA Low Time tCLCK 37 X1 Low Time tCLCL 42 CLKOUTA Period tCLCLX 80 LCS Inactive Delay tCLCSL 81 LCS Active Delay Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Alphabetical Key to Switching Parameter Symbols (continued) Parameter Symbol No. Description tCLCSV 16 MCS/PCS Active Delay tCLDOX 30 Data Hold Time tCLDV 7 Data Valid Delay tCLDX 2 Data in Hold tCLHAV 62 HLDA Valid Delay tCLRF 82 CLKOUTA High to RFSH Invalid tCLRH 27 RD Inactive Delay tCLRL 25 RD Active Delay tCLSH 4 Status Inactive Delay tCLSRY 48 SRDY Transition Hold Time tCLTMV 55 Timer Output Delay tCOAOB 83 CLKOUTA to CLKOUTB Skew tCSHARYL 88 Chip Select to ARDY Low tCVCTV 20 Control Active Delay 1 tCVCTX 31 Control Inactive Delay tCVDEX 21 DEN Inactive Delay tCXCSX 17 MCS/PCS Hold from Command Inactive tDSHDIR 92 DS High to Data Invalid—Read tDSHDIW 98 DS High to Data Invalid—Write tDSHDX 93 DS High to Data Bus Turn-off Time tDSHLH 41 DS Inactive to ALE Inactive tDSLDD 90 DS Low to Data Driven tDSLDV 91 DS Low to Data Valid tDVCL 1 Data in Setup tDVDSL 97 Data Valid to DS Low tDXDL 19 DEN Inactive to DT/R Low tHVCL 58 HOLD Setup tINVCH 53 Peripheral Setup Time tINVCL 54 DRQ Setup Time tLCRF 86 LCS Inactive to RFSH Active Delay tLHAV 23 ALE High to Address Valid tLHLL 10 ALE Width tLLAX 13 AD Address Hold from ALE Inactive tLOCK 61 Maximum PLL Lock Time tLRLL 84 LCS Precharge Pulse Width tRESIN 57 RES Setup Time tRFCY 85 RFSH Cycle Time tRHAV 29 RD Inactive to AD Address Active tRHDX 59 RD High to Data Hold on AD Bus tRHDZ 94 RD High to Data Bus Turn-off Time tRHLH 28 RD Inactive to ALE High Am186/188ES and Am186/188ESLV Microcontrollers 63 P R E L I M I N A R Y Alphabetical Key to Switching Parameter Symbols (continued) Parameter Symbol No. Description tRLRH 26 RD Pulse Width tSRYCL 47 SRDY Transition Setup Time tWHDEX 35 WR Inactive to DEN Inactive tWHDX 34 Data Hold after WR tWHLH 33 WR Inactive to ALE High tWLWH 32 WR Pulse Width Note: The following parameters are not defined or used as this time: 56, 60, 71–78. 64 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Numerical Key to Switching Parameter Symbols No. Parameter Symbol Description 1 tDVCL Data in Setup 2 tCLDX Data in Hold 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV AD Address Valid Delay 6 tCLAX Address Hold 7 tCLDV Data Valid Delay 8 tCHDX Status Hold Time 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 tAVLL AD Address Valid to ALE Low 13 tLLAX AD Address Hold from ALE Inactive 14 tAVCH AD Address Valid to Clock High 15 tCLAZ AD Address Float Delay 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low 20 tCVCTV Control Active Delay 1 21 tCVDEX DEN Inactive Delay 22 tCHCTV Control Active Delay 2 23 tLHAV ALE High to Address Valid 24 tAZRL AD Address Float to RD Active 25 tCLRL RD Active Delay 26 tRLRH RD Pulse Width 27 tCLRH RD Inactive Delay 28 tRHLH RD Inactive to ALE High 29 tRHAV RD Inactive to AD Address Active 30 tCLDOX Data Hold Time 31 tCVCTX Control Inactive Delay 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High 34 tWHDX Data Hold after WR 35 tWHDEX WR Inactive to DEN Inactive 36 tCKIN X1 Period 37 tCLCK X1 Low Time 38 tCHCK X1 High Time 39 tCKHL X1 Fall Time 40 tCKLH X1 Rise Time 41 tDSHLH DS Inactive to ALE Inactive 42 tCLCL CLKOUTA Period Am186/188ES and Am186/188ESLV Microcontrollers 65 P R E L I M I N A R Y Numerical Key to Switching Parameter Symbols (continued) 66 No. Parameter Symbol Description 43 tCLCH CLKOUTA Low Time 44 tCHCL CLKOUTA High Time 45 tCH1CH2 CLKOUTA Rise Time 46 tCL2CL1 CLKOUTA Fall Time 47 tSRYCL SRDY Transition Setup Time 48 tCLSRY SRDY Transition Hold Time 49 tARYCH ARDY Resolution Transition Setup Time 50 tCLARX ARDY Active Hold Time 51 tARYCHL ARDY Inactive Holding Time 52 tARYLCL ARDY Setup Time 53 tINVCH Peripheral Setup Time 54 tINVCL DRQ Setup Time 55 tCLTMV Timer Output Delay 57 tRESIN RES Setup Time 58 tHVCL HOLD Setup 59 tRHDX RD High to Data Hold on AD Bus 61 tLOCK Maximum PLL Lock Time 62 tCLHAV HLDA Valid Delay 63 tCHCZ Command Lines Float Delay 64 tCHCV Command Lines Valid Delay (after Float) 65 tAVWL A Address Valid to WR Low 66 tAVRL A Address Valid to RD Low 67 tCHCSV CLKOUTA High to LCS/UCS Valid 68 tCHAV CLKOUTA High to A Address Valid 69 tCICOA X1 to CLKOUTA Skew 70 tCICOB X1 to CLKOUTB Skew 79 tCHRFD CLKOUTA High to RFSH Valid 80 tCLCLX LCS Inactive Delay 81 tCLCSL LCS Active Delay 82 tCLRF CLKOUTA High to RFSH Invalid 83 tCOAOB 84 tLRLL LCS Precharge Pulse Width 85 tRFCY RFSH Cycle Time 86 tLCRF LCS Inactive to RFSH Active Delay 87 tAVBL A Address Valid to WHB, WLB Low 88 tCSHARYL Chip Select to ARDY Low 89 tARYHDV ARDY Assert to Data Valid 90 tDSLDD DS Low to Data Driven 91 tDSLDV DS Low to Data Valid 92 tDSHDIR DS High to Data Invalid—Read 93 tDSHDX DS High to Data Bus Turn-off Time CLKOUTA to CLKOUTB Skew Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Numerical Key to Switching Parameter Symbols (continued) No. Parameter Symbol Description 94 tRHDZ 95 tARYHDSH RD High to Data Bus Turn-off Time ARDY High to DS High 96 tARYLDSH ARDY Low to DS High 97 tDVDSL Data Valid to DS Low 98 tDSHDIW DS High to Data Invalid—Write Note: The following parameters are not defined or used as this time: 56, 60, 71–78. Am186/188ES and Am186/188ESLV Microcontrollers 67 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over Commercial operating ranges Read Cycle (20 MHz and 25 MHz) Parameter No. Symbol Description General Timing Requirements Data in Setup 1 tDVCL Data in Hold(c) 2 tCLDX General Timing Responses Status Active Delay 3 tCHSV 4 tCLSH Status Inactive Delay AD Address Valid Delay and BHE 5 tCLAV Address Hold 6 tCLAX Status Hold Time 8 tCHDX ALE Active Delay 9 tCHLH ALE Width 10 tLHLL 11 12 13 tCHLL tAVLL tLLAX ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE Inactive(a) 14 tAVCH AD Address Valid to Clock High AD Address Float Delay 15 tCLAZ 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay DEN Inactive to DT/R Low(a) 19 tDXDL 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DEN Inactive Delay 22 tCHCTV Control Active Delay 2(b) ALE High to Address Valid 23 tLHAV PCS Low to ALE Low 99 tPLAL Read Cycle Timing Responses AD Address Float to RD Active 24 tAZRL RD Active Delay 25 tCLRL 26 tRLRH RD Pulse Width 27 tCLRH RD Inactive Delay 28 tRHLH RD Inactive to ALE High(a) RD Inactive to AD Address 29 tRHAV Active(a) 41 tDSHLH DS Inactive to ALE High 59 66 tRHDX tAVRL 67 68 tCHCSV tCHAV Preliminary 20 MHz 25 MHz Min Max Min Max 10 3 0 0 0 0 0 10 3 25 25 25 25 0 0 0 0 0 25 tCLCL –10= 40 0 0 0 0 0 20 15 0 0 2tCLCL –15= 85 0 tCLCH –3 tCLCL –10= 40 tCLCH –2= 21 RD High to Data Hold on AD Bus(c) 0 A Address Valid to RD Low(a) tCLCL + tCHCL–3 CLKOUTA High to LCS/UCS Valid 0 CLKOUTA High to A Address 0 Valid 20 20 20 20 20 25 0 tCLAX =0 0 tCLCH –2 ns ns tCLCL –10= 30 tCLCHL –2 tCHCL –2 20 tCLCH –2 tCHCL –2 25 25 25 25 12 25 28 25 25 25 25 0 tCLAX =0 0 tCLCH –2 0 0 0 0 0 15 15 0 0 2tCLCL –15= 65 0 tCLCH –3 tCLCL –10= 30 tCLCH –2= 16 0 tCLCL + tCHCL–3 0 0 Unit 20 20 20 20 12 20 24 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 ns ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. 68 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Read Cycle (33 MHz and 40 MHz) Preliminary Parameter No. Symbol Description General Timing Requirements Data in Setup 1 tDVCL Data in Hold(c) 2 tCLDX General Timing Responses Status Active Delay 3 tCHSV 4 tCLSH Status Inactive Delay AD Address Valid Delay and BHE 5 tCLAV Address Hold 6 tCLAX Status Hold Time 8 tCHDX ALE Active Delay 9 tCHLH ALE Width 10 tLHLL 11 tCHLL ALE Inactive Delay AD Address Valid to ALE Low(a) 12 tAVLL AD Address Hold from ALE 13 tLLAX Inactive(a) 14 tAVCH AD Address Valid to Clock High AD Address Float Delay 15 tCLAZ 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay DEN Inactive to DT/R Low(a) 19 tDXDL 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DEN Inactive Delay 22 tCHCTV Control Active Delay 2(b) ALE High to Address Valid 23 tLHAV PCS Low to ALE Low 99 tPLAL Read Cycle Timing Responses AD Address Float to RD Active 24 tAZRL RD Active Delay 25 tCLRL RD Pulse Width 26 tRLRH RD Inactive Delay 27 tCLRH RD Inactive to ALE High(a) 28 tRHLH RD Inactive to AD Address 29 tRHAV Active(a) 41 tDSHLH DS Inactive to ALE Inactive RD High to Data Hold on AD Bus(c) 59 tRHDX 66 tAVRL A Address Valid to RD Low(a) 67 68 tCHCSV tCHAV CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid 33 MHz Min 40 MHz Min Max 8 3 0 0 0 0 0 5 2 15 15 15 15 0 0 0 0 0 15 tCLCL –10=20 0 0 0 0 0 10 12 0 0 2tCLCL –15=45 0 tCLCH –3 tCLCL –10=20 12 tCLCH –2 tCHCL –2 15 15 0 tCLAX =0 0 tCLCH –2 15 0 0 0 0 0 7.5 10 15 12 15 20 15 15 tCLCH –2=11.5 0 tCLCL + tCHCL–3 0 0 12 12 12 12 12 15 15 15 0 0 2tCLCL –10=40 0 tCLCH –2 tCLCL –5=20 tCLCH –2=9.25 0 tCLCL + tCHCL– 1.125 0 0 Unit ns ns tCLCL –5=20 tCLCH –2 tCHCL –2 0 tCLAX =0 0 tCLCH –2 Max 12 12 12 12 12 12 18 10 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 ns ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Am186/188ES and Am186/188ESLV Microcontrollers 69 P R E L I M I N A R Y Read Cycle Waveforms t1 t2 t3 t4 tW CLKOUTA 66 Address A19–A0 8 68 S6/LOCK S6 LOCK S6 14 1 6 AD15–AD0*, AD7–AD0** Address Data 2 Address AO15–AO8** 23 29 9 11 59 ALE 15 10 RD 28 24 26 12 5 27 25 BHE* BHE 67 18 13 LCS, UCS 16 MCS1–MCS0, PCS6–PCS5, PCS3–PCS0 17 99 20 21 DEN, DS 41 19 DT/R 22 *** 4 S2–S0 Status 3 UZI Notes: * Am186ES microcontroller only ** *** 70 Am188ES microcontroller only Changes in t phase preceding next bus cycle if followed by read, INTA, or halt. Am186/188ES and Am186/188ESLV Microcontrollers *** 22 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Write Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol Description General Timing Responses Status Active Delay 3 tCHSV 4 tCLSH Status Inactive Delay AD Address Valid Delay and BHE 5 tCLAV Address Hold 6 tCLAX 7 tCLDV Data Valid Delay Status Hold Time 8 tCHDX 9 tCHLH ALE Active Delay ALE Width 10 tLHLL 11 tCHLL ALE Inactive Delay AD Address Valid to ALE Low(a) 12 tAVLL 13 tLLAX AD Address Hold from ALE Inactive(a) 14 tAVCH AD Address Valid to Clock High 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DS Inactive Delay 22 tCHCTV Control Active Delay 2 23 tLHAV ALE High to Address Valid Write Cycle Timing Responses 30 tCLDOX Data Hold Time 31 tCVCTX Control Inactive Delay(b) 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 34 tWHDX Data Hold after WR(a) 35 tWHDEX WR Inactive to DEN Inactive(a) 41 tDSHLH DS Inactive to ALE High 65 67 68 tAVWL tCHCSV tCHAV 87 tAVBL 98 tDSHDIW A Address Valid to WR Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low DS High to Data Invalid—Write 20 MHz Min 0 0 0 0 0 0 Max 25 MHz Min 25 25 25 25 15 0 0 0 0 0 0 25 tCLCL –10=40 tCLCH –2 tCHCL–2 0 0 2tCLCL –10=90 tCLCH –2 tCLCL –10=40 tCLCH –3 tCLCH –2= 21 tCLCL+tCHCL –3 0 0 tCHCL –3 20 20 20 20 20 ns ns ns ns ns ns ns ns ns ns ns 20 20 tCLCH –2 tCHCL–2 0 0 25 tCLCH –2 0 0 0 0 0 20 Unit tCLCL –10=30 25 0 0 Max 20 tCLCH –2 25 15 25 25 0 0 0 0 0 15 25 25 0 0 2tCLCL –10=70 tCLCH –2 tCLCL –10=30 tCLCH –3 tCLCH –2= 16 tCLCL +tCHCL –3 0 0 25 25 20 20 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 ns ns ns tCHCL –3 20 ns 0 30 ns 35 Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. Am186/188ES and Am186/188ESLV Microcontrollers 71 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Write Cycle (33 MHz and 40 MHz) Preliminary Parameter No. Symbol Description General Timing Responses Status Active Delay 3 tCHSV 4 tCLSH Status Inactive Delay AD Address Valid Delay and BHE 5 tCLAV Address Hold 6 tCLAX 7 tCLDV Data Valid Delay Status Hold Time 8 tCHDX 9 tCHLH ALE Active Delay ALE Width 10 tLHLL 11 tCHLL ALE Inactive Delay AD Address Valid to ALE Low(a) 12 tAVLL 13 tLLAX AD Address Hold from ALE Inactive(a) 14 tAVCH AD Address Valid to Clock High 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DS Inactive Delay 22 tCHCTV Control Active Delay 2 23 tLHAV ALE High to Address Valid Write Cycle Timing Responses 30 tCLDOX Data Hold Time 31 tCVCTX Control Inactive Delay(b) 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 34 tWHDX Data Hold after WR(a) 35 tWHDEX WR Inactive to DEN Inactive(a) 65 tAVWL A Address Valid to WR Low 67 68 tCHCSV tCHAV 87 tAVBL 98 tDSHDIW CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low DS High to Data Invalid—Write 33 MHz Min 0 0 0 0 0 0 Max 15 15 15 25 15 40 MHz Min 0 0 0 0 0 0 15 tCLCL –10=20 tCLCH –2 tCHCL–2 0 0 2tCLCL –10=50 tCLCH –2 tCLCL –10=20 tCLCH –5 tCLCL +tCHCL –3 12 12 12 20 12 ns ns ns ns ns ns ns ns ns ns ns 12 12 tCLCH –2 tCHCL–2 15 tCLCH –2 0 0 0 0 0 10 Unit tCLCL –5=20 15 0 0 Max 0 0 12 tCLCH –2 15 15 15 15 0 0 0 0 0 7.5 0 0 15 15 0 0 2tCLCL –10=40 tCLCH –2 tCLCL –10=15 tCLCH tCLCL +tCHCL – 1.25 0 0 tCHCL –3 15 0 20 15 12 12 12 12 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 ns ns tCHCL –1.25 12 ns 0 15 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. 72 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Write Cycle Waveforms t1 t2 t3 t4 tW CLKOUTA 65 A19–A0 Address 68 8 S6/LOCK S6 S6 LOCK 14 7 AD15–AD0*, AD7–AD0** 30 Address Data 6 AO15–AO8** Address 23 11 9 34 13 ALE 31 10 33 32 WR 12 20 WHB*, WLB* WB** 20 31 87 5 BHE* BHE 67 41 LCS, UCS 16 18 99 MCS3–MCS0, PCS6–PCS5, PCS3–PCS0 17 35 20 31 DEN 98 21 20 DS 19 DT/R *** 22 *** 22 S2–S0 Status 3 4 UZI Notes: * Am186ES microcontroller only ** Am188ES microcontroller only *** Changes in t phase preceding next bus cycle if followed by read, INTA, or halt. Am186/188ES and Am186/188ESLV Microcontrollers 73 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Read Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol Description General Timing Requirements 20 MHz Min 25 MHz Max Min Max Data in Setup Data in Hold(b) 10 3 General Timing Responses 5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 0 0 25 0 0 20 ns ns 20 ns ns 20 ns ns 20 20 ns ns 1 2 tDVCL tCLDX 7 8 tCLDV tCHDX Data Valid Delay Status Hold Time 9 10 tCHLH tLHLL ALE Active Delay ALE Width 11 23 tCHLL tLHAV ALE Inactive Delay ALE High to Address Valid 20 80 81 tCLCLX tCLCSL LCS Inactive Delay LCS Active Delay 0 0 LCS Precharge Pulse Width 84 tLRLL Read Cycle Timing Responses 24 25 tAZRL tCLRL AD Address Float to RD Active RD Active Delay 26 27 tRLRH tCLRH RD Pulse Width RD Inactive Delay 28 59 tRHLH tRHDX 66 tAVRL RD Inactive to ALE High(a) RD High to Data Hold on AD Bus(b) A Address Valid to RD Low 68 tCHAV CLKOUTA High to A Address Valid 10 3 Unit 25 tCLCL –10=40 ns ns tCLCL –10=30 25 15 25 25 0 0 tCLCL+ tCLCH–3 tCLCL + tCLCH –3 ns 0 0 25 0 0 20 ns ns 25 2tCLCL –15=65 0 20 ns ns 2tCLCL –15=85 0 tCLCH –3 0 tCLCH –3 0 ns ns tCLCL + tCHCL–3 tCLCL + tCHCL–3 ns 0 25 0 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC –0.5 V. a Testing is performed with equal loading on referenced pins. b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. 74 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Read Cycle (33 MHz and 40 MHz) Preliminary Parameter No. Symbol Description General Timing Requirements 33 MHz Min 40 MHz Max Min Max Data in Setup Data in Hold(b) 8 3 General Timing Responses 5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 0 0 15 0 0 12 ns ns 12 ns ns 12 ns ns 12 12 ns ns 1 2 tDVCL tCLDX 7 8 tCLDV tCHDX Data Valid Delay Status Hold Time 9 10 tCHLH tLHLL ALE Active Delay ALE Width 11 23 tCHLL tLHAV ALE Inactive Delay ALE High to Address Valid 10 80 81 tCLCLX tCLCSL LCS Inactive Delay LCS Active Delay 0 0 84 tLRLL LCS Precharge Pulse Width Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 25 26 tCLRL tRLRH RD Active Delay RD Pulse Width 27 28 tCLRH tRHLH RD Inactive Delay RD Inactive to ALE High(a) 59 tRHDX 66 tAVRL RD High to Data Hold on AD Bus(b) A Address Valid to RD Low 68 tCHAV CLKOUTA High to A Address Valid 5 2 Unit 15 tCLCL –10=20 ns ns tCLCL –5=20 15 7.5 15 15 tCLCL + tCLCH –3 0 0 tCLCL + tCLCH – 1.25 0 ns 0 ns 0 2tCLCL –15=45 15 0 2tCLCL –10=40 10 ns ns 0 tCLCH –3 15 0 tCLCH –1.25 12 ns ns 0 0 ns tCLCL + tCHCL–3 tCLCL + tCHCL– 1.25 0 ns 0 15 10 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC –0.5 V. a Testing is performed with equal loading on referenced pins. b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Am186/188ES and Am186/188ESLV Microcontrollers 75 P R E L I M I N A R Y PSRAM Read Cycle Waveforms t1 t3 t2 t4 t1 tW CLKOUTA 66 Address A19–A0 8 68 S6 S6/LOCK S6 LOCK 1 7 AD15–AD0*, AD7–AD0** Address Address Data 2 Address AO15–AO8** 23 9 11 59 ALE 10 28 24 26 RD 27 5 25 27 LCS 80 81 84 Notes: * Am186ES microcontroller only ** Am188ES microcontroller only 76 Am186/188ES and Am186/188ESLV Microcontrollers 80 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Write Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol Description General Timing Responses 20 MHz 25 MHz Min Max Min Max Unit 25 25 0 0 20 20 ns ns 20 ns ns 20 ns ns 5 7 tCLAV tCLDV AD Address Valid Delay and BHE Data Valid Delay 0 0 8 9 tCHDX tCHLH Status Hold Time ALE Active Delay 0 10 11 tLHLL tCHLL ALE Width ALE Inactive Delay 20 23 tCVCTV tLHAV Control Active Delay 1(b) ALE High to Address Valid 0 20 25 0 15 20 ns ns 80 81 tCLCLX tCLCSL LCS Inactive Delay LCS Active Delay 0 0 25 25 0 0 20 20 ns ns 20 ns ns LCS Precharge Pulse Width 84 tLRLL Write Cycle Timing Responses 0 25 tCLCL –10=40 tCLCL –10=30 25 tCLCL + tCLCH –3 tCLCL + tCLCH –3 0 0 0 0 30 31 tCLDOX tCVCTX Data Hold Time Control Inactive Delay(b) 32 33 tWLWH tWHLH WR Pulse Width WR Inactive to ALE High(a) 2tCLCL –10=90 tCLCH –2 2tCLCL –10=70 tCLCH –2 ns ns 34 65 tWHDX tAVWL Data Hold after WR(a) A Address Valid to WR Low tCHAV CLKOUTA High to A Address Valid 25 tCLCL –10=30 tCLCL +tCHCL –3 0 ns ns 68 tCLCL –10=40 tCLCL +tCHCL –3 0 20 ns 87 tAVBL A Address Valid to WHB, WLB Low tCHCL –3 25 tCHCL –3 20 ns 25 Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN, WR, WHB, and WLB signals. Am186/188ES and Am186/188ESLV Microcontrollers 77 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Write Cycle (33 MHz and 40 MHz) Preliminary Parameter 33 MHz No. Symbol Description General Timing Responses 40 MHz Min Max Min Max Unit 15 15 0 0 12 12 ns ns 12 ns ns 12 ns ns 5 7 tCLAV tCLDV AD Address Valid Delay and BHE Data Valid Delay 0 0 8 9 tCHDX tCHLH Status Hold Time ALE Active Delay 0 10 11 tLHLL tCHLL ALE Width ALE Inactive Delay 20 23 tCVCTV tLHAV Control Active Delay 1(b) ALE High to Address Valid 0 10 15 0 7.5 12 ns ns 80 81 tCLCLX tCLCSL LCS Inactive Delay LCS Active Delay 0 0 15 15 0 0 12 12 ns ns 84 tLRLL LCS Precharge Pulse Width Write Cycle Timing Responses 30 tCLDOX Data Hold Time Delay(b) 0 15 tCLCL –10=20 tCLCL –5=20 15 tCLCL + tCLCH – 3 tCLCL + tCLCH – 1.25 0 0 15 0 2tCLCL –10=40 ns 31 32 tCVCTX tWLWH Control Inactive WR Pulse Width 0 2tCLCL –10=50 12 ns ns 33 34 tWHLH tWHDX WR Inactive to ALE High(a) Data Hold after WR(a) tCLCH –2 tCLCL –10=20 tCLCH –2 tCLCL –10=15 ns ns 65 tAVWL A Address Valid to WR Low tCHAV 15 10 ns 87 tAVBL CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low tCLCL +tCHCL –1.25 0 ns 68 tCLCL +tCHCL –3 0 tCHCL –3 15 tCHCL –1.25 12 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN, WR, WHB, and WLB signals. 78 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y PSRAM Write Cycle Waveforms t1 t2 t3 t1 t4 tW CLKOUTA 65 Address A19–A0 68 8 S6 S6/LOCK LOCK S6 7 AD15–AD0*, AD7–AD0** 30 Address Data Address AO15–AO8** 23 11 9 ALE 34 10 33 32 WR 31 5 20 20 WHB*, WLB* WB** LCS 31 87 80 84 81 80 Notes: * Am186ES microcontroller only ** Am188ES microcontroller only Am186/188ES and Am186/188ESLV Microcontrollers 79 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Refresh Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol Description General Timing Responses 9 10 tCHLH tLHLL ALE Active Delay ALE Width 20 MHz Min tCLRL tRLRH RD Active Delay RD Pulse Width 27 28 tCLRH tRHLH RD Inactive Delay RD Inactive to ALE High(a) 80 81 tCLCLX tCLCSL LCS Inactive Delay LCS Active Delay Refresh Timing Cycle Parameters 79 tCLRFD CLKOUTA Low to RFSH Valid Min 25 tCLCL –10=40 ALE Inactive Delay 11 tCHLL Read/Write Cycle Timing Responses 25 26 25 MHz Max Max Unit 20 ns ns 20 ns tCLCL –10=30 25 0 2tCLCL –15=85 25 0 2tCLCL –15=65 20 ns ns 0 25 0 20 ns ns 20 20 ns ns tCLCH –3 0 0 tCLCH –3 25 25 0 0 0 25 0 20 ns 82 85 tCLRF tRFCY CLKOUTA High to RFSH Invalid RFSH Cycle Time 0 6 • tCLCL 25 0 6 • tCLCL 20 ns ns 86 tLCRF LCS Inactive to RFSH Active Delay 2tCLCL –3 2tCLCL –3 Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a 80 Testing is performed with equal loading on referenced pins. Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Refresh Cycle (33 MHz and 40 MHz) Preliminary Parameter No. Symbol Description General Timing Responses 9 10 tCHLH tLHLL ALE Active Delay ALE Width 33 MHz Min tCLRL tRLRH RD Active Delay RD Pulse Width 27 28 tCLRH tRHLH RD Inactive Delay RD Inactive to ALE High(a) 80 81 tCLCLX tCLCSL LCS Inactive Delay LCS Active Delay Refresh Timing Cycle Parameters 79 tCLRFD CLKOUTA Low to RFSH Valid Min 15 tCLCL –10=20 ALE Inactive Delay 11 tCHLL Read/Write Cycle Timing Responses 25 26 40 MHz Max Max Unit 12 ns ns 12 ns tCLCL –5=20 15 0 2tCLCL –15=45 15 0 2tCLCL –10=40 10 ns ns 0 15 0 12 ns ns 12 12 ns ns tCLCH –3 0 0 tCLCH –2 15 15 0 0 0 15 0 12 ns 82 85 tCLRF tRFCY CLKOUTA High to RFSH Invalid RFSH Cycle Time 0 6 • tCLCL 15 0 6 • tCLCL 12 ns ns 86 tLCRF LCS Inactive to RFSH Active Delay 2tCLCL –3 2tCLCL –1.25 Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. Am186/188ES and Am186/188ESLV Microcontrollers 81 P R E L I M I N A R Y PSRAM Refresh Cycle Waveforms t1 t2 t3 t4 t1 tW * CLKOUTA Address A19–A0 11 9 ALE 27 10 28 26 RD 80 27 25 LCS 79 RFSH 82 85 86 Notes: * The period tw is fixed at 3 wait states for PSRAM auto refresh only. 82 Am186/188ES and Am186/188ESLV Microcontrollers 81 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Interrupt Acknowledge Cycle (20 MHz and 25 MHz) Preliminary Parameter 20 MHz No. Symbol Description General Timing Requirements 1 2 tDVCL tCLDX Min Data in Setup Data in Hold 25 MHz Max 10 3 General Timing Responses 3 tCHSV Status Active Delay Min Max 10 3 Unit ns ns 0 25 0 20 ns 4 7 tCLSH tCLDV Status Inactive Delay Data Valid Delay 0 0 25 25 0 0 20 20 ns ns 8 9 tCHDX tCHLH Status Hold Time ALE Active Delay 0 20 ns ns 10 11 tLHLL tCHLL ALE Width ALE Inactive Delay 20 ns ns 12 tAVLL AD Address Invalid to ALE Low(a) 15 19 tCLAZ tDXDL AD Address Float Delay DEN Inactive to DT/R Low(a) 20 21 tCVCTV tCVDEX 22 23 31 68 0 25 tCLCL –10=40 tCLCL –10=30 25 tCLCH tCLCH ns tCLAX =0 0 25 tCLAX =0 0 20 ns ns Control Active Delay 1(b) DEN Inactive Delay 0 0 25 25 0 0 20 20 ns ns tCHCTV tLHAV Control Active Delay 2(c) ALE High to Address Valid 0 20 25 0 15 20 ns ns tCVCTX tCHAV Control Inactive Delay(b) CLKOUTA High to A Address Valid 0 0 25 25 0 0 20 20 ns ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the INTA1–INTA0 signals. c This parameter applies to the DEN and DT/R signals. Am186/188ES and Am186/188ESLV Microcontrollers 83 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Interrupt Acknowledge Cycle (33 MHz and 40 MHz) Preliminary Parameter 33 MHz No. Symbol Description General Timing Requirements 1 2 tDVCL tCLDX Min Data in Setup Data in Hold 40 MHz Max 8 3 General Timing Responses 3 tCHSV Status Active Delay Min Max 5 2 Unit ns ns 0 15 0 12 ns 4 7 tCLSH tCLDV Status Inactive Delay Data Valid Delay 0 0 15 15 0 0 12 12 ns ns 8 9 tCHDX tCHLH Status Hold Time ALE Active Delay 0 12 ns ns 10 11 tLHLL tCHLL ALE Width ALE Inactive Delay 12 ns ns 12 tAVLL AD Address Invalid to ALE Low(a) 15 19 tCLAZ tDXDL AD Address Float Delay DEN Inactive to DT/R Low(a) 20 21 tCVCTV tCVDEX 22 23 31 68 0 15 tCLCL –10=20 tCLCL –5=20 15 tCLCH tCLCH ns tCLAX =0 0 15 tCLAX =0 0 12 ns ns Control Active Delay 1(b) DEN Inactive Delay 0 0 15 15 0 0 12 12 ns ns tCHCTV tLHAV Control Active Delay 2(c) ALE High to Address Valid 0 10 15 0 7.5 12 ns ns tCVCTX tCHAV Control Inactive Delay(b) CLKOUTA High to A Address Valid 0 0 15 15 0 0 12 10 ns ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the INTA1–INTA0 signals. c This parameter applies to the DEN and DT/R signals. 84 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Interrupt Acknowledge Cycle Waveforms t1 t2 t3 t4 tW CLKOUTA 68 Address A19–A0 7 S6 S6/LOCK 8 LOCK S6 1 AD15–AD0*, AD7–AD0** 2 12 (b) Ptr 15 Address AO15–AO8** 23 9 ALE 10 11 4 BHE BHE* 31 INTA1–INTA0 20 DEN 22 19 (c) 21 22 DT/R 4 (a) 3 22 (d) Status S2–S0 Notes: * Am186ES microcontroller only ** Am188ES microcontroller only a The status bits become inactive in the state preceding t4. b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to tCLDX (min). c This parameter applies for an interrupt acknowledge cycle that follows a write cycle. d If followed by a write cycle, this change occurs in the state preceding that write cycle. Am186/188ES and Am186/188ESLV Microcontrollers 85 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Software Halt Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol Description General Timing Responses 20 MHz 25 MHz Min Max Min Max Unit 3 4 tCHSV tCLSH Status Active Delay Status Inactive Delay 0 0 25 25 0 0 20 20 ns ns 5 9 tCLAV tCHLH AD Address Invalid Delay and BHE ALE Active Delay 0 25 25 0 20 20 ns ns 10 11 tLHLL tCHLL ALE Width ALE Inactive Delay 19 22 tDXDL tCHCTV DEN Inactive to DT/R Low(a) Control Active Delay 2(b) 0 0 68 tCHAV CLKOUTA High to A Address Invalid 0 tCLCL –10=40 tCLCL –10=30 20 ns ns 25 0 0 20 ns ns 25 0 20 ns 25 Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN signal. 86 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Software Halt Cycle (33 MHz and 40 MHz) Preliminary Parameter No. Symbol 33 MHz Description 40 MHz Min Max Min Max Unit General Timing Responses 3 4 tCHSV tCLSH Status Active Delay Status Inactive Delay 0 0 15 15 0 0 12 12 ns ns 5 9 tCLAV tCHLH AD Address Invalid Delay and BHE ALE Active Delay 0 15 15 0 12 12 ns ns 10 11 tLHLL tCHLL ALE Width ALE Inactive Delay 19 22 tDXDL tCHCTV DEN Inactive to DT/R Low(a) Control Active Delay 2(b) 0 0 68 tCHAV CLKOUTA High to A Address Invalid 0 tCLCL –10=20 tCLCL –5=20 12 ns ns 15 0 0 12 ns ns 15 0 10 ns 15 Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN signal. Am186/188ES and Am186/188ESLV Microcontrollers 87 P R E L I M I N A R Y Software Halt Cycle Waveforms t1 t2 ti CLKOUTA 68 A19–A0 Invalid Address 5 S6, AD15–AD0*, AD7–AD0**, AO15–AO8** Invalid Address 10 ALE 9 11 DEN 19 DT/R 22 4 Status S2–S0 3 Notes: * Am186ES microcontroller only ** Am188ES microcontroller only 88 Am186/188ES and Am186/188ESLV Microcontrollers ti P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Clock (20 MHz and 25 MHz) Preliminary Parameter No. Symbol CLKIN Requirements 20 MHz Description Max Min Max Unit 60 40 15 60 ns ns 36 37 tCKIN tCLCK X1 Period(a) X1 Low Time (1.5 V)(a) 50 15 38 39 tCHCK tCKHL X1 High Time (1.5 V)(a) X1 Fall Time (3.5 to 1.0 V)(a) 15 X1 Rise Time (1.0 to 3.5 V)(a) 40 tCKLH CLKOUT Timing 42 43 tCLCL tCLCH 44 tCHCL 45 tCH1CH2 46 tCL2CL1 61 69 70 CLKOUTA Period CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time (CL =50 pF) CLKOUTA Rise Time (1.0 to 3.5 V) 25 MHz Min 5 15 5 ns ns 5 5 ns 50 0.5tCLCL –2=23 40 0.5tCLCL –2=18 ns ns 0.5tCLCL –2=23 0.5tCLCL –2=18 ns 3 3 ns CLKOUTA Fall Time (3.5 to 1.0 V) 3 3 ns tLOCK tCICOA Maximum PLL Lock Time X1 to CLKOUTA Skew 1 15 1 15 ms ns tCICOB X1 to CLKOUTB Skew 25 25 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation. Am186/188ES and Am186/188ESLV Microcontrollers 89 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Clock (33 MHz and 40 MHz) Preliminary Parameter No. Symbol CLKIN Requirements 33 MHz Description Max Min Max Unit 60 25 7.5 60 ns ns 36 37 tCKIN tCLCK X1 Period(a) X1 Low Time (1.5 V)(a) 30 10 38 39 tCHCK tCKHL X1 High Time (1.5 V)(a) X1 Fall Time (3.5 to 1.0 V)(a) 10 X1 Rise Time (1.0 to 3.5 V)(a) 40 tCKLH CLKOUT Timing 42 43 tCLCL tCLCH 44 tCHCL 45 tCH1CH2 46 tCL2CL1 61 69 70 CLKOUTA Period CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time (CL =50 pF) CLKOUTA Rise Time (1.0 to 3.5 V) 40 MHz Min 5 7.5 5 ns ns 5 5 ns 30 25 0.5tCLCL –1.5 =13.5 0.5tCLCL –1.5 =13.5 0.5tCLCL –1.25 =11.25 0.5tCLCL –1.25 =11.25 ns ns ns 3 3 ns CLKOUTA Fall Time (3.5 to 1.0 V) 3 3 ns tLOCK tCICOA Maximum PLL Lock Time X1 to CLKOUTA Skew 1 15 1 15 ms ns tCICOB X1 to CLKOUTB Skew 25 25 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation. 90 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Clock Waveforms—Active Mode X2 37 36 38 X1 39 40 45 46 CLKOUTA (Active, F=000) 69 42 43 44 CLKOUTB 70 Clock Waveforms—Power-Save Mode X2 X1 CLKOUTA (Power-Save, F=010) CLKOUTB (Like X1, CBF=1) CLKOUTB (Like CLKOUTA, CBF=0) Am186/188ES and Am186/188ESLV Microcontrollers 91 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Ready and Peripheral (20 MHz and 25 MHz) Parameter Preliminary 20 MHz Preliminary 25 MHz Min Min No. Symbol Description Ready and Peripheral Timing Requirements Max Max Unit 47 48 tSRYCL tCLSRY SRDY Transition Setup Time(a) SRDY Transition Hold Time(a) 10 3 10 3 ns ns 49 tARYCH ARDY Resolution Transition Setup Time(b) 10 10 ns 50 51 tCLARX tARYCHL ARDY Active Hold Time(a) ARDY Inactive Holding Time 4 6 4 6 ns ns 52 53 tARYLCL tINVCH ARDY Setup Time(a) Peripheral Setup Time(b) 15 10 15 10 ns ns 10 10 ns DRQ Setup Time(b) 54 tINVCL Peripheral Timing Responses 55 tCLTMV Timer Output Delay 25 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. 92 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Ready and Peripheral (33 MHz and 40 MHz) Preliminary 33 MHz Parameter No. Symbol Description Min 40 MHz Max Min Max Unit Ready and Peripheral Timing Requirements 47 tSRYCL SRDY Transition Setup Time(a) 8 5 ns 48 tCLSRY SRDY Transition Hold Time(a) 3 2 ns 49 tARYCH ARDY Resolution Transition Setup Time(b) 8 5 ns 50 tCLARX ARDY Active Hold Time(a) 4 3 ns 51 tARYCHL ARDY Inactive Holding Time 6 5 ns ARDY Setup Time(a) 52 tARYLCL 10 5 ns 53 tINVCH Peripheral Setup Time(b) 8 5 ns 54 tINVCL DRQ Setup Time(b) 8 5 ns Peripheral Timing Responses 55 tCLTMV Timer Output Delay 15 12 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. Synchronous Ready Waveforms Case 1 tW tW tW t4 Case 2 t3 tW tW t4 Case 3 t2 t3 tW t4 Case 4 t1 t2 t3 t4 CLKOUTA 47 SRDY 48 Am186/188ES and Am186/188ESLV Microcontrollers 93 P R E L I M I N A R Y Asynchronous Ready Waveforms Case 1 tW tW tW t4 Case 2 t3 tW tW t4 Case 3 t2 t3 tW t4 Case 4 t1 t2 t3 t4 CLKOUTA 49 50 ARDY (Normally NotReady System) 49 ARDY (Normally Ready System) 50 51 52 Peripheral Waveforms CLKOUTA 53 INT4–INT0, NMI, TMRIN1–TMRIN0 54 DRQ1–DRQ0 55 TMROUT1– TMROUT0 94 Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Reset and Bus Hold (20 MHz and 25 MHz) Parameter No. Symbol Description Reset and Bus Hold Timing Requirements Preliminary 20 MHz 25 MHz Min Max Min Max Unit 25 25 0 0 20 20 ns ns 5 15 tCLAV tCLAZ AD Address Valid Delay and BHE AD Address Float Delay 0 0 57 58 tRESIN tHVCL RES Setup Time HOLD Setup(a) 10 10 Reset and Bus Hold Timing Responses 62 tCLHAV HLDA Valid Delay 63 64 tCHCZ tCHCV 0 Command Lines Float Delay Command Lines Valid Delay (after Float) 10 10 25 0 25 25 ns ns 20 ns 20 20 ns ns Reset and Bus Hold (33 MHz and 40 MHz) Preliminary No. Symbol Parameter Description Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay and BHE 33 MHz Min Max 40 MHz Min Max Unit 0 15 0 12 ns AD Address Float Delay RES Setup Time 0 8 15 0 5 12 ns ns HOLD Setup(a) 58 tHVCL Reset and Bus Hold Timing Responses 8 15 57 tCLAZ tRESIN 62 63 tCLHAV tCHCZ HLDA Valid Delay Command Lines Float Delay 64 tCHCV Command Lines Valid Delay (after Float) 0 5 15 15 0 15 ns 12 12 ns ns 12 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL =0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a This timing must be met to guarantee recognition at the next clock. Am186/188ES and Am186/188ESLV Microcontrollers 95 P R E L I M I N A R Y Reset Waveforms X1 57 57 RES CLKOUTA Signals Related to Reset Waveforms RES CLKOUTA BHE/ADEN, RFSH2/ADEN, S6/CLKDIV2, and UZI AD15–AD0 (186) AO15–AO8, AD7–AD0 (188) 96 three-state three-state Am186/188ES and Am186/188ESLV Microcontrollers P R E L I M I N A R Y Bus Hold Waveforms—Entering Case 1 ti ti ti Case 2 t4 ti ti CLKOUTA 58 HOLD 62 HLDA 15 AD15–AD0, DEN 63 A19–A0, S6, RD, WR, BHE, DT/R, S2–S0 WHB, WLB Bus Hold Waveforms—Leaving Case 1 ti ti ti t1 Case 2 ti ti t4 t1 CLKOUTA 58 HOLD 62 HLDA 5 AD15–AD0, DEN 64 A19–A0, S6, RD, WR, BHE, DT/R, S2–S0 WHB, WLB Am186/188ES and Am186/188ESLV Microcontrollers 97 P R E L I M I N A R Y TQFP PHYSICAL DIMENSIONS PQL 100, Trimmed and Formed Thin Quad Flat Pack Pin 100 Pin 75 Pin 1 ID 12.00 Ref –B– –A– 13.80 14.20 15.80 16.20 Pin 25 –D– Pin 50 12.00 Ref 13.80 14.20 15.80 16.20 Top View See Detail X 1.35 1.45 S 1.60 Max –A– –C– Seating Plane S 0.50 Basic 1.00 Ref Side View Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only. 98 Am186/188ES and Am186/188ESLV Microcontrollers pql100 4-15-94 P R E L I M I N A R Y PQL 100 (continued) 0° Min 1.60 Max Gage Plane 0.05 0.15 0.13 R 0.20 0.25 Seating Plane 0.45 0.75 0°–7° 0.17 0.27 Max 0.08 Lead Coplanarity 0.20 Detail X 0.17 0.27 0.14 0.18 Section S-S Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only. Am186/188ES and Am186/188ESLV Microcontrollers pql100 4-15-94 99 P R E L I M I N A R Y PQFP PHYSICAL DIMENSIONS PQR 100, Trimmed and Formed Plastic Quad Flat Pack 17.00 17.40 13.90 14.10 Pin 100 12.35 REF Pin 80 Pin 1 I.D. 18.85 REF 19.90 20.10 –B– –A– 23.00 23.40 Pin 30 –D– Pin 50 Top View See Detail X 0.65 BASIC S 2.70 2.90 3.35 Max 0.25 Min –A– –C– Seating Plane S Side View Notes: 1. All measurements are in millimeters, unless otherwise noted. 2. Not to scale; for reference only. 100 Am186/188ES and Am186/188ESLV Microcontrollers pqr100 4-15-94 P R E L I M I N A R Y PQFP PQR 100 (continued) 0.20 Min. Flat Shoulder 7° Typ. 0° Min. 0.30±0.05 R Gage Plane 3.35 Max 0.25 0.73 1.03 7° Typ. 0°-7° Detail X 0.22 0.38 0.15 0.23 0.22 0.38 0.15 0.23 Section S-S Note: pqr100 4-15-94 Not to scale; for reference only. Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. Am186, Am188, E86, K86, Élan, and AMD Facts-on-Demand are trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am186/188ES and Am186/188ESLV Microcontrollers 101 P R E L I M I N A R Y 102 Am186/188ES and Am186/188ESLV Microcontrollers