AMD AM27X010-120PI 1 megabit (128 k x 8-bit) cmos expressrom device Datasheet

FINAL
Am27X010
1 Megabit (128 K x 8-Bit) CMOS ExpressROM Device
DISTINCTIVE CHARACTERISTICS
■ ±10% power supply tolerance
■ As an OTP EPROM alternative:
— Factory optimized programming
■ High noise immunity
— Fully tested and guaranteed
■ Low power dissipation
— 100 µA maximum CMOS standby current
■ As a Mask ROM alternative:
■ Available in Plastic Dual-In-line Package (PDIP)
and Plastic Leaded Chip Carrier (PLCC)
— Shorter leadtime
— Lower volume per code
■ Latch-up protected to 100 mA from –1 V to
VCC + 1 V
■ Fast access time
— 55 ns
■ Versatile features for simple interfacing
■ Single +5 V power supply
— Both CMOS and TTL input/output compatibility
■ Compatible with JEDEC-approved EPROM
pinout
— Two line control functions
GENERAL DESCRIPTION
The Am27X010 is a factory programmed and tested
OTP EPROM. It is programmed after packaging prior to
final test. Every device is rigorously tested under AC
and DC operating conditions to your stable code. It is
organized as 128 Kwords by 8 bits per word and is
available in plastic dual in-line packages (PDIP), as
well as plastic leaded chip carrier (PLCC) packages.
ExpressROM devices provide a board-ready memory
solution for medium to high volume codes with short
leadtimes. This offers manufacturers a cost-effective
and flexible alternative to OTP EPROMs and mask programmed ROMs.
Data can be accessed as fast as 55 ns, allowing
high-performance microprocessors to operate with reduced WAIT states. The device offers separate Output
Enable (OE#) and Chip Enable (CE#) controls, thus
eliminating bus contention in a multiple bus microprocessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 100 µW in standby mode.
BLOCK DIAGRAM
VCC
Data Outputs DQ0–DQ7
VSS
OE#
CE#
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
A0–A16
Address
Inputs
X
Decoder
Output
Buffers
Y
Gating
1,048,576
Bit Cell
Matrix
12080F-1
Publication# 12080 Rev: F Amendment/0
Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options
Am27X010
VCC = 5.0 V ± 5%
-255
VCC = 5.0 V ± 10%
-55
-70
-90
-120
-150
-200
Max Access Time (ns)
55
70
90
120
150
200
250
CE# (E#) Access (ns)
55
70
90
120
150
200
250
OE# (G#) Access (ns)
35
70
40
50
65
75
100
CONNECTION DIAGRAMS
Top View
32
VCC
A16
2
31
PGM# (P#)
A15
3
30
NC
A12
4
29
A14
A7
5
28
A13
A6
6
27
A16
PGM# (P#)
NC
1
A12
A15
VPP
VPP
PLCC
VCC
DIP
4 3 2 1 32 31 30
A8
A7
5
29
A14
A6
6
28
A13
A5
7
26
A9
A4
8
25
A11
A5
A4
7
8
27
26
A8
A9
A3
9
24
OE# (G#)
A3
9
25
A11
A2
10
23
A10
A2
10
24
OE# (G#)
A1
11
22
CE# (E#)
A1
11
23
A10
A0
12
21
DQ7
A0
12
22
DQ0
13
20
DQ6
DQ0
13
CE# (E#)
DQ7
DQ4
VSS
16
17
DQ3
12080F-2
DQ5
DQ6
DQ5
18
DQ4
19
15
VSS
DQ3
14
DQ2
DQ1
DQ2
DQ1
21
14 15 16 17 18 19 20
12080F-3
Notes:.
1. JEDEC nomenclature is in parenthesis.
2. Don’t use (DU) for PLCC.
PIN DESIGNATIONS
A0–A16
= Address Inputs
CE# (E#)
= Chip Enable Input
DQ0–DQ7
= Data Input/Outputs
OE# (G#)
= Output Enable Input
PGM# (P#)
= Program Enable Input
VCC
= VCC Supply Voltage
VPP
= Program Voltage Input
VSS
= Ground
NC
= No Internal Connection
LOGIC SYMBOL
17
8
A0–A16
DQ0–DQ7
CE# (E#)
2
OE# (G#)
12080F-4
Am27X010
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM27X010
-55
J
C
XXXXX
CODE DESIGNATION
Assigned by AMD
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
P = 32-Pin Plastic Dual In-Line Package (PD 032)
J = 32-Pin Plastic Leaded Chip Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27X010
1 Megabit (128 K x 8-Bit) CMOS ExpressROM Device
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
AM27X010-55
AM27X010-70
AM27X010-90
AM27X010-120
PC, JC, PI, JI
AM27X010-150
AM27X010-200
AM27X010-255
VCC = 5.0 V ± 5%
Am27X010
3
FUNCTIONAL DESCRIPTION
Read Mode
CE# should be decoded and used as the primary device-selecting function, while OE# be made a common
connection to all devices in the array and connected to
the READ line from the system control bus. This assures that all deselected memory devices are in their
low-power standby mode and that the output pins are
only active when data is desired from a particular memory device.
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable for at least t ACC –t OE. Refer to the Switching
Waveforms section for the timing diagram.
System Applications
Standby Mode
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on ExpressROM device arrays, a 4.7 µF bulk electrolytic capacitor
should be used between VCC and VSS for each eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
The device enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Maximum VCC current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at VIH. Maximum VCC current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
■ Low memory power dissipation, and
■ Assurance that output bus contention will not occur.
MODE SELECT TABLE
Mode
CE#
OE#
PGM#
VPP
Outputs
Read
VIL
VIL
X
X
DOUT
Output Disable
X
VIH
X
X
High Z
Standby (TTL)
VIH
X
X
X
High Z
VCC ± 0.3 V
X
X
X
High Z
Standby (CMOS)
Note:
X = Either VIH or VIL.
4
Am27X010
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Voltage with Respect to VSS
All pins except VCC . . . . . . . . . –0.6 V to VCC + 0.6 V
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . –0.6 V to 7.0 V
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Note:
1. Minimum DC voltage on input or I/O pins –0.5 V. During
voltage transitions, the input may overshoot VSS to –2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is VCC + 5 V. During voltage transitions, input
and I/O pins may overshoot to VCC + 2.0 V for periods up
to 20 ns.
Supply Read Voltages
Operating ranges define those limits between which the functionality of the device is guaranteed.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.
Am27X010
5
DC CHARACTERISTICS over operating range (unless otherwise specified)
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –400 µA
VOL
Output LOW Voltage
IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
ILI
Input Load Current
ILO
Min
Max
Unit
2.4
V
0.45
V
2.0
VCC + 0.5
V
–0.5
+0.8
V
VIN = 0 V to VCC
1.0
µA
Output Leakage Current
VOUT = 0 V to VCC
10
µA
ICC1
VCC Active Current (Note 2)
CE# = VIL, f = 10 MHz,
IOUT = 0 mA
30
mA
ICC2
VCC TTL Standby Current
CE# = VIH
1.0
mA
ICC3
VCC CMOS Standby Current
CE# = VCC ± 0.3 V
100
µA
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP..
30
30
25
25
Supply Current
in mA
Supply Current
in mA
2. ICC1 is tested with OE# = VIH to simulate open outputs.
3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
20
15
Figure 1.
6
2
3
4
5
6
7
Frequency in MHz
8
9
15
10
–75 –50 –55 0 25 50 75 100 125 150
Temperature in °C
10
1
20
10
12080F-5
12080F-6
Typical Supply Current vs. Frequency
VCC = 5.5 V, T = 25°C
Figure 2. Typical Supply Current vs. Temperature
VCC = 5.5 V, f = 10 MHz
Am27X010
TEST CONDITIONS
Table 1.
5.0 V
Test Specifications
Test Condition
2.7 kΩ
Device
Under
Test
CL
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
100
pF
Input Rise and Fall Times
≤ 20
ns
Input Pulse Levels
0.45–2.4
V
Input timing measurement reference
levels
0.8, 2.0
V
Output timing measurement
reference levels
0.8, 2.0
V
6.2 kΩ
Note:
Diodes are IN3064 or equivalents.
All
12080F-7
Figure 3.
Test Setup
SWITCHING TEST WAVEFORM
2.4 V
2.0 V
2.0 V
Test Points
0.8 V
0.8 V
0.45 V
Input
Output
Note: For CL = 100 pF.
12080F-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
Am27X010
7
AC CHARACTERISTICS
Parameter Symbols
JEDEC
Standard
tAVQV
tACC
tELQV
Am27X010
Description
Test Setup
-55
-70
-90
-120
-150
-200
-255
Unit
Address to Output Delay
CE#,
Max
OE# = VIL
55
70
90
120
150
200
250
ns
tCE
Chip Enable to Output Delay
OE# = VIL Max
55
70
90
120
150
200
250
ns
tGLQV
tOE
Output Enable to Output Delay CE# = VIL Max
35
35
40
50
65
75
75
ns
tEHQZ
tGHQZ
tDF
(Note 2)
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First
Max
25
25
25
35
35
40
40
ns
tAXQX
tOH
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First
Min
0
0
0
0
0
0
0
ns
Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
Addresses
2.0
0.8
0.45
2.0
0.8
Addresses Valid
CE#
tCE
OE#
tDF (Note 2)
tOE
High Z
Output
tACC
(Note 1)
tOH
High Z
Valid Output
12080F-9
Notes:
1. OE# may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
Parameter
Symbol
CIN
COUT
PD 032
Parameter Description
Test Conditions
Typ
Max
Typ
Max
Unit
Input Capacitance
VIN = 0
8
12
8
10
pF
Output Capacitance
VOUT = 0
11
14
11
12
pF
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25°C, f = 1 MHz.
8
PL 032
Am27X010
PHYSICAL DIMENSIONS
PD 032—32-Pin Plastic Dual In-Line Package (measured in inches)
1.640
1.670
.600
.625
17
32
.009
.015
.530
.580
Pin 1 I.D.
.630
.700
16
.045
.065
0°
10°
.005 MIN
.140
.225
16-038-S_AG
PD 032
EC75
5-28-97 lv
SEATING PLANE
.090
.110
.120
.160
.016
.022
.015
.060
PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)
.447
.453
.485
.495
.009
.015
.585
.595
.042
.056
.125
.140
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
.026
.032
TOP VIEW
SIDE VIEW
Am27X010
16-038FPO-5
PL 032
DA79
6-28-94 ae
9
REVISION SUMMARY FOR AM27X010
Revision F
Global
Changed formatting to match current data sheets.
Distinctive Characteristics
Fast access time: Changed 70 ns to 55 ns.
General Description
Changed “Data can be accessed as fast as 70 ns” to
“Data can be accessed as fast as 55 ns”.
Product Selector Guide
Added the -55 speed option.
Ordering Information
Package Type: Corrected “P = 28-Pin Plastic Dual In-Line
Package (PD 028)” to “P = 32-Pin Plastic Dual In-Line Package (PD 032)”.
Speed Option: Changed -70 to -55.
Valid Combinations: Added Am27X010-55.
AC Characterisitics
Added the -55 speed option.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
10
Am27X010