AMD AM29F080B-75EI 8 megabit (1 m x 8-bit) cmos 5.0 volt-only, uniform sector flash memory Datasheet

PRELIMINARY
Am29F080B
8 Megabit (1 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 V ± 10%, single power supply operation
— Minimizes system level power requirements
■ Manufactured on 0.35 µm process technology
— Compatible with 0.5 µm Am29F080 device
■ High performance
— Access times as fast as 70 ns
■ Low power consumption
— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access
time to active mode)
■ Flexible sector architecture
— 16 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Group sector protection:
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■ Minimum 1,000,000 program/erase cycles per
sector guaranteed
■ Package options
— 40-pin TSOP
— 44-pin SO
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
■ Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
■ Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
Publication# 21503 Rev: C Amendment/+1
Issue Date: April 1998
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29F080B is an 8 Mbit, 5.0 volt-only Flash memory organized as 1,048,576 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F080B is offered in
40-pin TSOP and 44-pin SO packages. This device is
designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not
required for program or erase operations. The device
can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.35 µm
process technology, and offers all the features and benefits of the Am29F080, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention,
the device has separate chip enable (CE#), write enable
(WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
2
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y a n d c o s t
effectiveness. The device electrically erases all
bits within a sector simultaneously via
F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s
programmed using hot electron injection.
Am29F080B
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F080B
VCC = 5.0 V ± 5%
Speed Option
-75
VCC = 5.0 V ± 10%
-90
-120
-150
Max Access Time, ns (tACC)
70
90
120
150
Max CE# Access, ns (tCE)
70
90
120
150
Max OE# Access, ns (tOE)
40
40
50
75
Note: See the “AC Characteristics” section for more information.
BLOCK DIAGRAM
DQ0–DQ7
Sector Switches
VCC
VSS
Erase Voltage
Generator
RY/BY#
RESET#
WE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A19
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
21503C-1
Am29F080B
3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40-Pin Standard TSOP
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
21503C-2
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40-Pin Reverse TSOP
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
21503C-3
NC
RESET#
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
VSS
VSS
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO
Am29F080B
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE#
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
21503C-4
P R E L I M I N A R Y
PIN CONFIGURATION
A0–A19
=
LOGIC SYMBOL
20 Addresses
DQ0–DQ7 =
8 Data Inputs/Outputs
CE#
=
Chip Enable
WE#
=
Write Enable
OE#
=
Output Enable
RESET#
=
Hardware Reset Pin, Active Low
RY/BY#
=
Ready/Busy Output
VCC
= +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS
=
Device Ground
NC
=
Pin Not Connected Internally
20
A0–A19
8
DQ0–DQ7
CE#
OE#
WE#
RESET#
RY/BY#
21503C-5
Am29F080B
5
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29F080B
-75
E
I
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
E = 40-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 040)
F
= 40-Pin Thin Small Outline Package
(TSOP) Reverse Pinout (TSR040)
S
= 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F080B
8 Megabit (1 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
Valid Combinations
Valid Combinations
Am29F080B-75
Am29F080B-90
Am29F080B-120
Am29F080B-150
6
EC, EI, FC, FI, SC, SI
EC, EI, EE,
FC, FI, FE,
SC, SI, SE
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F080B
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the
commands, along with the address and data information needed to execute the command. The contents of
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F080B Device Bus Operations
CE#
OE#
WE#
RESET#
A0–A19
DQ0–DQ7
Read
L
L
X
H
AIN
DOUT
Write
L
H
L
H
AIN
DIN
TTL Standby
H
X
X
H
X
HIGH Z
CMOS Standby
VCC ± 0.3 V
X
X
VCC ± 0.3 V
X
HIGH Z
Output Disable
L
H
H
H
X
HIGH Z
Hardware Reset
X
X
X
VIL
X
HIGH Z
Temporary Sector Group Unprotect (See Note)
X
X
X
VID
AIN
X
Operation
Legend:
L = Logic Low = VIL, H = Logic High = VIH, DOUT = Data Out, DIN = Data In, AIN = Address In, X = Don’t Care. See DC Characteristics for voltage levels.
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should remain at VIH.
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the Command Definitions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Am29F080B
7
P R E L I M I N A R Y
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Characteristics section in the appropriate data sheet for timing
diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when
the device is in either of these standby modes, before it
is ready to read data.
The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, “RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
8
drives the RESET# pin low for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Am29F080B
P R E L I M I N A R Y
Table 2.
Am29F080B Sector Address Table
Sector
A19
A18
A17
A16
Address Range
SA0
0
0
0
0
000000h–00FFFFh
SA1
0
0
0
1
010000h–01FFFFh
SA2
0
0
1
0
020000h–02FFFFh
SA3
0
0
1
1
030000h–03FFFFh
SA4
0
1
0
0
040000h–04FFFFh
SA5
0
1
0
1
050000h–05FFFFh
SA6
0
1
1
0
060000h–06FFFFh
SA7
0
1
1
1
070000h–07FFFFh
SA8
1
0
0
0
080000h–08FFFFh
SA9
1
0
0
1
090000h–09FFFFh
SA10
1
0
1
0
0A0000h–0AFFFFh
SA11
1
0
1
1
0B0000h–0BFFFFh
SA12
1
1
0
0
0C0000h–0CFFFFh
SA13
1
1
0
1
0D0000h–0DFFFFh
SA14
1
1
1
0
0E0000h–0EFFFFh
SA15
1
1
1
1
0F0000h–0FFFFFh
Note: All sectors are 64 Kbytes in size.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
“Command Definitions” for details on using the autoselect mode.
Am29F080B
9
P R E L I M I N A R Y
Table 3.
Am29F080B Autoselect Codes (High Voltage Method)
Description
CE#
OE#
WE#
A19
to
A12
A11
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
Manufacturer ID: AMD
L
L
H
X
X
VID
X
L
X
L
L
01h
Device ID: Am29F080B
L
L
H
X
X
VID
X
L
X
L
H
D5h
Sector Group
Protection Verification
L
L
H
SGA
X
VID
X
L
X
H
L
01h (protected)
00h
(unprotected)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SGA = Sector Group Address, X = Don’t care.
Note: The system may also autoselect information in-system via the command register. See Table 5.
Sector Group Protection/Unprotection
Temporary Sector Group Unprotect
The hardware group sector protection feature disables both program and erase operations in any sector group. Each sector group consists of two adjacent
sectors. Table 4 shows how the sectors are grouped,
and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in
previously protected sector groups.
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated
by setting the RESET# pin to VID. During this mode,
formerly protected sector groups can be programmed
or erased by selecting the sector group addresses.
Once V ID is removed from the RESET# pin, all the
p r ev i ou s ly p ro t ec te d se ct o r gr o u p s a r e
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram
shows the timing waveforms, for this feature.
Sector group protection/unprotection must be implemented using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, listed in publication number 19945. Contact an AMD representative to obtain a copy of the appropriate document.
START
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sector groups at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” for
details.
Table 4.
RESET# = VIH
Sector Group Addresses
Sector
Group
A19
A18
A17
Sectors
SGA0
0
0
0
SA0–SA1
SGA1
0
0
1
SA2–SA3
SGA2
0
1
0
SA4–SA5
SGA3
0
1
1
SA6–SA7
SGA4
1
0
0
SA8–SA9
SGA5
1
0
1
SA10–SA11
SGA6
1
1
0
SA12–SA13
SGA7
1
1
1
SA14–SA15
Temporary Sector Group
Unprotect
Completed (Note 2)
21503C-6
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Figure 1.
10
Am29F080B
Temporary Sector Group Unprotect
Operation
P R E L I M I N A R Y
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than V LKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Am29F080B
11
P R E L I M I N A R Y
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the improper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
12
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the programmed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.
Am29F080B
P R E L I M I N A R Y
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The program command sequence
should be reinitiated once the device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Write Program
Command Sequence
Data Poll
from System
Sector Erase Command Sequence
Verify Data?
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
No
Yes
Increment Address
No
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
Last Address?
Yes
Programming
Completed
21503C-7
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latched.
START
Embedded
Program
algorithm
in progress
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
Am29F080B
13
P R E L I M I N A R Y
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for information on these status bits.
Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command.
14
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device has resumed erasing.
Am29F080B
P R E L I M I N A R Y
START
Write Erase
Command Sequence
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
21503C-8
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3.
Erase Operation
Am29F080B
15
P R E L I M I N A R Y
Table 5.
Am29F080B Command Definitions
Cycles
Bus Cycles (Notes 2–5)
Addr
Read (Note 3)
1
RA
RD
Reset (Note 4)
1
XXX
F0
Autoselect
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
01
Autoselect
Device ID
4
555
AA
2AA
55
555
90
X01
D5
90
SGA
X02
01
Command
Sequence
(Note 1)
First
Second
Data
Third
Fourth
Addr
Data
Addr
Data
Addr
Data
Fifth
Sixth
Addr
Data
Addr
Data
00
Autoselect
Sector Group
Protect Verify
(Note 5)
4
Byte Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend
(Note 6)
1
XXX
B0
Erase Resume
(Note 7)
1
XXX
30
555
AA
2AA
55
555
Legend:
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse.
SA = Address of the sector to be erased. Address bits A19–A16 uniquely select any sector.
SGA = Address of the sector group to be verified.
Notes:
1. All values are in hexadecimal.
2. See Table 1 for descriptions of bus operations.
3. No unlock or command cycles required when device is in read mode.
4. The Reset command is required to return to the read mode when the device is in the autoselect mode or if DQ5 goes high.
5. The data is 00h for an unprotected sector group and 01h for a protected sector group. The complete bus address in the fourth
cycle is composed of the sector group address (A19–A17), A1 = 1, and A0 = 0.
6. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode. The Erase Suspend command
is valid only during a sector erase operation.
7. The Erase Resume command is valid only during the Erase Suspend mode.
8. Unless otherwise noted, address bits A19–A11 are don’t care.
16
Am29F080B
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
Read DQ7–DQ0
Addr = VA
The Data# Polling bit, DQ7, indicates to the host
sys tem whether an Embedded Algor ithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 2 µs, then the device returns to reading
array data.
DQ7 = Data?
No
No
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected.
Yes
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am29F080B
21503C-9
Figure 4.
Data# Polling Algorithm
17
P R E L I M I N A R Y
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
18
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
Am29F080B
P R E L I M I N A R Y
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
check, the last command might not have been accepted. Table 6 shows the outputs for DQ3.
START
DQ5: Exceeded Timing Limits
Read DQ7–DQ0
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.”
Read DQ7–DQ0
Note 1
Toggle Bit
= Toggle?
No
Yes
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
No
DQ5 = 1?
DQ3: Sector Erase Timer
Yes
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between additional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command Sequence” section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Am29F080B
21503C-10
Figure 5.
Toggle Bit Algorithm
19
P R E L I M I N A R Y
Table 6.
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Write Operation Status
DQ7
(Note 1)
DQ6
DQ5
(Note 2)
DQ3
DQ2
(Note 1)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
20
Am29F080B
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
20 ns
20 ns
+0.8 V
–0.5 V
VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9, OE#, RESET# (Note 2) . . . .–2.0 V to +12.5 V
–2.0 V
All other pins (Note 1) . . . . . . . . . –2.0 V to +7.0 V
20 ns
Output Short Circuit Current (Note 3) . . . . . . 200 mA
21503-11
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 6. Maximum DC
voltage on output and I/O pins is VCC + 0.5 V. During
voltage transitions, outputs may overshoot to VCC + 2.0 V
for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5V. During voltage transitions, A9, OE#, RESET# pins
may overshoot VSS to –2.0 V for periods of up to 20 ns.
See Figure 6. Maximum DC input voltage on A9, OE#,
and RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Figure 6.
Maximum Negative Overshoot
Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
Stresses greater than those listed in this section may cause
permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure of the device to absolute
maximum rating conditions for extended periods may affect device reliability.
20 ns
21503-12
Figure 7.
Maximum Negative Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Case Temperature (TC) . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Case Temperature (TC) . . . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for± 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Am29F080B
21
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
ILIT
A9 Input Load Current
VCC = VCC Max, A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max
ICC1
VCC Read Current (Note 1)
CE# = VIL, OE# = VIH
ICC2
VCC Write Current (Notes 2, 3)
ICC3
VCC Standby Current
(CE# Controlled)
ICC4
VCC Standby Current
(RESET# Controlled)
VCC = VCC Max, RESET# = VIL
VIL
Input Low Level
VIH
Min
Typ
Max
Unit
±1.0
µA
50
µA
±1.0
µA
25
40
mA
CE# = VIL, OE# = VIH
40
60
mA
VCC = VCC Max, CE# = VIH,
RESET# = VIH
0.4
1.0
mA
0.4
1.0
mA
–0.5
0.8
V
Input High Level
2.0
VCC + 0.5
V
VID
Voltage for Autoselect and Sector
VCC = 5.0 V
Protect
11.5
12.5
V
VOL
Output Low Voltage
IOL = 12 mA, VCC = VCC Min
0.45
V
VOH
Output High Level
IOH = –2.5 mA VCC = VCC Min
VLKO
Low VCC Lock-out Voltage
2.4
V
3.2
4.2
V
Max
Unit
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
ILIT
A9 Input Load Current
VCC = VCC Max, A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC Max
Typ
±1.0
µA
50
µA
±1.0
µA
ICC1
VCC Read Current (Note 1)
CE# = VIL, OE# = VIH
25
40
mA
ICC2
VCC Write Current (Notes 2, 3)
CE# = VIL, OE# = VIH
30
40
mA
ICC3
VCC Standby Current
(CE# Controlled)
VCC = VCC Max, CE# = VCC ± 0.3 V,
RESET# = VCC ± 0.3 V
1
5
µA
ICC4
VCC Standby Current
(RESET# Controlled)
VCC = VCC Max,
RESET# = VSS ± 0.3 V
1
5
µA
VIL
Input Low Level
–0.5
0.8
V
VIH
Input High Level
0.7x VCC
VCC + 0.3
V
VID
Voltage for Autoselect
and Sector Protect
11.5
12.5
V
VOL
Output Low Voltage
VOH1
VOH2
VLKO
Output High Voltage
VCC = 5.0 V
IOL = 12 mA, VCC = VCC Min
0.45
V
IOH = –2.5 mA, VCC = VCC Min
0.85 VCC
V
IOH = –100 µA, VCC = VCC Min
VCC – 0.4
V
Low VCC Lock-out Voltage
3.2
Notes for DC Characteristics (both tables):
1. The ICC current listed includes is typically less than 1 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Program or Embedded Erase algorithm is in progress.
3. Not 100% tested.
22
Min
Am29F080B
4.2
V
P R E L I M I N A R Y
TEST CONDITIONS
Table 7.
5.0 V
Test Specifications
Test Condition
2.7 kΩ
Device
Under
Test
CL
-75
Output Load
6.2 kΩ
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
0.0–3.0
0.45–2.4
V
Input timing measurement
reference levels
1.5
0.8, 2.0
V
Output timing measurement
reference levels
1.5
0.8, 2.0
V
Input Pulse Levels
Note: Diodes are IN3064 or equivalent
All others
21503-13
Figure 8.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
KS000010-PAL
Am29F080B
23
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-only Operations
Parameter Symbol
JEDEC
Standard
tAVAV
tRC
Parameter Description
Read Cycle Time (Note 1)
-75
-90
-120
-150
Unit
Min
70
90
120
150
ns
Max
70
90
120
150
ns
Max
70
90
120
150
ns
Max
40
40
50
55
ns
Read
Min
0
0
0
0
ns
Toggle and
Data# Polling
Min
10
10
10
10
ns
tACC
Address to Output Delay
CE# = VIL
OE# = VIL
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
tGLQV
tOE
Output Enable to Output Delay
tOEH
Output Enable Hold
Time (Note 1)
tAVQV
Speed Options
Test
Setup
tEHQZ
tDF
Chip Enable to Output High Z
Max
20
20
30
35
ns
tGHQZ
tDF
Output Enable to Output High Z
Max
20
20
30
35
ns
tOH
Output Hold Time From Addresses CE#
or OE# Whichever Occurs First
Min
0
0
0
0
ns
RESET# Pin Low to Read Mode
(Note 1)
Max
20
20
20
20
µs
tAXQX
tReady
Notes:
1. Not 100% tested.
2. Refer to Figure 8 and Table 7 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
21503C-14
Figure 9.
24
Read Operation Timings
Am29F080B
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
Max
20
µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
21503C-15
Figure 10.
RESET# Timings
Am29F080B
25
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
JEDEC
Std.
Parameter Description
-75
-90
-120
-150
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
90
120
150
ns
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
40
45
50
50
ns
tDVWH
tDS
Data Setup Time
Min
40
45
50
50
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recover Time Before Write
(OE# high to WE# low)
Min
0
ns
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
20
ns
tWHWH1
tWHWH1
Byte Programming Operation (Note 2)
Typ
7
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
tVCS
VCC Set Up Time (Note 1)
Min
50
µs
tBUSY
WE# to RY/BY# Valid
Min
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
26
Am29F080B
40
40
45
40
50
50
50
60
ns
ns
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
Read Status Data (last two cycles)
PA
PA
PA
tAH
CE#
tCH
tGHWL
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
tVCS
VCC
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
21503C-16
Figure 11.
Program Operation Timings
Am29F080B
27
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tGHWL
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Note:
SA = Sector Address. VA = Valid Address for reading status data.
21503C-17
Figure 12.
28
Chip/Sector Erase Operation Timings
Am29F080B
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
21503C-18
Figure 13.
Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
21503C-19
Figure 14.
Toggle Bit Timings (During Embedded Algorithms)
Am29F080B
29
P R E L I M I N A R Y
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase Suspend
Read
Erase
Complete
Erase
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 must be read at an address within the erase-suspended
sector.
21503C-20
Figure 15.
DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std.
Description
tVIDR
VID Rise and Fall Time (See Note)
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
All Speed Options
Unit
Min
500
ns
Min
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
21503C-21
Figure 16.
30
Temporary Sector Group Unprotect Timing Diagram
Am29F080B
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Parameter Symbol
Speed Options
JEDEC
Standard
Parameter Description
-75
-90
-120
-150
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
90
120
150
ns
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
40
45
50
50
ns
tDVEH
tDS
Data Setup Time
Min
40
45
50
50
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recover Time Before Write
Min
0
ns
tWLEL
tWS
CE# Setup Time
Min
0
ns
tEHWH
tWH
CE# Hold Time
Min
0
ns
tELEH
tCP
Write Pulse Width
Min
tEHEL
tCPH
Write Pulse Width High
Min
20
ns
tWHWH1
tWHWH1
Byte Programming Operation (Note 2)
Typ
7
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
0
40
45
ns
50
50
ns
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
Am29F080B
31
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
21503C-22
Figure 17.
32
Alternate CE# Controlled Write Operation Timings
Am29F080B
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
1
8
sec
Chip Erase Time
16
128
sec
Byte Programming Time
7
300
µs
7.2
21.6
sec
Chip Programming Time (Note 3)
Comments
Excludes 00h programming prior to
erasure (Note 4)
Excludes system-level overhead
(Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 for -75), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 5 for further
information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 1,000,000 cycles are guaranteed.
LATCHUP CHARACTERISTIC
Input Voltage with respect to VSS on I/O pins
VCC Current
Min
Max
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
6
7.5
pF
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
CIN
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
Am29F080B
33
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package (measured in millimeters)
44
23
13.10
13.50
1
15.70
16.30
22
1.27 NOM.
TOP VIEW
28.00
28.40
2.17
2.45
0.10
0.21
2.80
MAX.
0.35
0.50
0.10
0.35
SEATING
PLANE
SIDE VIEW
34
0°
8°
0.60
1.00
END VIEW
16-038-SO44-2
SO 044
DF83
8-8-96 lv
Am29F080B
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
TS 040—40-Pin Standard Thin Small Outline Package
0.95
1.05
Pin 1 I.D.
1
40
9.90
10.10
0.50 BSC
21
20
0.05
0.15
18.30
18.50
19.80
20.20
0.08
0.20
0.10
0.21
1.20
MAX
0°
5°
0.50
0.70
Am29F080B
16-038-TSOP-1_AE
TS 040
2-27-97 lv
35
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
TSR040—40-Pin Reverse Thin Small Outline Package
0.95
1.05
Pin 1 I.D.
1
40
9.90
10.10
0.50 BSC
21
20
0.05
0.15
18.30
18.50
19.80
20.20
0.08
0.20
0.10
0.21
1.20
MAX
0°
5°
0.50
0.70
36
Am29F080B
16-038-TSOP-1_AE
TSR040
2-27-97 lv
P R E L I M I N A R Y
REVISION SUMMARY FOR AM29F080B
Revision B
Revision C+1
Global
Distinctive Characteristics
Formatted for consistency with other 5.0 volt-only data
sheets.
Changed minimum 100K write/erase cycles guaranteed to 1,000,000.
Figure 9, Read Operation Timings
AC Characteristics
Corrected RESET# waveform so that it is high for the
duration of the read cycle.
Erase/Program Operations; Erase and Program Operations Alternate CE# Controlled Writes: Corrected the
notes reference for tWHWH1 and tWHWH2. These parameters are 100% tested. Corrected the note reference for
tVCS. This parameter is not 100% tested.
Figure 11, Chip/Sector Erase Operation Timings
Corrected data unlock cycle in diagram to 55h.
Figure 17, Alternate CE# Controlled Program
Operation Timings
Temporary Sector Unprotect Table
Corrected command for sector erase to 30h, chip erase
to 10h.
Added note reference for tVIDR. This parameter is not
100% tested.
Command Definitions
Revision C
Corrected the shift in the table header.
Standby Mode
Erase and Programming Performance
Removed sentence in first paragraph referring to RESET# pulse.
Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.
Sector Group Protection/Unprotection, Temporary
Sector Group Unprotect
Changed references from “sector” to “sector group”.
Corrected text to indicate sector groups are composed
of two adjacent sectors.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29F080B
37