AMD AM29LV040B-60RJD 4 megabit (512 k x 8-bit) cmos 3.0 volt-only, uniform sector 32-pin flash memory Datasheet

Am29LV040B
Data Sheet
The Am29LV040B is not offered for new designs. Please contact a Spansion representative for alternates.
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro and
changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 21354 Revision E
Amendment 4 Issue Date October 11, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV040B
4 Megabit (512 K x 8-Bit)
CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory
The Am29LV040B is not offered for new designs. Please contact a Spansion representative for alternates.
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Manufactured on 0.32 µm process technology
■ High performance
— Full voltage range: access times as fast as 70 ns
— Regulated voltage range: access times as fast as
60 ns
■ Ultra low power consumption (typical values at
5 MHz)
■ Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■ Embedded Algorithms
— Embedded Erase algorithms automatically
preprogram and erase the entire chip or any
combination of designated sectors
— Embedded Program algorithms automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 erase cycles guaranteed
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
— Automatic sleep mode: 0.2 µA
— 32-pin PLCC
— Standby mode: 0.2 µA
— 32-pin TSOP
— Read mode: 7 mA
— Program/erase mode: 15 mA
■ Flexible sector architecture
— Eight 64 Kbyte sectors
— Any combination of sectors can be erased;
supports full chip erase
— Sector Protection features:
Hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked via programming
equipment
■ Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting program
or erase cycle completion
■ Erase Suspend/Resume
— Supports reading data from or programming data
to a sector not being erased
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21354 Rev: E Amendment: 4
Issue Date: October 11, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29LV040B is a single power supply, 4 Mbit, 3.0
Volt-only Flash memory device organized as 524,288
bytes. The data appears on DQ0-DQ7. The device is
available in 32-pin PLCC and 32-pin TSOP packages. All
read, erase, and program operations are accomplished
using only a single power supply. The device can also be
programmed in standard EPROM programmers.
The device offers access times of 60, 70, 90, and 120 ns
allowing high speed microprocessors to operate without
wait states. To eliminate bus contention, the device has
separate control pins—chip enable (CE#), write enable
(WE#), and output enable (OE#)—to control normal
read and write operations.
The device requires only a single power supply (2.7
V–3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automatically
4
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of
memory. This is achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1. Am29LV040B Device Bus Operations . . . . . . . . . . . . . . .10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22
Requirements for Reading Array Data . . . . . . . . . . . . . . . . .
Writing Commands/Command Sequences . . . . . . . . . . . . . .
Program and Erase Operation Status . . . . . . . . . . . . . . . . . .
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
11
11
11
Table 2. Am29LV040BT Sector Address Table . . . . . . . . . . . . . . .11
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Am29LV040B Autoselect Codes (High Voltage Method) .12
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 12
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Write Pulse “Glitch” Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 4. Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . 20
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. Maximum Negative Overshoot Waveform . . . . . . . . . . . 22
Figure 6. Maximum Positive Overshoot Waveform. . . . . . . . . . . . 22
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Typical ICC1 vs. Frequency . . . . . . . . . . . . . . . . . . . . . . 24
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Test Specifications ........................................................... 25
Key to Switching Waveforms. . . . . . . . . . . . . . . . 25
Figure 10. Input Waveforms and Measurement Levels . . . . . . . . 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . 26
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 13
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . 13
Byte Program Command Sequence . . . . . . . . . . . . . . . . . . . 13
Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Unlock Bypass Command Sequence . . . . . . . . . . . . . . . . . . . . . . .14
Alternate CE# Controlled Erase/Program Operations . . . . . . 31
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . 14
Figure 1. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . 15
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . 15
Figure 2. Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Am29LV040B Command Definitions . . . . . . . . . . . . . . . . .17
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 18
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 18
October 11, 2006 21354E4
Figure 12. Program Operation Timings. . . . . . . . . . . . . . . . . . . . .
Figure 13. Chip/Sector Erase Operation Timings . . . . . . . . . . . . .
Figure 14. Data# Polling Timings (During Embedded Algorithms)
Figure 15. Toggle Bit Timings (During Embedded Algorithms). . .
Figure 16. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
29
29
30
Figure 17. Alternate CE# Controlled Write Operation Timings . . . 32
Erase and Programming Performance . . . . . . . 33
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 33
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 33
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 34
TS 032—32-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . 34
PL 032—32-Pin Plastic Leaded Chip Carrier . . . . . . . . . . . . 35
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 36
Am29LV040B
5
D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options
Am29LV040B
Regulated Voltage Range: VCC =3.0–3.6 V
-60R
Full Voltage Range: VCC = 2.7–3.6 V
-70
-90
-120
Max access time, ns (tACC)
60
70
90
120
Max CE# access time, ns (tCE)
60
70
90
120
Max OE# access time, ns (tOE)
30
30
30
35
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
VCC
Sector Switches
VSS
Erase Voltage
Generator
WE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A18
6
Am29LV040B
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
21354E4 October 11, 2006
D A T A
S H E E T
WE#
A17
A18
VCC
A16
A12
A15
CONNECTION DIAGRAMS
4 3 2 1 32 31 30
A7
5
29
A14
A6
6
28
A13
A5
A4
7
8
27
26
A9
A3
9
25
A11
A2
10
24
OE#
A1
11
23
A10
A0
12
22
CE#
DQ0
13
21
DQ7
32-Pin PLCC
A8
A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4
October 11, 2006 21354E4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ5
DQ6
DQ4
VSS
DQ3
DQ1
DQ2
14 15 16 17 18 19 20
32-pin Standard TSOP
Am29LV040B
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
7
D A T A
PIN CONFIGURATION
A0–A18
S H E E T
LOGIC SYMBOL
= 19 address inputs
19
DQ0–DQ7 = 8 data inputs/outputs
A0–A18
CE#
= Chip enable
OE#
= Output enable
WE#
= Write enable
CE#
VCC
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
OE#
VSS
8
8
DQ0–DQ7
WE#
= Device ground
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29LV040B
-60R
E
C
TEMPERATURE RANGE
C
= Commercial (0°C to +70°C)
D
= Commercial (0°C to +70°C) with Pb-free package
I
= Industrial (–40°C to +85°C)
F
= Industrial (–40°C to +85°C) with Pb-free package
E
= Extended (–55°C to +125°C)
K
= Extended (–55°C to +125°C) with Pb-free package
PACKAGE TYPE
J
= 32-Pin Plastic Leaded Chip Carrier (PL 032)
E
= 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29LV040B
4 Megabit (512 K x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program and Erase
Valid Combinations
Valid Combinations
AM29LV040B-60R
JC, JD, JI, JF,
EC, ED, EI, EF,
AM29LV040B-70
AM29LV040B-90
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
JC, JD, JI, JF, JE, JK
EC, ED, EI, EF, EE, EK
AM29LV040B-120
October 11, 2006 21354E4
Am29LV040B
9
D A T A
S H E E T
DEVICE BUS OPERATIONS
the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory location. The register is composed of latches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1.
Operation
CE#
Am29LV040B Device Bus Operations
OE#
WE#
Addresses (Note 1)
DQ0–DQ7
Read
L
L
H
AIN
DOUT
Write
L
H
L
AIN
DIN
VCC ± 0.3 V
X
X
X
High-Z
Output Disable
L
H
H
X
High-Z
Reset
X
X
X
X
High-Z
Sector Protect (Note 2)
L
H
L
Sector Address, A6 = L, A1 = H, A0 = L
DIN, DOUT
Sector Unprotect (Note 2)
L
H
L
Sector Address, A6 = H, A1 = H, A0 = L
DIN, DOUT
Temporary Sector Unprotect
X
X
X
AIN
DIN
Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH.
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to Figure 11 for the timing diagram. ICC1 in the
DC Characteristics table represents the active current
specification for reading array data.
10
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has
details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
Am29LV040B
21354E4 October 11, 2006
D A T A
in this mode. Refer to the Autoselect Mode and Autosel e c t C o m m a n d S e q u e n c e s e c t i o n s fo r m o r e
information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
the standby mode, but the standby current will be
greater. The device requires standard access time (tCE)
for read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is both held at VCC ± 0.3 V. (Note that this is a
more restricted voltage range than VIH.) If CE# is held
at VIH, but not within VCC ± 0.3 V, the device will be in
Table 2.
S H E E T
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Am29LV040BT Sector Address Table
Sector
A18
A17
A16
Address Range
(in hexadecimal)
SA0
0
0
0
00000h-0FFFFh
SA1
0
0
1
10000h-1FFFFh
SA2
0
1
0
20000h-2FFFFh
SA3
0
1
1
30000h-3FFFFh
SA4
1
0
0
40000h-4FFFFh
SA5
1
0
1
50000h-5FFFFh
SA6
1
1
0
60000h-6FFFFh
SA7
1
1
1
70000h-7FFFFh
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
October 11, 2006 21354E4
Table 3. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Table 2). Table 3 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 4. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Am29LV040B
11
D A T A
Table 3.
S H E E T
Am29LV040B Autoselect Codes (High Voltage Method)
CE#
OE#
WE#
A18
to
A16
Manufacturer ID: AMD
L
L
H
X
X
VID
X
L
X
L
L
01h
Device ID: Am29LV040B
L
L
H
X
X
VID
X
L
X
L
H
4Fh
Description
A15
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection method intended only
for programming equipment requires VID on address
pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD
flash devices. Publication number 22168 contains
further details; contact an AMD representative to
request a copy.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadver tent writes (refer to Table 4 for
command definitions). In addition, the following hardware data protection measures prevent accidental
12
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When V CC is less than V LKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 4 defines the valid register command
sequences. Writing incorrect address and data values
or writing them in the improper sequence may place the
device in an unknown state. A reset command is then
required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies dur ing Erase
Suspend).
Autoselect Command Sequence
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more information on this mode.
The system must issue the reset command to reenable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parameters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
October 11, 2006 21354E4
however, the device ignores reset commands until the
operation is complete.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 4 shows the address and data requirements. This
method is an alternative to that shown in Table 3, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address 00h retrieves the
manufacturer code. A read cycle at address 01h
returns the device code. A read cycle containing a
sector address (SA) and the address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Table 2 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The byte program command sequence programs one
byte into the device. Programming is a four-bus-cycle
operation. The program command sequence is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verify the programmed cell margin.
Table 4 shows the address and data requirements for
the byte program command sequence. Note that the
autoselect function is unavailable when a program
operation is in progress.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Am29LV040B
13
D A T A
S H E E T
DQ7 or DQ6. See “Write Operation Status” for information on these status bits.
START
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programmin g o pe ra ti on . T he B y te P ro gra m c om ma nd
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Write Program
Command Sequence
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes to the device faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A twocycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 4 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. The device
then returns to reading array data.
Figure 1 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 12 for
timing diagrams.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
14
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See Table 4 for program command sequence.
Figure 1.
Program Operation
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence. Note that the autoselect function
is unavailable when an erase operation is in progress.
Any commands wr itten to the chip dur ing the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Am29LV040B
21354E4 October 11, 2006
D A T A
Characteristics” for parameters, and to Figure 13 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 4 shows the address and data
requirements for the sector erase command sequence.
Note that the autoselect function is unavailable when
an erase operation is in progress.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
October 11, 2006 21354E4
S H E E T
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, or
DQ2. (Refer to “Write Operation Status” for information
on these status bits.)
Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 13 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
Am29LV040B
15
D A T A
S H E E T
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
START
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
Write Erase
Command Sequence
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 4 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 2.
16
Am29LV040B
Erase Operation
21354E4 October 11, 2006
D A T A
S H E E T
Command Definitions
Command
Sequence
(Note 1)
Cycles
Table 4.
Am29LV040B Command Definitions
Bus Cycles (Notes 2-4)
First
Second
Addr
Data
Read (Note 5)
1
RA
RD
Reset (Note 6)
1
XXX
F0
Manufacturer ID
AutoDevice ID
select
(Note 7) Sector Protect Verify
(Note 8)
Addr
Data
Third
Addr
Fourth
Data Addr
Data
Fifth
Sixth
Addr Data
Addr
Data
4
555
AA
2AA
55
555
90
X00
01
4
555
AA
2AA
55
555
90
X01
4F
4
555
AA
2AA
55
555
90
(SA)
X02
00
Program
4
555
AA
2AA
55
555
A0
PA
PD
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program (Note 9)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 10)
2
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 11)
1
XXX
B0
Erase Resume (Note 12)
1
XXX
30
01
Legend:
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Don’t care
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A13 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
9. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all command
bus cycles are write operations.
4. Address bits A18–A11 are don’t cares for unlock and
command cycles.
5. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
10. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass
mode.
11. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
12. The Erase Resume command is valid only during the Erase
Suspend mode.
7. The fourth cycle of the autoselect command sequence is a
read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
October 11, 2006 21354E4
Am29LV040B
17
D A T A
S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 5 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
FAIL
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 14, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
18
Yes
DQ7 = Data?
Yes
No
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am29LV040B
Figure 3.
Data# Polling Algorithm
21354E4 October 11, 2006
D A T A
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either OE#
or CE# to control the read cycles. When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 5 shows the outputs for Toggle Bit I on DQ6.
Figure 4 shows the toggle bit algorithm. Figure 15 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 16 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
October 11, 2006 21354E4
S H E E T
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to compare outputs
for DQ2 and DQ6.
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 15 shows the toggle bit timing diagram. Figure
16 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).
Am29LV040B
19
D A T A
S H E E T
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
START
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Read DQ7–DQ0
(Note 1)
Read DQ7–DQ0
Toggle Bit
= Toggle?
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
No
DQ3: Sector Erase Timer
Yes
No
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches
from “0” to “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the “Sector Erase Command Sequence”
section.
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
Figure 4.
20
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 5 shows the outputs for DQ3.
Toggle Bit Algorithm
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
Table 5. Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ7#
Toggle
0
N/A
No toggle
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
October 11, 2006 21354E4
Am29LV040B
21
D A T A
S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
A9, OE# (Note 2) . . . . . . . . . . . . –0.5 V to +12.5 V
20 ns
+0.8 V
–0.5 V
–2.0 V
All other pins
(Note 1) . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
20 ns
Figure 5. Maximum Negative
Overshoot Waveform
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 5. Maximum
DC voltage on input or I/O pins is VCC +0.5 V. During
voltage transitions, input or I/O pins may overshoot to VCC
+2.0 V for periods up to 20 ns. See Figure 6.
2. Minimum DC input voltage on pins A9 and OE# is –0.5 V.
During voltage transitions, A9 and OE# may overshoot
VSS to –2.0 V for periods of up to 20 ns. See Figure 5.
Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns.
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
Figure 6. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range. . . . . . . 3.0 V to 3.6 V
VCC for full voltage range . . . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
22
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
Min
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH
ICC2
VCC Active Write Current
(Notes 2, 3, 4)
ICC3
VCC Standby Current (Note 2)
ICC4
VCC Reset Current (Note 2)
ICC5
Automatic Sleep Mode
(Notes 2, 5)
VIL
Input Low Voltage
VIH
Input High Voltage
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 3.3 V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
VOH1
Output High Voltage
VOH2
VLKO
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
5 MHz
7
12
1 MHz
2
4
CE# = VIL, OE# = VIH
15
30
mA
CE# = VCC ± 0.3 V
0.2
5
µA
0.2
5
µA
0.2
5
µA
–0.5
0.8
V
0.7 x VCC
VCC + 0.3
V
11.5
12.5
V
0.45
V
mA
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
IOH = –2.0 mA, VCC = VCC min
0.85 VCC
IOH = –100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage
(Note 4)
2.3
V
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC current specifications are tested with VCC=VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
October 11, 2006 21354E4
Am29LV040B
23
D A T A
S H E E T
DC CHARACTERISTICS (continued)
Zero Power Flash
Supply Current in mA
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 7.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
Supply Current in mA
8
3.6 V
6
2.7 V
4
2
0
1
2
3
Frequency in MHz
4
5
Note: T = 25 °C
Figure 8.
24
Typical ICC1 vs. Frequency
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
TEST CONDITIONS
Table 6.
Test Specifications
3.3 V
-60R,
-70
Test Condition
2.7 kΩ
Device
Under
Test
CL
Output Load
-90,
-120
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
6.2 kΩ
Input Rise and Fall Times
5
ns
0.0–3.0
V
Input timing measurement
reference levels
1.5
V
Output timing measurement
reference levels
1.5
V
Input Pulse Levels
Note: Diodes are IN3064 or equivalent
Figure 9.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
3.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.5 V
Measurement Level
1.5 V
Output
0.0 V
Figure 10.
October 11, 2006 21354E4
Input Waveforms and Measurement Levels
Am29LV040B
25
D A T A
S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
tGHQZ
tAXQX
Description
Test Setup
-60R
-70
-90
-120
Unit
Min
60
70
90
120
ns
CE# = VIL
OE# = VIL
Max
60
70
90
120
ns
OE# = VIL
Max
60
70
90
120
ns
Output Enable to Output Delay
Max
30
30
35
50
ns
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Min
0
ns
tOEH
Output Enable
Hold Time (Note 1)
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 6 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
0V
Figure 11.
26
Read Operations Timings
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Speed Options
Parameter
JEDEC
Std
Description
-60R
-70
-90
-120
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
60
70
90
120
ns
tWLAX
tAH
Address Hold Time
Min
45
45
45
50
ns
tDVWH
tDS
Data Setup Time
Min
35
35
45
50
ns
tWLWH
tWP
Write Pulse Width
Min
35
35
35
50
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWHWL
tWPH
Write Pulse Width High
Min
30
ns
tWHWH1
tWHWH1 Programming Operation (Note 2)
Typ
9
µs
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
0.7
sec
Min
50
µs
tVCS
VCC Setup Time (Note 1)
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
October 11, 2006 21354E4
Am29LV040B
27
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
DOUT
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 12.
Program Operation Timings
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
30h
In
Progress
Complete
10 for Chip Erase
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 13.
28
Chip/Sector Erase Operation Timings
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 14.
Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ6/DQ2
High Z
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 15.
October 11, 2006 21354E4
Toggle Bit Timings (During Embedded Algorithms)
Am29LV040B
29
D A T A
S H E E T
AC CHARACTERISTICS
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 16. DQ2 vs. DQ6
30
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Speed Options
Parameter
JEDEC
Std
Description
-60R
-70
-90
-120
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
60
70
90
120
ns
tELAX
tAH
Address Hold Time
Min
45
45
45
50
ns
tDVEH
tDS
Data Setup Time
Min
35
35
45
50
ns
tELEH
tCP
CE# Pulse Width
Min
35
35
35
50
ns
tAVEL
tAS
Address Setup Time
Min
0
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tEHEL
tCPH
CE# Pulse Width High
Min
30
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
9
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.7
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
October 11, 2006 21354E4
Am29LV040B
31
D A T A
S H E E T
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tDH
DQ7#
Data
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, DOUT is the data written
to the device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17.
32
Alternate CE# Controlled Write Operation Timings
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
0.7
15
s
Chip Erase Time
11
Byte Programming Time
9
300
µs
4.5
13.5
s
Chip Programming Time
(Note 3)
s
Comments
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V (3.0 V for -60R), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 4 for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9 and OE#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
October 11, 2006 21354E4
Am29LV040B
33
D A T A
S H E E T
PHYSICAL DIMENSIONS*
TS 032—32-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
34
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
PHYSICAL DIMENSIONS
PL 032—32-Pin Plastic Leaded Chip Carrier
PL 032
Dwg rev AH; 10/99
October 11, 2006 21354E4
Am29LV040B
35
D A T A
REVISION SUMMARY
Revision A (January 1998)
Revision B (April 1998)
S H E E T
Global
Added table of contents. Deleted burn-in option from
Ordering Information section.
Expanded data sheet from Advanced Information to
Preliminary version.
Revision E (March 12, 2003)
Distinctive Characteristics
Corrected the values for the automatic sleep mode and
standby mode.
Revision B+1 (November 1998)
Connection Diagrams
Command Definitions
Corrected the standard TSOP pinout.
Added new global text to first paragraph.
Revision C (January 1999)
Byte/Word Program Command Sequence, Sector
Erase Command Sequence, and Chip Erase Command Sequence
Distinctive Characteristics
Added 20-year data retention subbullet.
Revision C+1 (May 18, 1999)
Removed preliminary designation from data sheet.
Noted that the autoselect function is unavailable when
a program or erase operation is in progress.
Read Operations
Revision C+2 (July 20, 1999)
Physical Dimensions
Changed the t EHQZ and tGHQZ max to 16 ns for all
speed options.
Corrected the unit of measurement for the 32-pin PLCC
to inches.
Revision E+1 (June 11, 2004)
Ordering Information
Revision D (November 11, 1999)
Added Pb-free OPNs.
Global
Changed all references to 55R speed option (55 ns,
regulated voltage range) to 60R (60 ns, regulated
voltage range).
Revision E+2 (July 19, 2005)
Ordering Information
Added valid combination for Pb-free options.
Physical Dimensions
Global
Replaced all drawings with new versions.
Added colophon and updated trademark statement.
AC Characteristics—Figure 12. Program
Operations Timing and Figure 13. Chip/Sector
Erase Operations
Revision E+3 (January 31, 2006)
Deleted tGHWL and changed OE# waveform to start at
high.
Removed reverse TSOP option.
Revision D+1 (November 13, 2000)
Global
Global
Revision E4 (October 11, 2006)
Added notice on product availability.
36
Am29LV040B
21354E4 October 11, 2006
D A T A
S H E E T
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable ( i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are
for identification purposes only and may be trademarks of their respective companies.
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
October 11, 2006 21354E4
Am29LV040B
37