ADVANCE INFORMATION Am29LV640MU 64 Megabit (4 M x 16-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Single power supply operation — 3 V for read, erase, and program operations ■ VersatileI/O control — Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V ■ Manufactured on 0.23 µm MirrorBit process technology ■ SecSi (Secured Silicon) Sector region — 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer ■ Flexible sector architecture — One hundred twenty-eight 32 Kword sectors ■ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection ■ Minimum 100,000 erase cycle guarantee per sector ■ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS ■ High performance — 90 ns access time — 25 ns page read times — 0.4 s typical sector erase time — 5.9 µs typical write buffer word programming time: 16-word write buffer reduces overall programming time for multiple-word/byte updates — 4-word page read buffer — 16-word write buffer ■ Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current ■ Package options — 63-ball Fine-Pitch BGA — 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES ■ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: r ead/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices ■ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: VID-level method of changing code in locked sectors — ACC (high voltage) input accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.4/26/02 Publication# 25301 Rev: B Amendment/+1 Issue Date: April 26, 2002 Refer to AMD’s Website (www.amd.com) for the latest information. A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION The Am29LV640MU is a 64 Mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words. The device has a 16-bit only data bus, and can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Ordering Information sections. The device is offered in a 63-ball Fine-Pitch BGA or 64-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power c ons umption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The SecSi (Secured Silicon) Sector provides a 128-word area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. The VersatileI/O™ (VIO) control allows the host system to set the voltage levels that the device generates 2 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N MIRRORBIT 64 MBIT DEVICE FAMILY Device Bus Sector Architecture Packages VIO RY/BY# WP#, ACC WP# Protection x8 Uniform (64 Kbyte) 48-pin TSOP (std. & rev. pinout), 63-ball FBGA Yes Yes ACC only No WP# LV640MT/B x8/x16 Boot (8 x 8 Kbyte at top & bottom) 48-pin TSOP, 63-ball Fine-pitch BGA, 64-ball Fortified BGA No Yes WP#/ACC pin 2 x 8 Kbyte top or bottom LV640MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout), 64 Fortified BGA Yes Yes WP#/ACC pin 1 x 64 Kbyte high or low LV641MH/L x16 Uniform (32 Kword) 48-pin TSOP (std. & rev. pinout) Yes No Separate WP# and ACC pins 1 x 32 Kword top or bottom LV640MU x16 Uniform (32 Kword) 63-ball Fine-pitch BGA Yes Yes ACC only No WP# LV065MU RELATED DOCUMENTS To download related documents, click on the following links or go to www.amd.com→Flash Memory→ Product Information→MirrorBit→Flash Information→Technical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read April 26, 2002 Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices AMD MirrorBit™ White Paper Migrating from Single-byte to Three-byte Device IDs M i g r a t i o n f r o m A m 2 9 LV 6 4 0 D U t o M i r r o r B i t Am29LV640MU Am29LV640MU 3 A D V A N C E I N F O R M A T I O N TABLE OF CONTENTS MirrorBit 64 Mbit Device Family . . . . . . . . . . . . . . 3 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6 Special Package Handling Instructions .................................... 7 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10 Table 1. Device Bus Operations .....................................................10 VersatileIO (VIO) Control ..................................................... 10 Requirements for Reading Array Data ................................... 10 Page Mode Read .................................................................... 11 Writing Commands/Command Sequences ............................ 11 Write Buffer ............................................................................. 11 Accelerated Program Operation ............................................. 11 Autoselect Functions .............................................................. 11 Standby Mode ........................................................................ 11 Automatic Sleep Mode ........................................................... 11 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 12 Table 2. Sector Address Table ........................................................13 Autoselect Mode..................................................................... 15 Table 3. Autoselect Codes, (High Voltage Method) .......................15 Sector Group Protection and Unprotection ............................. 16 Table 4. Sector Group Protection/Unprotection Address Table .....16 Temporary Sector Group Unprotect ....................................... 17 Figure 1. Temporary Sector Group Unprotect Operation................ 17 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18 SecSi (Secured Silicon) Sector Flash Memory Region .......... 19 Table 5. SecSi Sector Contents ......................................................19 Hardware Data Protection ...................................................... 19 Low VCC Write Inhibit ............................................................ 19 Write Pulse “Glitch” Protection ............................................... 20 Logical Inhibit .......................................................................... 20 Power-Up Write Inhibit ............................................................ 20 Common Flash Memory Interface (CFI) . . . . . . . 20 Table 6. CFI Query Identification String .............................. 20 Table 7. System Interface String......................................................21 Table 8. Device Geometry Definition................................... 21 Table 9. Primary Vendor-Specific Extended Query............. 22 Command Definitions . . . . . . . . . . . . . . . . . . . . . 22 Reading Array Data ................................................................ 22 Reset Command ..................................................................... 23 Autoselect Command Sequence ............................................ 23 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23 Word Program Command Sequence ..................................... 23 Unlock Bypass Command Sequence ..................................... 24 Write Buffer Programming ...................................................... 24 Accelerated Program .............................................................. 25 Figure 3. Write Buffer Programming Operation............................... 26 Figure 4. Program Operation .......................................................... 27 Program Suspend/Program Resume Command Sequence ... 27 Figure 5. Program Suspend/Program Resume............................... 28 Chip Erase Command Sequence ........................................... 28 Sector Erase Command Sequence ........................................ 28 Erase Suspend/Erase Resume Commands ........................... 29 4 Figure 6. Erase Operation.............................................................. 30 Command Definitions ............................................................. 31 Table 10. Command Definitions...................................................... 31 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 32 DQ7: Data# Polling ................................................................. 32 Figure 7. Data# Polling Algorithm .................................................. 32 RY/BY#: Ready/Busy#............................................................ 33 DQ6: Toggle Bit I .................................................................... 33 Figure 8. Toggle Bit Algorithm........................................................ 34 DQ2: Toggle Bit II ................................................................... 34 Reading Toggle Bits DQ6/DQ2 ............................................... 34 DQ5: Exceeded Timing Limits ................................................ 35 DQ3: Sector Erase Timer ....................................................... 35 DQ1: Write-to-Buffer Abort ..................................................... 35 Table 11. Write Operation Status ................................................... 35 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 36 Figure 9. Maximum Negative Overshoot Waveform ..................... 36 Figure 10. Maximum Positive Overshoot Waveform..................... 36 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 36 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 11. Test Setup.................................................................... 38 Table 12. Test Specifications ......................................................... 38 Key to Switching Waveforms. . . . . . . . . . . . . . . . 38 Figure 12. Input Waveforms and Measurement Levels...................................................................... 38 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 Read-Only Operations ........................................................... 39 Figure 13. Read Operation Timings ............................................... 39 Figure 14. Page Read Timings ...................................................... 40 Hardware Reset (RESET#) .................................................... 41 Figure 15. Reset Timings ............................................................... 41 Erase and Program Operations .............................................. 42 Figure 16. Program Operation Timings.......................................... Figure 17. Accelerated Program Timing Diagram.......................... Figure 18. Chip/Sector Erase Operation Timings .......................... Figure 19. Data# Polling Timings (During Embedded Algorithms)...................................................... Figure 20. Toggle Bit Timings (During Embedded Algorithms)...................................................... Figure 21. DQ2 vs. DQ6................................................................. 43 43 44 45 46 46 Temporary Sector Unprotect .................................................. 47 Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 47 Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 48 Alternate CE# Controlled Erase and Program Operations ..... 49 Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 50 Erase And Programming Performance. . . . . . . . 51 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 51 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 51 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 52 LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package .............................................................. 52 FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm Package .............................................................. 53 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 54 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N PRODUCT SELECTOR GUIDE Part Number Am29LV640MU VCC = 3.0–3.6 V Speed Option 90R (VIO = 3.0–3.6 V) VCC = 2.7–3.6 V 101 (VIO = 2.7–3.6 V) 112 (VIO = 1.65–3.6 V) 120 (VIO = 1.65–3.6 V) Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access time (tPACC) 25 30 40 40 Max. OE# Access Time (ns) 25 30 40 40 Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM DQ0–DQ15 RY/BY# VCC Sector Switches VSS VIO Erase Voltage Generator Input/Output Buffers RESET# WE# ACC State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Timer A21–A0 April 26, 2002 Am29LV640MU Address Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 5 A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAMS 64-Ball Fortified BGA (FBGA) Top View, Balls Facing Down 6 A8 B8 C8 D8 E8 F8 G8 H8 NC NC NC VIO VSS NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 A13 A12 A14 A15 A16 NC DQ15/A-1 VSS A6 B6 C6 D6 E6 F6 G6 H6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A5 B5 C5 D5 E5 F5 G5 H5 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 A4 B4 C4 D4 E4 F4 G4 H4 RY/BY# ACC A18 A20 DQ2 DQ10 DQ11 DQ3 A3 B3 C3 D3 E3 F3 G3 H3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 A3 A4 A2 A1 A0 CE# OE# VSS A1 B1 C1 D1 E1 F1 G1 H1 NC NC NC NC NC VIO NC NC Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAMS 63-Ball Fine-Pitch BGA (FBGA) Top View, Balls Facing Down A8 B8 L8 M8 NC NC NC* NC* A7 B7 NC NC C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 NC* NC* A13 A12 A14 A15 A16 VIO DQ15 VSS C6 D6 E6 F6 G6 H6 J6 K6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 C5 D5 E5 F5 G5 H5 J5 K5 DQ4 WE# RESET# A21 A19 DQ5 DQ12 VCC C4 D4 E4 F4 G4 H4 J4 K4 RY/BY# ACC A18 A20 DQ2 DQ10 DQ11 DQ3 C3 D3 E3 F3 G3 H3 J3 K3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 NC* A3 A4 A2 A1 A0 CE# OE# VSS NC* NC* L1 M1 NC* NC* A1 B1 * Balls are shorted together via the substrate but not connected to the die. NC* NC* Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, SSOP, PDIP, PLCC). The package and/or data integrity may be April 26, 2002 compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29LV640MU 7 A D V A N C E PIN DESCRIPTION A21–A0 I N F O R M A T I O N LOGIC SYMBOL = 22 Address inputs 22 DQ15–DQ0 = 15 Data inputs/outputs A21–A0 CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input ACC = Programming Acceleration input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output RESET# VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VIO VIO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally CE# 16 DQ15–DQ0 OE# WE# 8 ACC Am29LV640MU RY/BY# April 26, 2002 A D V A N C E I N F O R M A T I O N ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29LV640M U 90R PC I TEMPERATURE RANGE I = Industrial (–40°C to +85°C) PACKAGE TYPE PC = 64-Ball Fortified Ball Grid Array (FBGA), 1.0 mm pitch, 13 x 11 mm package (LAA064) WH = 63-Ball Fine Pitch Ball Grid Array (FBGA), 0.80 mm pitch, 12 x 11 mm package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE U = Uniform sector device (WP# not available) DEVICE NUMBER/DESCRIPTION Am29LV640MU 64 Megabit (4 M x 16-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO Control, 3.0 Volt-only Read, Program, and Erase Valid Combinations Valid Combinations for Fortified or Fine-Pitch BGA Package Order Number Am29LV640MU90R Am29LV640MU101 Am29LV640MU102 Am29LV640MU120 April 26, 2002 Package Marking WHI L640MU90R PCI L640MU90N WHI L640MU01V PCI L640MU01P WHI L640MU11V PCI L640MU11P WHI, L640MU12V PCI L640MU12P Speed (ns) V IO Range VCC Range 90 3.0– 3.6 V 3.0– 3.6 V 100 2.7– 3.6 V 110 1.65– 3.6 V 120 1.65– 3.6 V Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. I 2.7– 3.6 V Am29LV640MU 9 A D V A N C E I N F O R M A T I O N DEVICE BUS OPERATIONS register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. Device Bus Operations CE# OE# WE# RESET# ACC Addresses (Note 2) DQ0– DQ15 Read L L H H X AIN DOUT Write (Program/Erase) L H L H X AIN (Note 3) Accelerated Program L H L H VHH AIN (Note 3) VCC ± 0.3 V X X VCC ± 0.3 V H X High-Z Output Disable L H H H X X High-Z Reset X X X L X X High-Z Sector Group Protect (Note 2) L H L VID X SA, A6=L, A3=L, A2=L, A1=H, A0=L (Note 3) Sector Group Unprotect (Note 2) L H L VID X SA, A6=H, A3=L, A2=L, A1=H, A0=L (Note 3) Temporary Sector Group Unprotect X X X VID X AIN (Note 3) Operation Standby Legend: L = Logic Low = VIL, H = Logic High = VIH , VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0. Sector addresses are A21:A15. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection and Unprotection” section. 3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2). VersatileIO (VIO) Control The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on VIO. See “Ordering Information” on page 9 for VIO options on this device. For example, a VI/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 V devices on the same data bus. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output con- 10 trol and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N Refer to the DC Characteristics table for the active current specification for reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE . Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput during system production. April 26, 2002 If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin returns the device to normal operation. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. Am29LV640MU 11 A D V A N C E I N F O R M A T I O N RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current. If RESET# is held at VIL but not within V SS ±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash 12 memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sys tem can thus monitor RY/BY # to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data t RH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29LV640MU April 26, 2002 A D V A N C E Table 2. Sector A21–A15 I N F O R M A T I O N Sector Address Table 16-bit Address Range (in hexadecimal) Sector 16-bit Address Range (in hexadecimal) A21–A15 SA0 0 0 0 0 0 0 0 000000–007FFF SA32 0 1 0 0 0 0 0 100000–107FFF SA1 0 0 0 0 0 0 1 008000–00FFFF SA33 0 1 0 0 0 0 1 108000–10FFFF SA2 0 0 0 0 0 1 0 010000–017FFF SA34 0 1 0 0 0 1 0 110000–117FFF SA3 0 0 0 0 0 1 1 018000–01FFFF SA35 0 1 0 0 0 1 1 118000–11FFFF SA4 0 0 0 0 1 0 0 020000–027FFF SA36 0 1 0 0 1 0 0 120000–127FFF SA5 0 0 0 0 1 0 1 028000–02FFFF SA37 0 1 0 0 1 0 1 128000–12FFFF SA6 0 0 0 0 1 1 0 030000–037FFF SA38 0 1 0 0 1 1 0 130000–137FFF SA7 0 0 0 0 1 1 1 038000–03FFFF SA39 0 1 0 0 1 1 1 138000–13FFFF SA8 0 0 0 1 0 0 0 040000–047FFF SA40 0 1 0 1 0 0 0 140000–147FFF SA9 0 0 0 1 0 0 1 048000–04FFFF SA41 0 1 0 1 0 0 1 148000–14FFFF SA10 0 0 0 1 0 1 0 050000–057FFF SA42 0 1 0 1 0 1 0 150000–157FFF SA11 0 0 0 1 0 1 1 058000–05FFFF SA43 0 1 0 1 0 1 1 158000–15FFFF SA12 0 0 0 1 1 0 0 060000–067FFF SA44 0 1 0 1 1 0 0 160000–167FFF SA13 0 0 0 1 1 0 1 068000–06FFFF SA45 0 1 0 1 1 0 1 168000–16FFFF SA14 0 0 0 1 1 1 0 070000–077FFF SA46 0 1 0 1 1 1 0 170000–177FFF SA15 0 0 0 1 1 1 1 078000–07FFFF SA47 0 1 0 1 1 1 1 178000–17FFFF SA16 0 0 1 0 0 0 0 080000–087FFF SA48 0 1 1 0 0 0 0 180000–187FFF SA17 0 0 1 0 0 0 1 088000–08FFFF SA49 0 1 1 0 0 0 1 188000–18FFFF SA18 0 0 1 0 0 1 0 090000–097FFF SA50 0 1 1 0 0 1 0 190000–197FFF SA19 0 0 1 0 0 1 1 098000–09FFFF SA51 0 1 1 0 0 1 1 198000–19FFFF SA20 0 0 1 0 1 0 0 0A0000–0A7FFF SA52 0 1 1 0 1 0 0 1A0000–1A7FFF SA21 0 0 1 0 1 0 1 0A8000–0AFFFF SA53 0 1 1 0 1 0 1 1A8000–1AFFFF SA22 0 0 1 0 1 1 0 0B0000–0B7FFF SA54 0 1 1 0 1 1 0 1B0000–1B7FFF SA23 0 0 1 0 1 1 1 0B8000–0BFFFF SA55 0 1 1 0 1 1 1 1B8000–1BFFFF SA24 0 0 1 1 0 0 0 0C0000–0C7FFF SA56 0 1 1 1 0 0 0 1C0000–1C7FFF SA25 0 0 1 1 0 0 1 0C8000–0CFFFF SA57 0 1 1 1 0 0 1 1C8000–1CFFFF SA26 0 0 1 1 0 1 0 0D0000–0D7FFF SA58 0 1 1 1 0 1 0 1D0000–1D7FFF SA27 0 0 1 1 0 1 1 0D8000–0DFFFF SA59 0 1 1 1 0 1 1 1D8000–1DFFFF SA28 0 0 1 1 1 0 0 0E0000–0E7FFF SA60 0 1 1 1 1 0 0 1E0000–1E7FFF SA29 0 0 1 1 1 0 1 0E8000–0EFFFF SA61 0 1 1 1 1 0 1 1E8000–1EFFFF SA30 0 0 1 1 1 1 0 0F0000–0F7FFF SA62 0 1 1 1 1 1 0 1F0000–1F7FFF SA31 0 0 1 1 1 1 1 0F8000–0FFFFF SA63 0 1 1 1 1 1 1 1F8000–1FFFFF April 26, 2002 Am29LV640MU 13 A D V A N C E Table 2. Sector A21–A15 I N F O R M A T I O N Sector Address Table (Continued) 16-bit Address Range (in hexadecimal) Sector 16-bit Address Range (in hexadecimal) A21–A15 SA64 1 0 0 0 0 0 0 200000–207FFF SA96 1 1 0 0 0 0 0 300000–307FFF SA65 1 0 0 0 0 0 1 208000–20FFFF SA97 1 1 0 0 0 0 1 308000–30FFFF SA66 1 0 0 0 0 1 0 210000–217FFF SA98 1 1 0 0 0 1 0 310000–317FFF SA67 1 0 0 0 0 1 1 218000–21FFFF SA99 1 1 0 0 0 1 1 318000–31FFFF SA68 1 0 0 0 1 0 0 220000–227FFF SA100 1 1 0 0 1 0 0 320000–327FFF SA69 1 0 0 0 1 0 1 228000–22FFFF SA101 1 1 0 0 1 0 1 328000–32FFFF SA70 1 0 0 0 1 1 0 230000–237FFF SA102 1 1 0 0 1 1 0 330000–337FFF SA71 1 0 0 0 1 1 1 238000–23FFFF SA103 1 1 0 0 1 1 1 338000–33FFFF SA72 1 0 0 1 0 0 0 240000–247FFF SA104 1 1 0 1 0 0 0 340000–347FFF SA73 1 0 0 1 0 0 1 248000–24FFFF SA105 1 1 0 1 0 0 1 348000–34FFFF SA74 1 0 0 1 0 1 0 250000–257FFF SA106 1 1 0 1 0 1 0 350000–357FFF SA75 1 0 0 1 0 1 1 258000–25FFFF SA107 1 1 0 1 0 1 1 358000–35FFFF SA76 1 0 0 1 1 0 0 260000–267FFF SA108 1 1 0 1 1 0 0 360000–367FFF SA77 1 0 0 1 1 0 1 268000–26FFFF SA109 1 1 0 1 1 0 1 368000–36FFFF SA78 1 0 0 1 1 1 0 270000–277FFF SA110 1 1 0 1 1 1 0 370000–377FFF SA79 1 0 0 1 1 1 1 278000–27FFFF SA111 1 1 0 1 1 1 1 378000–37FFFF SA80 1 0 1 0 0 0 0 280000–287FFF SA112 1 1 1 0 0 0 0 380000–387FFF SA81 1 0 1 0 0 0 1 288000–28FFFF SA113 1 1 1 0 0 0 1 388000–38FFFF SA82 1 0 1 0 0 1 0 290000–297FFF SA114 1 1 1 0 0 1 0 390000–397FFF SA83 1 0 1 0 0 1 1 298000–29FFFF SA115 1 1 1 0 0 1 1 398000–39FFFF SA84 1 0 1 0 1 0 0 2A0000–2A7FFF SA116 1 1 1 0 1 0 0 3A0000–3A7FFF SA85 1 0 1 0 1 0 1 2A8000–2AFFFF SA117 1 1 1 0 1 0 1 3A8000–3AFFFF SA86 1 0 1 0 1 1 0 2B0000–2B7FFF SA118 1 1 1 0 1 1 0 3B0000–3B7FFF SA87 1 0 1 0 1 1 1 2B8000–2BFFFF SA119 1 1 1 0 1 1 1 3B8000–3BFFFF SA88 1 0 1 1 0 0 0 2C0000–2C7FFF SA120 1 1 1 1 0 0 0 3C0000–3C7FFF SA89 1 0 1 1 0 0 1 2C8000–2CFFFF SA121 1 1 1 1 0 0 1 3C8000–3CFFFF SA90 1 0 1 1 0 1 0 2D0000–2D7FFF SA122 1 1 1 1 0 1 0 3D0000–3D7FFF SA91 1 0 1 1 0 1 1 2D8000–2DFFFF SA123 1 1 1 1 0 1 1 3D8000–3DFFFF SA92 1 0 1 1 1 0 0 2E0000–2E7FFF SA124 1 1 1 1 1 0 0 3E0000–3E7FFF SA93 1 0 1 1 1 0 1 2E8000–2EFFFF SA125 1 1 1 1 1 0 1 3E8000–3EFFFF SA94 1 0 1 1 1 1 0 2F0000–2F7FFF SA126 1 1 1 1 1 1 0 3F0000–3F7FFF SA95 1 0 1 1 1 1 1 2F8000–2FFFFF SA127 1 1 1 1 1 1 1 3F8000–3FFFFF Note: All sectors are 32 Kwords in size. 14 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N Autoselect Mode In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 3 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be program me d with its cor resp onding pr ogram m in g algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 10. This method does not require V ID . Refer to the Autoselect Command Sequence section for more information. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 3. Table 3. Description Device ID Manufacturer ID: AMD Autoselect Codes, (High Voltage Method) CE# OE# WE# A21 to A15 A14 to A10 A9 A8 to A7 A6 A5 to A4 A3 to A2 A1 A0 DQ15 to DQ0 L L H X X VID X L X L L L 0001h L L H 227Eh L L H X X VID X L X H H L 2213h H H H 2201h Cycle 1 Cycle 2 Cycle 3 Sector Protection Verification L L H SA X VID X L X L H L XX01h (protected), XX00h (unprotected) SecSi Sector Indicator Bit (DQ7) L L H X X VID X L X L H H XX88h (factory locked), XX08h (not factory locked) Legend: L = Logic Low = VIL, H = Logic High = V IH, SA = Sector Address, X = Don’t care. April 26, 2002 Am29LV640MU 15 A D V A N C E I N F O R M A T I O N Sector Group Protection and Unprotection Table 4. Sector Group Protection/Unprotection Address Table The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4). The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector Group A21–A17 SA0–SA3 00000 Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. SA28–SA31 00111 SA32–SA35 01000 SA36–SA39 01001 SA40–SA43 01010 SA44–SA47 01011 SA48–SA51 01100 SA52–SA55 01101 SA56–SA59 01110 The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See the Autoselect Mode section for details. SA4–SA7 00001 SA8–SA11 00010 SA12–SA15 00011 SA16–SA19 00100 SA20–SA23 00101 SA24–SA27 00110 SA60–SA63 01111 SA64–SA67 10000 SA68–SA71 10001 SA72–SA75 10010 SA76–SA79 10011 SA80–SA83 10100 SA84–SA87 10101 SA88–SA91 10110 SA92–SA95 10111 SA96–SA99 11000 SA100–SA103 11001 SA104–SA107 11010 SA108–SA111 11011 SA112–SA115 11100 SA116–SA119 11101 SA120–SA123 11110 SA124–SA127 11111 Note: All sector groups are 128 Kwords in size. 16 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N Temporary Sector Group Unprotect (Note: In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4). START This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once V ID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature. RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Group Unprotect Completed (Note 2) Notes: 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected once again. Figure 1. Temporary Sector Group Unprotect Operation April 26, 2002 Am29LV640MU 17 A D V A N C E I N F O R M A T I O N START START PLSCNT = 1 RESET# = VID Wait 1 µs Temporary Sector Group Unprotect Mode No PLSCNT = 1 Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address RESET# = VID Wait 1 µs First Write Cycle = 60h? First Write Cycle = 60h? Temporary Sector Group Unprotect Mode Yes Yes Set up sector group address No All sector groups protected? Yes Sector Group Protect: Write 60h to sector group address with A6–A0 = 0xx0010 Set up first sector group address Sector Group Unprotect: Write 60h to sector group address with A6–A0 = 1xx0010 Wait 150 µs Verify Sector Group Protect: Write 40h to sector group address with A6–A0 = 0xx0010 Increment PLSCNT No Reset PLSCNT = 1 Read from sector group address with A6–A0 = 0xx0010 Wait 15 ms Verify Sector Group Unprotect: Write 40h to sector group address with A6–A0 = 1xx0010 Increment PLSCNT No No PLSCNT = 25? Read from sector group address with A6–A0 = 1xx0010 Data = 01h? Yes No Yes Device failed Protect another sector group? Yes No PLSCNT = 1000? No Yes Remove VID from RESET# Device failed Write reset command Sector Group Protect Algorithm Sector Group Protect complete Set up next sector group address Data = 00h? Yes Last sector group verified? No Yes Sector Group Unprotect Algorithm Remove VID from RESET# Write reset command Sector Group Unprotect complete Figure 2. 18 In-System Sector Group Protect/Unprotect Algorithms Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N SecSi (Secured Silicon) Sector Flash Memory Region representative for details on using AMD’s ExpressFlash service. The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 words in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory AMD offers the device with the SecSi Sector either fac tory l oc ke d o r c u stom e r l oc ka ble . The fac tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi sector address space in this device is allocated as follows: Table 5. SecSi Sector Address Range SecSi Sector Contents Standard ExpressFlash Factory Locked Factory Locked 000000h–000007h ESN ESN or determined by customer 000008h–00007Fh Unavailable Determined by customer Customer Lockable Determined by customer The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0. Factory Locked: SecSi Sector Programmed and Protected At the Factory In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. See Table 5 for SecSi Sector addressing. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD April 26, 2002 As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-word SecSi sector. The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sector Group Protection and Unprotection” section. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 10 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control Am29LV640MU 19 A D V A N C E I N F O R M A T I O N pins to prevent unintentional writes when V C C is greater than VLKO. CE# and WE# must be a logical zero while OE# is a logical one. Write Pulse “Glitch” Protection Power-Up Write Inhibit Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 6–9. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 6–9. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the Wor ld Wide We b at http://w ww.amd.co m/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents. Table 6. CFI Query Identification String Addresses (x16) Data 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 20 Description Am29LV640MU April 26, 2002 A D V A N C E Table 7. I N F O R M A T I O N System Interface String Addresses (x16) Data Description 1Bh 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0007h Typical timeout per single word write 2N µs 20h 0007h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0001h Max. timeout for word write 2N times typical 24h 0005h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual block erase 2N times typical 26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Table 8. Device Geometry Definition Addresses (x16) Data 27h 0017h Device Size = 2N byte 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) (00h not supported) 2Ah 2Bh 0005h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0001h Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) 2Dh 2Eh 2Fh 30h 007Fh 0000h 0000h 0001h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 0000h 0000h 0000h 0000h Erase Block Region 2 Information (refer to CFI publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h Erase Block Region 3 Information (refer to CFI publication 100) 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to CFI publication 100) April 26, 2002 Description Am29LV640MU 21 A D V A N C E Table 9. I N F O R M A T I O N Primary Vendor-Specific Extended Query Addresses (x16) Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII 45h 0008h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0004h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme 04 = 29LV800 mode 4Ah 0000h Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0001h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 00B5h 4Eh 00C5h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 4Fh 0000h 50h 0001h 00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 10 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. 22 Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. April 26, 2002 Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific addresses: Identifier Code A7:A0 Manufacturer ID 00h Device ID, Cycle 1 01h Device ID, Cycle 2 0Eh Device ID, Cycle 3 0Fh SecSi Sector Factory Protect 03h Sector Protect Verify (SA)02h Note: The device ID is read over three cycles. SA = Sector Address Table 10 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Table 10 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Word Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the Am29LV640MU 23 A D V A N C E I N F O R M A T I O N programmed cell margin. Table 10 shows the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 10 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write 24 Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. A write-buffer-page is selected by address bits A MAX –A 4 . All subsequent addr ess/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host s y s t e m m u s t t h e r e fo r e a c c o u n t f o r l o a d in g a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Additionally, the last data loaded prior to the Program Buffer to Flash command will be programmed into the device. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load command. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the de- April 26, 2002 vice for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the ACC pin. When the system asserts VHH on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. Figure 4 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams. Am29LV640MU 25 A D V A N C E I N F O R M A T I O N Write “Write to Buffer” command and Sector Address Part of “Write to Buffer” Command Sequence Write number of addresses to program minus 1(WC) and Sector Address Write first address/data Yes WC = 0 ? No Write to a different sector address Abort Write to Buffer Operation? Yes Write to buffer ABORTED. Must write “Write-to-buffer Abort Reset” command sequence to return to read mode. No (Note 1) Write next address/data pair WC = WC - 1 Write program buffer to flash sector address Notes: Read DQ7 - DQ0 at Last Loaded Address When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified. 3. If this flowchart location was reached because DQ5= “1”, then the device FAILED. If this flowchart location was reached because DQ1= “1”, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command. 4. See Table 10 for command sequences required for write buffer programming. Yes DQ7 = Data? No 1. No No DQ1 = 1? DQ5 = 1? Yes Yes Read DQ7 - DQ0 with address = Last Loaded Address (Note 2) DQ7 = Data? Yes No (Note 3) FAIL or ABORT Figure 3. 26 PASS Write Buffer Programming Operation Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 1 ms and updates the status bits. Addresses are not required when writing the Program Suspend command. START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? Yes Increment Address No Last Address? Yes Programming Completed Note: See Table 10 for program command sequence. Figure 4. Program Operation No After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming. April 26, 2002 Am29LV640MU 27 A D V A N C E I N F O R M A T I O N When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Program Operation or Write-to-Buffer Sequence in Progress Write address/data XXXh/B0h Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations Wait 1 ms Read data as required No Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors Done reading? Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 10 shows the address and data requirements for the sector erase command sequence. Write Program Resume Command Sequence Device reverts to operation prior to Program Suspend Figure 5. Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams. Sector Erase Command Sequence Yes Write address/data XXXh/30h Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Program Suspend/Program Resume Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 10 shows the address and data requirements for the chip erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S e c to r E ra se or E ra s e S us pe nd dur ing t he time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. 28 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max- April 26, 2002 imum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Am29LV640MU 29 A D V A N C E I N F O R M A T I O N START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1. See Table 10 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 6. 30 Erase Operation Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N Command Definitions Table 10. Cycles Bus Cycles (Notes 1–4) Addr Data Read (Note 6) 1 RA RD Reset (Note 7) Command Sequence (Notes) Command Definitions Addr Data Addr Data Addr Data XXX F0 4 555 AA 2AA 55 555 90 X00 0001 Device ID (Note 9) 6 555 AA 2AA 55 555 90 X01 227E SecSi Sector Factory Protect (Note 10) 4 555 AA 2AA 55 555 90 X03 (Note 10) Sector Group Protect Verify (Note 11) 4 555 AA 2AA 55 555 90 (SA)X02 00/01 Enter SecSi Sector Region 3 555 AA 2AA 55 555 88 Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00 Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (Note 12) 6 555 AA 2AA 55 SA 25 SA WC Program Buffer to Flash 1 SA 29 Autoselect (Note 8) 1 Manufacturer ID Addr Data Addr Data X0E 2213 X0F 2201 PA PD WBL PD Write to Buffer Abort Reset (Note 13) 3 555 AA 2AA 55 555 F0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 14) 2 XXX A0 PA PD Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Program/Erase Suspend (Note 16) 1 BA B0 Program/Erase Resume (Note 17) 1 BA 30 CFI Query (Note 18) 1 55 98 Legend: X = Don’t care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address . Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. 10. The data is 88h for factory locked and 08h for not factory locked. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. All others are write cycles. 11. The data is 00h for an unprotected sector group and 01h for a protected sector group. 4. During unlock and command cycles, when lower address bits are 555 or 2AA as shown in table, address bits higher than A11 and data bits higher than DQ7 are don’t care. 12. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 21. 5. Unless otherwise noted, address bits A21–A11 are don’t cares. 6. No unlock or command cycles required when device is in read mode. 13. Command sequence resets device for next command after aborted write-to-buffer operation. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect Command Sequence section for more information. 9. The device ID must be read in three cycles. 14. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 15. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 17. The Erase Resume command is valid only during the Erase Suspend mode. 18. Command is valid when device is ready to read array data or when device is in autoselect mode. April 26, 2002 Am29LV640MU 31 A D V A N C E I N F O R M A T I O N WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. valid data, the data outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles. Table 11 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling algorithm. Figure 19 in the AC Characteristics section shows the Data# Polling timing diagram. DQ7: Data# Polling START The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode. Read DQ7–DQ0 Addr = VA DQ7 = Data? No No During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has 32 Yes DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am29LV640MU Figure 7. Data# Polling Algorithm April 26, 2002 A D V A N C E I N F O R M A T I O N RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or the device is in the erase-suspend-read mode. Table 11 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. April 26, 2002 After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 11 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. Am29LV640MU 33 A D V A N C E I N F O R M A T I O N DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. START Read DQ7–DQ0 DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 11 to compare outputs for DQ2 and DQ6. Read DQ7–DQ0 Toggle Bit = Toggle? No Yes No Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? Reading Toggle Bits DQ6/DQ2 No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 8. Toggle Bit Algorithm Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform 34 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 8). DQ5: Exceeded Timing Limits DQ5 indic ates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase comTable 11. Standard Mode Program Suspend Mode Erase Suspend Mode Write-toBuffer Status Embedded Program Algorithm Embedded Erase Algorithm Program-Suspended Program- Sector Suspend Non-Program Read Suspended Sector Erase-Suspended EraseSector Suspend Non-Erase Suspended Read Sector Erase-Suspend-Program (Embedded Program) Busy (Note 3) Abort (Note 4) mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11 shows the status of DQ3 relative to the other status bits. DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer Write Operation Status DQ7 (Note 2) DQ7# 0 1 DQ6 Toggle Toggle No toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A RY/BY# 0 0 Invalid (not allowed) 1 Data 1 0 N/A Toggle N/A Data 1 1 DQ7# Toggle 0 N/A N/A N/A 0 DQ7# DQ7# Toggle Toggle 0 0 N/A N/A N/A N/A 0 1 0 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to ‘1’ when tthe device has aborted the write-to-buffer operation. April 26, 2002 Am29LV640MU 35 A D V A N C E I N F O R M A T I O N ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C 20 ns 20 ns +0.8 V –0.5 V Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V –2.0 V VIO . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V 20 ns A9, OE#, ACC, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V Figure 9. Maximum Negative Overshoot Waveform All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During v ol tage transitions, input or I/O pi ns may overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 9. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot V SS to –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns Figure 10. Maximum Positive Overshoot Waveform 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute max imum rating conditions for extended periods may affect device reliability. OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7–3.6 V VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.0 V Notes: 1. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. See Ordering Information section for valid VCC/VIO range combinations. The I/Os cannot go to 3 V when VIO = 1.8 V. 36 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min ILI Input Load Current (Note 1) VIN = VSS to VCC, VCC = VCC max ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH ICC2 VCC Initial Page Read Current (1, 2) ICC3 VCC Intra-Page Read Current (1, 2) Typ Max Unit ±1.0 µA 35 µA ±1.0 µA 5 MHz 15 20 1 MHz 15 20 CE# = VIL, OE# = VIH 30 50 mA CE# = VIL, OE# = VIH 10 20 mA ICC4 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V, WP# = V IH 1 5 µA ICC6 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V, WP# = VIH 1 5 µA ICC7 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 1 5 µA ACC Accelerated Program Current (Note 2) ACC pin 10 20 mA IACC CE# = VIL, OE# = V IH VCC pin 30 60 mA VIL1 Input Low Voltage 1(Notes 5, 6) –0.5 0.8 V VIH1 Input High Voltage 1 (Notes 5, 6) 0.7 x VCC VCC + 0.5 V VIL2 Input Low Voltage 2 (Notes 5, 7) –0.5 0.3 x VIO V VIH2 Input High Voltage 2 (Notes 5, 7) 0.7 x VIO VIO + 0.5 V VHH Voltage for ACC Program Acceleration VCC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min = VIO 0.15 x VIO V VOH1 Output High Voltage VOH2 VLKO mA IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V Low VCC Lock-Out Voltage (Note 8) 2.3 2.5 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is VIO + 0.3 V 6. VCC voltage requirements. 7. VIO voltage requirements. VCC = 3 V and VIO = 3 V or 1.8 V. When VIO is at 1.8 V, I/Os cannot operate at 3 V. 8. Not 100% tested. April 26, 2002 Am29LV640MU 37 A D V A N C E I N F O R M A T I O N TEST CONDITIONS Table 12. 3.3 V Test Condition 2.7 kΩ Device Under Test CL Test Specifications 6.2 kΩ All Speeds Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns 0.0–3.0 V Input timing measurement reference levels (See Note) 1.5 V Output timing measurement reference levels 0.5 VIO V Input Pulse Levels Note: Diodes are IN3064 or equivalent Figure 11. Test Setup Unit Note: If VIO < VCC, the reference level is 0.5 V IO. KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 3.0 V Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 1.5 V Measurement Level 0.5 VIO V Output 0.0 V Note: If VIO < VCC, the input measurement reference level is 0.5 VIO. Figure 12. Input Waveforms and Measurement Levels 38 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Read-Only Operations Parameter Speed Options JEDEC Std. Description tAVAV tRC tAVQV tACC Address to Output Delay tELQV tCE Test Setup 90R 101 112 120 Unit Min 90 100 110 120 ns CE#, OE# = VIL Max 90 100 110 120 ns OE# = VIL Max 90 100 110 120 ns Max 25 30 40 40 ns 25 30 40 40 ns Read Cycle Time (Note 1) Chip Enable to Output Delay tPACC Page Access Time tGLQV tOE Output Enable to Output Delay Max tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns Min 0 ns tOEH Read Output Enable Hold Toggle and Time (Note 1) Data# Polling Min 10 ns Notes: 1. Not 100% tested. 2. See Figure 11 and Table 12 for test specifications. tRC Addresses Stable Addresses tACC CE# tRH tRH tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 13. April 26, 2002 Read Operation Timings Am29LV640MU 39 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Same Page A21-A2 A1-A0 Aa tACC Data Bus Ab tPACC Qa Ad Ac tPACC Qb tPACC Qc Qd CE# OE# Note: Toggle A0, A1, A2. Figure 14. Page Read Timings 40 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description All Speed Options Unit tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 15. April 26, 2002 Reset Timings Am29LV640MU 41 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Erase and Program Operations Parameter Speed Options JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns Write Buffer Program Operation (Notes 2, 3) Typ 100 µs Effective Write Buffer Program Operation, Per Word (Notes 2, 4) Typ 5.9 µs Accelerated Effective Write Buffer Program Operation, Per Word (Notes 2, 4) Typ 4.7 µs Single Word Program (Note 2) Typ 100 µs Accelerated Single Word Programming Operation (Note 2) Typ 80 µs tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Min 90 ns tWLAX tWHWH1 tWHWH2 tWHWH1 tBUSY 90R 101 112 120 Unit 90 100 110 120 ns Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. 42 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status tBUSY DOUT tRB RY/BY# VCC tVCS Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 16. Program Operation Timings VHH ACC VIL or VIH VIL or VIH tVHH tVHH Figure 17. Accelerated Program Timing Diagram April 26, 2002 Am29LV640MU 43 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). Figure 18. 44 Chip/Sector Erase Operation Timings Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ0–DQ6 Status Data Status Data True Valid Data High Z True Valid Data tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 19. Data# Polling Timings (During Embedded Algorithms) April 26, 2002 Am29LV640MU 45 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS tAHT tAS Addresses tAHT tASO CE# tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Data Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle Figure 20. Toggle Bit Timings (During Embedded Algorithms) Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 21. 46 DQ2 vs. DQ6 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Group Unprotect Min 4 µs Note: Not 100% tested. VID RESET# VID VSS, VIL, or VIH VSS, VIL, or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRRB tRSP RY/BY# Figure 22. April 26, 2002 Temporary Sector Group Unprotect Timing Diagram Am29LV640MU 47 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Group Protect or Unprotect Data 60h 60h Valid* Verify 40h Status Sector Group Protect: 150 µs, Sector Group Unprotect: 15 ms 1 µs CE# WE# OE# * For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010. Figure 23. 48 Sector Group Protect and Unprotect Timing Diagram Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter Speed Options JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns Write Buffer Program Operation (Notes 2, 3) Typ 100 µs Effective Write Buffer Program Operation, Per Word (Notes 2, 4) Typ 5.9 µs Accelerated Effective Write Buffer Program Operation, Per Word (Notes 2, 4) Typ 4.7 µs Single Word Program (Note 2) Typ 100 µs Accelerated Single Word Programming Operation (Note 2) Typ 80 µs Sector Erase Operation (Note 2) Typ 0.4 sec tWHWH1 tWHWH2 tWHWH1 tWHWH2 90R 101R 112R 120 Unit 90 100 110 120 ns Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Write buffer program is typical per word. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. April 26, 2002 Am29LV640MU 49 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tCP CE# tWS tWHWH1 or 2 tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. Figure 24. 50 Alternate CE# Controlled Write (Erase/Program) Operation Timings Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 15 sec Chip Erase Time 90 Excludes 00h programming prior to erasure (Note 4) Effective Write Buffer Program Time, Per Word 5.9 210 µs Word Program Time 100 218 µs Accelerated Word Program Time 4.8 TBD µs TBD TBD sec Chip Program Time (Note 3) sec Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA V CC Current Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance V IN = 0 7.5 9 pF Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Description Minimum Pattern Data Retention Time April 26, 2002 Am29LV640MU 51 A D V A N C E I N F O R M A T I O N PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package 52 Am29LV640MU April 26, 2002 A D V A N C E I N F O R M A T I O N PHYSICAL DIMENSIONS FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm Package Dwg rev AF; 10/99 April 26, 2002 Am29LV640MU 53 A D V A N C E I N F O R M A T I O N REVISION SUMMARY Revision A (August 3, 2001) Initial release as abbreviated Advance Information data sheet. tain specifications for the Am29LV640MU part number. For Am29LV640MH/L part number specifications, refer to publication number 26191. Revision A+1 (September 12, 2001) Revision B+1 (April 26, 2002) Global Global Changed description of chip-scale package from 63-ball FBGA to 64-ball Fortified BGA. Deleted references to word mode. Ordering Information MirrorBit 64 Mbit Device Family Changed package part number designation from WH to PC. Deleted Am29LV641MT/B. Physical Dimensions Figure 2, In-System Sector Group Protect/Unprotect Algorithms Added the TS056 and LAA064 packages. Modified to show A2, A3 address requirements. Revision A+2 (October 3, 2001) Sector Protection/Unprotecton Global Deleted references to alternate method of sector protection. Ad ded i nform ation fo r WP # p rotec ted d evi ces (LV640MH/L). Clarfied VCC and VIO ranges. Connection Diagrams Changed RFU (reserved for future use) to NC (no connection). Added 63-ball FBGA drawing. Autoselect Command Substituted text with ID code table for easier reference. Table 10, Command Definitions Ordering Information Added H and L valid combinations for WP# protected devices. Changed voltage operating range for 90 ns device. Combined Notes 4 and 5 from Revision B. Corrected number of cycles indicated for Write-to-Buffer and Autoselect Device ID command sequences. Revision B (March 19, 2002) Global Expanded data sheet to full specification version. Starting with this revision, the data sheet will only con- Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 54 Am29LV640MU April 26, 2002