AMD AMMCL00XA 2 or 4 megabyte 3.0 volt-only flash miniature card Datasheet

PRELIMINARY
AmMCL00XA
2 or 4 Megabyte 3.0 Volt-only Flash Miniature Card
DISTINCTIVE CHARACTERISTICS
■ 2 or 4 Mbytes of addressable Flash memory
■ 2.7 V to 3.6 V, single power supply operation
— Write and read voltage: 3.0 V –10/+20%
— No additional supply current required for VPP
■ Fast access time
— 150 ns maximum access time
■ CMOS low power consumption
— Typical active read current:
35 mA (word mode)
— Typical active erase/write current:
40 mA (word mode)
— Typical standby current:
10 µA (4 Mbyte); 5 µA (2 Mbyte)
■ High write endurance
— Guaranteed minimum 100,000 write/erase
cycles per card
— More than 1,000,000 cycles per card typical
■ Uniform sector architecture
— 64K byte individually useable sectors
— Erase Suspend/Resume increases system level
performance
— BUSY# and RESET# signals
■ Zero data retention power
— No power required to retain data
GENERAL DESCRIPTION
The Miniature Card is an expansion card that provides a low cost, low power, high-performance, small
form factor solution for data and file storage to the
portable, handheld market, which includes audio,
digital film, wireless, and PDA (Portable Digital
Assistant) applications.
Miniature cards can be easily “snapped” into the back
of an electronic system and can be readily removed
and replaced by end users. AMD’s 3 V Flash Miniature
Cards are manufactured using AMD’s industry leading
3.0 volt-only, single-power-supply Am29LV081 Flash
■ Available in industrial temperature grade
(–40°C to +85°C)
■ Miniature Card standard form factor
— True interchangeability
— 60-pad elastomeric connector
— Supports multiple technologies
— Sonic welded stainless steel case
— PCMCIA Type II adapter available
— Selectable byte- or word-wide configuration
— Small Form Factor (38 mm x 33 mm x 3.5 mm)
■ 60 connection bus
— 16-bit data bus
— 25-bit address bus
— Easy system integration
— Low cost implementation
— Low cost cards
■ Consumer-friendly mechanicals
— User can easily insert and remove card, upgrade
memory, and add applications
■ Voltage level keying
— Does not allow a 3 V card to plug into a 5 V
system and vice versa
— Single power supply design
— System does not need a separate program
voltage supply; only one is necessary to read
and write
Memory device, ensuring high reliability and excellent
performance. The Miniature Card is less than 30% of
the size of a PCMCIA memory card. Applications
include digital voice recorders, pocket PCs and intelligent organizers, smart cellular telephones, voice and
data messaging pagers, digital still cameras and portable instrumentation equipment.
The Miniature Card specification will be defined by
PCMCIA as of October 1997. The participating association members include major Flash memory vendors
and leading consumer electronics OEMs. The goal of
the Miniature Card specification is to promote an open,
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 21138 Rev: E Amendment/0
Issue Date: September 1997
PRELIMINARY
interoperable small-form-factor memory card standard.
For more information on the Miniature Card specification, visit the PCMCIA web site at
http://www.pc-card.com.
AMD Flash Miniature Cards can be read in either a
byte-wide or word-wide mode, which allows for flexible
integration into various system platforms. Compatibility
is assured at the hardware interface and software interchange specification.
The Miniature Card is also designed with low-cost and
rugged handling in mind. The card contains virtually no
control logic, which keeps cost and power consumption
to a minimum. The Miniature Card is packaged in a
sonic welded, stainless steel case that guarantees
durability, provides good ESD protection and ease of
handling.
The Miniature Card has extensive third-party support,
including socket and connector solutions, software
Table 1.
support from the major FTL software vendors, and
PCMCIA adapter solutions and programmer support.
AMD's Miniature Flash cards can be used for both code
and data storage. Since fast random access is possible, code can be directly executed from the card,
reducing the amount of system RAM required. In addition. AMD’s Flash technology offers unsurpassed
endurance, data retention and reliability, eliminating
the need for complex error correction and defect management hardware and software. Each Flash sector
provides a minimum of 100,000 cycles, and a typical
card life of one million or more cycles.
For more information, please contact your local AMD
sales office or visit our Web site at
http://www.amd.com/html/products/nvd/nvd.html.
DEFINITIONS
Table 1 lists the terms and definitions that may be used
in conjunction with Miniature Card specifications.
Miniature Card Definitions
Term
Meaning
AIS
Acronym for Attribute Information Structure. AIS is a Miniature Card specification for storing
Miniature Card attribute information.
ESD
Acronym for Electrostatic Discharge. ESD is part of the Miniature Card physical test.
FAT
Acronym for File Allocation Table. Using an FAT is a common method for managing files in a
DOS-based system.
Flash
A type of non-volatile memory that is both readable and writeable, but requires the media to
be erased before it is rewritten.
Host
Any system that incorporates a Miniature Card socket.
User Perception: Insertion of the Miniature Card when the host is off.
Insertion, Cold
Host State: The host would be either off or in sleep mode, no bus activity is occurring, the
host is non-operational by the user. The user inserts the Miniature Card and then presses a
button to turn the host on before the system is operational.
User Perception: Insertion of a Miniature Card when the host is running.
Insertion, Hot
Host State: The host would be in running mode, bus activity is occurring, the host is
operational by the user. The user inserts the card, the host recognizes it, and the host
continues to be operational. Note: Hot insertion may require buffering on the host system for
proper operation.
User Perception: Insertion of a Miniature Card when the host is running.
Insertion, Pseudo Hot
Host State: The host would be in running mode, bus activity is occurring, the host is
operational by the user. The user inserts the card, the host immediately powers off before the
Miniature Card makes contact with the host’s internal bus. The user would then need to press
a button to turn the host on for it to become operational.
Interface Signals
Miniature Card signals that make connection through the 60-pad connector area.
JEDEC
Acronym for Joint Electronic Device Engineering Council.
Miniature Card Backside
The side of the Miniature Card that contains the latching mechanism. The backside is
opposite the frontside.
Miniature Card Bottomside
The side of the Miniature Card that contains the interface signals. The bottomside is opposite
the topside.
2
AmMCL00XA
PRELIMINARY
Table 1.
Miniature Card Definitions (Continued)
Term
Meaning
Miniature Card Frontside
The side of the Miniature Card that contains power, insertion, ground, voltage keys, and
alignment notch. The frontside is opposite the backside.
Miniature Card Topside
The side of the Miniature Card that contains the Miniature Card label. The topside is opposite
the bottomside.
PC Card
A memory or I/O card compatible with the PC Card Standard.
PC Card Adapter
The hardware that connects the Miniature Card 60 contact bus to the PC Card 68 pin bus.
This hardware can be mechanically implemented by following the PC Card Type II
specification.
Power/Insertion Signals
The three signals on the frontside of the Miniature Card that provide ground, power and early
detection of insertion.
Pull-Ups
Resistors used to ensure that signals do not float when no device is driving them.
User Perception: Removal of a Miniature Card when the host is off.
Removal, Cold
Host State: The host would either be off or in sleep mode, no bus activity is occurring, the
host is non-operational by the user. User would turn off the host, then remove the Miniature
Card and then press a button to turn the host on for it to become operational again.
User Perception: Removal of the Miniature Card when the host is running.
Removal, Hot
Host State: The host would be in running mode, bus activity is occurring, the host is
operational by the user. User removes the card, the host recognizes the event, and the host
continues to be operational.
User Perception: Removal of the Miniature Card when the host is running.
Removal, Pseudo Hot
Host State: The host would be in running mode, bus activity is occurring, the host is
operational by the user. User removes the card, the host recognizes the event, the host
immediately powers off before the Miniature Card removes contact with the host’s internal
bus. The user would then need to press a button to turn the host on for it to be operational
again.
Sector
Usually 64 KBytes. In word mode, a sector is 64 Kwords.
Tuple
An element of the PC Card Standard CIS that provides card attribute information, and a link
to the next tuple in a string of tuples.
User Insertable
All Miniature Cards should be inserted into the host by the user without the need for any
special tools.
User Removable
This type of Miniature Card can be removed by the user without the need for any special
tools. It contains programs and data that users may want to switch often. The use of this type
of card is similar to a floppy disk.
User Non-Removable
This type of Miniature Card must be removed by the user with a special tool. It contains
memory upgrades or boot program that users switches only when they require an upgrade.
The use of this type of card is similar to a SIMM memory expansion or boot hard disk.
XIP
Acronym for eXecute-In-Place, which refers to code that executes directly from a Miniature
Card.
AmMCL00XA
3
PRELIMINARY
Write Protect Switch (optional)
Pad 60
Pad 31
Pad 30
Pad 1
VCC
Figure 1.
3V/5V
Key
Alignment
Notch
CINS#
GND
21138E-1
Miniature Card Connector (Card Bottom View)
Note: Refer to the Physical Dimensions section for more information. Also refer to the MCIF specification for detailed mechanical
information, available on the Web at http://www.mcif.org.
Table 2.
4
AMD Flash Miniature Cards and Flash Devices
Family Part Number
Density
No. of Flash Devices
AMD Flash Memory
AmMCL002AWP
2 Mbyte
2
Am29LV081
AmMCL004AWP
4 Mbyte
4
Am29LV081
AmMCL00XA
PRELIMINARY
BLOCK DIAGRAM
VCC
VCC
100K
100K
VCC
RY/BY#
BUSY#
10K
RESET#
RESET# to all Flash devices
WE#
WE# to all Flash devices
Write Protect
Switch
OE# to all Flash devices
OE#
D8-D15
D0-D7
A0-A20
VCC
100K
VSS VCC
VCC
A0-A19
D0-D7
CE#
WE# S0**
OE#
RESET# RY/BY#
100K
A20
CEL#
CEL0#
CEH#
CEH0#
CEL1#
CEH1#
Decoder*
VSS VCC
A0-A19
D0-D7
CE#
WE# S2**
OE#
RESET# RY/BY#
VSS VCC
A0-A19
D8-D15
CE#
WE# S1**
OE#
RESET# RY/BY#
VSS VCC
A0-A19
D8-D15
CE#
WE# S3**
OE#
RESET# RY/BY#
21138E-2
*
4 Mbyte card only. Not used on 2 Mbyte card.
** 2 Mbyte card: Two Am29LV081 devices, S0 and S1
4 Mbyte card: Four Am29LV081 devices, S0...S3
Note: On the 2 Mbyte card, A20–A24 are not connected. On the 4 Mbyte card, A21–A24 are not connected. Connections not
shown in this diagram are not connected internally.
AmMCL00XA
5
PRELIMINARY
MINIATURE CARD PAD ASSIGNMENTS
A0–A24
Address A0 to A24 are the address bus lines that can
address up to 32 Mwords (64 Mbytes). The address
lines are word addressed. The Miniature Card specification does not require the Miniature Card to decode
the upper address lines. A 2 Mbyte Miniature Card that
does not decode the upper address lines would repeat
its address space every 2 Mbytes. Address 0h would
access the same physical location as 200000h,
400000h, 600000h, etc. On the 2 Mbyte cards, A20–
A24 are not connected. On the 4 Mbyte cards,
A21–A24 are not connected.
D0–D15
Data lines D0 through D15 constitute the data bus. The
data bus is composed of two bytes; the low byte is
D0–D7 and the high byte is D8–D15. These lines are
tristated when OE# is high.
OE#
OE# indicates to the card that the current bus cycle is
a read cycle. The output enable access time (tOE) is the
delay from the falling edge of OE# to valid data at the
output pins (assuming the addresses have been stable
for at least tACC – tOE time).
WE#
WE# indicates to the card that the current bus cycle is
a write cycle. The falling edge of WE# (or CE#), whichever occurs later, latches address information and the
rising edge of WE# (or CE#), whichever occurs first
latches data/command information.
VS1#
Voltage Sense 1 signal. This signal is grounded.
VS2#
Voltage Sense 2 signal. This signal is left open or not
connected.
CEL#
CEL# enables the low byte of the data bus (D0–D7) on
the card.
RESET#
RESET# controls card initialization. When RESET#
transitions from a low state to a high state, the Miniature Card resets to the Read state after a maximum
delay of 20 µs.
BUSY#
BUSY# is a signal generated by the card to indicate the
status of operations within the Miniature Card. When
BUSY# is high, the Miniature Card is ready to accept
the next command from the host. When BUSY# is low,
the Miniature Card is busy and unable to accept most
data operations from the host. In Flash Miniature Cards
the BUSY# signal is tied to the components’ RY/BY#
signal.
CD#
CD# is a grounded interface signal. After a Miniature
Card has been inserted, CD# will be forced low. The
card detect signal is located in the center of the second
row of interface signals, and should be one of the last
interface signals to connect to the host. Do not confuse
CD# with CINS#.
CINS#
CINS# is a grounded signal on the front of the Miniature
Card that is used for early detection of a card insertion.
CINS# makes contact on the host when the front of the
card is inserted into the socket, before the interface
signals connect.
BS8#
The BS8# (Bus size 8) signal indicates to the Miniature Card that the host has an 8-bit bus. AMD Flash
Miniature Cards ignore this signal (no internal connection). An 8-bit host must connect its D0–D7 data
lines to D8–D15 on the Miniature Card to retrieve the
upper (odd) byte.
GND
Ground
VCC
Vcc is used to supply power to the card.
NC
CEH#
CEH# enables the high byte of the data bus (D8–D15)
on the card.
No connect
RFU
Reserved for future use
6
AmMCL00XA
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
AM
MC
L
004
A
WP
-150
I
TEMPERATURE RANGE
Blank = Commercial (0°C to +70°C)
I
= Industrial (–40°C to +85°C)
SPEED OPTION
WRITE PROTECT SWITCH OPTION
WP = Switch installed
REVISION LEVEL
MEMORY CARD DENSITY
002 = 2 Megabyte Card
004 = 4 Megabyte Card
3 V, SINGLE SUPPLY OPERATION
2.7 V to 3.6 V, extended
operating voltage
MINIATURE CARD
AMD
AmMCL00XA
7
PRELIMINARY
INTERFACE SIGNAL ASSIGNMENTS
Pad Number
Signal Name
Pad Number
Signal Name
Pad Number
Signal Name
1
A18
21
D12
41
A4
2
A16
22
D10
42
CEL#
3
A14
23
D9
43
A1
4
NC
24
D0
44
NC
5
CEH#
25
D2
45
NC
6
A11
26
D4
46
CD#
7
A9
27
RFU
47
A21
8
A8
28
D7
48
BUSY#
9
A6
29
NC
49
WE#
10
A5
30
NC
50
D14
11
A3
31
A19
51
RFU
12
A2
32
A17
52
D11
13
A0
33
A15
53
VS2#
14
NC
34
A13
54
D8
15
A24
35
A12
55
D1
16
A23
36
RESET#
56
D3
17
A22
37
A10
57
D5
18
OE#
38
VS1#
58
D6
19
D15
39
A7
59
RFU
20
D13
40
BS8#
60
A20
Note: NC = No Connect; RFU = Reserved for Future Use.
FLASH MINIATURE CARD OPERATIONS
Voltage Sensing
AMD Miniature Cards provide two voltage sense
signals for hosts that support multiple voltages. The
multivoltage host can sense the voltage level of the
Miniature Card and power up the card at that voltage.
S ee Tab l e 3 f o r a de s c r i pt i on o f th e v ol t ag e
sense signals.
ensure the card can only be inserted into host systems
that can supply the proper voltage levels to the card.
Refer to Section 4.1.2 in the Miniature Card specification for more information on mechanical keying.
Table 3. Voltage Sense Signals
Miniature Card
Power-Up Voltage
VS1#
VS2#
3 volt-only
Gnd
Open
In addition to the voltage sense pins, there are also
mechanical voltage keys on the Miniature Card that
8
AmMCL00XA
PRELIMINARY
Data Accesses
The Miniature Card has a 16-bit data bus that can
accommodate word or byte accesses. By individually
asserting CEL# and CEH#, a host can access either
byte. However, byte swapping (moving the high byte
data to the low byte) is not supported.
Figure 2 shows the connections between the host and
Miniature Card. The host system address lines range
from A0–A25, whereas the Miniature Card address
lines range from A0–A24. On the host, A0 and the
byte/word line are sent to a decoder and output to
CEL# and CEH# on the Miniature Card. These two bits
enable a single device for byte accesses and two
devices for word accesses, as shown by the decoder
truth table in Figure 2. Again, the Miniature Card
address lines do not receive input from host address bit
A0. In this document, all address references are card
addresses, unless otherwise noted. Table 4 shows the
read/write modes for Miniature Cards.
Byte/Word
A0
Decoder
Decoder Truth Table
Input
Host Bus
A24
A22
A23
A21
A2
A1
A1
A0
Output
A0
B/W
CEL#
CEH#
0
0
0
0
0
1
0
1
1
0
0
0
1
1
1
0
A25
60-Pad Connector
A24*
A23*
A22*
A21*
A20**
Card Bus
*
Not connected
**
Not connected on 2 Mbyte card
CEL#
CEH#
21138E-3
Figure 2. Host/Card Address Connections
Word-Wide Operations
Card Detection
The AMD Miniature Card provide the flexibility to
operate on data in a byte-wide or word-wide format. In
word-wide operations, the low bytes are controlled with
CEL#. The high bytes are controlled with CEH#. Refer to
the block diagram for more information.
Each CD# (output) pin should be detected by the host
system to determine if the memory card is adequately
seated in the socket. CD# and CINS# are internally tied
to ground. If both bits are not detected, the system
should indicate that the card must be re-inserted.
Byte-Wide Operations
Data Protection
Byte-wide data is available for read and write operations (CEL# = 0, CEH# = 1). Even and odd bytes are
stored in separate memory devices (for example, S0
and S1) and are accessed by controlling CEL# and
CEH#. The even byte is the low order byte and the odd
byte is the high order byte of a 16-bit word.
An optional mechanical write protect switch provides
user-initiated write protection. When this switch is activated, WE# is internally forced high. The Flash memory
command register is disabled from accepting any write
commands. This prevents the card from responding to
any commands (for example, an Autoselect command). See Figure 3.
Each memory sector or device pair must be addressed
separately for erase operations. Refer to the block
diagram for more information.
AmMCL00XA
9
PRELIMINARY
ensure that the control pins are in the correct logical
state when VCC > VLKO to prevent unintentional writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#,
or WE# will neither initiate a write cycle nor change the
command registers.
Write Enabled
Logical Inhibit
Write Disabled
Figure 3. Write Protect Switch
(Card Right Side View)
21138E-1
Writing is inhibited by holding any one of OE# = VIL,
CE# = VIH, or WE# = VIH. To initiate a write cycle CE#
and WE# must be a logical zero while OE# is a logical
one.
Power-Up Write Inhibit
In addition to card-level data protection, AMD Flash
Miniature Cards offer several device-level data protection features.
Device-Level Data Protection
AMD Flash memory devices offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up, each device automatically
resets the internal state machine to the read mode. The
control register architecture allows alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
AMD Flash memory devices also incorporates the following features to prevent inadvertent write cycles
resulting from VCC power-up and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up
and power-down, the AMD memory devices in the Miniature Card lock out write cycles for VCC < VLKO (see
“DC Characteristics” on page 22 for voltages). When
V CC < V LKO , the command register is disabled, all
internal program/erase circuits are disabled, and the
device resets to the read mode. The memory devices
ignore all writes until V CC > V LKO . The user must
10
Power-up of the device with CE# = WE# = VIL and OE#
= VIH will not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to the read mode on power-up.
Read Mode
Two Card Enable (CE#) pins are available on the
memory card. Both CE# pins must be active low for
word-wide read accesses. Only one CE# is required for
byte-wide accesses. The CE# pins select and determine when to apply power to the high-byte and
low-byte memory devices. The Output Enable (OE#)
controls gating accessed data from the memory device
outputs. Refer to Table 4.
The Miniature Card automatically powers up in the
read/reset state. In this case, a command sequence is
not required to read data. Standard microprocessor
read cycles will retrieve array data. This default state
ensures that no spurious alteration of the memory
content occurs during the power transition. Refer to the
AC Read Characteristics and Waveforms for the specific timing parameters.
Output Disable
Data outputs from the card are disabled when OE# is
at a logic-high level. Under this condition, outputs are
in the high-impedance state.
AmMCL00XA
PRELIMINARY
Table 4.
Miniature Card Read/Write Modes
CEH#
CEL#
WE#
OE#
D8–D15
D0–D7
Word Access
L
L
H
L
High Byte Data
Low Byte Data
Low Byte Access
H
L
H
L
High-Z
Low Byte Data
High Byte Access
L
H
H
L
High Byte Data
High-Z
Word Access
L
L
L
H
High Byte Data
Low Byte Data
Low Byte Access
H
L
L
H
High-Z
Low Byte Data
High Byte Access
L
H
L
H
High Byte Data
High-Z
H
H
X
X
High-Z
High-Z
Function
Read Mode
Write Mode
Standby Mode
Standby
Notes:
1. Unlisted access combinations are invalid and may return unexpected results.
2. X indicates a don’t care value.
Erase Operations
The AMD Flash Miniature Card is organized as an
array of individual devices. Each Am29LV081 device
contains sixteen 64 KByte sectors, for a total of 1 Mbyte
of memory space per device.
Flash technology allows any logical “1” data bit to be programmed to a logical “0”. The only way to reset bits to a
logical “1” is to erase that entire memory sector or
memory device. Once a memory sector or memory
device is erased, any address location may be programmed. Two or more devices may be erased concurrently when additional ICC current is supplied to the card.
However, erasing more than two devices concurrently is
not typical in battery-powered applications, but may take
place during procedures such as card testing.
array. Each device internally latches address and data
during write cycles. Refer to Table 4.
Standby Mode
The AMD flash devices are designed to accommodate
low standby power consumption. In order to achieve
standby mode, the CE# line must be deselected. In
addition, while in the standby mode, data I/O pins
remain in the high impedance state independent of the
voltage level applied to the OE# input. See the DC
Characteristics section for more details on Standby
Modes.
■ Erase a sector pair
Deselecting CE# (CE# and RESET# = VCC ± 0.3 V)
puts the device into the I CC3 standby mode. If the
device is deselected during an Embedded Algorithm
operation, it continues to draw active power (ICC2) prior
to entering the standby mode, until the operation is
complete. When the device is again selected (CE# =
VIL), active operations occur in accordance with the
AC timing specifications.
■ Erase multiple device pairs*
Automatic Sleep Mode
Erase operations can be performed in several ways:
■ Erase a single sector or multiple sectors in a device
■ Erase the entire card*
* This operation is only feasible in solutions capable of
supplying more than the specified miniature card
supply current requirement (150mA) per system. Each
AMD Flash memory device pair can accept a
maximum of 120mA supply current.
The common memory space data contents are altered
in a similar manner to writing to individual Flash
memory devices. An on-card address decoder activates the appropriate Flash device in the memory
Advanced power management features such as the
automatic sleep mode minimize Flash device energy
consumption. This is extremely important in battery-powered applications. The AMD memory devices
automatically enable the low-power, automatic sleep
mode when addresses remain stable for 300 ns. Automatic sleep mode is independent of the CE#, WE#, and
OE# control signals. Typical sleep mode current draw
from each device is < 1 µA. Standard address access
timings provide new data when addresses are
AmMCL00XA
11
PRELIMINARY
changed. While in sleep mode, output data is latched
and always available to the system.
ing them in the improper sequence will reset the
device to the read mode.
Command Definitions
The byte-wide commands are defined in Tables 6 and
7; word-wide commands are defined in Table 5. Note
that the Erase Suspend (B0h) and Erase Resume
(30h) commands are valid only while the Sector Erase
operation is in progress.
Each memory device contains a command register,
which is a latch that saves address, commands, and
data information used by the state machine and
memory array. The state machine is active when VCC is
greater than VLKO (2.3 - 2.5 V). This is required for valid
program and erase operations.
When Write Enable (WE#) and appropriate CE#
signals are at a logic-low level, and Output Enable
(OE#) is at a logic-high, the command register is
enabled for write operations. The falling edge of WE#
or CE#, whichever occurs later, latches address information and the rising edge of WE# or CE#, whichever
occurs first, latches data/command information.
Commands are accomplished by writing non-specific
address and specific data sequences into the command register of accessed Flash memory devices.
Writing incorrect address and data values or writ-
12
Autoselect Operation
A host system or external card reader/writer can determine the on-card manufacturer and device I.D. codes.
Codes are available after writing the 90h command to
the command register of a memory device, as shown in
Tables 5 through 7. When the autoselect command is
issued to card address 00000h, the Miniature Card
returns the manufacturer I.D. If the autoselect
command is issued to card address 00001h, the Miniature Card provides the device I.D.
To terminate the autoselect operation, the Read/Reset
command sequence must be written to the same
device. The Autoselect command operates only if the
card is not write protected.
AmMCL00XA
PRELIMINARY
Table 5.
Word Command Definitions
Cycles
Bus Cycles (Notes 2–9)
Addr
Read
1
RA
RW
Reset
1
XXXX
F0F0
Autoselect Manufacturer ID
(Note 4)
4
XXXX
AAAA
XXXX
5555
XXXX
9090
XX00
0101
Autoselect Device ID
(Note 4)
4
XXXX
AAAA
XXXX
5555
XXXX
9090
XX01
3838
Word Write
4
XXXX
AAAA
XXXX
5555
XXXX
A0A0
PA
PW
Device Erase
6
XXXX
AAAA
XXXX
5555
XXXX
8080
XXXX
AAAA
XXXX
5555
XXXX
1010
Sector Erase
6
XXXX
AAAA
XXXX
5555
XXXX
8080
XXXX
AAAA
XXXX
5555
SA
3030
Sector Erase Suspend (Note 7)
1
XXXX
B0B0
Sector Erase Resume (Note 8)
1
XXXX
3030
Embedded Command
Sequence (Note 1)
First
Data
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr Data
Addr Data
Addr Data
Addr Data
Legend:
X = Don’t care
PW = Data to be programmed at location PA. Data is latched
on the rising edge of WE#.
RA = Address of the memory location to be read.
RW = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
SA = Address of the sector to be erased. Refer to Table 8 for
sector addresses.
Notes:
1. Write protect must not be enabled for proper operation of
all commands. No command required for reading array
data, and can thus be done with write protect enabled.
2. During word addressing, CEL# = 0, CEH# = 0, and
address is applied to Memory Device Pair 0 (S0 and S1).
On 4 Mbyte cards, address for Memory Device Pair 1 =
(Addr) + 200000h, and address is applied to Memory
Device Pair 1 (S2 and S3). For host-to-card address bit
connections, see Figure 2.
7. The Erase Suspend command is valid only during a
sector erase operation. Refer to “Sector Erase Suspend”.
8. The Erase Resume command is valid only during the
Erase Suspend mode.
9. See Table 4 for bus operations.
3. All values are in hexadecimal.
4. The last bus cycle in an autoselect command sequence is
a read operation.
5. Word = high byte + low byte.
6. Address bits = X = Don’t Care for all commands except for
Read Address (RA), Program Address (PA), and Sector
Address (SA).
AmMCL00XA
13
PRELIMINARY
Embedded Command Sequence
(Note 1)
Cycles
Table 6.
Read
1
Reset
Even Byte Command Definitions
Bus Cycles (Notes 2–8)
First
Second
Addr
Data
RA
RD
Third
Fourth
Addr
Data
Addr
Data
Addr
Data
1
XXXX XXF0
Autoselect Manufacturer ID (Note 4)
4
XXXX XXAA XXXX
XX55
XXXX
XX90
XX00
XX01
Device ID (Note 4)
4
XXXX XXAA XXXX
XX55
XXXX
XX90
XX01
XX38
Byte Write
4
XXXX XXAA XXXX
XX55
XXXX
XXA0
PA
PD
Device Erase
6
XXXX XXAA XXXX
XX55
XXXX
Sector Erase
6
XXXX XXAA XXXX
XX55
XXXX
Sector Erase Suspend (Note 6)
1
XXXX XXB0
Sector Erase Resume (Note 7)
1
XXXX XX30
Fifth
Sixth
Addr
Data
Addr
Data
XX80
XXXX XXAA XXXX
XX55
XXXX
XX10
XX80
XXXX XXAA XXXX
XX55
SA
XX30
Note for Table 6: During even (low) byte accesses, CEL# = 0, CEH# = 1. Address is applied to Memory Device 0 (S0). On 4 Mbyte
cards, address for Memory Device 2 (S2) = (Addr) + 200000h.
Table 7.
Read
Reset
Bus Cycles (Notes 2–8)
Cycles
Embedded Command Sequence
(Note 1)
Odd Byte Command Definitions
Addr
Data
1
RA
RD
First
Second
Third
Fourth
Addr
Data
Addr
Data
Addr
Data
1
XXXX XXF0
Autoselect Manufacturer ID (Note 4)
4
XXXX AAXX XXXX
55XX
XXXX
90XX
XX00
01XX
Autoselect Device ID (Note 4)
4
XXXX AAXX XXXX
55XX
XXXX
90XX
XX01
38XX
Byte Write
4
XXXX AAXX XXXX
55XX
XXXX
A0XX
PA
PDXX
Device Erase
6
XXXX AAXX XXXX
55XX
XXXX
Sector Erase
6
XXXX AAXX XXXX
55XX
XXXX
Sector Erase Suspend (Note 6)
1
XXXX XXB0
Sector Erase Resume (Note 7)
1
XXXX XX30
Fifth
Sixth
Addr
Data
Addr
Data
80XX
XXXX AAXX XXXX
55XX
XXXX
10XX
80XX
XXXX AAXX XXXX
55XX
SA
30XX
Note for Table 7: During odd (high) byte accesses, CEL#= 1, CEH# = 0, and address is applied to Memory Device 1 (S1). On 4 Mbyte
cards, address for Memory Device 3 (S3) = (Addr) + 200000h + 100000h.
Legend for Tables 6 and 7:
X = Don’t care
PW = Data to be programmed at location PA. Data is latched on
the rising edge of WE#.
RA = Address of the memory location to be read.
RW = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
SA = Address of the sector to be erased. Refer to Table 8 for
sector addresses.
Notes for Tables 6 and 7:
1. Write protect must not be enabled for proper operation of all
commands. No command required for reading array data,
and can thus be done with write protect enabled.
6. The Erase Suspend command is valid only during a sector
erase operation. Refer to “Sector Erase Suspend”.
2. For host-to-card address bit connections, see Figure 2.
7. The Erase Resume command is valid only during the Erase
Suspend mode.
3. All values are in hexadecimal.
8. See Table 4 for bus operations.
4. The last bus cycle in an autoselect command sequence is a
read operation.
5. Address bits = X = Don’t Care for all commands except for
Read Address (RA), Program Address (PA), and Sector
Address (SA).
14
AmMCL00XA
PRELIMINARY
Table 8.
Memory Sector Addresses
Device 0 and/or 1 (Note 1)
Device 2 and/or 3 (Note 1)
Sector
A19
Card Address Bits
A18
A17
A16
Card Address Range
Card Address Range
0
0
0
0
0
00000h–0FFFFh
100000h–10FFFFh
1
0
0
0
1
10000h–1FFFFh
110000h–11FFFFh
2
0
0
1
0
20000h–2FFFFh
120000h–12FFFFh
3
0
0
1
1
30000h–3FFFFh
130000h–13FFFFh
4
0
1
0
0
40000h–4FFFFh
140000h–14FFFFh
5
0
1
0
1
50000h–5FFFFh
150000h–15FFFFh
6
0
1
1
0
60000h–6FFFFh
160000h–16FFFFh
7
0
1
1
1
70000h–7FFFFh
170000h–17FFFFh
8
1
0
0
0
80000h–8FFFFh
180000h–18FFFFh
9
1
0
0
1
90000h–9FFFFh
190000h–19FFFFh
10
1
0
1
0
A0000h–AFFFFh
1A0000h–1AFFFFh
11
1
0
1
1
B0000h–BFFFFh
1B0000h–1BFFFFh
12
1
1
0
0
C0000h–CFFFFh
1C0000h–1CFFFFh
13
1
1
0
1
D0000h–DFFFFh
1D0000h–1DFFFFh
14
1
1
1
0
E0000h–EFFFFh
1E0000h–1EFFFFh
15
1
1
1
1
F0000h–FFFFFh
1F0000h–1FFFFFh
Notes:
1. For word addressing, devices 0 and 1 (S0 and S1) together form Memory Device Pair 0; devices 2 and 3 (S2 and S3) form
Memory Device Pair 1. Refer to the block diagram for device connections.
2. Card address bits range from A0 to A19. Host address bits range from A0 to A20. Host address bit A0 is used for controlling
the CEL# and CEH# inputs to the card. Refer to Figure 2 for host-to-card address bit connections.
AmMCL00XA
15
PRELIMINARY
AMD FLASH MEMORY PROGRAM AND
ERASE OPERATIONS
To simplify program and erase operations, AMD Flash
Memory devices include Embedded Algorithms
(Embedded Erase Algorithm and Embedded Program
Algorithm) that allow the host to simply issue a command, after which it is free to perform other tasks. The
host then only needs to monitor appropriate status bits
to determine when the operation is complete.
Embedded Erase Algorithm
When erasing a sector or device, the Embedded Erase
algorithm does not require the host to first entirely
pr e- p r o g r am th e d ev i c e . Up o n e x ec u t in g t he
Embedded Erase command sequence, the addressed
memory sector or memory device automatically writes
and verifies the entire memory device or memory
sector for an all “0” data pattern. The system is not
required to provide any controls or timing during these
operations.
When the memory sector or memory device is automatically verified to contain an all “0” pattern, a
self-timed chip erase-and-verify begins. The erase and
verify operations are complete when the data on D7
(D15 on the odd byte) of the memory sector or memory
device is “1” (see Write Operation Status section), at
which time the device returns to the read mode. The
system is not required to provide any control or timing
during these operations. If a Reset command is issued
while the erase operation is in progress, the erase
operation will stop, and the data in that device will be
undefined. In that case, restart the erase on that sector
and allow it to complete.
When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin
has been achieved for the memory array (no erase
verify command is required).
The Embedded Erase command sequence is a
command only operation that stages the memory
sector or memory device for automatic electrical
erasure of all bytes in the array. The automatic erase
begins on the rising edge of the WE# and terminates
when the data on D7 (D15 on the odd byte) of the
memory sector or memory device is “1” (see Write
Operation Status section) at which time the device
returns to the Read mode. Please note that for the
memory device or memory sector erase operation,
Data Polling may be performed at any address in that
device or sector.
Figure 4 and Table 9 illustrate the Embedded Erase
Algorithm, a typical command string and bus operations.
As described earlier, once the memory sector in a
device or memory device completes the Embedded
Erase operation, it returns to the Read mode and
addresses are no longer latched. Therefore, the device
16
requires that a valid address input to the device is
supplied by the system at this particular instant of time.
Otherwise, the system will never read a “1” on D7 (D15
on the odd byte). A system designer has the following
choices to implement the Embedded Erase algorithm:
1. The host may keep the sector address (within any
of the sectors being erased) valid during the entire
Embedded Erase operation.
2. Once the system executes the Embedded Erase
command sequence, the host may remove the address from the device and perform other tasks. The
host is required to keep track of the valid sector address by loading it into a temporary register. When
the host comes back to Data Poll the device, it must
reassert the same address.
3. The host may monitor BUSY# (RY/BY#) to determine the status of the Embedded Algorithm in
progress. A “0” indicates that the device is busy; a
“1” indicates that the algorithm is complete.
Sector Erase
Sector erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the sector erase command. The
sector address (any address location within the desired
sector) is latched on the falling edge of WE# (or CE#),
whichever occurs later, while the data is latched on the
rising edge of WE# (or CE#) pulse, whichever occurs
first. A time-out of 80 µs from the rising edge of the last
sector erase command will initiate the sector erase
command.
Multiple sectors can be specified for erase by writing
the six bus cycle operation as described above and
then following it by additional writes of the Sector Erase
command to addresses of other sectors to be erased.
The time between Sector Erase command writes must
be less than 80 µs, otherwise that command will not be
accepted. It is recommended that processor interrupts
be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector
Erase command is written. A time-out of 80 µs from the
rising edge of the last WE# (or CE#) will initiate the execution of the Sector Erase command(s). If another
falling edge of the WE# (or CE#) occurs within the 80
µs time-out window, the timer is reset. During the 80 µs
window, any command other than Sector Erase or
Erase Suspend written to the device will reset the device back to Read mode. Once the 80 µs window has
timed out, only the Erase suspend command is recognized. Note that although the Reset command is not
recognized in the Erase Suspend mode, the device is
available for read or program operations in sectors that
are not erase suspended. The Erase Suspended and
Erase Resume commands may be written as often as
required during a sector erase operation. Hence, once
erase has begun, it must ultimately complete unless
AmMCL00XA
PRELIMINARY
Hardware Reset is initiated. Loading the sector erase
registers may be done in any sequence and with any
number of sectors (0 to 15).
Start
A Reset command issued after the device has begun
execution stops the erase operation, but the data in the
sector will be undefined. In that case, restart the erase
on that sector and allow it to complete.
Write Embedded Erase
Command Sequence
(See Tables 5–7)
The automatic sector erase begins after the 80 µs time
out from the rising edge of the WE# (or CE#) pulse for
the last sector erase command pulse and terminates
when the data on D7 is “1” (see Write Operation Status
section) at which time the device returns to read mode.
Data Polling must be performed at an address within
any of the sectors being erased.
If DATA Polling or the Toggle Bit indicates the device
has been written with a valid Sector Erase command,
D3 may be used to determine if the sector erase timer
window is still open. If D3 is high (‘1’), the internally
controlled erase cycle has begun; attempts to write
subsequent commands to the device will be ignored
until the erase operation is completed as indicated by
the DATA Polling or Toggle Bit. If D3 is low (‘0’), the
device will accept additional sector erase commands.
To be certain the command has been accepted, the
software should check the status of D3 following each
Sector Erase command. If D3 was high on the second
status check, the command may not have been
accepted.
It is recommended that the user guarantee the time
between sector erase command writes be less than 80
µs by disabling the processor interrupts just for the
duration of the Sector Erase (30H) commands. This
approach will ensure that sequential sector erase
command writes will be written to the device while the
sector erase timer window is still open.
Figure 4 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Table 9.
Bus
Operation
Embedded Erase Algorithm
Command
Wait for VCC ramp
Standby
Write
Read
Comments
Embedded Erase
command sequence
6 bus cycle operation
Data Poll or check
BUSY# (RY/BY#)
to verify erasure
Data Poll from Device
or wait for BUSY#
(RY/BY#)
Erasure Complete
21138E-5
Figure 4.
Embedded Erase Algorithm
Note: The latest release of the software drivers for AMD
Miniature Cards and devices may be downloaded from the
AMD web site at http://www.amd.com.
Embedded Program Algorithm
The Embedded Program setup is a four bus cycle operation that stages the addressed memory location or
memory device for automatic programming.
Once the Embedded Program setup operation is performed, the next WE# pulse causes a transition to an
active programming operation. Addresses are internally latched on the falling edge of the WE# (or CE#)
pulse. Data is internally latched on the rising edge of
the WE# pulse. The rising edge of WE# also begins the
programming operation. The system is not required to
provide further control or timing. The device will automatically provide an adequate internally generated
write pulse and verify margin. The automatic programming operation is completed when the data on D7 of
the addressed memory sector or memory device is
equivalent to data written to this bit (see Write Operation Status section) at which time the device returns to
the Read mode (no write verify command is required).
Addresses are latched on the falling edge of WE# (or
CE#) during the Embedded Program command execution and hence the system is not required to keep the
addresses stable during the entire Programming operation. However, once the device completes the
Embedded Program operation, it returns to the Read
mode and addresses are no longer latched. Since a
verify valid data must occur on D7, at this particular
instant, the system is required to supply a valid address
input to the device. A system designer has three choices
to implement the Embedded Programming algorithm:
AmMCL00XA
17
PRELIMINARY
1. The system (CPU) keeps the address valid during
the entire Embedded Programming operation, or
Start
2. Once the system executes the Embedded Programming command sequence, the CPU takes
away the address from the device and becomes
free to do other tasks. In this case, the CPU is required to keep track of the valid address by loading
it into a temporary register. When the CPU comes
back for performing Data Polling, it should reassert
the same address.
Write Embedded Write Command
Sequence per Tables 5–7
Data Poll Device
or wait for BUSY# (RY/BY#)
3. The host may monitor BUSY# (RY/BY#) to determine the status of the Embedded Algorithm in
progress. A “0” indicates that the device is busy; a
“1” indicates that the algorithm is complete.
However, since the Embedded Programming operation
takes only 9 µs typically, it may be easier for the CPU
to keep the address stable during the entire Embedded
Programming operation instead of reasserting the valid
address during Data Polling. Any commands written to
the device during this period will be ignored. Figure 5
and Table 10 illustrate the Embedded Program Algorithm, a typical command string, and bus operation.
Y
Increment
Address
N
Last
Address
Y
Completed
Table 10. Embedded Program Algorithm
Bus
Operation
21138E-6
Figure 5. Embedded Program Algorithm
Command
Comments
Wait for VCC ramp
Standby
Write
Embedded Program
3 bus cycle operation
command sequence
Write
Program
Address/Data
Read
N
Verify
Data
1 bus cycle operation
Data Poll or check
BUSY# (RY/BY#) to
verify program
Reset Command
The device will automatically power up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor cycles
will retrieve array data. This default value ensures that
no spurious alteration of the memory content occurs
during the power transition. Refer to the AC Characteristics section for the specific timing parameters.
The reset operation is initiated by writing the read/reset
command sequence into the command register. Microprocessor read cycles retrieve array data from the
memory. The device remains enabled for reads until
the command register contents are altered.
Sector Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data
read or programs in a sector not being erased. This
command is applicable only during the Sector Erase
operation, which includes the time-out period for Sector
Erase. The Erase Suspend command will be ignored if
written during the execution of the Chip Erase operation or Embedded Program Algorithm (but will reset the
chip if written improperly during the command sequences.) Writing the Erase Suspend command during
the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation. Once in Erase Suspend, the device is avail-
18
AmMCL00XA
PRELIMINARY
able for read (note that in the Erase Suspend mode, the
Reset/Read command is not required for read operations and is ignored) or program operations in sectors
not being erased. Any other command written during
the Erase Suspend mode will be ignored, except for the
Erase Resume command. Writing the Erase Resume
command resumes the sector erase operation. The addresses are “don’t cares” when writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during a
Sector Erase operation, the chip will take between 0.1
µs and 20 µs to actually suspend the operation and go
into erase suspended read mode (pseudo-read mode),
at which time the user can read or program from a sector that is not erase suspended. Reading data in this
mode is the same as reading from the standard read
mode, except that the data must be read from sectors
that have not been erase suspended.
ded Program Algorithm, an attempt to read the device
will produce the true data last written to D7. Note that
just at the instant when D7 switches to true data, the
other bits, D6–D0, may not yet be true data. However,
they will all be true data on the next read from the device. Please note that Data Polling (D7) may give an
inaccurate result when an attempt is made to write
to a protected sector. During an Embedded Erase Algorithm, an attempt to read the device will produce a ‘0’
at the D7 output. Upon completion of the Embedded
Erase Algorithm, an attempt to read
the device will produce a ‘1’ at D7.
START
Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode
will cause D2 to toggle. Polling D2 on successive reads
from a given sector provides the system the ability to
determine if a sector is in Erase Suspend.
After entering the erase-suspend-read mode, the user
can program the device by writing the appropriate command sequence for Byte Program. This program mode
is known as the erase suspend-program mode. Again,
programming in this mode is the same as programming
in the regular Byte Program mode, except that the data
must be programmed to sectors that are not erase suspended. Successively reading from the erase suspended sector while the device is in the erase
suspend-program mode will cause D2 to toggle. Completion of the erase suspend operation can be determined two ways:
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
DQ7 = Data?
Yes
No
■ Checking the status of the toggle bit D2
■ Checking the status of the RY/BY# pin
FAIL
To resume the operation of Sector Erase, the Resume
command (30H) should be written. Any further writes of
the Resume command at this point will be ignored.
However, another Erase Suspend command can be
written after the device has resumed sector erase operations.
PASS
21138E-7
Note: D7 is rechecked even if D5 = 1 because D7 may
change simultaneously with D5.
Figure 6. Data Polling Algorithm
Write Operation Status
Table 11 shows the status bit states for device program
and erase operations.
Data Polling—D7 (D15 on Odd Byte)
The Miniature card features DATA Polling as a method
to indicate to the host system that the embedded algorithms are in progress or completed.
During the Embedded Program Algorithm, an attempt
to read the device will produce the compliment of the
data last written to D7. Upon completion of the Embed-
AmMCL00XA
19
PRELIMINARY
Table 11. Hardware Sequence Flags
Status
D7
D6
D5
D3
D2
D7
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle
(Note 1)
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
D7
Toggle
(Note 2)
0
1
1
(Note 3)
D7
Toggle
1
0
1
0
Toggle
1
1
N/A
D7
Toggle
1
1
N/A
Byte Program in Embedded Program Algorithm
Embedded Erase Algorithm
Erase Suspend Read
(Erase Suspended Sector)
In Progress
Erase Suspended Mode
Byte Program in Embedded Program Algorithm
Exceeded
Time Limits
Program/Erase in Embedded Erase Algorithm
Erase Suspended Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
Notes:
1. Performing successive read operations from the erase-suspended sector will cause D2 to toggle.
2. Performing successive read operations from any address will cause D6 to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the D2 bit.
However, successive reads from the erase-suspended sector will cause D2 to toggle.
WORD-WIDE PROGRAMMING
BUSY# (RY/BY#—Ready/Busy)
The BUSY# signal indicates to the host the status of
operations within the Miniature Card. The BUSY#
signal is tied to the components’ RY/BY# pins.
The RY/BY# signal from AMD Flash devices in
the Miniature Card indicate that the Embedded Algorithms are either in progress or have been completed.
If the output is low, the device is busy with either a
program or erase operation. If the output is high, the
device is ready to accept any read/write or erase operation. When the RY/BY# pin is low, the device will
not accept any additional program or erase commands with the exception of the Erase Suspend command. If a Flash device is placed in an Erase
Suspend mode, the RY/BY# output will be high. Refer
to the section “Sector Erase Suspend” for more information.
20
The Word-Wide Programming sequence will be as
usual per Table 5. The Program word command is
A0A0H. Each byte is independently programmed. For
example, if the high byte of the word indicates
the successful completion of programming via one of
its write status bits such as D15, software polling
should continue to monitor the low byte for write completion and data verification, or vice versa. During the
Embedded Programming operations the device executes programming pulses in 9 µs increments.
WORD-WIDE SECTOR ERASING
The Word-Wide Sector Erasing of a memory device
pair is similar to word-wide programming. The erase
word command is a six-bus-cycle command sequence
(see Table 5). Each sector is independently erased and
verified. Word-wide erasure reduces total erase time
when compared to byte erasure. Each Flash memory
device in the card may erase at different rates. Therefore, each device (byte) must be verified separately.
AmMCL00XA
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . –40°C to +90°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . –40°C to +85°C
Voltage at All Pins (Note 1) . . . . –0.5 V to VCC+0.5 V
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output Short Circuit Current (Note 2) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshoot VSS to –2.0 V
for periods of up to 20 ns. Maximum DC voltage on output
and I/O pins is VCC + 0.5 V. During voltage transitions,
outputs may overshoot to VCC + 2.0 V for periods up to
20ns.
2. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Conditions equal VOUT = 0.5 V or 3.6 V, VCC = VCCmax.
These values are chosen to avoid test problems caused
by tester ground degradation. This parameter is sampled
and not 100% tested, but guaranteed by characterization.
3. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device
reliability.
OPERATING RANGES
Commercial Devices
Case Temperature (TC). . . . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Case Temperature (TC). . . . . . . . . . . .–40°C to +85°C
VCC Supply Voltages
AmMCL00XAWP-150 . . . . . . . . . . . . +2.7 V to +3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
AmMCL00XA
21
PRELIMINARY
DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
ILI
Input Leakage Current
VIN = VSS to VCC, VCC = VCC max
±5
µA
ILO
Output Leakage Current
VIN = VSS to VCC, VCC = VCC max
±5
µA
30
µA
VCC Standby Current
CEL#, CEH#, RESET# = VCC ± 0.3 2 Mbyte
V
4 Mbyte
V = 3.6V; V = V or V
40
µA
Read
40
mA
Write
60
mA
ICCS
CC
IN
SS
CC
ICC
VCC Supply Current, word
mode (Note 2)
RESET# = VIH; CEL# and CEH# =
VIL
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.5
V
VOL
Output Low Voltage
IOUT = 5.8 mA
0.45
V
VOH
Output High Voltage
IOUT = –2.0 mA
VLKO
Low VCC Lock-Out Voltage
0.85 VCC
V
2.3
Notes:
1. VCC = 2.7 V to 3.6 V.
2.5
V
2. Supply current is a max RMS value. Read frequency = 5
MHz.
CONNECTOR DC SPECIFICATIONS
Parameter
Min
Interface Signal Resistance (Note 2)
Interface Signal Current (Notes 1, 2)
Max
Units
2.0
Ω
125
Power/Insertion Signal Resistance
mA
0.060
Power/Insertion Signal Current (Note 1)
500
Ω
mA
Notes:
1. This current is a minimum that the connector should withstand, and a maximum that the host should provide.
2. On the host, these specifications must be met for one conducting channel on elastomeric connectors.
CARD AND PAD CAPACITANCE
Parameter Symbol
Parameter Description
Max
Unit
CCARD
Card Input Capacitance
40
pF
CHOST
System Load Capacitance
120
pF
I/O Capacitance D0-D15
40
pF
CI/O
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
22
Test Conditions
AmMCL00XA
PRELIMINARY
AC CHARACTERISTICS
Read-only Operations
Parameter Symbol
JEDEC
Standard
tAVAV
tRC
Read Cycle Time
Min
tELQV
tCE
Chip Enable Access Time
Max
150
ns
tAVQV
tACC
Address Access Time
Max
150
ns
tGLQV
tOE
Output Enable Access Time
Max
50
ns
tELQX
tLZ
Chip Enable to Output in Low-Z
Min
5
ns
tEHQZ
tDF
Chip Disable to Output in High-Z
Max
30
ns
tGLQX
tOLZ
Output Enable to Output in Low-Z
Min
5
ns
tGHQZ
tDF
Output Disable to Output in High-Z
Max
30
ns
tAXQX
tOH
Output Hold from First of Address, CE#, or OE# Change
Min
5
ns
RESET# Pin Low to Read Mode
Max
20
µs
tReady
Parameter Description
-150
AmMCL00XA
150
Unit
ns
23
PRELIMINARY
AC CHARACTERISTICS
Write Operations (Erase/Program)
Parameter Symbols
JEDEC
Standard
tAVAV
tWC
-150
Unit
Write Cycle Time
Min
150
ns
tWLWH
WE# pulse width
Min
50
ns
tELGL
tELWL
CE# setup time to WE# or OE# active
Min
0
ns
tAVGL
tAVWL
Address setup time to WE# or OE# active
Min
0
ns
tDVWH
Data setup time to WE# inactive
Min
50
ns
tWHDX
Data hold time from WE# inactive
Min
0
ns
tWHAX
Address hold time from WE# inactive
Min
0
ns
tWHEH
CE# hold time from WE# inactive
Min
0
ns
RESET# Pulse Width
Min
500
ns
Program/Erase Valid to RY/BY# Delay
Min
90
ns
Typ
9
Max
300
Typ
1.5
Max
15
tRP
tBUSY
24
Parameter Description
tWHWH1
Programming Operation
tWHWH2
Sector Erase Operation
AmMCL00XA
µs
s
PRELIMINARY
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010
SWITCHING WAVEFORMS
tAVAV
tAVQV
tAXQX
tAVGL
A0–A25
tELGL
tELQV
tEHQX
tELQNZ
CEL#/CEH#
tGLQV
tGHQZ
tGLQNZ
tGHQX
OE#
Valid Data
D0–D15
21138E-8
Figure 7.
AC Waveforms for Read Operations
AmMCL00XA
25
PRELIMINARY
SWITCHING WAVEFORMS
tAVAV
tAVWL
tWHAX
A0–A25
tELWL
tWHEH
CEL#/CEH#
tWLWH
tDVWH
tWHDX
WE#
Valid Data
D0–D15
21138E-9
Figure 8. AC Waveforms for Write Operations
CE#
tCH
tDF
tOE
OE#
tOEH
tCE
WE#
*
D7#
D7
tOH
D7=
Valid Data
High Z
tWHWH1 or tWHWH2
D0–D6=Invalid
D0–D6
D0–D7
Valid Data
*D7=Valid Data (The device has completed the Embedded operation).
Figure 9.
26
AC Waveforms for Data Polling During Embedded Algorithm Operations
AmMCL00XA
21138E-10
PRELIMINARY
SWITCHING WAVEFORMS
CE#
The rising edge of the last WE# signal
WE#
Entire programming
or erase operations
RY/BY#
tBUSY
21138E-11
Figure 10. RY/BY# Timing Diagram During Program/Erase Operations
RESET#
tRP
tReady
21138E-12
Figure 11. RESET# Timing Diagram
AmMCL00XA
27
PRELIMINARY
AC CHARACTERISTICS-ALTERNATE CE# CONTROLLED WRITES
Write/Erase/Program Operations
Parameter Symbols
JEDEC
Standard
Parameter Description
-150
Unit
tAVAV
tWC
Write Cycle Time
Min
150
ns
tAVEL
tAS
Address Setup Time
Min
10
ns
tELAX
tAH
Address Hold Time
Min
50
ns
tDVEH
tDS
Data Setup Time
Min
50
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGLDV
tOEH
Output Enable Hold Time for Embedded Algorithm
Min
10
ns
Read Recovery Time before Write
Min
0
µs
tGHEL
tWLEL
tWS
WE# Setup Time before CE#
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
50
ns
tEHEL
tCPH
CE# Pulse Width HIGH (Note 3)
Min
20
ns
Typ
9
Max
300
tEHEH3
Embedded Programming Operation (Notes 3,4)
Embedded Erase Operation for each 64K byte Memory
Sector (Notes 1, 2)
Typ
1.5
tEHEH4
Max
15
s
tVCS
VCC Setup Time to Write Enable LOW
Min
50
µs
µs
Notes:
1. Rise/fall time ≤10 ns.
2. Maximum specification not needed due to the internal stop timer that will stop any erase or write operation that exceed the
device specification.
3. Card Enable Controlled Programming:
Flash Programming is controlled by the valid combination of the Card Enable (CE1#, CE2#) and Write Enable (WE#) signals.
For systems that use the Card Enable signal(s) to define the write pulse width, all setup, hold, and inactive write enable timing
should be measured relative to the Card Enable signal(s).
4. Under worst case condition of 90° C, Vcc = 2.7 V, 100,000 cycles. Excludes system level overhead, the time required to
execute the four bus cycle command necessary to program each byte.
28
AmMCL00XA
PRELIMINARY
tWC
Addresses
Data# Polling
tAS
XXXXh
PA
PA
tAH
WE#
tWH
OE#
tGHEL
tCP
CE#
tWS
tEHEH3_or_4
tCPH
tDS
tDH
A0h
Data
DQ7#
PD
DOUT
VCC
tVCS
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. D7 is the complement of the data written to the device.
4. DOUT is the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. These waveforms are for the x16 mode.
21138E-13
Figure 12.
Alternate CE# Controlled Write Operation Timings
AIS MEMORY MAP
The AIS (Attribute Information Structure) is an area of
memory used for storing information about the configuration of the Miniature Card. The AIS is recommended
to be stored in the first sector of the first device of the
Flash array. As this area is not explicitly protected, the
AIS information must be reloaded onto the card in the
event that the information is erased.
The AIS has five unique information areas:
1. Identification Data: This data includes Manufacturer
information (Manufacturer and card name).
2. Compatibility Data: This data specifies basic information about the card (memory size, access time,
memory type, power, etc.)
The AIS supports up to four different memory technologies on a card. Some of the information areas are
repeated in the memory map in order to specify different technologies (see Table 12). The Technology
Count field in the Identification Data section defines the
number of different technologies on a card. The first
memory technology is defined in the AIS memory map
from address 40H through 7FH. The second memory
technology is defined from 80H through BFH. The third
memory technology is defined from C0H to DFH. The
fourth memory technology is defined from E0H to FFH.
The AIS is stored as bytes within the 16-bit Miniature
Card data word. The even byte D0–D7 stores the AIS
data, and the odd byte D8–D15 is reserved by the card
manufacturer for manufacturing information.
3. Burst Data (not applicable)
4. DRAM Data (not applicable)
5. Reserved Data: This data area is reserved for future use.
AmMCL00XA
29
PRELIMINARY
Table 12. Miniature Card AIS Memory Assignments
Card Address
Section
00h–0Fh
PC Card Compatibility Area*
10h–1Fh
Identification Data Identifies Card Type
20h–2Fh
Identification Data Identifies Card Type
30h–3Fh
Identification Data Identifies Card Type
40h–4Fh
Compatibility Data (Area 1)
50h–5Fh
Burst Data (not applicable)
60h–6Fh
DRAM Data (not applicable)
70h–7Fh
Reserved for future use
80h–8Fh
Compatibility Data (not applicable)
90h–9Fh
Burst Data (not applicable)
A0h–AFh
DRAM Data (not applicable)
B0h–BFh
Reserved for future use
C0h–CFh
Compatibility Data (not applicable)
D0h–DFh
Reserved for future use
E0h–EFh
Compatibility Data (not applicable)
F0h–FFh
Reserved for future use
Description
Reserved for PC Card Tuples
Memory Technology #1
(Memory Technology #2)
(Memory Technology #3)
(Memory Technology #4)
* For more information on PC Card Compatibility refer to table 13 or the Miniature Card PC Compatibility Guide.
Note: “Not applicable” indicates the address space does not apply to AMD Flash Miniature Cards, but is defined by MCIF.
30
AmMCL00XA
PRELIMINARY
Table 13. PC Card Compatibility Memory Assignments
Address
Values
Description
00h
01h
TPL_CODE CISTPL_DEVICE
01h
03h
TPL_LINK
02h
53
Device ID
03h
2 MB = 7C, 4 MB = FC
04h
FF
05h
1Ch
TPL_CODE CISTPL_DEVICE_OC
06h
03h
TPL_LINK
07h
53h
Device ID
08h
2MB = 7C; 4MB = FC
09h
FFh
End of CISTPL_DEVICE_OC
0Ah
00h
CISTPL_NULL
0Bh
00h
CISTPL_NULL
0Ch
00h
CISTPL_NULL
0Dh
00h
CISTPL_NULL
0Eh
80h
TPL_CODE CISTPL_MINI
0Fh
F0h
TPL_LINK
Device Size
End of CISTPL_DEVICE
AmMCL00XA
Device Size
31
PRELIMINARY
Identification Data
Compatibility Data
The identification data provides basic identification
information about the card. This data section is
required on all cards. Table 14 shows the Identification
Data for AMD’s 3 volt-only Miniature cards.
The compatibility data provides basic compatibility
across all cards. This data section is required on all
cards. The addresses in parentheses are specified for
cards with more than one memory technology on the
card. Table 15 shows the compatibility data for AMD
3-volt only Miniature Cards
Table 14.
AMD Identification Data
Card Address
Value
Description
10h
99h
Miniature Card Identifier: Fixed value for a host to identify an inserted
Miniature Card
11h
11h
Level of Compliance: Defines the level of AIS supported. The
Miniature Cards described in this document are rev 1.1 compliant.
12h
78h or 76h
AIS Checksum: The modulo-256 sum of all even bytes from 10h–FFh.
A valid checksum sums to 00H (2’s complement).
9
2 Mbyte card: 88h + 78h = 00h
4 Mbyte card: 8Ah + 76h = 00h
32
13h
41h
Manufacturer Name: 13h–26h. String of ASCII characters at
addresses 13H to 26H to identify the manufacturer of the Miniature
Card.
ASCII character “A”
14h
4Dh
ASCII character “M”
15h
44h
ASCII character “D”
16h
20h
ASCII character - SPACE
17h
49h
ASCII character - “I”
18h
4Eh
ASCII character - “N”
19h
43h
ASCII character - “C”
1Ah
00h
ASCII character - NULL
1Bh
00h
ASCII character - NULL
1Ch–26h
00h
Unused space in manufacturer name field
27h
33h
Card Name: (addresses 27h–3Ah). String of ASCII characters to
identify the card name.
ASCII character “3”
28h
56h
ASCII character “V”
29h
4Dh
ASCII character “M”
2Ah
43h
ASCII character “C”
2Bh
20h
ASCII character - SPACE
2Ch
53h
ASCII character “S”
2Dh
65h
ASCII character “e”
2Eh
72h
ASCII character “r”
2Fh
69h
ASCII character “i”
30h
65h
ASCII character “e”
AmMCL00XA
PRELIMINARY
Table 14.
AMD Identification Data (Continued)
Card Address
Value
Description
31h
73h
ASCII character “s”
32h
00h
ASCII character - NULL
33h–3Ah
00h
Unused space in card name field
3Bh
01h
Technology Count: Defines the number of different memory
technologies on the Miniature Card.
Technology count set to 1
3Ch–3Fh
00h
Reserved space set to 00h; for future use
.
Table 15. AMD Compatibility Data
Card Address
Value
Description
40h
00h
Defines the type of memory technology; Flash = 000 Binary
41h
01h
Device JEDEC Manufacturer ID
42h
38h
Device JEDEC Component ID: Am29LV081 = 38h
43h
01h or 03h
44h
00h
N/A
45h
0Fh
3.3V access time: 150 ns
46h
00h
N/A
47h
00h
N/A
48h
24h
Typical read/write current at 3.3V: 20 mA read, 40 mA write (word mode)
49h
00h
N/A
4Ah
00h
Typical card standby current: 10 µA for 2 Mbyte, 40 µA for 4 Mbyte
4Bh–4Fh, 8Ch–8Fh,
CCh–CFh, ECh–EFh
00h
Reserved for future use
80h–8Bh, C0–CBh,
E0h–EBh
00h
These addresses are designated for other memory technologies, which
are not used in AMD Flash Miniature Cards.
100h
18h
TPL_CODE CISTPL_JEDEC_C
101h
02h
TPL_LINK
102h
01h
Manufacturer ID
103h
38h
Device ID
104h
1Eh
TPL_CODE CISTPL_DEVICEGEO
105h
06h
TPL_LINK
106h
02h
DGTPL_BUS: Bus Width
107h
01h
DGTPL_EBS:11h = 64K Byte Erase Block size
108h
01h
DGTPL_RBS: Read Byte Size
109h
01h
DGTPL_WBS: Write Byte Size
10Ah
01h
DGTPL_PART: Number of partition
10Bh
01h
FL DEVICE INTERLEAVE: No interleave.
Memory array size: 02 = 2 Mbyte, 04 = 4 Mbyte
Note: All reserved bytes must be set to 00h. All reserved fields (bits) within bytes must be set to 0Bh. All unused fields must be
set to 00h.
AmMCL00XA
33
PRELIMINARY
PHYSICAL DIMENSIONS
Top View
33.00 mm
1.299 in.
.118 in.
3.212 mm
.118 in.
3.00 mm
.217 in.
5.50 mm
.118 in.
3.00 mm
center line
.284 in.
7.21 mm
.161 in.
.189 in. 4.09 mm
4.81 mm
38.00 mm
1.496 in.
.217 in.
5.50 mm
.118 in.
3.00 mm
34
AmMCL00XA
PRELIMINARY
PHYSICAL DIMENSIONS
Bottom View
0.600
0.245
Write Protect Switch Location
Right Side View
0.245
Write Protect Switch Location
AmMCL00XA
35
PRELIMINARY
REVISION HISTORY FOR AMMCL00XA
Distinctive Characteristics
Added industrial temperature bullet. Revised low
power consumption specifications. Deleted “Small
Form Factor” bullets.
General Description
Revised text to indicate that the Miniature Card specification will be defined by PCMCIA. Deleted references
to the elastomeric connector.
Table 2, AMD Flash Miniature Cards and Flash
Devices
Added WP as part of required base part number.
commands, moved RA, RW, RD, PA, PW, PD, X, SA
definitions to legend. Moved Erase Suspend and Erase
Resume definitions from table to notes.
Operating Ranges
Added industrial temperature range.
AC Characteristics, Write Operations
Deleted tELQV, tAVQV, tGLQV, tELQX, tEHQZ, tGLQX, tGHQZ,
tAXQX, tWHGL, tGLQNZ
Embedded Erase Algorithm
Removed last paragraph.
Miniature Card Pad Assignments
BUSY#: Revised to indicate that the Miniature Card
cannot accept most operations when BUSY# is low.
CD#: Deleted last sentence.
Absolute Maximum Ratings
Revised storage and ambient temperature ratings.
Operating Ranges
Added industrial temperature range.
Ordering Information
Added Industrial temperature range. Deleted NP option
from part number. Added WP as part of required base
part number.
DC Characteristics
Revised ICC specifications. Added frequency specification to Note 2.
Figure 2, Host/Card Address Assignments
Labeled host bus in drawing. Deleted NC callouts in
drawing.
AC Characteristics, Write (Erase/Program)
Operations
Deleted tELQV, tAVQV, tGLQV, tELQX, tEHOZ, tGLOX, tGHQZ,
tAXQX, tWHGL, tGLQNZ.
Tables 5–9, Command Definitions
Revised for easier reference: removed “H” designators
from table (now indicated in notes), removed 4-cycle
Reset/Read command, separated Read and Reset
Table 19, AMD Compatibility Data
Added two tuples of data to list, covering addresses
100h–10Bh.
Trademarks
Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
36
AmMCL00XA