Intel AN80196CA Advanced 16-bit chmos microcontroller with integrated can 2.0 Datasheet

87C196CA/87C196CB 20 MHz
ADVANCED 16-BIT CHMOS MICROCONTROLLER
WITH INTEGRATED CAN 2.0
Automotive
Y
High Performance CHMOS 16-Bit CPU
(up to 20 MHz Operation)
Y
Full Duplex Synchronous Serial I/O
Port (SSIO)
Y
Register-Register Architecture
Y
Y
Up to 56 Kbytes of On-Chip EPROM
Interprocessor Communication Slave
Port
Up to 1.5 Kbyte of On-Chip Register
RAM
Y
Y
Selectable Bus Timing Modes for
Flexible Interfacing
Up to 512 Bytes of Additional RAM
(Code RAM)
Y
Y
Oscillator Fail Detection Circuitry
Y
High Speed Peripheral Transaction
Server (PTS)
Y
Up to 16 Mbyte Linear Address Space
Supports CAN (Controller Area
Network) Specification 2.0
Y
Y
Two Dedicated 16-Bit High-Speed
Compare Registers
15 Message Objects of 8 Bytes Data
Length
Y
Y
High Speed Capture/Compare (EPA)
Y
Two Flexible 16-Bit Timer Counters
Y
10-Bit A/D with Sample/Hold
Y
Y
38 Prioritized Interrupts
Flexible 8-/16-Bit External Bus
(Programmable)
Up to Seven 8-Bit (60) I/O Ports
Y
Y
Programmable Bus (HLD/HLDA)
Full Duplex Serial Port (SIO) with
Dedicated Baudrate Generator
Y
Y
1.4 ms 16 x 16 Multiply
Y
2.4 ms 32/16 Divide
b 40§ C to a 125§ C Ambient
Address
Space
Device
Pins/Package
EPROM
Reg RAM
Code RAM
I/O
EPA
SIO
SSIO
CAN
A/D
87C196CB
84-Pin PLCC
56K
1.5K
512b
56
10
Y
Y
Y
8
1 Mbyte
87C196CB
100-Pin QFP
56K
1.5K
512b
60
10
Y
Y
Y
8
16 Mbyte
87C196CA
68-Pin PLCC
32K
1.0K
256b
38
6
Y
Y
Y
6
64 Kbyte
The 87C196CA/CB are new members of the MCSÉ 96 microcontroller family. These devices are based upon
the MCS 96 Kx/Jx microcontroller product families with enhancements ideal for automotive and industrial
applications. The CA/CB are the first devices in the Kx family to support networking through the integration of
the CAN 2.0 (Controller Area Network) peripheral on-chip. The 87C196CB offers the highests memory density
of the MCS 96 microcontroller family, with 56K of on-chip EPROM, 1.5K of on-chip register RAM, and 512
bytes of additional RAM (Code RAM). In addition, the 87C196CB provides up to 16 Mbyte of Linear Address
Space. The 87C196CA is a sub-set of the CB, offering 32K of on-chip EPROM, up to 1.0K of on-chip register
RAM, and 256 bytes of additional RAM (Code RAM).
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1996
April 1996
Order Number: 272405-004
87C196CA/87C196CB
The MCS 96 microcontroller family members are all high-performance microcontrollers with a 16-bit CPU. The
87C196CB is composed of the high-speed (20 MHz) macrocore with up to 16 Mbyte linear address space, 56
Kbytes of program EPROM, up to 1.5 Kbytes of register RAM, and up to 512 bytes of code RAM (16-bit
addressing modes) with the ability to execute from this RAM space. It supports the high-speed, serial communications protocol CAN 2.0, with 15 message objects of 8 bytes data length, an 8-channel, 10-bit / 3 LSB
analog to digital converter with programmable S/H times, and conversion times k 20 ms at 20 MHz. It has an
asynchronous/synchronous serial I/O port (SIO) with a dedicated 16-bit baud rate generator, an additional
synchronous serial I/O port (SSIO) with full duplex master/slave transceivers, a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities. There are ten modularized, multiplexed, highspeed I/O for capture and compare (called Event Processor Array) with 200 ns resolution and double buffered
inputs, and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server
(PTS) implementing several channel modes, including single/burst block transfers from any memory location
to any memory location, a PWM and PWM toggle mode to be used in conjunction with the EPA , and an A/D
scan mode.
NOTICE:
This is an advance information data sheet. The A.C. and D.C. parameters contained within this data
sheet may change after full automotive temperature characterization of the device has been performed. Contact your local sales office before finalizing the timing and D.C. characteristics of a design
to verify you have the latest information.
272405 – 30
Figure 1. 8XC196CB Block Diagram
2
87C196CA/87C196CB
PROCESS INFORMATION
These devices are manufactured on P629.5, a
CHMOS III-E process. Additional process and reliability information is available in Intel’s Components
Quality and Reliability Handbook , Order Number
210997.
All thermal impedance data is approximate for static
air conditions at 1.0W of power dissipation. Values
will change depending on operation conditions and
application. See the Intel Packaging Handbook (order number 240800) for a description of Intel’s thermal impedance test methodology.
272405 – 2
Figure 2. The 87C196CA/CB Familiy Nomenclature
Thermal Characteristics
Device and Package
iJA
iJC
AN87C196CB
(84-Lead PLCC Package)
35.0§ C/W
11.0§ C/W
AN87C196CA
(68-Lead PLCC Package)
36.5§ C/W
10.0§ C/W
NOTES:
1. iJA e Thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft.
away from case in air flow environment.
iJC e Thermal resistance between junction and package face (case).
2. All values of iJA and iJC may fluctuate depending on the environment (with or without airflow, and how much airflow)
and device power dissipation at temperature of operation. Typical variations are g 2§ C/W.
3. Values listed are at a maximum power dissipation of 1.0W.
3
87C196CA/87C196CB
272405 – 14
Figure 3. 84-Pin PLCC AN87C196CB Diagram
4
87C196CA/87C196CB
272405 – 33
Figure 4. 100-Pin QFP AS87C196CB Diagram
5
87C196CA/87C196CB
272405 – 3
Figure 5. 68-Pin PLCC 87C196CA Diagram
6
87C196CA/87C196CB
Symbol
Name and Function
VCC
Main Supply Voltage ( a 5V).
VSS,VSS1
Digital circuit ground (0V). There are 7 VSS pins CB (4 on CA), all of which MUST be
connected to a single ground plane.
VREF
Reference for the A/D converter ( a 5V). VREF is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for
A/D and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential
as VSS.
VPP
Programming voltage for EPROM parts. It should be a 12.5V for programming. It is
also the timing pin for the return from powerdown circuit. Connect this pin with a 1 mF
capacitor to VSS and a 1Mohm resistor to VCC. If this function is not used, VPP may be
tied to VCC.
XTAL1
Input of the oscillator inverter and the internal clock generator.
XTAL2
Output of the Oscillator Inverter.
RESETÝ
Reset input to the chip. Input low for at least 16 state times will reset the chip. The
subsequent low to high transition resynchronizes CLKOUT and commences a
10-state time sequence in which the PSW is cleared, bytes are read from 2018H,
201Ah and 201CH (if enabled) loading the CCB’s, and a jump to location 2080H is
executed. Input high for normal operation. RESETÝ has an internal pullup.
NMI
A positive transition causes a non-maskable interrupt vector through memory location
203EH. If not used, this pin should be tied to VSS. May be used by Intel Evaluation
boards.
EAÝ
Input for memory select (External Access). EAÝ equal to a high causes memory
accesses to locations 0FF2000H through 0FFFFFFH to be directed to on-chip
EPROM/ROM. EAÝ equal to a low causes accesses to these locations to be directed
to off-chip memory. EAÝ e a 12.5V causes execution to begin in the Programming
Mode. EAÝ is latched at reset.
PLLEN
(196CB only)
Selects between PLL mode or PLL bypass mode. This pin must be either tied high or
low. PLLEN pin e 0, bypass PLL mode. PLLEN pin e 1, places a 4x PLL at the input
of the crystal oscillator. Allows for a low frequency crystal to drive the device (i.e.,
5 MHz e 20 MHz operation).
P6.4–6.7/SSIO
Dual function I/O ports have a system function as Synchronous Serial I/O. Two pins
are clocks and two pins are data providing for full duplex capability. Also LSIO when
not used as SSIO.
P6.3/T1DIR
(CB only)
Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it
may also be used as a TIMER1 Direction input. The TIMER1 will increment when this
pin is high and decrements when this pin is low.
P6.2/T1CLK
(CB only)
Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however may
also be used as a TIMER1 Clock input. The TIMER1 will increment or decrement on
both positive and negative edges of this pin.
P6.0–6.1/EPA8–9
Dual function I/O port pins. Primary function is that of bidirectional I/O. System
function is that of High Speed capture and compare.
7
87C196CA/87C196CB
Symbol
Name and Function
P5.7/BUSWIDTH
(CB only)
Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin
dynamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low,
an 8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is ‘‘0’’
and CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is
‘‘0’’, all bus cycles are 16-bit. CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal. Also
an LSIO pin when not used as BUSWIDTH.
P5.6/READY
Ready input to lengthen external memory cycles, for interfacing with slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller
goes into a wait state mode until the next opositive transition in CLKOUT occurs with
READY high. When external memory is not used, READY has no effect. The max
number of wait states inserted into the bus cycle is controlled by the CCR/CCR1.
Also an LSIO if READY is not selected.
P5.5/BHEÝ/WRHÝ
Byte High Enable or Write High output, as selected by the CCR. BHEÝ e 0 selects
the bank of memory that is connected to the high byte of the data bus. A0 e 0
selects the bank of memory that is connected to the low byte. Thus accesses to a
16-bit wide memory can be to the low byte only (A0 e 0, BHEÝ e 1), to the high
byte only (A0 e 1, BHEÝ e 0) or both bytes (A0 e 0, BHEÝ e 0). If the WRHÝ
function is selected, the pin will go low if the bus cycle is writing to an odd memory
location. BHEÝ/WRHÝ is only valid during 16-bit external. Also an LSIO pin when
not BHE/WRHÝ.
P5.4/SLPINT
Dual function I/O pin. As a bidirectional port pin or as a system function. The system
function is a Slave Port Interrupt Output Pin (on CA, bidirectional port pin only).
P5.3/RDÝ
Read signal output to external memory. RDÝ is active only during external memory
reads or LSIO when not used as RDÝ.
P5.2/WRÝ/WRLÝ
Write and Write Low output to external memory, as selected by the CCR, WRÝ will
go low for every external write, while WRLÝ will go low only for external writes where
an even byte is being written. WRÝ/WRLÝ is active during external memory writes.
Also an LSIO pin when not used as WRÝ/WRLÝ.
P5.1/INST
(CB only)
Output high during an external memory read indicates the read is an instruction
fetch. INST is valid throughout the bus cycle. INST is active only during external
memory fetches, during internal EPROM fetches INST is held low. Also LSIO when
not INST.
P5.0/ALE/ADVÝ
Address Latch Enable or Address Valid Output, as selected by CCR. Both pin
options provide a latch to demultiplex the address from the address/data bus. When
the pin is ADVÝ, it goes inactive (high) at the end of the bus cycle. ADVÝ can be
used as a chip select for external memory. ALE/ADVÝ is active only during external
memory accesses. Also LSIO when not used as ALE.
8
87C196CA/87C196CB
Symbol
Name and Function
PORT 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
P2.7/CLKOUT
Output of the internal clock generator. The frequency is the oscillator frequency.
CLKOUT has a 50% duty cycle. Also LSIO pin when not used as CLKOUT.
P2.6/HLDAÝ
Bus Hold Acknowledge. Active-low output indicates that the bus controller has
relinquished control of the bus. Occurs in response to an external device asserting the
HLDÝ signal. Also LSIO when not used as HLDAÝ.
P2.5/HLDÝ
(CB only)
Bus Hold. Active-low signal indictes that an external device is requesting control of the
bus. Also LSIO when not used as HLDÝ.
P2.4/INTOUTÝ
Interrupt Output. This active-low output indicates that a pending interrupt requires use
of the external bus. Also LSIO when not used as INTOUTÝ
P2.3/BREQÝ
(CB only)
Bus Request. This active-low output signal is asserted during a HOLD cycle when the
bus controller has a pending external memory cycle. Also LSIO when not used as
BREQÝ
P2.2/EXTINT
A positive transition on this pin causes a maskable interrupt vector through memory
location 203CH. Also LSIO when not used as EXTINT.
P2.1/RXD
Receive data input pin for the Serial I/O port. Also LSIO if not used as RXD.
P2.0/TXD
Transmit data output pin for the Serial I/O port. Also LSIO if not used as TXD.
PORT 1/EPA0–7
Dual function I/O port pins. Primary function is that of bidirectional I/O. System function
is that of High Speed capture and compare. EPA0 and EPA2 have another function of
T2CLK and T2DIR of the TIMER2 timer/counter.
PORT 0/ACH0–7
8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter. These pins are also used as inputs to
EPROM parts to select the Programming Mode.
EPORT
(CB only)
8-bit bidirectional standard and I/O Port. These bits are shared with the extended
address bus, A16–A19 for CB PLCC, A16 – A23 for CB QFP. Pin function is selected on
a per pin basis.
TXCAN
Push-pull output to the CAN bus line.
RXCAN
High impedance input-only from the CAN bus line.
9
87C196CA/87C196CB
87C196CB Memory Map
Address
Description
FFFFFFH
FF2080H
Program Memory - Internal EPROM or External Memory
(Determined by EAÝ Pin)
FF207FH
FF2000H
Special Purpose Memory (Internal EPROM or External Memory)
(Determined by EAÝ Pin)
FF1FFFH
FF0600H
External Memory
FF05FFH
FF0400H
Internal RAM (Identically Mapped into 00400H – 005FFH)
FF03FFH
FF0100H
External Memory
FF00FFH
FF0000H
Reserved for ICE
FEFFFFH
0F0000H
Overlayed Memory (External)ÐAccesses into Memory Ranges 0F0000H to FEFFFFH will
Overlay Page 15 (0FH) for CB QFP packageÐExternal Memory.(5)
0EFFFFH
010000H
900 Kbytes External Memory
00FFFFH
002080H
External Memory or Remapped OTPROM (Program Memory)(1)
00207FH
002000H
External Memory or Remapped OTPROM (Special Purpose Memory)(1, 3)
001FFFH
001FE0H
Memory Mapped Special Function Registers (SFR’s)
001FDFH
001F00H
Internal Peripheral Special Function Registers (SFR’s)(5)
001EFFH
001E00H
Internal CAN Peripheral Memory(5)
001DFFH
001C00H
Internal Register RAM
001BFFH
000600H
External Memory
0005FFH
000400H
Internal RAM (Code RAM)
(Address with Indirect or Indexed Modes)
0003FFH
000100H
Register RAM – Upper Register File (Address with Indirect or Indexed Modes or through
Windows.)(2)
10
87C196CA/87C196CB
87C196CB Memory Map (Continued)
Address
Description
0000FFH
000018H
Register RAM – Lower Register File. (Address with Direct, Indirect, or Indexed Modes.)(2)
000017H
000000H
CPU SFR’s(4)
NOTES:
1. These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EAÝ e 5V. Otherwise they are external
memory.
2. Code executed in locations 0000H to 003FFH will be forced external.
3. Reserved memory locations must contain 0FFH unless noted.
4. Reserved SFR bit locations must be written with 0.
5. Refer to 8XC196CB User’s Guide for SFR, CAN and Paging Descriptions.
87C196CA Memory Map
Address
Description
00FFFFH
00A000H
External Memory
009FFFH
002080H
Internal EPROM (32 Kbytes)
00207FH
002000H
Reserved Memory (Internal EPROM or External Memory)
(Determined by EAÝ Pin)
001FFFH
001FE0H
Memory Mapped Special Function Registers (SFR’s)
001FDFH
001F00H
Internal Special Function Registers (SFR’s)(1)
001EFFH
001E00H
Internal CAN Peripheral Memory
001DFFH
000500H
External Memory
0004FFH
000400H
Internal RAM (Code RAM)
(Address with Indirect or Indexed Modes)
0003FFH
000100H
Internal Register RAM – Upper Register File (Address with Indirect or Indexed Modes or
through Windows)(2)
0000FFH
000018H
Internal Register RAM – Lower Register File (Address with Direct, Indirect, or Indexed
Modes(2).
000017H
000000H
CPU Special Function Registers (SFR’s)(2, 4)
NOTES:
1. Refer to 8XC196KX Family User’s Guide for SFR Description.
2. Code executed in locations 0000H to 03FFH will be forced external.
3. Reserved SFR bit locations must be written with 0.
11
87C196CA/87C196CB
(2018h : Byte)
CCB
CCB1 (201Ah : Byte)
0
PD
e
‘‘1’’ Enables Powerdown
0
CCR2
e
‘‘1’’ fetch CCB2 (‘‘0’’ for CA)
1
BW0
e
See Table
1
IRC2
e
See Table
2
WR
e
‘‘1’’ e WRÝ/BHEБ‘0’’ e WRLÝ/WRHÝ
2
BW1
e
See Table
3
ALE
e
‘‘1’’ e ALEБ‘0’’ e ADVÝ
3
WDE
e
‘‘0’’ e Always Enabled
4
IRC0
e
See Table
4
1
e
Reserved Must Be ‘‘1’’
5
IRC1
e
See Table
5
0
e
Reserved Must Be ‘‘0’’
6
LOC0
e
See Table
6
MEMSEL0
e
See Table (‘‘1’’ for CA)
7
LOC1
e
See Table
7
MEMSEL1
e
See Table (‘‘1’’ for CA)
CCB2 (201Ch : Byte) (CB Only)
0
0
e
Reserved Must be ‘‘0’’
1
MODE16
e
Select 16-Bit or 24-Bit Mode
2
REMAP
e
( ‘‘1’’ÐSelect Both Segment 0FFH and Segment 00H
3
1
e
Reserved Must be ‘‘1’’
4
1
e
Reserved Must be ‘‘1’’
5
1
e
Reserved Must be ‘‘1’’
6
1
e
Reserved Must be ‘‘1’’
7
1
e
Reserved Must be ‘‘1’’
‘‘0’’ÐSelect EPROM/CODERAM in Segment 0FFH only
LOC1
LOC0
Function
IRC2
IRC1
IRC0
Max Wait States
0
0
1
1
0
1
0
1
Read and Write Protected
Write Protected Only
Read Protected Only
No Protection
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
Zero Wait States
1 Wait State
2 Wait States
3 Wait States
INFINITE
MSEL1 MSEL0
0
0
1
1
Mode 0
(1-Wait KR):
0
1
0
1
‘‘CB’’ Bus Timing Mode
Mode 0 (1-Wait KR)
Reserved Must Not Be Used
Reserved Must Not Be Used
Mode 3 (KR)
Designed to be similar to the 87C196KR bus
timing with 1 automatic wait state.
See AC Timings section for actual timings data.
Mode 3 (KR): Designed to be similar to the 87C196KR bus
timing.
See AC Timings section for actual timings data.
12
BW1
BW0
Bus Width
0
0
1
1
0
1
0
1
ILLEGAL
16-Bit Only
8-Bit Only
BW Pin Controlled
87C196CA/87C196CB
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 60§ C to a 150§ C
Voltage from VPP or EA to
VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5V to a 13.0V
Voltage from Any Other Pin
to VSS or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 0.5 to a 7.0V
This includes VPP on ROM and CPU devices .
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.0W
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
OPERATING CONDITIONS
Parameter
Min
Max
Units
TA
Symbol
Ambient Temperature Under Bias
b 40
a 125
§C
VCC
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V
FOSC
Oscillator Frequency
4
20
MHz(4)
NOTE:
ANGND and VSS should be nominally at the same potential.
DC CHARACTERISTICS
Symbol
ICC
(Under Listed Operating Conditions)
Parameter
Test Conditions
Min
Typ
VCC Supply Current
XTAL1 e 20 MHz,
( b 40§ C to a 125§ C Ambient)
VCC e VPP e VREF e 5.5V
CA (While device in Reset)
CB
IREF
A/D Reference Supply Current
IIDLE
Idle Mode Current
XTAL1 e 20 MHz,
CA VCC e VPP e VREF e 5.5V
CB
Max
Units
90
100
mA
mA
5
mA
40
35
mA
mA
IPD
Powerdown Mode Current
VCC e VPP e VREF e 5.5V(6, 9)
TBD
mA
VIL
Input Low Voltage (all pins)
For PORT0(8)
b 0.5V
0.3 VCC
V
VIH
Input High Voltage
For PORT0(8)
0.7 VCC
VCC a 0.5
V
VOL
Output Low Voltage
(Outputs Configured as
Complementary)
IOL e 200 mA(3,5)
IOL e 3.2 mA
IOL e 7.0 mA
0.3
0.45
1.5
V
V
V
VOH
Output High Voltage
(Outputs Configured as
Complementary)
IOH e b 200mA(3,5)
IOH e b 3.2 mA
IOH e b 7.0 mA
50
VCC b 0.3
VCC b 0.7
VCC b 1.5
V
V
V
13
87C196CA/87C196CB
87C196CB ICC vs Frequency
272405 – 31
87C196CA ICC vs Frequency
272405 – 32
14
87C196CA/87C196CB
DC CHARACTERISTICS
Symbol
(Under Listed Operating Conditions) (Continued)
Parameter
Test Conditions
Min
Typ
Max
Units
ILI
Input Leakage Current (Std. Inputs)
VSS k VIN k VCC
g 10
mA
ILI1
Input Leakage Current (Port 0)
VSS k VIN k VREF
CA g 1.5
CB g 1.0
mA
VOH1
SLPINT (P5.4) and HLDA (P2.6)
Output High Voltage in RESET
IOH e 0.8 mA(7)
2.0
V
VOH2
Output High Voltage in RESET
IOH e b 15 mA(1)
VCC b 1V
V
CS
Pin Capacitance (Any pin to VSS)
ftest e 1.0 MHz(6)
RWPU
Weak Pullup Resistance
(Note 6)
RRST
Reset Pullup Resistor
For CB
65K
180K
X
RRST
Reset Pullup Resistor CA
For CA
6K
65K
X
10
150K
pF
X
NOTES:
1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly
pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SPLINT (P5.4) and HLDA (P2.6).
2. Standard input pins include XTAL1, EA, RESET, and Port 1/2/5/6 when setup as inputs.
3. All bidirectional I/O pins when configured as Outputs (Push/Pull).
4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz.
5. Maximum IOL/IOH currents per pin will be characterized and published at a later date.
6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
VREF e VCC e 5.0V.
7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6).
8. When P0 is used as analog inputs, refer to A/D specifications for this characteristic.
9. For temperatures k100§ C typical is 10 mA.
8XC196CB ADDITIONAL BUS TIMING MODES
The 8XC196CB device has 2 bus timing modes for
external memory interfacing.
MODE 3:
MODE 0:
Mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus
cycles.
Mode 3 is the standard timing mode. Use this mode
for systems that emulate the 8XC196KR bus timings.
15
87C196CA/87C196CB
AC CHARACTERISTICS
(Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
The 87C196CA/CB will meet these specifications
Symbol
Parameter
Min
Max
Units
4.0
20
MHz(1)
XTAL1 Period (1/FXTAL)
50.0
250
ns
XTAL1 High to CLKOUT High or Low
a 20
110
ns
TOFD
Clock Failure to Reset Pulled Low(6)
4
40
ms
TCLCL
CLKOUT Period
FXTAL
Frequency on XTAL1
TOSC
TXHCH
2 TOSC
ns
TOSC b 10
TOSC a 15
TCHCL
CLKOUT High Period
TCLLH
CLKOUT Low to ALE/ADV High
b 15
ns
a 10
ns
TLLCH
ALE/ADV Low to CLKOUT High
b 20
TLHLH
ALE/ADV Cycle Time
TLHLL
ALE/ADV High Time
TOSC b 10
TAVLL
Address Valid to ALE Low
TOSC b 15
ns
TLLAX
Address Hold After ALE/ADV Low
TOSC b 40
ns
TLLRL
ALE/ADV Low to RD Low
TOSC b 30
ns
TRLCL
RD Low to CLKOUT Low
a 15
CA
CB
a4
b8
TRLRH
RD Low Period
TRHLH
RD High to ALE/ADV High
TRLAZ
RD Low to Address Float
TLLWL
ALE/ADV Low to WR Low
TCLWL
CLKOUT Low to WR Low
TQVWH
Data Valid before WR High
TOSC b 23
TCHWH
CLKOUT High to WR High
b 10
TWLWH
WR Low Period
TOSC a 10
ns
ns
TOSC a 25
ns(3)
ns(5)
5
TOSC b 10
b5
CB
CA
ns
a 30
a 20
TOSC b 10
TOSC
ns
ns(5)
4 TOSC
ns
ns
a 25
ns
ns
a 15
ns
ns(5)
TOSC b 30
TOSC b 20
TWHQX
Data Hold after WR High
TOSC b 25
TWHLH
WR High to ALE/ADV High
TOSC b 10
ns
TWHBX
BHE, INST Hold after WR High
TOSC b 10
ns
TWHAX
AD8–15 Hold after WR High
TOSC b 30
ns(4)
TRHBX
BHE, INST Hold after RD High
TOSC b 10
ns
TRHAX
AD8–15 Hold after RD High
TOSC b 30
ns(4)
TOSC a 15
ns(3)
NOTES:
1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2 Tosc c n, where n e number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2 TOSC to specification.
6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H. Programming the CDE bit enables oscillator fail detection.
16
87C196CA/87C196CB
AC CHARACTERISTICS
(Over Specified Operating Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise anf Fall Times e 10 ns.
The system must meet these specifications to work with the 87C196CA/CB.
Symbol
Parameter
Min
TAVYV
Address Valid to Ready Setup
TLLYV
ALE Low to READY Setup
TYLYH
Non READY Time
TCLYX
READY Hold after CLKOUT Low
TAVGV
Address Valid to BUSWIDTH Setup
TLLGV
ALE Low to BUSWIDTH Setup
TCLGX
BUSWIDTH Hold after CLKOUT Low
TAVDV
Address Valid to Input Data Valid
TRLDV
RD active to input Data Valid
CLKOUT Low to Input Data Valid
TRHDZ
End of RD to Input Data Float
TRHDX
Data Hold after RD High
Units
2 TOSC b 75
ns(3)
TOSC b 70
ns(3)
No Upper Limit
0
0
ns
TOSC b 30
ns(1)
2 TOSC b 75
ns(2, 3)
TOSC b 60
ns(2, 3)
3 TOSC b 55
ns(2)
TOSC b 22
TOSC b 30
ns(2)
ns(2)
TOSC b 50
ns
TOSC
ns
0
CA
CB
TCLDV
Max
ns
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 Tosc c n, where n e number of wait states.
3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 Tosc to the
specification.
17
87C196CA/87C196CB
87C196CA/CB SYSTEM BUS TIMING
272405 – 17
* If mode 0 operation is selected, add 2 Tosc to this time.
18
87C196CA/87C196CB
87C196CA/CB READY TIMINGS (ONE WAIT STATE)
272405 – 18
*If mode 0 selected (CB only), one wait state is always added. If additional wait states are required, add 2 Tosc to these
specifications.
87C196CB BUSWIDTH TIMINGS
272405 – 19
*If mode 0 selected (CB only), add 2 Tosc to these specifications.
19
87C196CA/87C196CB
8XC196CB HOLD/HOLDA TIMINGS
(Over Specified Operation Conditions)
Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns.
Symbol
Parameter
Min
Max
Units
ns(1)
THVCH
HOLD Setup Time
a 65
TCLHAL
CLKOUT Low to HLDA Low
b 15
a 15
ns
TCLBRL
CLKOUT Low to BREQ Low
b 15
a 15
ns
TAZHAL
HLDA Low to Address Float
a 20
ns
TBZHAL
HLDA Low to BHE, INST, RD, WR Weakly Driven
a 25
ns
TCLHAH
CLKOUT Low to HLDA High
b 15
a 15
ns
TCLBRH
CLKOUT Low to BREQ High
b 25
a 25
ns
THAHAX
HLDA High to Address No Longer Float
b 15
THAHBV
HLDA High to BHE, INST, RD, WR Valid
b 10
ns
a 15
ns
NOTE:
1. To guarantee recognition at next clock.
8XC196CB HOLD/HOLDA TIMINGS
272405 – 20
20
87C196CA/87C196CB
8XC196CB AC CHARACTERISTICSÐSLAVE PORT
SLAVE PORT WAVEFORMÐ(SLPL e 0)
272405 – 21
SLAVE PORT TIMINGÐ(SLPL e 0, 1, 2, 3)
Symbol
Parameter
Min
Max
Units
TSAVWL
Address Valid to WR Low
50
ns
TSRHAV
RD High to Address Valid
60
ns
TSRLRH
RD Low Period
TOSC
ns
TSWLWH
WR Low Period
TOSC
TSRLDV
RD Low to Output Data Valid
TSDVWH
Input Data Setup to WR High
20
ns
TSWHQX
WR High to Data Invalid
30
ns
TSRHDZ
RD High to Data Float
15
ns
ns
60
ns
NOTES:
1. Test Conditions: FOSC e 20 MHz, TOSC e 60 ns. Rise/Fall Time e 10 ns. Capacitive Pin Load e 100 pF.
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.
3. Specifications above are advanced information and are subject to change.
21
87C196CA/87C196CB
AC CHARACTERISTICSÐSLAVE PORT (Continued)
SLAVE PORT WAVEFORMÐ(SLPL e 1)
272405 – 22
SLAVE PORT TIMINGÐ(SLPL e 1, 2, 3)
Parameter
Min
TSELLL
Symbol
CS Low to ALE Low
20
Max
Units
ns
TSRHEH
RD or WR High to CS High
60
ns
TSLLRL
ALE Low to RD Low
TOSC
ns
TSRLRH
RD Low Period
TOSC
ns
TSWLWH
WR Low Period
TOSC
ns
TSAVLL
Address Valid to ALE Low
20
ns
TSLLAX
ALE Low to Address Invalid
20
ns
TSRLDV
RD Low to Output Data Valid
TSDVWH
Input Data Setup to WRHigh
20
ns
TSWHQX
WR High to Data Invalid
30
ns
TSRHDZ
RD High to Data Float
15
ns
60
NOTES:
1. Test Conditions: FOSC e 20 MHz, TOSC e 60 ns. Rise/Fall Time e 10 ns. Capacitive Pin Load e 100 pF.
2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests.
3. Specifications above are advanced information and are subject to change.
22
ns
87C196CA/87C196CB
t e 1 state time (125 ns
@
16 MHz)
NORMAL MASTER/SLAVE OPERATION
Symbol
Parameter
Min
Max
Units
TCHCH
Clock Period
4t
TCLCH
Clock Low Time/Clock High Time
2t b 10
TCLDV
Clock Falling to Data Out Valid (Master)
0.5t
1.5t a 20
TCLDV1
Clock Falling to Data Out Valid (Slave)
0.5t
1.5t a 50
TDVCH
Data In Setup to Clock Rising Edge
10
ns
t a 15
ns
TCHDX
Clock Rising Edge to Data in Invalid
*Timings are guaranteed by design.
ns
ns(1)
ns
ns
HANDSHAKE OPERATION
Symbol
TCHCH
Parameter
Min
Max
Clock Period
4t
TCLCH
Clock Low Time/Clock High Time
2t b 10
TCLDV
Clock Falling to Data Out Valid (Master)
0.5t
1.5t a 20
1.5t a 50
Units
ns
ns(1)
ns
TCLDV1
Clock Falling to Data Out Valid (Slave)
0.5t
TDVCH
Data In Setup to Clock Rising Edge
10
ns
ns
TCLDX
Clock Rising Edge to Data in Invalid
t a 15
ns
*Timings are guaranteed by design.
NOTE:
1. This specification refers to input clocks during slave operation. During master operation, the device will output a nominal
50% duty cycle clock.
272405 – 34
NOTE:
The top SCx signal assumes that the SSIO is configured to sample on the leading edge with an active-high clock signal.
The SCx signal will be different for other configurations, however, setup and hold timings will still be the same in relation
to the latching edge of SCx.
Figure 6. Synchronous Serial Port
23
87C196CA/87C196CB
EXTERNAL CLOCK DRIVE
Symbol
Parameter
1/TXLXL
Oscillator Frequency
TXLXL
Oscillator Period (TOSC)
TXHXX
TXLXX
TXLXH
TXHXL
Min
Max
Units
4
20
MHz
50.0
250
ns
High Time
0.35 c TOSC
0.65 TOSC
ns
Low Time
0.35 c TOSC
0.65 TOSC
ns
Rise Time
10
ns
Fall Time
10
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
272405 – 23
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272405 – 25
272405 – 24
AC Testing inputs are driven at 3.5V for a logic ‘‘1’’ and
0.45V for a logic ‘‘0’’. Timing measurements are made
at 2.0V for a logic ‘‘1’’ and 0.8V for logic ‘‘0’’.
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’
for time. The characters in a pair indicate a signal
and its condition, respectively. Symbols represent
the time between the two signal/condition points.
24
For timing purposes a Port Pin is no longer floating
when a 150 mV change from load voltage occurs and
begins to float when a 150 mV change from the loading
VOH/VOL level occurs IOL/IOH s 15 mA.
Conditions:
HÐHigh
LÐLow
VÐValid
XÐNo Longer
Valid
ZÐFloating
Signals:
AÐAddress
BÐBHE
BRÐBREQ
CÐCLKOUT
DÐDATA
GÐBuswidth
HÐHOLD
HAÐHLDA
LÐALE/ADV
QÐData Out
RDÐRD
WÐWR/WRH/WRI
XÐXTAL1
YÐREADY
87C196CA/87C196CB
EPROM SPECIFICATIONS
AC EPROM PROGRAMMING CHARACTERISTICS
Operating Conditions: Load Capacitance e 150 pF; TC e 25§ C g 5§ C, VCC, VREF e 5.0V g 0.5V, VSS,
ANGND e 0V.
VPP e 12.5V g 0.25V; EA e 12.5V g 0.25V; Fosc e 5.0 MHz.
Symbol
Parameter
Min
Max
Units
TAVLL
Address Setup Time
0
TOSC
TLLAX
Address Hold Time
100
TOSC
TDVPL
Data Setup Time
0
TOSC
TPLDX
Data Hold Time
400
TOSC
TLLLH
PALE Pulse Width
50
TOSC
TPLPH
PROG Pulse Width(2)
50
100
TOSC
TOSC
CA
CB
TLHPL
PALE High to PROG Low
220
TOSC
TPHLL
PROG High to next PALE Low
220
TOSC
TPHDX
Word Dump Hold Time
TPHPL
PROG High to next PROG Low
220
TOSC
TLHPL
PALE High to PROG Low
220
TOSC
TPLDV
PROG Low to Word Dump Valid
CA
CB
TSHLL
RESET High to First PALE Low
TPHIL
PROG High to AINC Low
TILIH
TILVH
50
50
100
TOSC
TOSC
TOSC
1100
TOSC
0
TOSC
AINC Pulse Width
240
TOSC
PVER Hold after AINC Low
50
TOSC
TILPL
AINC Low to PROG Low
170
TOSC
TPHVL
PROG High to PVER Valid
220
TOSC
NOTES:
1. Run-time programming is done with Fosc e 6.0 MHz to 10.0 MHz, VCC, VPD, VREF e 5V g 0.5V, TC e 25§ C g 5§ C and
VPP e 12.5V g 0.25V. For run-time programming over a full operating range, contact factory.
2. Programming specifications are not tested, but guaranteed by design.
3. This specification is for the word dump mode. For programming pulses use 300 Tosc a 100 ms.
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
IPP
VPP Programming Supply Current
Min
Max
Units
200
mA
NOTE:
VPP must be within 1V of VCC while VCC k 4.5V. VPP must not have a low impedance path to ground or VSS while VCC l
4.5V.
25
87C196CA/87C196CB
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
272405 – 26
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
272405 – 27
26
87C196CA/87C196CB
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
272405 – 28
AC CHARACTERISTICSÐSERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFT REGISTER MODE 0
Test Conditions: TA e b 40§ C to a 125§ C; VCC e 5.0V g 10%; VSS e 0.0V; Load Capacitance e pF
Symbol
TXLXL
Parameter
Serial Port Clock Period
TXLXH
Serial Port Clock Falling Edge to Rising Edge
TQVXH
Output Data Setup to Clock Rising Edge
TXHQX
Output Data Hold after Clock Rising Edge
TXHQV
Next Output Data Valid after Clock Rising Edge
TDVXH
Input Data Setup to Clock Rising Edge
TXHDX(8)
Input Data Hold after Clock Rising Edge
TXHQZ(8)
Last Clock Rising to Output Float
Min
Max
8 TOSC
4 TOSC b 50
Units
ns
4 TOSC a 50
3 TOSC
ns
ns
2 TOSC b 50
ns
2 TOSC a 50
ns
2 TOSC a 200
ns
0
ns
5 TOSC
ns
NOTE:
8. Parameters not tested.
27
87C196CA/87C196CB
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE
272405 – 29
A TO D CHARACTERISTICS
The sample and conversion time of the A/D converter in the 8-bit or 10-bit modes is programmed by
loading a byte into the ADÐTIME Special Function
Register. This allows optimizing the A/D operation
for specific applications. The ADÐTIME register is
functional for all possible values, but the accuracy of
the A/D converter is only guaranteed for the times
specified in the operating conditions table.
The value loaded into ADÐTIME bits 5, 6, 7 determines the sample time, SAMP. The value loaded
into ADÐTIME bits 0, 1, 2, 3 and 4 determines the
bit conversion time, CONV. These bits, as well as
the equation for calculating the total conversion
time, T, are shown in the following table:
7
6
ADÐTIME
5
4
1FAFH:Byte
3
2
1
Sample Time
Bit Conversion Time
(SAMP)
4n a 1 state times
n e 1 to 7
(CONV)
n a 1 state times
n e 2 to 31
Equation: T e (SAMP) a Bx (CONV) a 2.5
T e total conversion time (states)
B e number of bits conversion (8 or 10)
n e programmed register value
28
0
The converter is ratiometric, so absolute accuracy is
dependent on the accuracy and stability of VREF.
VREF must be close to VCC since it supplies both the
resistor ladder and the analog portion of the converter and input port pins. There is also an ADÐTEST
SFR that allows for conversion on ANGND and
VREF as well as adjusting the zero offset. The absolute error listed is without doing any adjustments.
A/D CONVERTER SPECIFICATION
The specifications given assume adherence to the
operating conditions section of this data sheet. Testing is performed with VREF e 5.12V and 20 MHz
operating frequency. After a conversion is started,
the device is placed in IDLE mode until the conversion is complete.
87C196CA/87C196CB
10-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature
b40
a 125
§C
VCC
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V(1)
TSAM
Sample Time
2.0
TCONV
Conversion Time
15
18
ms(2)
FOSC
Oscillator Frequency
4.0
20.0
MHz
ms(2)
NOTES:
1. VREF must be within 0.5V of VCC.
2. The value of ADÐTIME is selected to meet these specifications.
10-BIT MODE A/D CHARACTERISTICS
Parameter
(Using Above Operating Conditions)(6)
Typ*(1)
Resolution
Absolute Error
Min
Max
Units*
1024
10
1024
10
Level
Bits
0
g 3.0
LSBs
Full Scale Error
0.25 g 0.5
LSBs
Zero Offset Error
0.25 g 0.5
LSBs
Non-Linearity
1.0 g 2.0
g 3.0
LSBs
b0.75
a 0.75
LSBs
g 0.1
0
g 1.0
LSBs
Repeatability
g 0.25
0
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.009
0.009
0.009
Differential Non-Linearity
Channel-to-Channel Matching
Off Isolation
LSBs(1)
LSB/C(1)
LSB/C(1)
LSB/C(1)
dB(1,2,3)
b60
Feedthrough
b60
dB(1,2)
VCC Power Supply Rejection
b60
dB(1,2)
Input Resistance
DC Input Leakage
g 1.0
Voltage on Analog Input Pin
Sampling Capacitor
750
1.2K
X(4)
0
g 3.0
mA
ANGND b 0.5
VREF a 0.5
V(5)
3.0
pF
*An ‘‘LSB’’ as used here has a value of approximately 5 mV.
NOTES:
1. These values are expected for most parts at 25§ C, but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer break-before-make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
6. All conversions performed with processor in IDLE mode.
29
87C196CA/87C196CB
8-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
TA
Ambient Temperature
b40
a 125
§C
VCC
Digital Supply Voltage
4.50
5.50
V
VREF
Analog Supply Voltage
4.50
5.50
V(1)
TSAM
Sample Time
2.0
TCONV
Conversion Time
12
15
ms(2)
FOSC
Oscillator Frequency
4.0
20.0
MHz
ms(2)
NOTES:
1. VREF must be within 0.5V of VCC.
2. The value of ADÐTIME is selected to meet these specifications.
8-BIT MODE A/D CHARACTERISTICS
Parameter
(Using Above Operating Conditions)(6)
Typ*(1)
Resolution
Absolute Error
Min
Max
Units*
256
8
256
8
Level
Bits
0
g 1.0
LSBs
Full Scale Error
g 0.5
LSBs
Zero Offset Error
g 0.5
LSBs
Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability
g 0.25
Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity
0.003
0.003
0.003
Off Isolation
0
g 1.0
LSBs
b0.5
a 0.5
LSBs
0
g 1.0
LSBs
LSBs(1)
0
LSB/C(1)
LSB/C(1)
LSB/C(1)
dB(1,2,3)
b60
Feedthrough
b60
dB(1,2)
VCC Power Supply Rejection
b60
dB(1,2)
Input Resistance
DC Input Leakage
g 1.0
Voltage on Analog Input Pin
Sampling Capacitor
750
1.2K
X(4)
0
g 1.5
mA
ANGND b 0.5
VREF a 0.5
V(5)
3.0
*An ‘‘LSB’’ as used here has a value of approximately 20 mV.
NOTES:
1. These values are expected for most parts at 25§ C, but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer break-before-make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted.
6. All conversions performed with processor in IDLE mode.
30
pF
87C196CA/87C196CB
87C196CA DESIGN CONSIDERATIONS
The 87C196CA device is a memory scalar of the
87C196KR device with integrated CAN 2.0. The CA
is designed for strict functional and electrical compatibility to the Kx family as well as integration of onchip networking capability. The 87C196CA has fewer peripheral functions than the 196KR, due in part
to the integration of the CAN peripheral. Following
are the functionality differences between the 196KR
and 196CA devices.
196KR Features Unsupported on the 196CA:
Analog Channels 0 and 1
INST Pin Functionality
SLPINT and SLPCS Pin Support
HLD/HLDA Functionality
External Clocking/Direction of Timer 1
Quadrature Clocking Timer 1
Dynamic Buswidth
EPA Capture Channels 4–7
(1) External Memory. Removal of the Buswidth pin
means the bus cannot dynamically switch from
8- to 16-bit bus mode or vice versa. The programmer must define the bus mode by setting
the associated bits in the CCB.
(2) Auto-Programming Mode. The 87C196CA device will ONLY support the 16-bit zero wait state
bus during auto-programming.
(3) EPA4 through EPA7. Since the CA device is
based on the KR design, these functions are in
the device, however there are no associated
pins. A programmer can use these as compareonly channels or for other functions like software
timer, start an A/D conversion, or reset timers.
(4) Slave Port Support. The Slave port can not be
used on the 196CA due to a function change for
P5.4/SLPINT and P5.1/SLPCS not being bonded-out.
Additionally, these port pins should be setup internally by software as follows:
1. Written to PxREG as ‘‘1’’ or ‘‘0’’.
2. Configured as Push/Pull, PxIO as ‘‘0’’.
3. Configured as LSIO.
This configuration will effectively strap the pin
either high or low. DO NOT Configure as
Open Drain output ‘’1’’, or as an Input pin.
This device is CMOS.
(6) EPA Timer RESET/Write Conflict. If the user
writes to the EPA timer at the same time that the
timer is reset, it is indeterminate which will take
precedence. Users should not write to a timer if
using EPA signals to reset it.
(7) Valid Time Matches. The timer must increment/decrement to the compare value for a
match to occur. A match does not occur if the
timer is loaded with a value equal to an EPA
compare value. Matches also do not occur if a
timer is reset and 0 is the EPA compare value.
(8) Write Cycle during Reset. If RESET occurs during a write cycle, the contents of the external
memory device may be corrupted.
(9) Indirect Shift Instruction. The upper 3 bits of
the byte register holding the shift count are not
masked completely. If the shift count register has
the value 32 c n, where n e 1, 3, 5, or 7, the
operand will be shifted 32 times. This should
have resulted in no shift taking place.
(10) P2.7 (CLKOUT). P2.7 (CLKOUT) does not operate in open drain mode.
(5) Port Functions. Some port pins have been removed. P5.1, P6.2, P6.3, P1.4 through P1.7,
P2.3, P2.5, P0.0 and P0.1. The PxREG, PxSSEL,
and PxIO registers can still be updated and read.
The programmer should not use the corresponding bits associated with the removed port pins to
conditionally branch in software. Treat these bits
as RESERVED.
31
87C196CA/87C196CB
87C196CA ERRATA
Register Bits
This data sheet was published prior to first available
silicon. Consequently, there is no known errata at
this time.
P2ÐPIN.x
(x e 3,5)
1
P2ÐREG.x
(x e 3,5)
1
P2ÐDIR.x
(x e 3,5)
1
P2ÐMODE.x
(x e 3,5)
0
87C196CA DESIGN CONSIDERATIONS
When Read
Writing to these bits will have no effect.
1. PORT0
4. PORT5
On the 87C196CA the analog inputs for P0.0 and
P0.1 have been multiplexed and tied to VREF. Therefore, initiating an analog conversion on ACH0 or
ACH1 will result in a value equal to full scale (3FFh).
On the CA, the digital inputs for these two channels
are tied to ground, therefore, reading P0.0 or P0.1
will result in a digital ‘‘0’’.
On the 87C196CA, P5.1 and P5.7 have been removed from the device and are not available to the
programmer. Corresponding bits in the port registers
have been ‘‘hard-wired’’ to provide the following results when read:
Register Bits
When Read
2. PORT1
P5ÐPIN.x
(x e 1,7)
1
On the 87C196CA, P1.4, P1.5, P1.6 and P1.7 have
been removed from the device and is unavailable to
the programmer. Corresponding bits in the port registers have been ‘‘hard-wired’’ to provide the following results when read:
P5ÐREG.x
(x e 1,7)
1
P5ÐDIR.x
(x e 1,7)
1
P5ÐMODE.x
(x e 1)
0
P5ÐMODE.x
(x e 7)
1
Register Bits
When Read
Writing to these bits will have no effect.
P1ÐPIN.x
(x e 4,5,6,7)
1
5. PORT6
P1ÐREG.x
(x e 4,5,6,7)
1
P1ÐDIR.x
(x e 4,5,6,7)
1
P1ÐMODE.x
(x e 4,5,6,7)
0
On the 87C196CA, P6.2 and P6.3 have been removed from the device and are not available to the
programmer. Corresponding bits in the port registers
have been ‘‘hard-wired’’ to provide the following results when read:
Writing to these bits will have no effect.
3. PORT2
Register Bits
On the 87C196CA, P2.3 and P2.5 have been removed from the device and are not available to the
programmer. Corresponding bits in the port registers
have been ‘‘hard-wired’’ to provide the following results when read.
P6ÐPIN.x
(x e 2,3)
1
P6ÐREG.x
(x e 2,3)
1
P6ÐDIR.x
(x e 2,3)
1
P6ÐMODE.x
(x e 2,3)
0
When Read
Writing to these bits will have no effect.
32
87C196CA/87C196CB
DATA SHEET REVISION HISTORY
This is the -003 revision of the 87C196CA/CB data
sheet. The following differences exist between the
-002 version and the -003 revision.
1. The data sheet has been revised to ADVANCE
from PRELIMINARY, indicaitng the specifications have been verified through electrical tests.
2. The 87C196CB 100-ld QFP package and device
pinout has been added to the data sheet.
3. The 87C196CB 100-ld QFP device supports up
the 16 Mbyte of linear address space.
4. The package thermal characteristics for the
PLCC packages was added to the data sheet,
for the CB iJA e 35.0§ C/W, iJC e 11.0§ C/W.
For the CA, iJA e 36.5§ C/W and iJA e
10.0§ C/W.
5. The AN87C196CB pin package diagram was
corrected to show EAÝ as opposed to EA.
6. The REMAP bit funciton for CCB2 was
corrected. Setting this bit to 0 selects EPROM/
CODERAM in segment 0FFH only. Setting this
bit to 1 selects both segment 0FFH and segment
00H.
7. tRLAZ has been changed to 5 ns from 20 ns.
8. tWLWH for the CA has been changed to tOSC
b 20 from tOSC b 30.
9. tCLGX has been changed to 0 ns min, from tOSC
b 46 max.
10. Timing specifications for the SSIO are now added. These timings are currently guaranteed by
design.
11. Added frequency designation to family nomenclature Figure 2.
This is the -002 revision of the 87C196CA data
sheet. The following difference exist between the
-001 version and the -002 revision.
1. This data sheet now includes the specifications
for the 87C196CB as well as the 87C196CA.
2. ABSOLUTE MAXIMUM RATINGS have been
added.
3. Maximum Frequency has been increased to
20 MHz.
4. Maximum ICC has been increased from 75 mA
to 100 mA for the CB, 90 mA for the CA.
5. Idle Mode current has been increased to 35 mA
from 30 mA for the CB, 40 mA for the CA.
6. Input leakage current for Port 0 (ILI1) was decreased to 1.5 mA from 2.0 mA for the CA.
7. The electrical characteristics for the CAN module were removed. The electrical characteristics
for TXCAN and RXCAN are identical to standard
port pins.
8. tOSC (1/freq) was modified to reflect 20 Mhz timings.
9. tOFD (Oscillator Fail Detect Specification) for
clock failure to RESET pin pulled low, was added
to the data sheet (4 ms min, 40 ms max)
10. tWHQX has been increased to tOSC b 25 ns min
from tOSC b 30 ns min.
11. tRXDX has been replaced by tRHDX. tRLAZ has
been increased to 20 ns max from 5 ns max.
12. IPP programming supply current has been increased to 200 mA from 100 mA.
13. tCONV Conversion time for 10 bit A/D conversions has been decreased to reflect 20 Mhz operation.
14. RRST was added for the 87C196CA (min e 6
kX/max e 65 kX.
15. tCLLHÐmin/max parameters switched to accurately reflect this timing parameter.
16. tRLCLÐSeparate timings for the 87C196CA vs
87C196CB. tRLCL for the CB is min b 8 ns, max
a 20 ns. For the CA, tRLCL min a 4 ns/max
a 30 ns.
17. tRLRH changed to TOSC b 10 ns from TOSC
b 5 ns.
18. tAVGV added for the 87C196CB.
19.
20.
21.
tLLGV added for the 87C196CB.
tCLGX added for the 87C196CB.
tRLDVÐSeparate timings for 87C196CB. tRLDV
max e TOSC b 30 ns. For the 87C196CA,
tRLDV max e TOSC b 22 ns.
22. HOLD/HOLDA
timings
added
for
the
87C196CB.
23. Slave Port Timings added for the 87C196CB.
24. Separate specifications for tPLPH for the
87C196CB, tPLPH, min e 100 TOSC. For the
87C196CA, tPLPH min e 50 TOSC.
25. Separate specificatons for tPLDV for the
87C196CB, tPLDV min e 100 TOSC for the
87C196CA, tPLDV min e 50 TOSC.
26. 8-Bit mode A/D characteristics added.
33