APT51M50J 500V, 51A, 0.075Ω Max N-Channel MOSFET S S Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. A proprietary planar stripe design yields excellent reliability and manufacturability. Low switching loss is achieved with low input capacitance and ultra low Crss "Miller" capacitance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control slew rates during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency. Reliability in flyback, boost, forward, and other circuits is enhanced by the high avalanche energy capability. D G SO 2 T- 27 "UL Recognized" file # E145592 ISOTOP ® D APT51M50J Single die MOSFET G S TYPICAL APPLICATIONS FEATURES • Fast switching with low EMI/RFI • PFC and other boost converter • Low RDS(on) • Buck converter • Ultra low Crss for improved noise immunity • Two switch forward (asymmetrical bridge) • Low gate charge • Single switch forward • Avalanche energy rated • Flyback • RoHS compliant • Inverters Absolute Maximum Ratings Symbol ID Parameter Unit Ratings Continuous Drain Current @ TC = 25°C 51 Continuous Drain Current @ TC = 100°C 32 A IDM Pulsed Drain Current VGS Gate-Source Voltage ±30 V EAS Single Pulse Avalanche Energy 2 1580 mJ IAR Avalanche Current, Repetitive or Non-Repetitive 37 A 1 230 Thermal and Mechanical Characteristics Typ Max Unit W PD Total Power Dissipation @ TC = 25°C 480 RθJC Junction to Case Thermal Resistance 0.26 RθCS Case to Sink Thermal Resistance, Flat, Greased Surface Operating and Storage Junction Temperature Range VIsolation RMS Voltage (50-60hHz Sinusoidal Waveform from Terminals to Mounting Base for 1 Min.) WT Torque Package Weight Terminals and Mounting Screws. Microsemi Website - http://www.microsemi.com -55 150 °C/W °C V 2500 1.03 oz 29.2 g 10 in·lbf 1.1 N·m 2-2007 TJ,TSTG 0.15 Rev A Min Characteristic 050-8083 Symbol Static Characteristics TJ = 25°C unless otherwise specified Symbol Parameter Test Conditions Min VBR(DSS) Drain-Source Breakdown Voltage VGS = 0V, ID = 250µA 500 ∆VBR(DSS)/∆TJ Breakdown Voltage Temperature Coefficient RDS(on) Drain-Source On Resistance VGS(th) Gate-Source Threshold Voltage ∆VGS(th)/∆TJ Zero Gate Voltage Drain Current IGSS Gate-Source Leakage Current Dynamic Characteristics Symbol Forward Transconductance Ciss Input Capacitance Crss Reverse Transfer Capacitance Coss Output Capacitance TJ = 125°C 0.60 0.064 4 -10 0.075 5 25 500 ±100 Min f = 1MHz Co(er) 5 Effective Output Capacitance, Energy Related Typ Max 55 11600 160 1250 VGS = 0V, VDS = 25V Effective Output Capacitance, Charge Related Unit V V/°C Ω V mV/°C µA nA Unit S pF 725 VGS = 0V, VDS = 0V to 333V Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge td(on) Turn-On Delay Time tf VGS = 0V Test Conditions VDS = 50V, ID = 37A 4 td(off) TJ = 25°C Max TJ = 25°C unless otherwise specified Co(cr) tr VDS = 500V Typ VGS = ±30V Parameter gfs 3 VGS = VDS, ID = 2.5mA Threshold Voltage Temperature Coefficient IDSS Reference to 25°C, ID = 250µA VGS = 10V, ID = 37A 3 APT51M50J Current Rise Time Turn-Off Delay Time 365 290 65 130 45 55 120 39 VGS = 0 to 10V, ID = 37A, VDS = 250V Resistive Switching VDD = 333V, ID = 37A RG = 2.2Ω 6 , VGG = 15V Current Fall Time nC ns Source-Drain Diode Characteristics Symbol IS ISM Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Test Conditions MOSFET symbol showing the integral reverse p-n junction diode (body diode) Diode Forward Voltage ISD = 37A, TJ = 25°C, VGS = 0V trr Reverse Recovery Time ISD = 37A 3 Qrr Reverse Recovery Charge Peak Recovery dv/dt Typ Max Unit 51 A G VSD dv/dt Min D 230 S diSD/dt = 100A/µs, TJ = 25°C ISD ≤ 37A, di/dt ≤1000A/µs, VDD = 333V, TJ = 125°C 1 695 17 V ns µC 8 V/ns 1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 2 Starting at TJ = 25°C, L = 2.31mH, RG = 2.2Ω, IAS = 37A. 050-8083 Rev A 2-2007 3 Pulse test: Pulse Width < 380µs, duty cycle < 2%. 4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(cr) for any value of VDS less than V(BR)DSS, use this equation: Co(er) = -1.65E-7/VDS^2 + 5.51E-8/VDS + 2.03E-10. 6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452) Microsemi reserves the right to change, without notice, the specifications and information contained herein. 300 V GS = 10V J TJ = -55°C 200 TJ = 25°C 150 100 TJ = 150°C 50 ID, DRIAN CURRENT (A) 6V 80 60 40 5V 20 TJ = 125°C 0 25 20 15 10 5 0 VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V) 4.5V 0 NORMALIZED TO VDS> ID(ON) x RDS(ON) MAX. 250µSEC. PULSE TEST @ <0.5 % DUTY CYCLE VGS = 10V @ 37A 2.0 200 1.5 1.0 0.5 150 TJ = -55°C TJ = 25°C 100 TJ = 125°C 50 0 0 25 50 75 100 125 150 0 -55 -25 TJ, JUNCTION TEMPERATURE (°C) Figure 3, RDS(ON) vs Junction Temperature 100 0 8 7 6 5 4 3 2 1 VGS, GATE-TO-SOURCE VOLTAGE (V) Figure 4, Transfer Characteristics 20,000 10,000 TJ = -55°C Ciss 80 TJ = 125°C 40 1000 Coss 100 Crss 20 0 16 20 30 40 50 60 70 ID, DRAIN CURRENT (A) Figure 5, Gain vs Drain Current 10 500 400 300 200 100 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 6, Capacitance vs Drain-to-Source Voltage 12 VDS = 100V 10 VDS = 250V 8 6 VDS = 400V 4 2 50 100 150 200 250 300 350 400 Qg, TOTAL GATE CHARGE (nC) Figure 7, Gate Charge vs Gate-to-Source Voltage 0 0 200 ID = 37A 14 0 10 80 180 160 140 120 TJ = 25°C 100 80 TJ = 150°C 60 40 20 0 1.5 1.2 0.9 0.6 0.3 VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 8, Reverse Drain Current vs Source-to-Drain Voltage 0 2-2007 0 Rev A 60 C, CAPACITANCE (pF) TJ = 25°C ISD, REVERSE DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE 30 25 20 15 10 5 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 2, Output Characteristics 250 ID, DRAIN CURRENT (A) RDS(ON), DRAIN-TO-SOURCE ON RESISTANCE 2.5 = 7,8 & 10V GS 100 Figure 1, Output Characteristics VGS, GATE-TO-SOURCE VOLTAGE (V) V 050-8083 ID, DRAIN CURRENT (A) T = 125°C 120 250 0 APT51M50J 140 300 100 IDM 13µs 100µs 1ms 10ms Rds(on) 100ms DC line 1 13µs 100µs 1ms 10ms 10 Rds(on) 0.1 100ms DC line TJ = 150°C TC = 25°C 1 TJ = 125°C TC = 75°C 1 IDM Scaling for Different Case & Junction Temperatures: ID = ID(T = 25 C)*(TJ - TC)/125 C ° 800 100 10 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 10, Maximum Forward Safe Operating Area 800 100 10 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 9, Forward Safe Operating Area TJ (°C) 1 TC (°C) 0.0394 0.217 0.00348 ZEXT 10 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100 0.1 APT51M50J 300 Dissipated Power (Watts) 0.0255 0.422 153.3 ZEXT are the external thermal impedances: Case to sink, sink to ambient, etc. Set to zero when modeling only the case to junction. Figure 11, Transient Thermal Impedance Model 0.25 D = 0.9 0.20 0.7 0.15 Note: 0.5 PDM ZθJC, THERMAL IMPEDANCE (°C/W) 0.30 0.10 0.3 t1 t2 t1 = Pulse Duration t 0.05 0 0.1 SINGLE PULSE 0.05 10 -5 Duty Factor D = 1/t2 Peak TJ = PDM x ZθJC + TC 10-1 10-2 10 RECTANGULAR PULSE DURATION (seconds) Figure 12. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration 10 -3 -4 1.0 SOT-227 (ISOTOP®) Package Outline 11.8 (.463) 12.2 (.480) 31.5 (1.240) 31.7 (1.248) 7.8 (.307) 8.2 (.322) r = 4.0 (.157) (2 places) W=4.1 (.161) W=4.3 (.169) H=4.8 (.187) H=4.9 (.193) (4 places) 25.2 (0.992) 0.75 (.030) 12.6 (.496) 25.4 (1.000) 0.85 (.033) 12.8 (.504) 4.0 (.157) 4.2 (.165) (2 places) 2-2007 14.9 (.587) 15.1 (.594) Rev A 3.3 (.129) 3.6 (.143) 38.0 (1.496) 38.2 (1.504) 050-8083 8.9 (.350) 9.6 (.378) Hex Nut M4 (4 places) 1.95 (.077) 2.14 (.084) * Source 30.1 (1.185) 30.3 (1.193) Drain * Emitter terminals are shorted internally. Current handling capability is equal for either Source terminal. * Source Gate Dimensions in Millimeters and (Inches) ISOTOP® is a registered trademark of ST Microelectronics NV. Microsemi's products are covered by one or more of U.S.patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 and foreign patents. US and Foreign patents pending. All Rights Reserved.