Anpec APW7108 Dual mobile-friendly pwm controller Datasheet

APW7108
Dual Mobile-Friendly PWM Controller
Features
•
•
General Description
Adjustable Output Voltage up to 5.5V
- 0.9V Reference Voltage
The APW7108 is a dual-channel, constant on-time, and
synchronous PWM controller which drives dual N-
- ±1% Accuracy Over Temperature
channel MOSFETs for each channel. The APW7108 steps
down high voltage of a battery to generate low-voltage
Operates from an Input Battery Voltage Range of
5V to 24V or from 3.3V/5V System Rail
chipset or RAM supplies in notebook computers.
•
Power-On-Reset Monitoring on VCC Pin
The APW7108 provides excellent transient response and
•
Selectable Forced PWM or Automatic PFM/PWM
Mode
accurate DC voltage output in either PFM or PWM
mode. In PFM mode, the APW7108 provides very high
•
Constant-On-Time Control Scheme
- Switching Frequency Compensation for PWM
efficiency over light to heavy loads with loading-modulated switching frequencies. The Forced-PWM mode
works nearly at constant frequency for low-noise
requirements.
Mode
- Constant Switching Frequency (CH1: 345kHz,
CH2: 255KHz) in PWM Mode with DC Output Current
The APW7108 is equipped with accurate current-limit,
•
Excellent Line and Load Transient Responses
•
output under-voltag, and output over-voltage protections,
perfect for NB applications. A Power-On-Reset function
Adjustable Soft-Start and Soft-Stop
•
Power-Good Outputs for both Channels
monitors the voltage on V CC to prevent wrong operation during power on. A soft-start ramps up the output
•
Adjustable Current-Limit Protection
- Using Sense Resistor or MOSFET’s RDS(ON)
voltage with programmable slew rate to reduce the
start-up current. A soft-stop function actively discharges
•
115% Over-Voltage Protection
the output capacitors with controlled reverse inductor
current. At the end of the soft-stop, the APW7108 forces
- No Negative Output Voltage Occurred
•
70% Under-Voltage Protection
•
Adaptive Dead-Time Control
LGATE high to prevent over-voltage in shutdown. The
APW7108 has individual enable controls for each
channel. Pulling both EN pin low shuts down the whole
chip with low quiescent current close to zero.
- Sensing G-to-S Voltage of Power MOSFETs
•
Shutdown Control for both Channels
•
28-pin SSOP (SSOP-28) and 4mmx4mm 24-lead
The APW7108 is available in SSOP-28 and QFN4x4-24
packages.
QFN (QFN4x4-24) Packages
•
Simplified Application Circuit
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
•
Q1
Note Book Computers
VOUT1
- Chipset/RAM Supplies as low as 0.9V
- 1.8V and 2.5V Supplies
•
EN1
VIN
+5V~24V
VCC=5V
EN2
SSOP-28
PWM1
Q3
Q2
Step-Down Converters Requiring High Efficiency
VOUT2
PWM2
Q4
ROCSET1
ROCSET2
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
1
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APW7108
Ordering and Marking Information
Package Code
N : SSOP-28
QA: QFN4x4-24
Operating Ambient Temperature Range
I : -40 to 85 ° C
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7108
Assembly Material
Handling Code
Temperature Range
Package Code
APW7108
XXXXX
APW7108 N :
APW7108 QA :
XXXXX - Date Code
XXXXX - Date Code
APW7108
XXXXX
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish;
which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and
halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed
1500ppm by weight).
Pin Configuration
PHASE2 19
LGATE2 20
VCC 21
GND 22
LGATE1 23
PHASE1 24
UGATE1 1
BOOT1 2
ISEN1 3
18
17
16
15
Backside
Exposed Pad
EN1 4
VOUT1 5
VSEN1 6
UGATE2
BOOT2
ISEN2
EN2
14 VOUT2
13 VSEN2
GND
1
28 VCC
LGATE1
2
27 LGATE2
26 PGND2
PGND1
3
PHASE1
4
25 PHASE2
UGATE1
5
24 UGATE2
BOOT1
6
23 BOOT2
ISEN1
7
22 ISEN2
EN1
8
21 EN2
VOUT1
9
20 VOUT2
VSEN1 10
19 VSEN2
18 OCSET2
OCSET1 11
12 SOFT2
11 PG2
10 PG1
9 VIN
8 SOFT1
7 OCSET
SOFT1 12
APW7108 (QFN4x4-24)
Top View
16
VIN 14
15 PG1
PG2
APW7108 (SSOP-28)
Top View
Absolute Maximum Ratings
Symbol
17 SOFT2
NC 13
(Note 1)
Parameter
Rating
Unit
VCC
VCC Supply Voltage (VCC to GND)
-0.3 ~ 7
V
VIN
Input Power Voltage (VIN to GND)
-0.3 ~ 28
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to GND)
-0.3 ~ 35
V
<400ns pulse width
>400ns pulse width
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3
V
<400ns pulse width
>400ns pulse width
-5 ~ VCC+0.3
-0.3 ~ VCC+0.3
V
VBOOT
VBOOT-GND
UGATE Voltage (UGATE to PHASE)
LGATE Voltage (LGATE to GND)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Absolute Maximum Ratings (Cont.)
Symbol
(Note 1)
Parameter
Rating
Unit
-5 ~ 35
-2 ~ 28
V
PGND to GND Voltage
-0.3 ~ 0.3
V
VISEN
ISEN Supply Voltage (ISEN to GND)
-0.3 ~ 28
V
VPG
PG1, PG2 Supply Voltage (PG1, PG2 to GND)
-0.3 ~ 7
V
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
PHASE Voltage (PHASE to GND)
VPHASE
<400ns pulse width
>400ns pulse width
o
260
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
Typical Value
Junction-to-Ambient Thermal Resistance in Free Air
Unit
(Note 2)
θJA
SSOP-28
80
QFN4x4-24
40
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol
VCC
VOUT1
VOUT2
VIN1
VIN2
IOUT1
IOUT2
Parameter
Range
Unit
VCC Supply Voltage
4.5 ~ 5.5
V
Converter Output Voltages
0.9 ~ 5.5
V
5 ~ 24
V
Converter Output Currents
~ 20
A
Converter Input Voltages
OCSET Resistance Range
39 ~ 200
kΩ
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
ROCSET
C
C
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VCC=5V, VIN=5~24V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
Test Conditions
APW7108
Unit
Min.
Typ.
Max.
-
1.2
3.0
mA
-
-
1.0
µA
SUPPLY CURRENT
ICC
ICC_SHDN
VCC Nominal Supply Current
UGATEx and LGATEx Open, VSENx
forced above regulation point
VCC Shutdown Supply Current
POWER-ON-RESET (POR)
VCCR
Rising VCC Threshold Voltage
4.1
4.2
4.3
V
VCC POR Hysteresis
0.1
0.2
0.3
V
VIN Pin Sink Current
-
-
35
µA
VIN Shutdown Current
-
-
1.0
µA
VIN PIN
IVIN
IVIN_SHDN
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
3
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APW7108
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VCC=5V, VIN=5~24V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
Test Conditions
APW7108
Min.
Typ.
Max.
Unit
REFERENCE VOLTAGE
VREF
Reference Voltage
Accuracy
-
0.9
-
-1.0
-
+1.0
%
Line Regulation
VCC = 4.5V to 5.5V, VIN = 5~24V
-0.1
-
+0.1
%
Load Regulation
0A < IOUT < 5A; 5V < VIN < 24V
-1.0
-
+1.0
%
-100
-
+100
nA
-
550
-
ns
-
134
-
kΩ
PWM CONVERTERS
IVSEN
VSEN Pin Bias Current
Minimum off-time of UGATE
VOUT Pin Input Impedance
VOUT = 5V
VUV
VSEN Under-Voltage Threshold
~ 2µs noise filter, VSEN Falling
65
70
75
%
VOV
VSEN Over-Voltage Threshold
~ 2µs noise filter, VSEN Rising
110
115
120
%
PWM1
294
345
396
PWM2
217
255
293
SWITCHING FREQUENCY
FSW
Switching Frequency in PWM
mode
DC output current
kHz
MOSFET GATE DRIVERS
TD
UGATE Source Resistance
VBOOT = 5V, IUGATE = 0.1A
-
1
2
Ω
UGATE Sink Resistance
VBOOT = 5V, IUGATE = 0.1A
-
0.9
1.8
Ω
LGATE Source Resistance
VCC = 5V, ILGATE= 0.1A
-
1
2
Ω
LGATE Sink Resistance
VCC = 5V, ILGATE= 0.1A
-
0.6
1.2
Ω
-
25
-
ns
POK is high：~ 3µs noise filter, VSEN is
from low to target value
87
92
95
%
POK is high：~ 3µs noise filter, VSEN is
from high to target value
107
112
117
%
-
3
-
%
VPG1,2 = 5.5V
-
-
1
µA
Dead-Time
PGOOD AND CONTROL FUNCTIONS
PGOOD Threshold
POK Hysteresys
PG1, PG2 Leakage Current
VPG1, 2
PG1, PG2 Voltage Low
IPG1,2 = -4mA
-
0.5
1
V
ISEN
ISEN Sourcing Current
By Design
-
-
260
µA
-
-
0.1
V
0.9
-
-
V
Continuous-Conduction-Mode
(CCM) Enforced (PFM Operation VOUTx pulled low
Inhibited)
Automatic CCM/PFM Operation
Enabled
VOUTx connected to the output
SOFT-START, SOFT-STOP, AND ENABLE
ISTART
Soft-Start Current Source
Sourcing current
-
4.5
-
µA
ISTOP
Soft-Stop Current Sink
Sinking current
-
2.2
-
µA
VST
SOFTx Pull-Low Impedance
-
2
-
kΩ
Soft-Start Complete Threshold
-
1.5
-
V
-
2.4
-
V
EN Voltage Low (OFF)
-
-
0.8
V
EN Voltage High (ON)
2.0
-
-
V
Soft-Start Clamp Voltage
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
Voltage Threshold of SOFT Pin
4
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APW7108
Typical Operating Characteristics
CH2 Output Voltage vs. Output Current
CH1 Output Voltage vs. Output Current
1.81
2.510
VOUT2=1.8V
Output Voltage,VOUT2 (V)
Output Voltage,VOUT1 (V)
VOUT1=2.5V
2.507
2.504
2.501
VIN1=10V, PWM
VIN1=15V, PWM
VIN1=19V, PWM
VIN1=10V, PFM/PWM
VIN1=15V, PFM/PWM
VIN1=19V, PFM/PWM
2.498
2.495
0
1
2
3
4
1.807
1.804
VIN2=10V, PWM
VIN2=15V, PWM
VIN2=19V, PWM
VIN2=10V, PFM/PWM
VIN2=15V, PFM/PWM
VIN2=19V, PFM/PWM
1.801
1.798
1.795
5
6
7
8
9
10
0
1
2
Output Current,IOUT1 (A)
5
6
7
8
9
10
100
100
VOUT1=2.5V
90
90
VOUT2=1.8V
80
80
70
60
50
40
60
50
40
30
30
20
20
10
10
0
0.01
0.1
1
VIN2=10V, PWM
VIN2=15V, PWM
VIN2=19V, PWM
VIN2=10V, PFM/PWM
VIN2=15V, PFM/PWM
VIN2=19V, PFM/PWM
70
VIN1=10V, PWM
VIN1=15V, PWM
VIN1=19V, PWM
VIN1=10V, PFM/PWM
VIN1=15V, PFM/PWM
VIN1=19V, PFM/PWM
Efficiency (%)
Efficiency (%)
4
CH2 Efficiency vs. Output Current
CH1 Efficiency vs. Output Current
0
0.01
10
0.1
1
10
Output Current,IOUT2 (A)
Output Current,IOUT1 (A)
CH1 Switching Frequency Over
Temperature
CH2 Switching Frequency Over
Temperature
395
290
385
280
375
365
270
Frequency (kHz)
Frequency (kHz)
3
Output Current,IOUT2 (A)
355
345
335
325
260
250
240
315
230
305
295
-50 -30 -10 10
30
50 70
220
90 110 130 150
-50 -30 -10
Junction Temperature,TJ (oC)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
10
30
50
70
90 110 130 150
Junction Temperature,TJ (oC)
5
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APW7108
Typical Operating Characteristics (Cont.)
Reference Voltage Accuracy
Over Temperature
CH1 Switching Frequency vs. VIN
375
Switching Frequency,FSW (kHz)
0.909
Output Voltage (V)
0.906
0.903
0.9
0.897
In PWM Mode
DC Output Current
365
355
345
335
325
0.894
0.891
-50 -30 -10
315
10
30
50
70
90 110 130 150
5
7
9
400
In PWM Mode
DC Output Current
Switching Frequency,FSW (kHz)
Switching Frequency,FSW (kHz)
13
15
17
19
21
23 25
CH1 Switching Frequency vs. Ouput
Current
CH2 Switching Frequency vs. VIN
280
11
Input Voltage, VIN (V)
Junction Temperature,TJ (oC)
270
260
250
240
350
300
250
VOUT1=2.5V,PWM
VOUT1=2.5V,PFM/PWM
200
150
100
50
230
5
7
9
11
13
15
17
19
21
0
23 25
0
Input Voltage, VIN (V)
2
4
6
8
10
Output Current, IOUT1 (A)
CH2 Switching Frequency vs. Ouput
Current
Switching Frequency,FSW (kHz)
300
250
200
VOUT2=1.8V,PWM
VOUT2=1.8V,PFM/PWM
150
100
50
0
0
2
4
6
Output Current, IOUT2 (A)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
8
10
6
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APW7108
Operating Waveforms
Enable before End of Soft-Stop
Enable at Zero Initial Voltage of VOUT
1
1
2
2
3
3
4
4
CH1: VEN1 (5V/div)
CH2: VPG1 (5V/div)
CH3: VSOFT1 (1V/div)
CH4: VOUT1 (2V/div)
Time: 2ms/div
CH1: VEN1 (5V/div)
CH2: VPG1 (5V/div)
CH3: VSOFT1 (1V/div)
CH4: VOUT1 (2V/div)
Time: 2ms/div
Shutdown at IOUT1=5A
Shutdown with Soft-Stop at No Load
1
1
2
2
3
3
4
4
CH1: VEN1 (5V/div)
CH2: VPG1 (5V/div)
CH3: VSOFT1 (1V/div)
CH4: VOUT1 (2V/div)
Time: 5ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
7
CH1: VEN1 (5V/div)
CH2: VPG1 (5V/div)
CH3: VSOFT1 (1V/div)
CH4: VOUT1 (2V/div)
Time: 5ms/div
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APW7108
Operating Waveforms (Cont.)
UVP, PWM Mode (CH2)
UVP, PWM Mode (CH1)
1
1
2
2
3
3
4
4
CH1: VPHASE1 (20V/div)
CH2: VOUT1 (2V/div)
CH3: IL1 (5A/div)
CH4: VOUT2 (2V/div)
Time: 100µs/div
CH1: VPHASE2 (20V/div)
CH2: VOUT2 (2V/div)
CH3: IL2 (5A/div)
CH4: VOUT1 (2V/div)
Time: 200µs/div
Input Step-Down Transient at PFM Mode
Input Step-Up Transient at PFM Mode
IOUT1 = 80mA
IOUT1 = 80mA
1
1
2
2
3
3
CH1: VIN (10V/div)
CH2: VOUT1 (AC, 100mV/div)
CH3: VOUT2 (AC, 50mV/div)
Time: 50µs/div
CH1: VIN (10V/div)
CH2: VOUT1 (AC, 100mV/div)
CH3: VOUT2 (AC, 100mV/div)
Time: 50µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Operating Waveforms (Cont.)
Input Step-Down Transient at PWM Mode
Input Step-Up Transient at PWM Mode
IOUT1 = 5A
IOUT1 = 5A
1
1
2
2
3
3
CH1: VIN (10V/div)
CH2: VOUT1 (AC, 100mV/div)
CH3: VOUT2 (AC, 100mV/div)
Time: 20µs/div
CH1: VIN (10V/div)
CH2: VOUT1 (AC, 100mV/div)
CH3: VOUT2 (AC, 100mV/div)
Time: 20µs/div
Mode Transient of PFM to PWM
Mode Transient of PWM to PFM
IOUT1 = 5A to 0.1A
IOUT1 = 0.1A to 5A
1
1
2
2
3
3
4
4
CH1: VOUT1 (AC, 100mV/div)
CH2: VPHASE1 (20V/div)
CH3: IL1 (5A/div)
CH4: VOUT2 (AC, 100mV/div)
Time: 10µs/div
CH1: VOUT1 (AC, 100mV/div)
CH2: VPHASE1 (20V/div)
CH3: IL1 (5A/div)
CH4: VOUT2 (AC, 100mV/div)
Time: 10µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Operating Waveforms (Cont.)
Load Transient at PWM Mode
0A->5A->0A (CH1)
Load Transient at PFM Mode
0A->5A->0A (CH1)
IOUT1 rise/fall time = 1µs
IOUT1 rise/fall time = 1µs
1
1
2
2
3
3
4
4
CH1: VOUT1 (AC, 50mV/div)
CH2: VPHASE1 (20V/div)
CH3: IL1 (5A/div)
CH4: VOUT2 (AC, 50mV/div)
Time: 20µs/div
CH1: VOUT1 (AC, 50mV/div)
CH2: VPHASE1 (20V/div)
CH3: IL1 (5A/div)
CH4: VOUT2 (AC, 50mV/div)
Time: 20µs/div
Load Transient at PWM Mode
0A->5A->0A (CH2)
Load Transient at PFM Mode
0A->5A->0A (CH2)
IOUT2 rise/fall time = 1µs
IOUT2 rise/fall time = 1µs
1
1
2
2
3
3
4
4
CH1: VOUT1 (AC, 50mV/div)
CH2: VPHASE1 (20V/div)
CH3: IL1 (5A/div)
CH4: VOUT2 (AC, 50mV/div)
Time: 20µs/div
Copyright  ANPEC Electronics Corp.
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CH1: VOUT1 (AC, 50mV/div)
CH2: VPHASE1 (20V/div)
CH3: IL1 (5A/div)
CH4: VOUT2 (AC, 50mV/div)
Time: 20µs/div
10
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APW7108
Operating Waveforms (Cont.)
Current-Limit and UV Protections (CH2)
Current-Limit and UV Protections (CH1)
IOUT2 rises with
slow slew rate
IOUT1 rises with
slow slew rate
1
1
2
2
3
3
4
4
CH1: VPHASE1 (20V/div)
CH2: VOUT1 (2V/div)
CH3: IL1 (10A/div)
CH4: VOUT2 (2V/div)
Time: 2ms/div
CH1: VPHASE2 (20V/div)
CH2: VOUT1 (2V/div)
CH3: IL2 (10A/div)
CH4: VOUT2 (2V/div)
Time: 1ms/div
Short Circuit Test
Operating at Light Load of 100mA (CH1)
In PFM Operation
1
1
2
2
3
3
4
4
CH1: VOUT1 (AC, 100mV/div)
CH2: VPHASE1 (20V/div)
CH3: IL1 (2A/div)
CH4: VOUT2 (AC, 100mV/div)
Time: 10µs/div
CH1: VPHASE1 (20V/div)
CH2: VOUT1 (2V/div)
CH3: IL1 (5A/div)
CH4: VOUT2 (2V/div)
Time: 10µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Operating Waveforms (Cont.)
Operating at Heavy Load of 5A (CH1)
1
2
3
4
CH1: VOUT1 (AC, 100mV/div)
CH2: VPHASE1 (20V/div)
CH3: IL1 (2A/div)
CH4: VOUT2 (AC, 100mV/div)
Time: 2µs/div
Pin Description
PIN
NAME
FUNCTION
QFN-24
SSOP-28
22
1
GND
23
2
LGATE1
Output of the low-side MOSFET driver (PWM 1). Connect this pin to Gate of the low-side
MOSFET. Swings from PGND1 or PGND to VCC.
-
3
PGND1
Power ground of the LGATE1 low-side MOSFET driver. Connect the pin to the Source of
the low-side MOSFET.
24
4
PHASE1
Junction point of the high-side MOSFET Source, output filter inductor and the low-side
MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE1
serves as the lower supply rail for the UGATE1 high-side gate driver.
1
5
UGATE1
Output of the high-side MOSFET driver (PWM 1). Connect this pin to Gate of the
high-side MOSFET.
2
6
BOOT1
Supply Input for the UGATE1 Gate Driver and an internal level-shift circuit. Connect to
an external capacitor and diode to create a boosted voltage suitable to drive a logic-level
N-channel MOSFET.
Signal ground for the IC.
3
7
ISEN1
Current sense pin (PWM 1). This pin is used to monitor the voltage drop across the
Drain and Source of the low-side MOSFET for current limit. For precise current
detection, this input can be connected to the optional current sense resistor placed in
series with the Source of the low-side MOSFET.
4
8
EN1
Enable pin of the PWM 1 controller. The PWM 1 is enabled when EN1=1. When both
EN1 and EN2 are low, the chip is disabled and only low leakage current is taken from
VCC and VIN.
5
9
VOUT1
Selection pin for PWM 1 controller to operate in either forced PWM or automatic
PFM/PWM mode.
6
10
VSEN1
Output voltage feedback pin (PWM1). This pin is connected to the resistive divider that
set the desired output voltage for PWM 1. The PGOOD, UVP, and OVP circuits detect
this signal to report output voltage status.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Pin Description (Cont.)
PIN
QFN-24
SSOP-28
-
11
8
12
NAME
FUNCTION
OCSET1
Current-limit threshold setting pin (PWM1). This pin is a buffered 0.9V internal reference
voltage. A resistor from this pin to the ground sets the current limit threshold for the
converter.
SOFT1
Soft-start and soft-stop interval setting pin. The SOFT1 pin can source 4.5µA in soft-start
process or sink 2.2µA in soft-stop process. The SOFT1 current charges or discharges
the capacitor connected from the pin to the GND. The output voltage of the converter
follows the ramping-up/down voltage on the SOFT1 pin in the soft-start/soft-stop process
with the SOFT1 pin voltage as reference. When the SOFT1 pin voltage is higher than
internal reference 0.9V, the error amplifier will use the reference to regulate output
voltage. In the event of under-voltage, or EN1 shutdown, the SOFT1 is used by the
soft-stop function and then pulled down though a 2K resistor to the ground after the
falling SOFT1 voltage reaches about 50mV threshold. In soft-stop process, the converter
only has sinking capability even though the output voltage is below the regulated
voltage.
-
13
NC
No comment
9
14
VIN
Battery voltage input pin.
10
15
PG1
Power-good output pin of PWM 1. PGOOD1 is an open drain output used to indicate the
status of the output voltage. This pin is pulled low when the PWM 1 Converter output is
out of -11% ~ +15% of the set value.
Power-good output pin of PWM 2. The function is same as the PG1 pin.
11
16
PG2
12
17
SOFT2
Soft-start and soft-stop interval setting pin. The function is the same as the SOFT1 pin.
-
18
OCSET2
Current-limit threshold setting pin (PWM 2). This pin is a buffered 0.9V internal reference
voltage. A resistor from this pin to ground sets the current-limit threshold for the
converter.
13
19
VSEN2
Output voltage feedback pin. This pin is connected to the resistive divider that set the
desired output voltage for PWM 2. The PGOOD, UVP, and OVP circuits use this signal to
report output voltage status.
14
20
VOUT2
Selection pin for PWM 2 controller to operate in either forced PWM or automatic
PFM/PWM mode.
15
21
EN2
16
22
ISEN2
Current sense pin (PWM 2). This pin has the same function as ISEN1.
17
23
BOOT2
Supply Input for the UGATE2 Gate Driver and an internal level-shift circuit. Its function is
same as BOOT1.
18
24
UGATE2
Output of the high-side MOSFET driver (PWM 2). Connect this pin to Gate of the
high-side MOSFET.
19
25
PHASE2
Junction point of the high-side MOSFET source, output filter inductor and the low-side
MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE2
serves as the lower supply rail for the UGATE2 high-side gate driver.
-
26
PGND2
Power ground of the LGATE2 low-side MOSFET driver. Connect the pin to the Source of
the low-side MOSFET.
20
27
LGATE2
Output of the low-side MOSFET driver (PWM 2). Connect this pin to Gate of the low-side
MOSFET. Swings from PGND2 or PGND to VCC.
21
28
VCC
7
-
OCSET
Current limit threshold setting pin for PWM1 and PWM 2. This pin is a buffered 0.9V
internal reference voltage. A resistor from this pin to the ground sets the current-limit
threshold for the converter.
Thermal
Pad
-
PGND
Power ground of the both channels’low-side MOSFET drivers. Connect the Sources of
the both channels' low-side MOSFETs to the IC thermal pad as close as possible.
Enable pin of the PWM 2 controller. The PWM 2 is enabled when EN2 = 1. When both
EN1 and EN2 are low, the chip is disabled and only low leakage current is taken from
VCC and VIN.
Supply voltage input pin for control circuitry and both low-side MOSFET drivers.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Block Diagram
1. SSOP-28
PG1 EN1 VOUT1 VCC
GND VOUT2 EN2 PG2
BOOT1
BOOT2
UGATE1
UGATE2
PHASE1
VCC
ADAPTIVE DEADTIME DIODE
EMULATION PWM/
PFM TRANSITION
VCC
ADAPTIVE DEADTIME DIODE
EMULATION PWM/
PFM TRANSITION
PHASE2
VCC
LGATE1
LGATE2
PGND1
PGND2
POR
MODE CHANGE COMP 1
MODE CHANGE COMP 2
ENABLE
BIAS SUPPLIES
115% VREF
REFERENCE
OV1
OV2
FAULT LATCH
89% VREF
115% VREF
89% VREF
OV1 OV2
UV1
UV2
70% VREF
UGATE1
TON1
Generator
TON2
Generator
70% VREF
UGATE2
VSEN1
VSEN2
0.9V
VREF
SOFT1
Error
Comparator1
Soft-Start
Soft-Stop
4.5µA
-2.2µA
Soft-Start
Soft-Stop
LGATE1
ISEN1
0.9V
VREF
Error
Comparator2
SOFT2
4.5µA
-2.2µA
LGATE2
140Ω
140Ω
OCSET1
ISEN2
0.9V VOCSET1
ISEN1
Current
Limit 1
Current
Limit 2
ISEN2
IOCSET1
R
OCSET2
0.9V VOCSET2
IOCSET2
R
11.4
R
11.4
R
VIN
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Block Diagram
2. QFN4x4-24
PG1 EN1 VOUT1 VCC
GND
VOUT2 EN2 PG2
BOOT1
BOOT2
UGATE1
UGATE2
PHASE1
VCC
ADAPTIVE DEAD-TIME
DIODE EMULATION
PWM/PFM TRANSITION
PHASE2
ADAPTIVE DEAD-TIME
DIODE EMULATION
PWM/PFM TRANSITION
VCC
VCC
LGATE1
LGATE2
POR
ENABLE
MODE CHANGE COMP 1
MODE CHANGE COMP 2
BIAS SUPPLIES
PGND
REFERENCE
FAULT LATCH
115% VREF
OV1
OV2
89% VREF
115% VREF
89% VREF
OV1 OV2
UV1
UV2
70% VREF
UGATE1
TON1
Generator
TON2
Generator
70% VREF
UGATE2
VSEN1
VSEN2
0.9V
VREF
Error
Comparator1
Soft-Start
Soft-Stop
SOFT1
4.5µA
-2.2µA
0.9V
VREF
Error
Comparator2
Soft-Start
Soft-Stop
LGATE1
SOFT2
4.5µA
-2.2µA
LGATE2
140Ω
140Ω
ISEN1
ISEN2
OCSET
0.9V VOCSET
ISEN1
Current
Limit 1
Current
Limit 2
ISEN2
IOCSET1
R
IOCSET2
R
11.4
R
11.4
R
VIN
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
15
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APW7108
Typical Application Circuit
1. SSOP-28
VIN
+5V
Bias Supply VCC
C1
4.7µF
VIN VCC
D1
BAT54W
C2
10µF
BOOT1
R1
0
Q1
APM4412
L1
4.7µH
VOUT1
2.5V
C3
4.7µF
C4
150µFx2
C5
10nF
C6
0.15µF
D2
BAT54W
R6
0
UGATE1
PHASE1
Q3
APM4412
UGATE2
C12
0.15µF
PHASE2
ISEN1
Q2
APM4412
R7
1k
R4
10k
LGATE1
LGATE2
PGND1
PGND2
VOUT1
VOUT2
VSEN1
VSEN2
PG1
C9
4.7µF
C11
10nF
R8
10k
R9
10k
EN2
SOFT1
SOFT2
OCSET1 OCSET2
C13
10nF
GND
R5
100k
C10
150µFx2
Q4
APM4412
PG2
EN1
C7
10nF
VOUT2
1.8V
L2
4.7µH
ISEN2
R2
1k
R3
17.8k
C8
10µF
BOOT2
R10
100k
APW7108
2. QFN4x4-24
VIN
+5V
Bias Supply VCC
C1
4.7µF
VIN VCC
D1
BAT54W
C2
10µF
BOOT1
R1
0
Q1
APM4412
VOUT1
2.5V
L1
4.7µH
R6
0
UGATE1
Q3
APM4412
UGATE2
C6
0.15µF
C12
0.15µF
ISEN1
C4
150µFx2
Q2
APM4412
C8
10µF
BOOT2
PHASE1
C3
4.7µF
D2
BAT54W
VOUT2
1.8V
L2
4.7µH
PHASE2
ISEN2
R2
1k
R7
1k
LGATE1
C10
150µFx2
Q4
APM4412
C9
4.7µF
LGATE2
PGND
C5
10nF
R3
17.8k
R4
10k
VOUT1
VOUT2
VSEN1
VSEN2
PG1
EN2
SOFT2
SOFT1
OCSET
GND
APW7108
R5
100k
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
C11
10nF
R9
10k
PG2
EN1
C7
10nF
R8
10k
16
C13
10nF
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APW7108
Function Description
critical conduction point). The on-time of PFM mode is
designed at 1.5 time of the nominal on-time of PWM
Constant-On-Time PWM Controller with Input FeedForward
mode. The on-time of PFM is given by:
Th e c o ns t an t -o n - t im e c o n t r o l a r c h i t ec t u r e i s a
pseudo-fixed frequency with input voltage feed-
TON - PFM =
forward. This architecture relies on the output filter
capacitor’s effective series resistance (ESR) to act as a
1.5 VOUT
×
FSW
VIN
current-sense resistor, therefore, the output ripple voltage provides the PWM ramp signal. In PFM operation, the
Where FSW is the nominal switching frequency of the con-
high-side switch on-time controlled by the on-time generator is determined solely by a one-shot whose pulse
This design provides a hysteresis of converter’s output
current to prevent wrong or repeatedly PFM/PWM handoff
width is inversely proportional to input voltage and directly proportional to output voltage. In PWM operation,
with constant output current. The load current at handoff
from PFM to PWM mode is given by:
verter in PWM mode.
the high-side switch on-time is determined by a switching frequency control circuit in the on-time generator block
1 VIN - VOUT
×
× TON − PFM
L
2
V -V
1.5 VOUT
= IN OUT ×
×
2L
FSW
VIN
ILOAD(PFM to PWM) =
for each channel. The switching frequency control circuit
senses the switching frequency of the high-side switch
and keeps regulating it at a constant frequency in PWM
mode. The design improves the frequency variation and
The load current at handoff from PWM to PFM mode is
given by:
is more outstanding than a conventional constant-on-time
controller which has large switching frequency variation
1 VIN - VOUT
×
× TON − PWM
L
2
V -V
1
V
= IN OUT ×
× OUT
2L
FSW
VIN
ILOAD(PWM to PFM) =
over input voltage, output current and temperature. Both
in PFM and PWM, the on-time generator, which senses
input voltage on VIN pin, provides very fast on-time response to input line transients.
Therefore, the ILOAD(PFM to PWM) is 1.5 time of the ILOAD(PWM to PFM).
The on-times for channel 2 are set 35% higher than the
on-times for channel 1. This is done to prevent audiofrequency “beating” between the two sides, which
Forced PWM Mode
switch asynchronously for each side.
The forced-PW M mode disables the zero-crossing
Another one-shot sets a minimum off-time (typical:
comparator, which controls the low-side switch on time.
This causes the low-side gate-drive waveform to
550ns). The on-time one-shot is triggered if the error
comparator is high, the low-side switch current is be-
become the complement of the high-side gate-drive
waveform. This in turn causes the inductor current to
low the current-limit threshold, and the minimum offtime one-shot has timed out.
reverse at light loads while UGATE maintains a duty factor of VOUT/VIN. The benefit of forced-PWM mode is to keep
the switching frequency fairly constant. Forced-PWM
mode is the most useful for reducing audio frequency
PFM Mode
In PFM mode, an automatic switchover to pulse-fre-
noise, improving load-transient response, and providing
sink-current capability for dynamic output voltage
quency modulation (PFM) takes place at light loads.
This switchover is effected by a comparator that truncates
adjustment.
the low-side switch on-time at the inductor current’s
zero crossing. This mechanism causes the thresh-
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
old between PFM and PW M operation to coincide
with the boundary between continuous and discon-
wrong logic controls when the VCC voltage is low. The
POR function continually monitors the bias supply volt-
tinuous inductor-current operation (also known as the
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
age on the VCC pin if at least one of the enable pins is
17
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APW7108
Function Description (Cont.)
ing as a sinking linear regulator. The soft-stop process is
completed when the falling SOFT voltage reaches about
Power-On-Reset
set high. When the rising VCC voltage reaches the ris-
50mV (typical) threshold. At this moment, the LGATE goes
high level with latch and SOFT pulls low by using the
ing POR voltage threshold (4.2V typical), the POR signal goes high and the chip initiates soft-start opera-
internal 2kΩ resistor to the ground. The latch can be reset by cycling both of the EN signals or VCC power-on-
tions for the enabled channels. This voltage should
drop lower than 4V (typical), the POR disables the chip.
reset signal.
Soft-Start/Soft-Stop
Under-Voltage Protection (UVP)
When soft-start is initiated, the voltage on the SOFT pin of
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. When load current is bigger
the enabled channel starts to ramp up gradually with the
internal 4.5µA current charging the soft-start capacitor. The
than current-limit threshold value, the output voltage will
fall out of the required regulation range. The under-
output voltage follows the soft-start voltage with the
converter operating in PWM mode. When the SOFT pin
voltage continually monitors the VSEN voltage after softstart is completed. If a load step is strong enough to pull
voltage reaches 0.9V, the output voltage comes into
regulation. When the SOFT voltage reaches 1.5V, the
the output voltage lower than the under-voltage
threshold, the offending channel pulls low the PGOOD
power-good (PGOOD) is enabled. Even though the SOFT
pin voltage continues to rise after reaching 1.5V, this
immediately and starts a soft-stop process to shut down
the output gradually. The offending channel is latched
voltage does not affect the output voltage. The maximum SOFT voltage is clamped about 2.4V.
off when the soft-stop process is completed.
The soft-start time (the time from the moment when EN
becomes high to the moment when PGOOD is reported)
The under-voltage threshold is 70% of the nominal output voltage. The under voltage comparator has a built-in
2µs noise filter to prevent the chip from wrong UVP shut-
is determined by the following equation:
TSOFT =
down caused by noise. Toggling both enable pins
to low, or recycling VCC, will clear the latch and bring the
1.5V × CSOFT
4.5µA
chip back to operation.
The time that takes the output voltage to come into
Over-Voltage Protection (OVP)
regulation can be obtained from the following equation:
The over-voltage function monitors the output voltage by
TRISE = 0.6 × TSOFT
VSEN pin. The V SEN voltage should increase over 115%
of the reference voltage due to the high-side MOSFET
During the soft-start stage before the PGOOD pin is ready,
the under-voltage protection is prohibited. The over-
failure or for other reasons, and the over-voltage protection comparator designed with a 2µs noise filter will
voltage and current-limit protection functions are enabled.
If the output capacitor has residue voltage before start-
force the low-side MOSFET gate driver to be high. This
action actively pulls down the output voltage and eventu-
up, both low-side and high-side MOSFETs are in off-state
until the soft-start capacitor charges equal to the VSEN
ally attempts to blow the battery fuse. As soon as the output voltage is within regulation, the OVP comparator is
pin voltage. This will ensure the output voltage starts
from its existing voltage level.
disengaged. The chip will restore its normal operation.
When the OVP occurs, the PGOOD will drop to low as
In the event of under-voltage or shutdown, the SOFT pin
well.
is used by the soft-stop function. The soft-stop function
discharges the voltage on SOFT pin with the internal
This OVP scheme only clamps the voltage overshoot and
does not invert the output voltage when otherwise
2.2µA current sink. The channel with soft-stop enabled
gradually ramps down the output voltage, following the
activated with a continuously high output from low-side
MOSFET driver-a common problem for OVP schemes with
SOFT voltage, by controlling the low-side MOSFET work-
a latch.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
18
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APW7108
Function Description (Cont.)
Power Good Indicator
Both PWM controllers use the low-side MOSFETs on-resistance RDS(ON), to monitor the current for protection
In the soft-start process, the PGOOD is an open-drain and
established after the soft pin voltage is above 1.5V. In
against shortened outputs. The sensed current from
the ISEN pin is compared with a current set by a resis-
normal operation, the PGOOD window is from 89% to
115% of the converter’s reference voltage. The VSEN
tor connected from the OCSET pin to the ground:
pin has to stay within this window for PGOOD to be high.
Since the VSEN pin is used for both feedback and moni-
ROCSET =
10.3
IOC ⋅ RDS(ON)
RISEN +140 Ω
toring purposes, the output voltage deviation can be coupled
directly to the VSEN pin by the capacitor in parallel with the
+ 8µA
voltage divider as shown in the typical applications. In order
to prevent false PGOOD drop, capacitors need to parallel
where, IOC is a desired current-limit threshold and R ISEN
i s t h e va l u e of t h e c u r re n t se n s e re s i s to r con-
at the output to confine the voltage deviation with severe load step transient. The PGOOD comparator has
nected to the ISEN pin. The 8µ A is the offset current
added on top of the sensed current from the ISEN pin for
a built-in 3µs noise filter.
internal circuit biasing.
IPEAK
INDUCTOR CURRENT
W hen POR=0, EN= 0, or after UVP, the PGOOD is
pulled low regardless of the output voltage.
Enable Control
When the EN pin is high (EN=1), the PWM is enabled and
the soft-start is initiated. When both EN1 and EN2 are low
(EN=0), the chip is in the shutdown and only low leakage
current is taken from VCC and VIN. In shutdown mode,
LGATE will be pulled high.
IOUT
IOC
0
Time
Figure 1. Current Limit Algorithm
Current-Limit
The current-limit circuit employs an unique “valley” current sensing algorithm (Figure 1). If the magnitude of the
current-sense signal at ISEN pin is above the current-limit threshold, the PWM is not allowed to initiate a
new cycle. The actual peak current is greater than the current-limit threshold by an amount equals to the inductor
ripple current. Therefore, the exact current-limit characteristic and maximum load capability are the function of the
sense resistance, inductor value, and battery voltage.
The current sensing pin can source up to 260µA. The
current sense resistor RISEN and OCSET resistor ROCSET
can be adjusted simultaneously for the same current-limit
threshold level. The relationship between the sampled
current and MOSFET current is given by:
ISEN (RISEN + 140) = RDS(ON) ⋅ ID
Which means the current sensing pin will source
current to make the voltage drop on the MOSFET equals
to the voltage generated on the sensing resistor, plus the
internal resistor, along the ISEN pin current flowing path.
Copyright  ANPEC Electronics Corp.
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19
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APW7108
Application Information
Output Voltage Selection
capable of carrying the required peak current without
The output voltage can be adjustable from 0.9V to
going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple cur-
5.5V with a resistor-divider. Using 1% or better resistors
for the resistive divider is recommended. The VSEN
rent will increase abruptly when it saturates. This
will result in a larger output ripple voltage.
pin is the inverter input of the error amplifier, and the
reference voltage is 0.9V. Take APW7108 as the example,
Output Capacitor Selection
the output voltage is determined by:
Output voltage ripple and the transient voltage de-

R1 

VOUTX = 0.9 × 1 +

 RGND 
viation are factors that have to be taken into consideration when selecting an output capacitor. Higher
Where R1 is the resistor connected from VOUTX to VSENx
capacitor value and lower ESR reduce the output ripple
and the load transient drop. Therefore, it’s important to
and RGND is the resistor connected from VSENx to the
GND.
select high performance low ESR capacitors that are intended for switching regulator applications. In addition to
Output Inductor Selection
high frequency noise related MOSFET turn-on and turnoff, the output voltage ripple includes the capaci-
The duty cycle of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
tance voltage drop and ESR voltage drop caused by
the AC peak-to-peak current. These two voltages can be
is fixed, it can be written as:
D=
VOUT
VIN
represented by:
∆VESR
and affects the load transient reponse. Higher inductor
value reduces the inductor’s ripple current and induces
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
lower output ripple voltage. The ripple current and ripple
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
voltage can be approxminated by:
IRIPPLE =
VIN - VOUT VOUT
×
FSW × L
VIN
another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR
Where FSW is the switching frequency of the regulator.
Although increase the inductor value and frequency would
reduce the ripple current and voltage, there is a tradeoff
between the inductor’s ripple current and the regulator
load transient response time.
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
current. Increasing the switching frequency (FSW) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power
dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting
point is to choose the ripple current to be approximately
30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
IRIPPLE
8COUTFSW
= IRIPPLE × RESR
∆VCOUT =
The inductor value determises the inductor ripple current
20
and suppress the voltage ripple to a tolerable level. A
small decoupling capacitor in parallel for bypassing
the noise is also recommended, and the voltage rating
of the output capacitors are also must be considered.
To support a load transient that is faster than the
switching frequency, more capacitors have to be used
to reduce the voltage excursion during load step change.
Another aspect of the capacitor selection is that the
total AC current going through the capacitors has to be
less than the rated RMS current specified on the capacitors to prevent the capacitor from over-heating.
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation,
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APW7108
Application Information (Cont.)
conduction loss and transition loss. For the high-side
and low-side MOSFETs, the losses are approximately
Input Capacitor Selection
select the capacitor voltage rating to be at least 1.3 times
given by the following equations:
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately I OUT /2,
2
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
2
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
where I OUT is the load current. During power up, the
input capacitors have to handle large amount of surge
Where
current. In low-duty notebook appliactions, ceramic capacitors are recommended. The capacitors must be con-
I
is the load current
OUT
TC is the temperature dependency of RDS(ON)
nected between the drain of high-side MOSFET and the
source of low-side MOSFET with very low-impeadance
FSW is the switching frequency
tSW is the switching interval
PCB layout.
D is the duty cycle
Note that both MOSFETs have conduction losses while
MOSFET Selection
the high-side MOSFET includes an additional transition loss. The switching internal, t SW , is the func-
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with
tion of the reverse transfer capacitance CRSS. The (1+TC)
term is to factor in the temperature dependency of the RDS
the RDS(ON) of the MOSFET:
and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET.
• For the low-side MOSFET, before it is turned on, the
(ON)
body diode has been conducted. The low-side MOSFET
driver will not charge the miller capacitor of this
Layout Consideration
MOSFET.
In any high switching frequency converter, a correct layout
• In the turning-off process of the low-side MOSFET,
is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the
the load current will shift to the body diode first. The
high dv/dt of the phase node voltage will charge the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
miller capacitor through the low-side MOSFET driver
sinking current path. This results in much less
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the
switching loss of the low-side MOSFETs.The duty
cycle is often very small in high battery voltage
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling
applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, the less
by the low-side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage
the RDS(ON) of the low-side MOSFET loss, the less the
power loss. The gate charge for this MOSFET is usu-
spike during the switching interval. In general, using short
and wide printed circuit traces should minimize intercon-
ally of secondary consideration. The high-side
MOSFET does not have the zero voltage switch-
necting impedances and the magnitude of voltage spike.
Signal and power grounds are to be kept separating and
ing condition, and because it conducts for less time
compared to the low-side MOSFET, the switching
finally combined using ground plane construction or
single point grounding. The best tie-point between the
loss tends to be dominant. Priority should be given
to the MOSFETs with less gate charge, so that both
signal ground and the power ground is at the negative
side of the output capacitor on each channel, where there
the gate driver loss and switching loss will be
minimized.
The selection of the N-channel power MOSFETs are
is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
determined by the R DS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement.
The losses in the MOSFETs have two components:
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
21
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APW7108
Application Information (Cont.)
Layout Consideration (Cont.)
•
• Keep the switching nodes (UGATEx, LGATEx, BOOTx,
PHASEx, and ISENx) away from sensitive small sig-
The APW7108 uses ripple mode control. Build the
resistor divider close to the VSENx pin so that the
high impedance trace is shorter. The VSENx pin traces
can’t be closed to the switching signal traces (UGATEx,
nal nodes since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as
LGATEx, BOOTx, PHASEx, and ISENx).
possible and there should be no other weak signal
traces in parallel with theses traces on any layer.
•
• The signals going through theses traces have both
•
high dv/dt and high di/dt, with high peak charging and
The PGNDx trace should be a seperate trace, and
inpendently go to the source of the low-side MOSFET.
For QFN4x4-24 package only, the thermal pad is the
PGND of the dual channels. The sources of the both
channels’ low-side MOSFETs should be near the
discharging current. The traces from the gate drivers
to the MOSFETs (UGATEx and LGATEx) should be short
PGND respectively.
and wide.
• Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane
between the two pads reduces the voltage bounce of
the node.
• The ISENx trace should be a separate trace, and
independently go to the drain terminal of the low-side
MOSFET. The current sense resistor should be close
to ISENx pin. The loop formed by the bottom MOSFET,
output inductor, and output capacitor, should be very
small. The source of the bottom MOSFET should tie
to the negative side of the output capacitor in order
for the ISENx pin to get the voltage drop on the RDS(ON).
• Decoupling capacitor, compensation component,
the resistor dividers, boot capacitors, and soft-start
capacitors should be close their pins. (For example,
place the decoupling ceramic capacitor near the drain
of the high-side MOSFET as close as possible. The
bulk capacitors are also placed near the drain).
• The input capacitor should be near the drain of the
high-side MOSFET; the high quality ceramic
decoupling capacitor can be put close to the VCC and
GND pins; the output capacitor should be near the
loads. The input capacitor GND should be close to
the output capacitor GND and the low-side MOSFET
GND.
• The drain of the MOSFETs (V and PHASEx nodes)
IN
should be a large plane for heat sinking. And
PHASEx pin traces are also the return path for
UGATEx. Connect these pins to the respective
converter’s high-side MOSFET source.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
22
www.anpec.com.tw
APW7108
Package Information
SSOP-28
D
h X 45
E
E1
SEE VIEW
A
b
A
0.25
c
A2
A1
GAUGE PLANE
SEATING PLANE
L
0
e
VIEW A
S
Y
M
B
O
L
SSOP-28
MIN.
MIN.
MAX.
A
A1
INCHES
MILLIMETERS
MAX.
0.069
1.75
0.004
0.25
0.10
0.010
0.049
A2
1.24
b
0.20
0.30
0.008
0.012
c
0.15
0.25
0.006
0.010
D
9.80
10.00
0.386
0.394
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
e
0.635 BSC
0.025 BSC
L
0.40
1.27
0.016
0.050
h
0.25
0.50
0.010
0.020
0
0°
8°
0°
8°
Note : 1. Followed from JEDEC MO-137 AF.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
23
www.anpec.com.tw
APW7108
Package Information
QFN4x4-24
D
b
E
A
Pin 1
D2
A1
A3
L K
E2
Pin 1 Corner
e
QFN4x4-24
S
Y
M
B
O
L
A
MIN.
MAX.
MIN.
MAX.
0.80
1.00
0.031
0.039
A1
0.00
0.05
0.000
0.002
MILLIMETERS
A3
INCHES
0.20 REF
0.008 REF
b
0.18
0.30
0.008
D
3.90
4.10
0.154
0.012
0.161
2.80
0.098
0.110
D2
2.50
E
3.90
4.10
0.154
0.161
E2
2.50
2.80
0.098
0.110
0.45
0.014
e
0.50 BSC
L
0.35
K
0.20
0.020 BSC
0.018
0.008
Note : 1. Followed from JEDEC MO-220 WGGD-6.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
24
www.anpec.com.tw
APW7108
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SSOP-28
Application
QFN4x4-24
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
16.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
16.0±0.30
1.75±0.10
7.5±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
8.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.4±0.20
10.2±0.20
2.1±0.20
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±0.20
1.30±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SSOP-28
Tape & Reel
2500
QFN4x4-24
Tape & Reel
3000
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Taping Direction Information
SSOP-28
USER DIRECTION OF FEED
QFN4x4
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 sec
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Time 25°C to Peak Temperature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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APW7108
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Volume mm3
≥350
225 +0/-5°C
225 +0/-5°C
3
Package Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
240 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Package Thickness
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2009
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