ams AS3515E-ELQP Stereo audio codec with system power management Datasheet

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austriamicrosystems
AS3515 V15
Data Sheet, Confidential
Data Sheet, Confidential
AS3515
The AS3515 is a low power stereo audio codec and is
designed for Portable Digital Audio Applications. It allows
playback in CD quality and recording in FM-stereo quality. It
has a variety of audio inputs and outputs to directly connect
electret microphones, 16Ω headset, 4Ω speaker and auxiliary
signal sources via a 10-channel mixer. It only consumes 22mW
in playback mode.
High Power Speaker Amplifier
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 2x500mW @8Ω driver capability
– over-current detection
Power Management
– step up for system supply (3.0V – 3.6V)
– charge pump for CPU core (0.85V – 1.8V, 200mA)
– step up for backlight (15V, 38.5mA)
– LDO for digital supply (2.9V, 200mA)
– LDO for analogue supply (2.9V, 200mA)
– LDO for peripherals (1.7V-3.3V, 200mA)
– LDO for peripherals (3.1V-3.3V, 200mA)
– LDO for RTC (1.0V-2.5V, 2mA)
– LDO for USB 1.1 transceiver (3.26V, 10mA)
– battery supervision
– 10sec emergency shut-down
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Further the device offers advanced power management
functions. All necessary ICs and peripherals in a flash based
Digital Audio Player are supplied by the AS3515. The power
management block generates 9 different supply voltages out of
the battery supply. CPU, NAND flash, SRAM, memory cards,
LCD back-light, USB RX/TX can be powered. The different
supply voltages are programmable via the serial control
interface. It also contains a charger and is designed for battery
supplies from 1V to 5V.
High Efficiency Headphone Amplifier
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 2x40mW @16Ω driver capability
– headphone and over-current detection
– phantom ground eliminates large capacitors
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1 General Description
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Stereo Audio Codec with System Power Management
The AS3515 has an on-chip, phase locked loop (PLL)
controlled, clock generator. It generates 44.1kHz, 48kHz and
other sample rates defined in MP3, AAC, WMA, OGG VORBIS
etc. No additional external crystal or PLL is needed. Further the
AS3515 has an independent 32kHz real time clock (RTC) on
chip which allows a complete power down of the system CPU.
2 Key Features
Multi-bit Sigma Delta Converters
– DAC: 18bit with 94dB SNR (‘A’ weighted) , 48kHz
– ADC: 14bit with 82dB SNR (‘A’ weighted), 16kHz
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2 Microphone Inputs
– 3 gain pre-setting (28dB/34dB/40dB) and AGC
– 32 gain steps @1.5dB and MUTE
– supply for electret microphone
– microphone detection
– remote control by switch
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2 Line Inputs
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– stereo or 2x mono or mono differential
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Line Outputs
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 1Vp @10kΩ
– mono differential 5mW to 32Ω (ear-peace)
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Audio Mixer
– 10 channel input/output mixer with AGC
– mixes line inputs and microphones with DAC
– left and right channels independent
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Battery Charger
– automatic trickle charge (50mA)
– prog. constant current charging (100-400mA)
– prog. constant voltage charging (3.9V-4.25V)
Real Time Clock
– ultra low power 32kHz oscillator
– 32bit RTC sec counter
– selectable alarm (seconds or minutes)
General Purpose ADC
– 10bit resolution
– 16 inputs analogue multiplexer
Interfaces
– I²S digital audio interface
– 2 wire serial control interface
– watchdog via serial interface
– power good pin
– 128bit unique ID (OTP)
– 17 different interrupts
Package
– CTBGA64 [7.0x7.0x1.1mm] 0.8mm pitch
– LQFP64 [10x10x1.4mm] 0.5mm pitch
3 Application
Portable Digital Audio Player and Recorder
PDA, Smartphone
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AS3515 V15
Data Sheet, Confidential
4 Block Diagram
AS3515 Block Diagram
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Figure 1
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AS3515 V15
Data Sheet, Confidential
Contents
General Description ......................................................................................................................................... 1
Key Features.................................................................................................................................................... 1
Application ....................................................................................................................................................... 1
Block Diagram.................................................................................................................................................. 2
Absolute Maximum Ratings (Non-Operating)................................................................................................... 6
5.1
Operating Conditions ................................................................................................................................ 7
6 Detailed Functional Block Description.............................................................................................................. 8
6.1
Line Output ............................................................................................................................................... 8
6.1.1
General.............................................................................................................................................. 8
6.1.2
Register Description .......................................................................................................................... 8
6.1.3
Parameter .......................................................................................................................................... 9
6.2
Headphone Output ................................................................................................................................. 10
6.2.1
General............................................................................................................................................ 10
6.2.2
Phantom Ground ............................................................................................................................. 10
6.2.3
No-Pop Function.............................................................................................................................. 10
6.2.4
Over-current Protection ................................................................................................................... 10
6.2.5
Headphone Detection ...................................................................................................................... 10
6.2.6
Power Save Options ........................................................................................................................ 10
6.2.7
Parameter ........................................................................................................................................ 11
6.2.8
Register Description ........................................................................................................................ 11
6.3
Speaker Output....................................................................................................................................... 13
6.3.1
General............................................................................................................................................ 13
6.3.2
No-Pop Function.............................................................................................................................. 13
6.3.3
Over-current Protection ................................................................................................................... 13
6.3.4
Power Save Options ........................................................................................................................ 13
6.3.5
Parameter ........................................................................................................................................ 14
6.3.6
Register Description ........................................................................................................................ 14
6.4
Microphone Inputs (2x) ........................................................................................................................... 16
6.4.1
General............................................................................................................................................ 16
6.4.2
AGC................................................................................................................................................. 16
6.4.3
Supply & Detection .......................................................................................................................... 16
6.4.4
Remote Control................................................................................................................................ 16
6.4.5
Parameter ........................................................................................................................................ 17
6.4.6
Register Description ........................................................................................................................ 17
6.5
Line Inputs (2x) ....................................................................................................................................... 19
6.5.1
General............................................................................................................................................ 19
6.5.2
Parameter ........................................................................................................................................ 19
6.5.3
Register Description ........................................................................................................................ 19
6.6
Digital Audio Interface............................................................................................................................. 21
6.6.1
Input................................................................................................................................................. 21
6.6.2
Output.............................................................................................................................................. 21
6.6.3
Signal Description............................................................................................................................ 21
6.6.4
Power Save Options ........................................................................................................................ 21
6.6.5
Clock Supervision ............................................................................................................................ 21
6.6.6
Parameter ........................................................................................................................................ 22
6.6.7
Register Description ........................................................................................................................ 22
6.7
Audio Output Mixer ................................................................................................................................. 24
6.7.1
General............................................................................................................................................ 24
6.7.2
AGC................................................................................................................................................. 24
6.7.3
Register Description ........................................................................................................................ 24
6.8
Audio Settings......................................................................................................................................... 25
6.8.1
Register Description ........................................................................................................................ 25
6.9
3V Step-Up Converter............................................................................................................................. 27
6.9.1
General............................................................................................................................................ 27
6.9.2
Parameter ........................................................................................................................................ 28
6.10
Low Drop Out Regulators.................................................................................................................... 29
6.10.1
General ........................................................................................................................................ 29
6.10.2
LDO1............................................................................................................................................ 29
6.10.3
LDO2............................................................................................................................................ 29
6.10.4
LDO3............................................................................................................................................ 29
6.10.5
LDO4............................................................................................................................................ 30
6.10.6
Parameter .................................................................................................................................... 30
6.11
Charge-Pump Step-Down Converter................................................................................................... 32
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1
2
3
4
5
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AS3515 V15
Data Sheet, Confidential
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6.11.1
General ........................................................................................................................................ 32
6.11.2
Functional Description.................................................................................................................. 32
6.11.3
Parameter .................................................................................................................................... 34
6.12
SYSTEM ............................................................................................................................................. 35
6.12.1
General ........................................................................................................................................ 35
6.12.2
Power Up ..................................................................................................................................... 35
6.12.3
Power Down................................................................................................................................. 35
6.12.4
Parameter .................................................................................................................................... 36
6.12.5
Register Description..................................................................................................................... 36
6.13
Charger ............................................................................................................................................... 38
6.13.1
General ........................................................................................................................................ 38
6.13.2
Trickle Charge.............................................................................................................................. 38
6.13.3
Temperature Supervision............................................................................................................. 38
6.13.4
Parameter .................................................................................................................................... 38
6.13.5
Register Description..................................................................................................................... 39
6.14
15V Step-Up Converter ....................................................................................................................... 40
6.14.1
General ........................................................................................................................................ 40
6.14.2
Parameter .................................................................................................................................... 40
6.14.3
Register Description..................................................................................................................... 41
6.15
Supervisor ........................................................................................................................................... 42
6.15.1
General ........................................................................................................................................ 42
6.15.2
BVDD Supervision ....................................................................................................................... 42
6.15.3
Junction Temperature Supervision............................................................................................... 42
6.15.4
Register Description..................................................................................................................... 42
6.16
Interrupt Generation ............................................................................................................................ 43
6.16.1
General ........................................................................................................................................ 43
6.16.2
IRQ Source Interpretation ............................................................................................................ 43
6.16.3
De-bouncer .................................................................................................................................. 43
6.16.4
Register Description..................................................................................................................... 43
6.17
Real Time Clock .................................................................................................................................. 45
6.17.1
General ........................................................................................................................................ 45
6.17.2
RTC supply .................................................................................................................................. 45
6.17.3
Register Description..................................................................................................................... 45
6.18
10-Bit ADC .......................................................................................................................................... 47
6.18.1
General ........................................................................................................................................ 47
6.18.2
Input Sources ............................................................................................................................... 47
6.18.3
Reference .................................................................................................................................... 47
6.18.4
Parameter .................................................................................................................................... 48
6.18.5
Register Description..................................................................................................................... 48
6.19
128 bit Fuse Array ............................................................................................................................... 50
6.19.1
General ........................................................................................................................................ 50
6.19.2
Register Description..................................................................................................................... 50
6.20
VTRM-LDO ......................................................................................................................................... 51
6.20.1
General ........................................................................................................................................ 51
6.21
I2C Control Interface ........................................................................................................................... 52
6.21.1
General ........................................................................................................................................ 52
6.21.2
Parameter .................................................................................................................................... 52
6.21.3
Register Description..................................................................................................................... 53
7 Electrical Specification ................................................................................................................................... 55
8 Pinout and Packaging .................................................................................................................................... 57
8.1
Pin Description........................................................................................................................................ 57
8.2
Ball & Pin Assignment............................................................................................................................. 59
8.2.1
CTBGA64 ........................................................................................................................................ 59
8.2.2
LQFP64 ........................................................................................................................................... 60
8.3
Package Drawings and Marking ............................................................................................................. 61
8.3.1
CTBGA64 ........................................................................................................................................ 61
8.3.2
LQFP64 ........................................................................................................................................... 62
9 Ordering Information ...................................................................................................................................... 65
10
Copyright .................................................................................................................................................... 66
11
Disclaimer................................................................................................................................................... 66
12
Contact Information .................................................................................................................................... 66
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AS3515 V15
Data Sheet, Confidential
Revision History
Revision
Date
Owner
Description
5.5.2005
pkm
final release
3.01
12.5.2005
pkm
changed soldering conditions (chapter 5)
3.02
12.5.2005
pkm
3.03
12.5.2005
pkm
updated charge pump and LDO typical performance characteristics(chapter 6.10,
6.11)
spelling corrections (chapter 6.18)
3.03
20.5.2005
pkm
updated 15V DCDC description (chapter 6.14)
3.04
18.10.05
pkm
updated 3V and 15V DCDC block diagram (chapter 6.9, 6.14)
3.04
18.10.05
pkm
changed interrupt de-bounce times (6.16)
3.04
11.4.06
pkm
changed block diagram
3.1
3.6.08
pkm
V15 changes: RTCSUP startup deleted, UID added, chip ID changed to 6h,
updated package and order information
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3.0
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AS3515 V15
Data Sheet, Confidential
5 Absolute Maximum Ratings (Non-Operating)
Stresses beyond the absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or beyond those listed is not implied.
Caution: Exposure to absolute maximum rating conditions may affect device reliability.
Table 1
Absolute Maximum Ratings
PARAMETER
Symbol
V in
Voltage at 5V pins:
NOTE
7.0
V
0.5
V
5.0
V
-0.5
DVDD+0.5
V
V in
-0.5
BVDD+0.5V
V
Voltage at Analogue pins:
V in
-0.5
AVDD+0.5
V
Voltage at Regulator pins:
V in
-0.5
5.0
V
Input Current (latchup
I scr
immunity)
Electrostatic Discharge HBM ESD
-100
100
mA
VB1V, CSCL, CSDA, PWR_UP
these pins have no diode to
DVDD
LRCK, SCLK, SDI, SDO,
P_PVDD, P_CVDD, BATTEMP,
ISINK, XIN32K, XOUT32K,
XIRQ, PWGOOD
BGND, HPH_CM, HPGND,
HPL/R, SPL/R
LOUTL/R, VREF, AGND,
LIN1L/R, LIN2L/R, MIC1P/N,
MIC2P/N, MIC1SUP, MIC2SUP
AVDD, DVDD, PVDD, CPVDD,
CVDD
Norm: Jedec 17
+/-1
kV
Norm: MIL 883 E method 3015
Total Power Dissipation (all
supplies and outputs)
Storage Temperature
Pt
-
1000
mW
Valid for BGA64 package
T strg
-55
125
°C
5
85
%
Humidity non-condensing
Table 2
Soldering Conditions
Parameter
T body
Package Body Temperature
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Symbol
T peak
Solder Profile*
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D well
MSL
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Voltage at Digital pins:
UNIT
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Voltage difference of VSSTerminals
Voltage at Digital pins
BVDD, UVDD,
-0.5
RTCSUP, CHGIN
DVSS, AVSS, VSS3, -0.5
VSS15, VSSCP, BVSS
V in
-0.5
MAX
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DC Supply Voltage
MIN
Min
Max
Unit
260
°C
235
245
°C
30
45
s
above 217 °C
1
Represents a max. floor live time of
168h
Moisture Sensitive Level
3
Comments
Norm IPC/JEDEC J-STD-020C, reflects
moisture sensitivity level only
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* austriamicrosystems AG strongly recommends to use underfill.
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Operating Conditions
Table 3
Operating Conditions
PARAMETER
Battery Supply Voltage
SYMBOL
BVDD
3.0
MIN
5.5
MAX
UNIT
V
DCDC 3V Supply Voltage
VB1V
1.0
3.6
V
USB Supply Voltage
UVDD
4.5
5.5
V
Digital Supply Voltage
DVDD
2.8
3.6
V
Analogue Supply Voltage
AVDD
2.8
3.6
V
Charger Supply Voltage
CHG_IN
4.5
5.5
V
Difference of Positive Supplies
AVDD-DVDD -0.25
0.25
V
Difference of Negative Supplies
Any
DVSS, AVSS, VSS3, VSS15, VSSCP, Combination
BVSS
-0.1
0.1
V
Ambient Temperature
T amb
-20
85
°C
Supply Current
BVDD
6.8
LRCLK
8
To achieve good performance,
the negative supply terminals
should be connected to low
ohmic ground plane.
DAC to HP without load and
bias reduction enabled
According to 8-48kSps
Audio Data
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mA
NOTE
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AS3515 V15
Data Sheet, Confidential
48
kHz
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System Clock Frequency
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Data Sheet, Confidential
6 Detailed Functional Block Description
6.1
Line Output
6.1.1
General
The line output is designed to provide the audio signal with typical 1Vp at a load of minimum 10kΩ, which is a minimum value for line
inputs. Additional this output amplifier is capable to drive a 32Ω load (e.g. an earpiece of a mobile phone. To achieve this, the operation
mode can be switched from single ended stereo to mono differential.
Figure 2 Line Output Mode Block Diagrams
Mono Differential Mode
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Stero Mode
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This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
40.5dB to +6dB.
Please observe that gain of upper amplifier needs to be
set to 0dB
6.1.2
Register Description
Enabling the output stage is done via a control bit in the audio settings register (AudioSet1 register 0x14h). The line out driver itself is
controlled by the following two registers.
Right Line Out Register (00h)
LINE_OUT_R Register
Name
7,6
5
4..0
reserved
LOR_VOL
Default
Access Description
00b
0b
00000b
R/W
R/W
R/W
For testing purpose only, must be set to 0h
not used
volume settings for right line output, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
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Table 4
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AS3515 V15
Data Sheet, Confidential
Left Line Out Register (01h)
Table 5
LINE_OUT_L Register
Bit
Name
Default
Access Description
7,6
LO_SES_DM
00b
R/W
5
4..0
LOL_VOL
0b
00000b
n/a
R/W
Table 6
Line Output Characteristics
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6.1.3
Single ended stereo or differential mono selection
11: tbd.
10: output switched to single ended stereo
01: output switched to differential mono
00: output switched to mute
not used
volume settings for left line output, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Symbol Parameter
Notes
Min
RL
Output Load
A0
—Ax
Gain
Gain Step-Size
Gain Step-Precision
Signal to Noise Ratio
Mute Attenuation
stereo mode
differential mode
programmable gain
10k
32
-40.5
SNR
stereo mode
Typ
Max
6
1.5
0.5
100
100
Unit
Ohm
Ohm
dB
dB
dB
dB
dB
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BVDD = 3.3V, TA= 25oC unless otherwise mentioned
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AS3515 V15
Data Sheet, Confidential
6.2
Headphone Output
6.2.1
General
The headphone output is designed to provide the audio signal with 2x40mW @ 16Ω or 2x20mW @32Ω, which are typical values for
headphones.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
43.43dB to +1.07dB. The maximum output power of 40mW @ 16Ω is achieved, by setting the mixer output to 1Vp and using the gain of
1.07dB.
6.2.2
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Figure 3 Headphone-Output
Phantom Ground
HPCM pin is the buffered HPGND output. It can be used to drive the loads without external blocking capacitors between HPL / HPR and
HPCM. If the load is between HPR / HPL and BVSS, 100uF of de-coupling capacitors are needed. The phantom ground can be switched
off to save power if not needed.
6.2.3
No-Pop Function
To avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output stage is disabled.
HPGND pin, which needs a 100nF capacitor outside, gets charged on power-up with 2uA to AGND=1.45V. After start-up the DC level of
the following pins are the same: HPR=HPL=HPCM=HPGND=AGND=1.45V. The Start-up time before releasing mute is about 90ms. To
avoid pop-noise 150ms discharging time of HPGND after a shutdown, have to be waited before starting up again.
6.2.4
Over-current Protection
6.2.5
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This output stage has an over-current protection, which disables the output for 256ms or 512ms. This value can be set in the headphone
registers. The over-current protection limit of HPR and HPL pin is typical 145mA while HPCM pin has a 210mA threshold. If needed, the
over-current condition can also be signalled via an interrupt to the controlling microprocessor.
Headphone Detection
6.2.6
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With a control bit the headphone detection can be enabled. The detection is only working as long as the headphone stage is in power
down mode and the load is applied between HPR / HPL and HPCM. the headphone detection can also trigger a corresponding interrupt.
Power Save Options
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To save power, especially when driving 32 Ohm loads, a reduction of the bias current can be selected. Together with switching off the
phantom ground this gives 4 possible operating modes.
Table 7
Headphone Power-Save Options
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HPCM_OFF IBR_HPH IDD_HPH (typ.) Load
0
0
2.2mA
16 Ohm
1
0
1
0
1
1
1.5mA
1.5mA
1.0mA
16 Ohm
32 Ohm
32 Ohm
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
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6.2.7
Parameter
Table 8
Power Amplifier Block Characteristics
Symbol Parameter
Notes
RL
Pout
Output Load
Maximum Output Power
stereo mode
A0
—Ax
Gain
Gain Step-Size
Gain Step-Precision
Power Supply Rejection Ratio 200Hz-20kHz, 720mVpp, R L = 16Ω
Short Current Protection Level
I OUT power down
HPGND is forced high (>1V)
I OUT_pd
T power_up
SNR
R L = 32Ω
R L = 16Ω
programmable nominal gain
Signal to Noise Ratio
Mute Attenuation
Max
16
20
40
-43.43
1.07
1.5
0.5
90
145
-20
20
90
100
100
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
Unit
Ohm
mW
mW
dB
dB
dB
dB
mA
uA
ms
dB
dB
Register Description
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6.2.8
Typ
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PSRR
Min
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AS3515 V15
Data Sheet, Confidential
To get an interrupt on an over-current event, the corresponding bit in the IRQ_ENRD1 register (0x26h) has to be set. Also the interrupt
request for HP detection has to be set in this register. The power-save options are controlled via AudioSet3 register (0x16h). All other
headphone driver settings are controlled by the following two registers.
Right Headphone Register (02h)
Table 9
HPH_OUT_R Register
Name
Description
7,6
HP_OVC_TO
5
4..0
HPR_VOL
speaker over current time out:
11: 0 ms
10: 512 ms
01: 128 ms
00: 256 ms
volume settings for right headphone output, adjustable in 32 steps @ 1.5dB
11111: 1.07 dB gain
11110: -0.43 dB gain
..
00001: -43.93dB gain
00000: -45.43 dB gain
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Bit
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The register is R/W; default value is 00h
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AS3515 V15
Data Sheet, Confidential
Left Headphone Register (03h)
Bit
Name
Description
7
HP_Mute
6
HP_ON
5
HPdetON
4..0
HPL_VOL
0: normal operation
1: headphone output set to mute (mute is on during power-up)
0: speaker stage not powered
1: power up headphone stage
0: no headphone detection
1: enable headphone detection
volume settings for left headphone output, adjustable in 32 steps @ 1.5dB
11111: 1.07 dB gain
11110: -0.43 dB gain
..
00001: -43.93dB gain
00000: -45.43 dB gain
Te
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The register is R/W; default value is 00h
al
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Table 10 HPH_OUT_L Register
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6.3
Speaker Output
6.3.1
General
The speaker output is designed to provide the stereo audio signal with 2x500mW @ 4Ω.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from
−40.5dB to +6dB. The maximum output power of 500mW @ 4Ω is achieved, by setting the mixer output to 1Vp and using the gain of
+6dB.
6.3.2
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Figure 4 Speaker Output
No-Pop Function
BGND pin, which needs a 100nF capacitor outside, gets charged on power-up to BVDD/2.To avoiding click and pop noise during powerup and shutdown, the output is automatically set to mute when the output stage is disabled.
The Start-up time before releasing mute is about 100ms. To avoid pop-noise the 150ms discharging time of SPR / SPL after a shutdown
(220µF capacitor in stereo single ended mode assumed), have to be waited before starting up again.
6.3.3
Over-current Protection
This output stage has an over-current protection, which disables the output for 0 to 512ms. This value can be set in the speaker registers.
The over-current protection limit of SPR and SPL pin is typical 700mA. To get an interrupt on an over-current event, the corresponding bit
in the IRQ_ENRD1 register (0x26h) has to be set.
6.3.4
Power Save Options
When driving > 4Ω, two power save options can be chosen.
ca
The output driver stage can be set to only 25% drive capacity, which will reduce the maximum output power. Additionally the bias currents
can be reduced to 50% in 3 steps.
Table 11 Speaker Power-Save Options
0
00
8mA
4 Ohm
00
01
10
11
2.8mA
2.4mA
1.9mA
1.5mA
16-32 Ohm
16-32 Ohm
16-32 Ohm
16-32 Ohm
ch
1
1
1
1
IBR_LSP IDD_HPH (typ.) Load
ni
LSP_LP
Te
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
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6.3.5
Parameter
Table 12 Speaker Amplifier Parameter
Notes
RL
Output Load
stereo mode
mono differential mode
Pout
A0
—Ax
Maximum Output Power
Gain
Gain Step-Size
Gain Step-Precision
Power Supply Rejection Ratio
Short Current Protection Level
I OUT power down
R L = 8Ω, mono differential mode
programmable nominal gain
I OUT_pd
T power_up
SNR
BGND is forced high (>1V)
6
1.5
0.5
75
700
-20
20
100
100
100
Signal to Noise Ratio
Mute Attenuation
Max
1
-40.5
200Hz-20kHz, 720mVpp, no load
BVDD = 5V, TA= 25oC unless otherwise mentioned
Unit
Ohm
Ohm
W
dB
dB
dB
dB
mA
uA
ms
dB
dB
Register Description
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6.3.6
Typ
4
8
lv
PSRR
Min
al
id
Symbol Parameter
To get an interrupt on an over-current event, the corresponding bit in the IRQ_ENRD1 register (0x25h) has to be set. Changing the bias
current or the output driver strength is done via AudioSet2 register (0x15h). All other speaker driver settings are controlled by the following
two registers.
Right Speaker Register (04h)
Table 13 LSP_OUT_R Register
Name
7,6
SP_OVC_TO
Description
5
4..0
SPR_VOL
speaker over current time out:
11: 0 ms
10: 512 ms
01: 128 ms
00: 256 ms
not used
volume settings for right speaker output, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
ca
Bit
Te
ch
ni
The register is R/W; default value is 00h
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Left Speaker Register (05h)
Bit
Name
Description
7
SP_Mute
6
SP_ON
5
4..0
SPR_VOL
0: normal operation
1: speaker output set to mute (mute is on during power-up)
0: speaker stage not powered
1: power up speaker stage
not used
volume settings for left speaker output, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Te
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The register is R/W; default value is 00h
al
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Table 14 LSP_OUT_L Register
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6.4
Microphone Inputs (2x)
6.4.1
General
AS3515 includes two identical microphone inputs. The blocks have differential inputs to a microphone amplifier with adjustable gain. This
stage also includes an AGC.
The following volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be
set from –40.5dB to +6dB. The stage is set to mute by default. If the microphone input is not enabled, the volume settings are set to their
default values. Changing of volume and mute control can only be done after enabling the input.
6.4.2
AGC
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Figure 5 Microphone Input
The microphone amplifier includes an AGC, which is limiting the signal to 1Vp. The AGC has 15 steps with a dynamic range of about
29dB. The AGC is ON by default but can be disabled by a microphone register bit.
6.4.3
Supply & Detection
6.4.4
ni
ca
Each microphone input generates a supply voltage of 1.5V above HPHCM. The supply is designed for ≤2mA and has a 10mA current
limit. In OFF mode the MICSUP terminal is pulled to AVDD with 30kohm. A current of typically 50uA generates an interrupt to inform the
CPU, that a circuit is connected. When using HPHCM as headset ground the HPH–stage gives the interrupt. After enabling the HPH-stage
through the CPU the microphone detection interrupt will follow.
Remote Control
Te
ch
Fast changes of the supply current of typically 500uA are detected as a remote button press, and an interrupt is generated. Then the CPU
can start the measurement of the microphone supply current with the internal 10-bit ADC to distinguish which button was pressed. As the
current measurement is done via an internal resistor, only two buttons generating a current of about 0.5mA and 1mA can be detected.
With this 1mA as microphone bias is still available.
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6.4.5
Parameter
Table 15 Microphone Inputs Parameter
Min
programmable gain
-40.5
differential
MicInGain = 0dB, MicAmp_Gain0
MicInGain = 0dB, MicAmp_Gain1
MicInGain = 0dB, MicAmp_Gain2
Typ
1.5
0.5
15
28
34
40
15*2.0
60
120
40
20
10
90
100
Max
Unit
6
dB
dB
dB
kOhm
dB
dB
dB
dB
us
ms
mVp
mVp
mVp
dB
dB
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Gain
Gain Step-Size
Gain Step-Precision
R inMIC
Input Resistance
A MIC 0
MicAmp_Gain0
A MIC 1
MicAmp_Gain1
A MIC 2
MicAmp_Gain2
SoftClip_AGC_Range
Attack_Time
Release_Time
V Innom 0
Nominal_Input_Voltage0
V Innom 1
Nominal_Input_Voltage1
V Innom 2
Nominal_Input_Voltage2
SNR
Signal to Noise Ratio
Mute Attenuation
Microphone Supply
V MICsup
Microphone Supply Voltage
I MIClim
Mic. Supply Current Limit
I MICdet
Mic. Detection Current
I REMdet
Remote Detection Current
V noise
Voltage Noise
al
id
Notes
A0
—Ax
lv
Symbol Parameter
0-2mA
2.95
10
50
500
5.7
V
mA
uA
uA
uV
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
6.4.6
Register Description
Enabling a microphone input is done via a control bit in the audio settings register (AudioSet1 register 0x14h). To get an interrupt on an
microphone detection event, the corresponding bit in the IRQ_ENRD1 register (0x26h) has to be set, while a remote detection interrupt is
controlled via IRQ_ENRD2 register (0x27h). All other microphone input settings are controlled by the following registers.
Right Microphone Registers (06h & 08h)
Table 16 MIC1_R & MIC2_R Register
Name
7
M1_AGC_off
M2_AGC_off
M1_Gain
M2_Gain
M1R_VOL
M2R_VOL
Te
ch
4..0
0: automatic gain control enabled
1: automatic gain control disabled
00: gain set to 28 dB
01: gain set to 34 dB
10: gain set to 40 dB
11: gain set to tbd.
volume settings for right microphone input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
ni
6,5
Description
ca
Bit
The registers are R/W; default value is 00h
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Left Microphone Register (07h & 09h)
Bit
Name
Description
7
M1_Sup_off
M2_Sup_off
M1_Mute_off
M2_Mute_off
M1L_VOL
M2L_VOL
0: microphone supply enabled
1: microphone supply disabled
0: microphone input set to mute
1: normal operation
Not used
Volume settings for left microphone input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
6
5
4..0
Te
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The registers are R/W; default value is 00h
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Table 17 MIC1_L & MIC2_L Register
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6.5
Line Inputs (2x)
6.5.1
General
AS3515 includes two identical line inputs. The blocks can work in mono differential, 2x mono single ended or in stereo single ended mode.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
34.5dB to +12dB. The stage is set to mute by default. If the line input is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
If using the inputs as mono differential, the volume setting for the right channel should be set to 0dB.
6.5.2
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Figure 6 Line Input
Parameter
Figure 7 Line Input Parameter
Symbol Parameter
Notes
Min
A0
—Ax
programmable gain
-34.5
R inLINE
SNR
Gain
Gain Step-Size
Gain Step-Precision
Input Resistance
Mute
Min Gain, single ended stereo
Signal to Noise Ratio
Mute Attenuation
Typ
1.5
0.5
49
100
100
100
Max
Unit
12
dB
dB
dB
kOhm
kOhm
dB
dB
6.5.3
ca
BVDD = 3.3V, TA= 25oC, fs=48kHz unless otherwise mentioned
Register Description
ni
Enabling a line-input is done via a control bit in the audio settings register (AudioSet1 register 0x14h). All other line input settings are
controlled by the following registers.
Right Line In Registers (0Ah & 0Ch)
ch
Table 18 LINE_IN1_R & LINE_IN2_R Register
Name
7,6
5
LI1R_Mute_off
LI2R_Mute_off
LI1R_VOL
LI2R_VOL
Te
Bit
4..0
Description
0: right line input is set to mute
1: normal operation
volume settings for right line input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
The registers are R/W; default value is 00h
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Left Line In Register (0Bh & 0Dh)
Name
Description
7,6
LI1_Mode
LI2_Mode
5
LI1L_Mute_off
LI2L_Mute_off
LI1L_VOL
LI2L_VOL
Single ended stereo or differential mono selection
00: inputs switched to single ended stereo
01: inputs switched to differential mono
10: inputs switched to single ended mono
11: tbd.
0: left line input is set to mute
1: normal operation
Volume settings for left microphone input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
4..0
lv
Bit
al
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Table 19 LINE_IN1_L & LINE_IN2_L Register
Te
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The registers are R/W; default value is 00h
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6.6
Digital Audio Interface
6.6.1
Input
Digital audio data can be fed into the AS3515 via the I2S interface These input data are then used by the 18-bit DAC to generate the
analog audio signal.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
6.6.2
Output
al
id
This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a
volume control to the 14 bit ADC. The digital output is done via an I2S interface.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
6.6.3
lv
The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate.
Signal Description
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The digital audio interface uses the standard I2S format:
•
•
left justified
MSB first
•
one additional leading bit
The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than
18 bits sampled, the data sample is completed with “0”s. The ADC output is always 16 bit. If more SCLK pulses are provided, only the first
16 will be significant. All following bit will be “0”.
SCLK has not to be necessarily synchronous to LRCK but the high going edge has to be separate from LRCK edges. The LRCK signal
has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always
in correct phase lock condition to the external LRCK.
Figure 8 I2S_Timing
LRCK
Left Channel
SCLK
SDI
18 bit
*
15
*
17
2
leading dummy bit
according to I2S
standard
0
2
15
1
tsu thd
0
17
2
1
0
2
1
0
ts1 ts2
Power Save Options
ni
6.6.4
1
ca
SDO
16 bit
Right Channel
ch
The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.
6.6.5
Clock Supervision
Te
The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the LRCK input changes. A bit
in the interrupt register represents the actual state (present or not present) of the LRCK.
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6.6.6
Parameter
Table 20 DAC/ADC Block Parameter
Symbol Parameter
Notes
A0
programmable gain DAC input
programmable gain ADC output
Gain
Typ
dB
dB
dB
dB
dB
1.02
2.6
80
80
80
0.42
DVDD
0.3
-
20
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-20
-
25oC
V
V
V
V
ns
ns
ns
lv
SCLK, LRCK, SDI (30%DVDD/2)
SCLK, LRCK, SDI (70%DVDD/2)
SDO @ 2mA
SDO @ 2mA
SDI versus high going edge of SCLK
SDI versus high going edge of SCLK
SCLK high going edges separation from
LRCK edges
LRCK
clock Jitter
BVDD = 3.3V, DVDD = 2.9V, TA=
6.6.7
Unit
1.07
12
1.5
0.5
100
—Ax
t jitter
Max
al
id
Gain Step-Size
Gain Step-Precision
Mute Attenuation
I2S inputs / outputs
V IL
V IH
V OL
V OH
t su
Set-up Time
t hd
Hold Time
t s1, t s2
Separation Time
Min
-43.43
-34.5
ns
unless otherwise mentioned
Register Description
Enabling the DAC or ADC is done via a control bit in the audio settings register (AudioSet1 register 0x14h). To get an interrupt on a LRCK
state change, the corresponding bit in the IRQ_ENRD1 register (0x25h) has to be set. Changing the bias current and adding a dither
signal is done via AudioSet2 register (0x15h). All other DAC or ADC settings are controlled by the following two registers.
Right DAC Register (0Eh)
Table 21 DAC_R Register
Bit
Name
7..5
4..0
DAR_VOL
Description
volume settings for right DAC input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
ca
The register is R/W; default value is 00h
Left DAC Register (0Fh)
ni
Table 22 DAC_R Register
Name
7
6
DAC_Mute_off
5
4..0
DAL_VOL
Te
ch
Bit
Description
0: DAC input is set to mute
1: normal operation
volume settings for left DAC input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
The register is R/W; default value is 00h
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Right ADC Register (10h)
Bit
Name
Description
7,6
ADCmux
00: Stereo Microphone
01: Line_IN1
10: Line_IN2
11: Audio SUM
5
4..0
ADR_VOL
volume settings for right ADC input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
lv
The register is R/W; default value is 00h
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Table 23 ADC_R Register
Left ADC Register (11h)
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Table 24 ADC_L Register
Bit
Name
Description
7
AD_FS2
6
ADC_Mute_off
5
4..0
ADL_VOL
Divider selection for ADC clock
0: ADC sample clock is I2S LRCK / 2
1: ADC sample clock is I2S LRCK / 4
0: ADC input is set to mute
1: normal operation
Volume settings for left ADC input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
The register is R/W; default value is 00h
PLL Mode Register (1Dh)
Table 25 PLLMode Register
Name
7..3
2,1
Not used
PLLmode<1:0> Sets the MCLK generation for different LRCK speeds:
00: LRCK: 24-48kHz
01: reserved
10: LRCK: 8-23kHz
11: reserved
Not used
ni
ch
0
Description
ca
Bit
Te
The register is R/W; default value is 00h
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6.7
Audio Output Mixer
6.7.1
General
The mixer stage sums up the audio signals of the following stages
•
•
Microphone Input 1
Microphone Input 2
•
•
•
Line Input 1
Line Input 2
Digital Audio Input (DAC)
al
id
The mixing ratios have to be with the volume registers of the corresponding input stages. Please be sure that the input signals of the
mixer stage are not higher than 1Vp. If summing up several signals, each has of course to be lower.
This shall insure that the output signal is also not higher than 1Vp to get a proper signal for the output amplifier. This stage has an
automatic gain control, which automatically avoids clipping.
AGC
lv
6.7.2
The audio mixer includes an AGC, which is limiting the signal to 1Vp. The AGC has 12 steps with a dynamic range of about 18dB. The
AGC is ON by default but can be disabled by a register bit.
Register Description
am
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6.7.3
The mixer stage has no direct associated registers.
Te
ch
ni
ca
Enabling the Summing / Mixer stage is done via a control bit in the audio settings register (AudioSet1 register 0x14h). Disabling the AGC
is done via AudioSet2 register (0x15h).
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6.8
Audio Settings
6.8.1
Register Description
First AudioSet Register (14h)
Name
Description
7
ADC_on
6
SUM_on
5
DAC_on
4
LOUT_on
3
LIN2_on
2
LIN1_on
1
MIC2_on
0
MIC1_on
1: ADC for recording is enables
0: ADC disabled
1: Summing / Mixing stage is enabled
0: Summing / Mixing stage is disabled (no audio output possible)
1: DAC enabled
0: DAC disabled
1: Line output enabled
0: Line output disabled
1: Line input 2 enabled
0: Line input 2 disabled
1: Line input 1 enabled
0: Line input 1 disabled
1: Microphone input 2 enabled
0: Microphone input 2 disabled
1: Microphone input 1 enabled
0: Microphone input 1 disabled
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Bit
al
id
Table 26 AudioSet1 Register
The register is R/W; default value is 00h
Second AudioSet Register (15h)
Table 27 AudioSet2 Register
Bit
Name
7
BIAS_off
4,3
2
ch
1,0
ca
5
ni
6
Description
1: Bias disabled
0: Bias enabled
DITH_off
1: no dither added
0: add dither to the audio stream
AGC_off
1: Automatic gain control for summing stage disabled
0: Automatic gain control for summing stage enabled
IBR_DAC<1:0> Bias current reduction settings for DAC:
00: 0%
01: 25%
10: 40%
11: 50%
LSP_LP
Low power mode for speaker output:
1: speaker output driver set for 16Ohm load or more (25%)
0: speaker output driver set for 4Ohm to 16Ohm load (100%)
IBR_LSP<1:0> Bias current reduction settings for speaker output:
00: 0%
01: 17%
10: 34%
11: 50%
Te
The register is R/W; default value is 00h
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Third AudioSet Register (16h)
Bit
Name
Description
7..3
2
ZCU_off
1
IBR_HPH
0
HPCM_off
Not used
Zero cross gain update of audio outputs
1: zero cross update disabled
0: zero cross update enabled
Bias current reduction settings for headphone output:
1: headphone output driver set for 32Ohm load or more (68%)
0: headphone output driver set for 16Ohm load (100%)
Headphone common mode buffer settings:
1: headphone CM buffer is switched off
0: headphone CM buffer is switched on
Te
ch
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ca
am
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The register is R/W; default value is 00h
al
id
Table 28 AudioSet3 Register
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6.9
6.9.1
3V Step-Up Converter
General
Output voltage 3V to 3.6V (BVDD) programmable in 4 steps via DCDC3p bit to save power
Input voltage 1V (1.2V) to 3V, voltages higher than that can be connected to BVDD directly
Maximum output current to BVDD: 150mA
•
•
•
Current mode operation
On-chip compensation and feedback network
On chip 300mΩ NMOS switch
•
•
•
•
PWM mode with 1.2MHz switching frequency
Inductor current limitation 850mA
Pulse skipping capability
Low quiescent current: 40μA in PFM-mode, 300μA in PWM mode
•
•
≤1μA shutdown current
uses external coil (6.8uH) and Schottky diode (500mA)
Figure 9 DCDC Block Diagram
SW
SW3
am
lc s
on A
te G
nt
st
il
VBAT
BVDD
lv
al
id
•
•
•
DCDC step up
Oscillator
1.2MHz
NMOS
Power
Device
300mΩ
PWM-LOGIC
Comparator
+
-
Current
sense
Σ
Ramp
generation
1MΩ
ca
Pulse skipping
logic
+
ch
ni
Error
amplifier
VSS
VSS
1MΩ
VSS3
PWR_GND
Te
PWR_UP
ENDCDC
Vref
1.6V
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AS3515 V15
Data Sheet, Confidential
6.9.2
Parameter
Table 29 DCDC Boost Parameter
Notes
I VDD2.9
Power down mode
PFM mode operation
PWM mode (low output load)
R Load >220Ω
I OUT =1mA, VBAT falling from 1.5 to 0V
Minimum Startup Voltage
Hold-on Voltage
Internal Switch R DS_ON
Switching Frequency
t ON_min
t OFF_min
η eff
Minimum On-time
Minimum Off-time
Efficiency
I SW_LIM
I OUT
ΔV OUT
Current Limit
Maximum Load Current
Output Voltage Ripple
Start-up, X3VOK=1
PWM mode operation, X3VOK=0
100
0.9
I OUT =20mA, Vin=1.35
I OUT =50mA, Vin=1.5
1.0V ≤ VB1V ≤ 3.0V
VB1V=1.0V
ΔI OUT =100mA in 100μs
Typ
40
300
1.0
0.5
300
250
1.2
100
100
85
87
0.85
150
Max
Unit
5
μA
μA
μA
V
V
mΩ
kHz
MHz
ns
ns
%
%
A
mA
mV
500
1.42
tbd.
am
lc s
on A
te G
nt
st
il
V STARTUP
V HOLD
R SW_on
f SW
Min
lv
Supply Current
al
id
Symbol Parameter
Vin=1.0..2.0V, C(Vbat) = 2.2μF ceramic || 2000μF elko, C(Vreg) = 3 x 2.2μF ceramic, L=DS1608 4.7μH, Temp = 25deg
Figure 10 DCDC Boost Typical Performance Characteristics
90,0
85,0
Eff. [%]
80,0
1,5V
1,35V
1,25V
1,1V
0,9V
75,0
70,0
65,0
ca
60,0
1
10
100
1000
Iout [mA]
Te
ch
ni
BVDD=3.1V, L=DS1608 4.7μH, Temp = 25deg
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Data Sheet, Confidential
6.10 Low Drop Out Regulators
6.10.1 General
These LDO’s are designed to supply sensitive analogue circuits, audio devices, AD and DA converters, micro-controller and other
peripheral devices.
The design is optimised to deliver the best compromise between quiescent current and regulator performance for battery powered
devices.
al
id
Stability is guaranteed with ceramic output capacitors of 1μF +/-20% (X5R) or 2.2μF +100/-50% (Z5U). The low ESR of these caps
ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the
power transistor has to operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output.
The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of
the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.
Figure 11 LDO Block Diagram
VBAT
BVDD
3V-5.5V
3-5.5V
lv
Vref
1.8V
Low Noise
DC reference
Low Gain
Ultra High Bandwidth
Amplifier
am
lc s
on A
te G
nt
st
il
High Gain
Low Bandwidth
Amplifier
PMOS
Power Device
1Ω max.
C_comp
(internal)
Vout
Vout
1.7 - 3.56V
1.85-3.4V
200mA
150mA load
Load
1μF
Z5U
external
GND
6.10.2 LDO1
This LDO generates the analog supply voltage used for the AS3515 itself.
Input voltage is BVDD
Output voltage is AVDD (typ. 2.9V)
ni
6.10.3 LDO2
ca
•
•
This LDO generates the digital supply voltage used for the AS3515 itself, microprocessor peripheral supply and external components like
SD-Cards, Nand-Flashes, FM-Radio…
Input Voltage is BVDD
Output Voltage is DVDD (typ. 2.9V)
Driver strength: 200mA
ch
•
•
•
Te
6.10.4 LDO3
This LDO will be used to supply the periphery voltage for a microprocessor.
•
•
•
•
Input Voltage BVDD
Output Voltage is PVDD 1.7 to 3.3V
Driver strength: 200mA
Programmable via P_PVDD pin and PVDDp bit in 8 steps
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Data Sheet, Confidential
Table 30 PVDD programming
P_PVDD
VSS
150k to VSS
Open
150k to DVDD
DVDD
PVDDp=0 PVDDp=1
OFF
2.50V
3.33V
2.90V
1.80V
OFF
2.36V
3.15V
2.74V
1.70V
al
id
6.10.5 LDO4
This LDO will be used to supply peripheral circuits. Default value is 3.3V, but it can be manually programmed to 3.1V if needed.
Input Voltage BVDD
Output Voltage is CPVDD (3.1 or 3.3)
Programmable via CPVDDp bit.
Driver strength: 200mA
lv
•
•
•
•
6.10.6 Parameter
am
lc s
on A
te G
nt
st
il
Table 31 LDOs Block Characteristics
Symbol Parameter
R ON
Notes
Min
Typ
On resistance
PSRR
Power supply rejection ratio
I OFF
I VDD
Noise
t start
V out_tol
Shut down current
Supply current
Output noise
Startup time
Output voltage tolerance
V LineReg
Line regulation
V LoadReg
Load regulation
I LIMIT
Current limitation
f=1kHz
f=100kHz
-50
Static
Transient;Slope: t r =10μs
Static
Transient;Slope: t r =10μs
LDO2, LDO3, LDO4
Unit
1
Ω
dB
100
50
50
200
50
nA
μA
μV rms
μs
mV
70
40
without load
10Hz < f < 100kHz
LDO1,
LDO1,
LDO1,
LDO1,
LDO1,
Max
<1
<10
<1
<10
400
mV
mV
mA
Te
ch
ni
ca
BVDD=4V; ILOAD=150mA; Tamb=25ºC; CLOAD =2.2μF (Ceramic); unless otherwise specified
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Figure 12 LDO Typical Performance Characteristics
Load regulation of LDO1
lv
al
id
Output noise of LDO1
Output load: 150mA
am
lc s
on A
te G
nt
st
il
transient load: 1mA – 100mA
slope: 1μs
LDO1
LDO1
output load: 10mA
transient input voltage ripple: 500mV
Te
ch
ni
ca
output load: 150mA
transient input voltage ripple: 500mV
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AS3515 V15
Data Sheet, Confidential
6.11 Charge-Pump Step-Down Converter
6.11.1 General
•
•
Input Voltage CPVDD
Output Voltage 0.85 to 1.8 V
•
•
•
•
Voltage setting via P_CVDD and CVDDp<1:0> bits in 16 steps
regulated 2:1 charge pump with pulse skipping
scaleable switches according to BVDD
Bypass LDO for higher currents or lower battery voltages respectively
•
Driver strength: 50mA / 200mA with bypass LDO
al
id
This converter will be used to supply the core voltage for a microprocessor.
2u2F
CPVDD
lv
Figure 13 Charge Pump Block Diagram
330nF
CN
am
lc s
on A
te G
nt
st
il
CP
CVDD Regulator
Charge-Pump
With ext. C-Fly
500kHz
Mode_2
CPVDD Length Reg.
LDO4
3.56V
clamp
BVDD
Mode_3
ChPump Length Reg.
CVDD
2u2F
Mode_1
VBAT Length Reg.
VB1V
6.11.2 Functional Description
ca
To reduce the power consumption when using CVDDs below 1.8V, CPVDD is automatically set to 3.3V and can be further reduced to
3.1V if needed.
ni
Table 32 CVDD programming
P_CVDD
OFF
1.0V
1.2V
1.5V
1.8V
Te
ch
VSS
150k to VSS
Open
150k to DVDD
DVDD
CVDD
CPVDD
CPVDDp=0 CPVDDp=1
3.3V
3.3V
3.3V
3.3V
3.56V
3.1V
3.1V
3.1V
3.1V
3.56V
Additional the CVDD voltage can be trimmed with two register bits in the range of 0mV to -150mV
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AS3515 V15
Data Sheet, Confidential
Table 33 CVDD trimming
CVDDp<1:0>
0
0
1
1
CVDD
0
1
0
1
Vnom (see )
Vnom – 50mV
Vnom - 100mV
Vnom - 150mV
This gives 0.85V to 1.8V as total range of the CVDD voltage.
VSS
150k to VSS
Open
150k to DVDD
DVDD
CVDDp=11
CVDDp=10
CVDDp=01
CVDD=00
OFF
0.85V
1.15V
1.35V
1.65V
OFF
0.90V
1.10V
1.40V
1.70V
OFF
0.95V
1.15V
1.45V
1.75V
OFF
1.00V
1.20V
1.50V
1.80V
Three different functional paths generate CVDD:
Direct length regulation from VB1V
am
lc s
on A
te G
nt
st
il
1.
lv
P_CVDD
al
id
Table 34 CVDD programming range
Mode1=true IF ((VNOM+Vmargin1) < VB1V < (VTH1)) && (NoUSB)
Vmargin1=50mV/150mV (100mV Hysteresis)
VTH1=1.7V/1.8V (100mV Hysteresis)
•
•
•
•
2.
VBAT LDO is used when VB1V>(VNOM+50mV) because length reg. is a 1ohm device.
VBAT LDO is used when VB1V<(1.8V) since Mode1 is efficient just with single battery cell.
VBAT LDO is not used when there is high supply present from USB even when VB1V is in range.
(there is no dependency on CHARGER_IN needed because with a charger a 4V LiIo battery is used anyway)
Direct length regulation from CPVDD
Mode2=true IF ((Not Mode1) && (CPVDD < (VNOM+Vmargin2)))
Vmargin2=200mV/300mV (100mV Hysteresis)
•
•
3.
CPVDD LDO is used when VBAT LDO Mode1 is not entered and
CPVDD is not high enough to do 2:1 charge-pump regulation.
Charge-Pump CPVDD division by 2 active plus length regulation
Te
ch
ni
ca
Mode3=true IF ((Not Mode1) && (Not Mode2))
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6.11.3 Parameter
Table 35 CVDD Charge Pump Parameter
Symbol Parameter
Notes
Regulated output voltage
Output voltage tolerance
Maximum Load current
I LIMIT
Current limitation
Min
Typ
0.85
-50
CP mode
LDO mode
LDO mode
Unit
V
mV
mA
50
200
400
mA
Figure 14 CVDD Charge Pump Typical Performance Characteristics
CVDD Charge Pump Regulation to 1.2V
lv
1,3
am
lc s
on A
te G
nt
st
il
1,25
V_CVDD [V]
Max
1.8
50
al
id
V OUT
V OUT_tol
I load
1,2
1,15
h
1,1
BVDD= 2.8V
1,05
0
50
BVDD= 3.0V BVDD= 3.2V
100
BVDD= 3.6V
BVDD= 3.4V
150
200
250
I_CVDD [mA]
CVDD Lengh Regulation to 1.2V
BVDD= 3.6V
1,25
ca
BVDD= 3.4V
ni
1,15
1,1
ch
V_CVDD [V]
1,2
BVDD= 3.0V
Te
1,05
BVDD= 3.2V
1
0
50
www.austriamicrosystems.com
100
150
200
250
300
350
400
I_CVDD [mA]
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Data Sheet, Confidential
6.12 SYSTEM
6.12.1 General
The system block handles the power up and power down of the AS3515.
6.12.2 Power Up
•
•
High signal on the PWR_UP pin (>80ms, >1V)
Input voltage on the UVDD pin (USB plug in: >80ms, BVDD>3V, UVDD>4.5V)
•
Input voltage on the CHG_IN pin (charger plug in: >80ms, BVDD>3V, CHG_IN>4.0V)
al
id
The AS3515 powers up when on of the following condition is true:
To hold the chip in power up mode the PwrUpHld bit in the SYSTEM register (0x20h)is set.
6.12.3 Power Down
The chip automatically shuts off if one of the following conditions arises:
Clearing the PwrUpHld bit in SYSTEM register (0x20h)
I2C watchdog power down if enabled
BVDD drops below the minimum threshold voltage (2.6V)
•
•
Junction temperature reaches maximum threshold, set in SUPERVISOR register (0x24h)
High signal on the PWR_UP pin for more than 11s.
am
lc s
on A
te G
nt
st
il
lv
•
•
•
Figure 15 Power Up Timing
Power up from PwrUp, CHG_IN,
UVDD or RTCSUP pin
BVDD
rising with VBAT1 supply (DCDC3V)
VREF, IREF
rising with vdd_bandgap
QLDO1 & 2
AVDD & DVDD for internal supply
EN LDO2 + DCDC
QLDO2=ok
Enable Startup Sequence
start sequencer with 1.2 MHz clock
Enable PVDD
+50ms
+52ms
ni
Enable CPVDD
ca
VREF=ok
Enable CVDD
ch
+54ms
PowerGood = XRES
Te
+56ms
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6.12.4 Parameter
Table 36 System Block Characteristics
Notes
Min
Typ
Max
2.15
2.0
100
2
IRQ, PWGOOD @ 8 mA
IRQ @ 8 mA, push/pull mode only
IRQ, PWGOOD
BVDD = 3.3V, DVDD = 2.9V, TA= 25oC unless otherwise mentioned
6.12.5 Register Description
2.6
8
10
kHz
us
0.3
-
V
V
uA
am
lc s
on A
te G
nt
st
il
SYSTEM Register (20h)
4.1
50
Unit
V
V
mV
al
id
DVDD_POR_OFF
DVDD_POR_ON
POR_ON/OFF_HYST
LRCK WATCHDOG
F(LRCK)_WD_OFF
ON_Delay
Digital Outputs
V OL
V OH
Ipullup
lv
Symbol Parameter
Table 37 System Register
Bit
Name
7..4
Version <3:0>
Description
3
PVDDp
2
CPVDDp
1
EnWDogPwdn
0
PwrUpHld
Unique number to identify the design version
0101: revision 6
PVDD trimming:
0: Vnom
1: Vnom *17/18
CPVDD trimming:
0: Vnom 3.3 or 3.56V depending on CVDD
1: 3.1V if CVDD is 1.5V or smaller
0: forced power down through watchdog is disabled
1: forced power down through watchdog is enabled
0: power up hold is cleared and supply is switched off
1: set to on after power on
Te
ch
ni
ca
The register is R/W (bits 7 to 4 are read only); default value is 21h
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CVDD / DCDC3 Register (21h)
Table 38 CVDD / DCDC3 Register
Name
Description
7
CP_SW
6
CP_on
5
LREG_CPnot
4,3
DCDC3p
2
LREG_off
0,1
CVDDp1
charge pump / length regulator switch margin reduction
0: margin set to 200/300 mV
1: margin reduced to 150/225 mV (automatic switching to length regulator is done “later”,
at a lower input voltage)
0: normal operation
1: keeps Mode 3 charge pump always on
Please note that bit 2 = “0”, overrides bit 6.
write:
For testing purpose only, must be set to 0h
read:
0: CP is working
1: LREG is working
DCDC3 Vout programminig
00: 3.6V
01: 3.2V
10: 3.1V
11: 3.0V
0: keeps Mode 2 length regulator always on
1: normal operation
CVDD trimming:
00: Vnom
01: Vnom –50mV
10: Vnom –100mV
11: Vnom – 150mV
am
lc s
on A
te G
nt
st
il
lv
al
id
Bit
Te
ch
ni
ca
The register is R/W; default value is 20h
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6.13 Charger
6.13.1 General
This block can be used to charge a 4V Li-Io accumulator. It supports constant current and constant voltage charging modes with
adjustable charging currents (50 to 400mA) and maximum charging voltage (3.9 to 4.25V).
6.13.2 Trickle Charge
al
id
If the battery voltage is below 3V, the charger goes automatically in trickle charge mode with 50mA charging current and 3.9V endpoint
voltage. In this mode charging current and voltage are not precise, but provide a charger function also for deep discharged batteries. Also
the temperature supervision
6.13.3 Temperature Supervision
This charger block also features a supply for an external 100k NTC resistor to measure the battery temperature while charging. If the
temperature is too high, an interrupt can be generated.
Table 39 Charger Parameter
I CHG_trick
V CHG_trick
I CHG (0-7)
Parameter
Notes
Charging Current
(trickle charge)
Charger Endpoint Voltage
(trickle charge)
Charging Current
BVDD<=3V, CHG_IN = 4.5V - 5.5V
Min
25
Typ
Max
Unit
50
100
mA
0.72*
CHG_IN
I NOM
4.1
V
I NOM
+20%
V NOM
+30mV
4.0
240
mA
am
lc s
on A
te G
nt
st
il
Symbol
lv
6.13.4 Parameter
BVDD<=3V, CHG_IN = 4.5V
BVDD > 3V, I CHG = 150 – 400mA
V CHG (0-7) Charging Voltage
BVDD > 3V, end of charge is true
V ON_ABS
V ON_REL
V OFF_REL
V BATEMP_ON
V BATEMP_OFF
I CHG_OFF
Charger On Voltage IRQ
Charger On Voltage IRQ
Charger Off Voltage IRQ
Battery Temp. high level
Battery Temp. low level
End Of Charge current level
BVDD = 3V
CHG_IN-CHG_OUT
CHG_IN-CHG_OUT
BVDD >3V
BVDD >3V
BVDD >3V
I REV_OFF
Reverse current shut down
CHG_OUT = 5V, CHG_IN = VSS
I NOM
-20%
V NOM
-60mV
40
380
480
V NOM
3.1
170
77
400
500
10%
I NOM
<1
420
520
V
V
mV
mV
mV
mV
mA
uA
Te
ch
ni
ca
BVDD=3.6V; Tamb=25ºC; unless otherwise specified
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6.13.5 Register Description
End of charge and battery over-temperature interrupts can be generated with the corresponding bits in the IRQ_ENRD0 register (0x25h).
Also the status of the charger (supply present or not) can be monitored via this register and if needed an interrupt is generated on a status
change.
All other charger functions are controlled in the following register.
Charger Register (22h)
Description
7
TMPSup_off
6..4
CHG_I
3..1
CHG_V
0
CHG_OFF
0: enables supply for external 100k NTC resistor
1: disables supply
set maximum charging current
111: 400 mA
110: 350 mA
..
001: 100 mA
000: 50 mA
set maximum charger voltage
111: 4.25 V
110: 4.2 V
..
001: 3.95 V
000: 3.9 V
0: enables Charger
1: disables Charger
lv
Name
am
lc s
on A
te G
nt
st
il
Bit
al
id
Table 40 Charger Register
Te
ch
ni
ca
The register is R/W; default value is 00h
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AS3515 V15
Data Sheet, Confidential
6.14 15V Step-Up Converter
6.14.1 General
The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 15V. A
constant switching-frequency results in a low noise on supply and output voltages.
It has an adjustable sink current (1.25 to 38.75mA) to provide e.g. dimming function when driving white LEDs as back-light.
Figure 16 15V Step-Up converter Block Diagram
Clock
Generation
DRIVER
NMOS
15V
Power
Device
0.85Ω typ.
am
lc s
on A
te G
nt
st
il
lv
PWM-LOGIC
SW15
al
id
BVDD
Σ
Pulse-Skip
Comparator
Ramp
Generatio
n
Current
Sense
VSS15
1.33V
ISINK
0.83V
Error
Amplifier
1.25 37.5 mA
VSS15
VSS
6.14.2 Parameter
ca
Table 41 15V Step-Up Converter Parameter
Symbol
Parameter
V PULSESKIP
High Voltage Pin
Quiescent Current
Feedback Voltage, Transient
Feedback Voltage, during
Regulation
Current Limit
Switch Resistance
Load Current
Pulse-skip Threshold
F IN
C OUT
L (Inductor)
Fixed Switching Frequency
Output Capacitor
I LOAD > 20mA
Te
ch
I SW_MAX
R SW
I LOAD
ni
V SW
I VDD
V FB
V FB
Notes
Min
Pin SW15
Pulse Skipping mode
Pin ISINK
Pin ISINK
V15_ON = 1
V15_ON = 0
@ 15V output voltage
Voltage at pin ISINK, pulse skips are
introduces when load current becomes
too low.
Ceramic
Use inductors with small C PARASITIC
(<100pF) for high efficency
I LOAD < 20mA
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Typ
0
Max
Unit
15
V
µA
V
V
140
0
5.5
0.83
510
0.85
mA
1.33
Ω
mA
V
17
0.6
1
22
27
MHz
µF
µH
8
10
27
0
38.75
40 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
Symbol
Parameter
t MIN_ON
MDC
Notes
Minimum On-Time
Maximum Duty Cycle
Min
Guaranteed per design
90
88
Typ
Max
Unit
91
180
94
ns
%
BVDD=3.6V; Tamb=25ºC; unless otherwise specified
am
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Figure 17 15V Step-Up Performance Characteristics
6.14.3 Register Description
All functions can be controlled via the following register.
DCDC15 Register (23h)
Table 42 DCDC15 Register
Name
7..5
4..0
Reserved
I_V15<4..0>
Description
For testing purpose only, must be set to 0h
Defines the current through the LED = 1.25mA * I_V15
00000: off
00001: 1.25mA
00010: 2.5mA
..
11110: 37.5mA
11111: 38.75mA
ni
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Bit
Te
ch
The register is R/W; default value is 00h
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6.15 Supervisor
6.15.1 General
This supervisor function can be used for automatic detection of BVDD brown out or junction over-temperature condition.
6.15.2 BVDD Supervision
The supervision level can be set in 8 steps @ 60mV from 2.74 to 3.16V. If the level is reached an interrupt can be generated. If BVDD
reaches 2.6V the AS3515 shuts down automatically.
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6.15.3 Junction Temperature Supervision
The temperature supervision level can also be set by 5 bits (120 to –15oC). If the temperature reaches this level, an interrupt can be
generated. The over-temperature shutdown level is always 20oC higher. If the IRQ level is set to 120oC the shutdown is disabled.
6.15.4 Register Description
lv
Interrupts for battery supervision has to be enabled in the IRQ_ENRD0 register (0x25h), while the over-temperature interrupt is controlled
via the IRQ_ENRD1 register (0x26h). All other functions can be set via the following register.
SUPERVISOR Register (24h)
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Table 43 Supervisor Register
Bit
Name
7..5
BVDD_Sup<2:0> Supervision of BVDD brown out
V_BrownOut=2.74+x*60mV
000: 2.74V
001: 2.80V
…
110: 3.10V
111: 3.16V
JT_Sup<4:0>
Junction temperature supervision:
Temp_ShutDown=140-x*5°C
Temp_IRQ=120-x*5°C
4..0
Description
JT_Sup
00000
00001
00010
:
11110
11111
IRQ ShutDown
120oC
115oC
110oC
:
-30oC
-35oC
OFF
135oC
130oC
:
-10oC
-15oC
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The register is R/W; default value is 00h
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6.16 Interrupt Generation
6.16.1 General
All interrupt sources can get enabled or disabled by corresponding bits in the 3 IRQ-bytes. By default no IRQ source is enabled.
The IRQ output can get configured to be PUSH/PULL or OPEN_DRAIN and ACTIVE_HIGH or ACTIVE LOW with 2 bits in IRQ_ENRD2
register (0x27h). Default state is push/pull and active_high.
6.16.2 IRQ Source Interpretation
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There are 3 different modules to process interrupt sources:
LEVEL
The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled
EDGE
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The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read.
STATUS CHANGE
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The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source.
The IRQ stays active until the corresponding interrupt register gets read.
6.16.3 De-bouncer
There is a de-bouncer function implemented for USB and CHARGER. Since these 2 signals can be unstable for the phase of plug-in or
unplug, a de-bounce time of 512ms/256ms/128ms/0ms can be selected by 2 bits in the IRQ_ENRD2 register (0x27h).
6.16.4 Register Description
First Interrupt Register (25h)
Table 44 IRQ_ENRD0 Register
Name
7
6
CHG_tmphigh
CHG_endofch
Int. Type
5
4
3
2
1
CHG_status
CHG_changed
USB_status
USB_changed
RVDD_waslow
0
BVDD_islow
Description
Level
Edge
1: battery temperature was too high and the charger was turned off
1: charging is complete, turn charger off
After turning off the charger, IRQ will be released.
1: charger connected, also valid if charger is connected during wakeup
Status change 1: charger status changed, check CHG_status
1: USB connected, also valid if USB is connected during wakeup
Status change 1: USB status changed, check UB_status
Level
1: if RTC supply was low, RTC not longer valid
IRQ will be released by any I2C action.
Level
1:BVDD has reached brown out level
ca
Bit
ni
The register is R/W; default value is 00h
Te
ch
By writing to the register the corresponding interrupt is enabled, reading the register delivers the interrupt source.
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Second Interrupt Register (26h)
Table 45 IRQ_ENRD1 Register
Bit
Name
Int. Type
7
6
5
4
3
2
JTEMP_high
LSP_overcurr
HPH_overcurr
I2S_status
I2S_changed
MIC2_connect
Level
Level
Level
1
MIC1_connect
0
HPH_connect
Description
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1: Junction temperature has reached supervision level
1: LSP output is in over-current off mode
1: HPH output is in over-current off mode
1: LRCK of I2S interface is present
Status change 1: I2S LRCK clock was started or stopped, check I2S_status
Level
1: Microphone was connected to MIC port 2
IRQ will be released after enabling the microphone stage.
Detecting a microphone during operation has to be done by measuring the supply
current.
Level
1: Microphone was connected to MIC port 1
IRQ will be released after enabling the microphone stage.
Detecting a microphone during operation has to be done by measuring the supply
current.
Level
1: Headphone was connected to HHP port
IRQ will be released after enabling the headphone output.
Detecting a headphone during operation is not possible.
The register is R/W; default value is 00h
By writing to the register the corresponding interrupt is enabled, reading the register delivers the interrupt source.
Third Interrupt Register (27h)
Table 46 IRQ_ENRD2 Register
Bit
Name
7..6
T_deb<1:0>
5
IRQ_Acthigh
4
IRQ_PushPull
3
Remote_Det2
2
Remote_Det1
1
0
RTC_update
ADC_EndCon
Int. Type
Description
-
USB and charger de-bounce time control
00: 512ms
01: 256ms
10: 128ms
00: not defined
1: IRQ is active high
0: IRQ is active low
1: IRQ output is push pull
0: IRQ output is open drain
1: Mic2 supply current got increased, Remote detection Î measure Mic2 supply
current
1: Mic1 supply current got increased, Remote detection Î measure Mic1 supply
current
1: RTC timer IRQ occured
1: 8-bit ADC conversion completed
-
-
Edge
ca
Edge
ni
Edge
Edge
The register is R/W; default value is 00h
Te
ch
By writing to bit 0 to 3, the corresponding interrupt is enabled, reading these bits delivers the interrupt source.
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6.17 Real Time Clock
6.17.1 General
The real time clock block is an independent block, which is still working even the AS3515, is shut down. The block uses a standard 32kHz
crystal that is connected to a low power oscillator. An internal 32bit second register stores the current time.
The RTC block has special functions for trimming the time base and generating interrupts every second or minute.
6.17.2 RTC supply
If the supply voltage on RTCSUP pin rises, the whole AS3515 gets powered up.
6.17.3 Register Description
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The internal RTC is supplied via the RTCSUP pin. The block has an internal LDO to generate the RTC supply voltage on RVDD pin. This
voltage can be programmed via the RTCV register (0x28h). If the internal RTC is not used, RVDD can be used to supply an external RTC
block.
lv
A RTCSUP low condition can be signalled by an interrupt request, if the corresponding bit in the IRQ_ENRD0 register (0x25h) is set. To
get a second or minute interrupt the enable bit in IRQ_ENRD2 register (0x27h) All other RTC functions can be controlled and accessed
via the following registers.
Table 47 RTCV Register
Bit
Name
7..4
VRTC<3..0>
3,2
1
Reserved
RTC_ON
0
OSC_ON
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RTCV Register (28h)
Description
Sets the RTC supply voltage, 16 steps @ 0.1V, default is 1.2V
0000: 1V
0001: 1.1V
0010: 1.2V
…
1110: 2.4V
1111: 2.5V
For testing purpose only, must be set to 0h
0: Disable clock for RTC
1: Enables clock for RTC
0: Disables RTC oscillator
1: Enables RTC oscillator
Te
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The register is R/W; default value is 23h
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RTCT Register (29h)
Bit
Name
Description
7
IRQ_MIN
6..0
TRTC<6..0>
0: generates an interrupt every second
1: generates an interrupt every minute
Trimming register for RTC, 128 steps @ 7.6ppm
000000: 1 (7.6ppm)
000001: 2 (15.2ppm)
…
100000: 64 (488ppm)
…
111110: 126 (960.8ppm)
111111: 127 (968.4ppm)
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Table 48 RTCT Register
RTC Registers (2Ah to 2Dh)
Table 49 RTC_0 to RTC_3 Register
lv
The register is R/W; default value is 40h
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
2Ah
2Bh
2Ch
2Dh
RTC_0
RTC_1
RTC_2
RTC_3
Qrtc<7>
Qrtc<15>
Qrtc<23>
Qrtc<31>
Qrtc<6>
Qrtc<14>
Qrtc<22>
Qrtc<30>
Qrtc<5>
Qrtc<13>
Qrtc<21>
Qrtc<29>
Qrtc<4>
Qrtc<12>
Qrtc<20>
Qrtc<28>
Qrtc<3>
Qrtc<11>
Qrtc<19>
Qrtc<27>
Qrtc<2>
Qrtc<10>
Qrtc<18>
Qrtc<26>
Qrtc<1>
Qrtc<9>
Qrtc<17>
Qrtc<25>
Bit 0
Description
Qrtc>0>
Qrtc<8>
Qrtc<16>
Qrtc<24>
second
second
second
second
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Addr
register
register
register
register
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The registers are R/W; default value is 00h
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6.18 10-Bit ADC
6.18.1 General
This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature
supervision, button press detection, etc..
6.18.2 Input Sources
Table 50 ADC10 Input Sources
Source
Range
LSB
Description
0
1
2
3
4
5
6
BVDD
RTCSUP
UVDD
CHG_IN
CVDD
BatTemp
MicSup1
5.120V
5.120V
5.120V
5.120V
2.560V
2.560V
2.560V
5mV
5mV
5mV
5mV
2.5mV
2.5mV
2.5mV
7
MicSup2
2.560V
2.5mV
8
9
10
11
12
13..15
VBE1
VBE2
I_MicSup1
I_MicSup2
VB1V
Reserved
check battery voltage of 4V LiIo accumulator
check RTC backup battery voltage
check USB host voltage
check charger input voltage
check charge pump output voltage
check battery charging temperature
check voltage on MicSup1 for remote control or external voltage
measurement
check voltage on MicSup2 for remote control or external voltage
measurement
measuring junction temperature @ 2uA
measuring junction temperature @ 1uA
check current of MicSup1 for remote control detection
check current of MicSup2 for remote control detection
check single cell battery voltage
for testing purpose only
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Nr.
1.024
1mV
1.024
1mV
2.048mA typ. 2.0uA
2.048mA typ. 2.0uA
2.560V
2.5mV
1.024V
1mV
BVDD, RTCSUP, UVDD, CHG_IN
These sources are fed into an 1/5 voltage divider (180kΩ typ.) and further amplified by 2.5.
CVDD, BatTemp, MicSup1, MicSup2
These sources are fed directly to the ADC input multiplexer.
VBE1, VBE2
These inputs are first amplified by 2.5 and than fed to the ADC input multiplexer.
ca
I_MicSup1, I_MicSup2
VB1V
ni
The measurement of the microphone supply LDOs is not very accurate, as the current-voltage conversion is only done by a single resistor
which shows wide process and temperature variations. These measurements should be only used for remote function detection.
ch
This source is divided by 2.5 with a voltage divider (180kΩ typ.) and than amplified by 2.5. This has to be done, as VB1V can represent
voltages up to 3.6V. Please note, that the maximum measurement rage will be still 2.560V
6.18.3 Reference
Te
AVDD=2.9V is used as reference to the ADC. AVDD is trimmed to +/-20mV with over all precision of +/-29mV. So the absolute accuracy is
+/-1%.
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6.18.4 Parameter
Table 51 ADC10 Parameter
Parameter
Notes
Min
Typ
Max
Unit
BVDD, RTCSUP, UVDD, CHG_IN,
VB1V
138k
180k
234k
Ω
ADC Full Scale Range
Division Factor 1
BVDD, RTCSUP, UVDD, CHG_IN
Division Factor 2
VB1V
ADC Gain Stage
Conversion Time
I_MicSup1/2 Full Scale Range
2.534
0.198
0.396
2.475
1.4
2.56
0.2
0.4
2.5
34
2
2.586
0.202
0.404
2.525
50
2.8
V
1
1
V
µs
mA
R DIV
Input Divider Resistance
ADC FS
Ratio1
Ratio2
Gain
T CON
I_MIC FS
BVDD=3.6V; Tamb=25ºC; unless otherwise specified
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6.18.5 Register Description
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Symbol
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The conversion gets started by writing to the ADC_0 register (0x2Eh). After finishing the conversion an interrupt request can be generated
if the corresponding bit in the IRQ_ENRD2 register (0x27h) is set. Conversion source and result can be set / read with the following two
registers.
ADC_0 Register (2Eh)
Table 52 ADC_0 Register
Name
7..4
ADC_Source
Description
3,2
1
0
ADC<9>
ADC<8>
0000: BVDD
0001: RTCSUP
0010: UVDD
0011: CHG_IN
0100: CVDD
0101: BatTemp
0110: MicSup1
0111: MicSup2
1000: VBE_1uA
1001: VBE_2uA
1010: I_MicSup1
1011: I_MicSup2
1100: VB1V
1101: reserved
1110: reserved
1101: reserved
Not used
ADC result bit 10
ADC result bit 9
ni
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Bit
Te
ch
The register is R/W; default value is 000000xxb
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ADC_1 Register (2Fh)
Table 53 ADC_1 Register
Name
Description
7
6
5
4
3
2
1
0
ADC<7>
ADC<6>
ADC<5>
ADC<4>
ADC<3>
ADC<2>
ADC<1>
ADC<0>
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
result
result
result
result
result
result
result
result
bit
bit
bit
bit
bit
bit
bit
bit
8
7
6
5
4
3
2
1
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Bit
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The register is R/W; default value is xxh
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6.19 128 bit Fuse Array
6.19.1 General
This fuse array is used to store a unique identification number, which can be used for DRM issues. The number is randomly generated
and programmed during the production process.
6.19.2 Register Description
UID Registers (30h to 3Fh)
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Table 54 UID_0 to UDI15_3 Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
UID_0
UID_1
UID_2
UID_3
UID_4
UID_5
UID_6
UID_7
UID_8
UID_9
UID_10
UID_11
UID_12
UID_13
UID_14
UID_15
ID<7>
ID<15>
ID<23>
ID<31>
ID<39>
ID<47>
ID<55>
ID<63>
ID<71>
ID<79>
ID<87>
ID<95>
ID<103>
ID<111>
ID<119>
ID<127>
ID<6>
ID<14>
ID<22>
ID<30>
ID<38>
ID<46>
ID<54>
ID<62>
ID<70>
ID<78>
ID<86>
ID<94>
ID<102>
ID<110>
ID<118>
ID<126>
ID<5>
ID<13>
ID<21>
ID<29>
ID<37>
ID<45>
ID<53>
ID<61>
ID<69>
ID<77>
ID<85>
ID<93>
ID<101>
ID<109>
ID<117>
ID<125>
ID<4>
ID<12>
ID<20>
ID<28>
ID<36>
ID<44>
ID<52>
ID<60>
ID<68>
ID<76>
ID<84>
ID<92>
ID<100>
ID<108>
ID<116>
ID<124>
ID<3>
ID<11>
ID<19>
ID<27>
ID<35>
ID<43>
ID<51>
ID<59>
ID<67>
ID<75>
ID<83>
ID<91>
ID<99>
ID<107>
ID<115>
ID<123>
ID<2>
ID<10>
ID<18>
ID<26>
ID<34>
ID<42>
ID<50>
ID<58>
ID<66>
ID<74>
ID<82>
ID<90>
ID<98>
ID<106>
ID<114>
ID<122>
ID<1>
ID<9>
ID<17>
ID<25>
ID<33>
ID<41>
ID<49>
ID<57>
ID<65>
ID<73>
ID<81>
ID<89>
ID<97>
ID<105>
ID<113>
ID<121>
ID<0>
ID<8>
ID<16>
ID<24>
ID<32>
ID<40>
ID<48>
ID<56>
ID<64>
ID<72>
ID<80>
ID<88>
ID<96>
ID<104>
ID<112>
ID<120>
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
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The register is read only.
Description
lv
Addr
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byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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6.20 VTRM-LDO
6.20.1 General
This LDO is generating a supply voltage for an external USB 1.1 transceiver out of the 5V USB master supply.
Input Voltage is UVDD (4.5 to 5.5V)
Output Voltage is VTRM (typ. 3.2V)
•
Driver strength: ~10mA
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•
•
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6.21 I2C Control Interface
6.21.1 General
There is an I2C slave block implemented to have access to 64 byte of setting information.
The I2C address is: Adr_Group8 - audioprocessors
•
•
8Ch_write
8Dh_read
RESET
SCL
8 7 6 5 4 3 2 1 A 8 7 6 5 4 3 2 1 A
DeviceWriteAddress 8Ch
Start
Condition
Register Address
Write Data
lv
8 7 6 5 4 3 2 1
SDA
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Figure 18 I2C timing
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Stop
Condition
6.21.2 Parameter
Table 55 I2C Operating Conditions
Symbol
Parameter
VIL
VIH
HYST
VOL
Tsp
Speed
Tsetup
CSCL, CSDA (max 30%DVDD)
CSCL, CSDA (min 70%DVDD)
CSCL, CSDA
CSDA @ 3mA
Spike insensitivity
Frequency at CSCL
Notes
CSDA has to change Tsetup before
rising edge of CSCL
No hold time needed for CSDA relative
to rising edge of CSCL
CSDA H hold time relative to CSDA
edge for start/stop/rep_start
CSDA prop delay relative to lowgoing
edge of CSCL
Thold
TS
ca
Tdata
Min
Typ
Max
Unit
0
2.03
200
50
250
450
100
-
0.87
5.5
800
0.4
400
-
V
V
mV
V
ns
kHz
ns
0
-
-
ns
600
-
-
ns
50
ns
Te
ch
ni
DVDD =2.9V, Tamb=25ºC; unless otherwise specified
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6.21.3 Register Description
Registers Overview (00h to 3Fh)
Table 56 I2C Register Overview
Name
D<5>
D<4>
00h
LINE_OUT_R reserved
-
01h
0
0
LINE_OUT_L LO_SES_DM<1:0>
0
-
02h
0
0
HPH_OUT_R HP_OVC_TO<1:0>
0
-
03h
HPH_OUT_L
0
0
HP_Mute HP_ON
0
HPdetON
04h
LSP_OUT_R
0
0
SP_OVC_TO<1:0>
0
-
05h
LSP_OUT_L
06h
MIC1_R
07h
MIC1_L
08h
MIC2_R
09h
MIC2_L
0Ah
Line_IN1_R
0Bh
Line_IN1_L
0Ch
Line_IN2_R
LOR_Vol<4:0>
Gain from Mixer_Out to Line_Out= (-40.5dB … +6dB)
0
0
0
0
0
LOL_Vol<4:0>
Gain from Mixer_Out to Line_Out= (-40.5dB … +6dB)
0
0
0
0
0
HPR_Vol<4:0>
Gain from Mixer_Out to HPH_Out= (-45.43dB … +1.07dB)
0
0
0
0
0
HPL_Vol<4:0>
Gain from Mixer_Out to HPH_Out= (-45.43dB … +1.07dB)
0
0
0
0
0
SPR_Vol<4:0>
Gain from Mixer_Out to LSP_Out= (-40.5dB … +6.0dB)
0
0
0
0
0
SPL_Vol<4:0>
Gain from Mixer_Out to LSP_Out= (-40.5dB … +6.0dB)
0
0
0
0
0
M1R_Vol<4:0>
Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB)
0
0
0
0
0
M1L_Vol<4:0>
Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB)
0
0
0
0
0
M2R_Vol<4:0>
Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB)
0
0
0
0
0
M2L_Vol<4:0>
Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB)
0
0
0
0
0
LI1R_Vol<4:0>
Gain from LineIn_Pin to Mixer_In=-34.5dB+LI1R_VOL*1.5dB
(-34.5dB … +12dB)
0
0
0
0
0
LI1L_Vol<4:0>
Gain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB)
0
0
0
0
0
LI2R_Vol<4:0>
Gain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB)
0
0
0
0
0
LI2L_Vol<4:0>
Gain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB)
0
0
0
0
0
DAR_Vol<4:0>
Gain from DAC_Out to Mixer_In= (-40.5dB … +6dB)
0
0
0
0
0
DAL_Vol<4:0>
Gain from DAC_Out to Mixer_In= (-40.5dB … +6dB)
0
0
0
0
0
ADR_Vol<4:0>
Gain from ADCMux_Out to ADC_In= (-34.5dB … +12dB)
0
SP_Mute
0
SP_ON
0
M1_AGC
_off
0
M1_Sup
_off
0
M2_AGC
_off
0
M2_Sup
_off
0
-
0
0
M1_Gain<1:0>
ca
0
-
0
0
LI2_Mode<1:0>
Line_IN2_L
0Fh
DAC_L
0
-
10h
ADC_R
Te
DAC_R
0
-
0Eh
0
M2_Mute
_off
0
-
ni
0
-
0
-
0
DAC_Mute
_off
0
0
ADCmux<1:0>
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D<3>
D<2>
D<1>
D<0>
lv
0
-
0
0
M1_Mute _off
0
0
M2_Gain<1:0>
0
0
LI1_Mode<1:0>
ch
0Dh
D<6>
am
lc s
on A
te G
nt
st
il
D<7>
al
id
Addr
0
-
0
LI1R_
Mute_off
0
LI1L_
Mute_off
0
LI2R_
Mute_off
0
LI2L_
Mute_off
0
0
0
-
Revision 3.1
53 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
1Dh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
D<4>
D<3>
D<2>
D<1>
D<0>
0
-
0
0
0
0
0
ADC_L
ADL_Vol<4:0>
Gain from ADCMux_Out to ADC_In= (-34.5dB … +12dB)
0
0
0
0
0
0
AudioSet1
DAC_on LOUT_on
LIN2_on
LIN1_on MIC2_on
MIC1_on
0
0
0
0
0
0
AudioSet2
AGC_off IBR_DAC<1:0>
LSP_LP IBR_LSP<1:0>
0
0
0
0
0
0
AudioSet3
ZCU_OFF IBR_HPH
HPCM_off
0
0
0
0
0
0
PLL_MODE
PLLmode<2:0>
0
0
0
0
0
0
SYSTEM
PVDDp
CVDDp
EnWDogPw PwrUPHld
dn
0
1
0
0
0
0
0
1
CVDD/DCDC3 CP_SW
CP_on
LREG_ DCDC3p<1:0>
LREG_off CVDDp<1:0>
CPnot
0
0
1
0
0
0
0
0
CHARGER
TmpSup_ CHGI<2:0>
CHGV<2:0>
CHG_off
off
0
0
0
0
0
0
0
0
DCDC15
For testing purpose only, must
I_V15<4:0>
be set to 0h
0
0
0
0
0
0
0
0
SUPERVISOR
BVDD_Sup<2:0>
JT_Sup<4:0>
0
0
0
0
0
0
0
0
IRQ_ENRD0 CHG
CHG
CHG
CHG
USB
USB
RVDD
BVDD
tmphigh
endofch status
changed
status
changed was low
Is low
0
0
0
0
0
0
0
0
IRQ_ENRD1 JTEMP
LSP
HPH
I2S
I2S
Mic2
Mic1
HeadPh
high
overcurr overcurr status
changed
connect
connect
Connect
0
0
0
0
0
0
0
0
IRQ_ENRD2 T_deb<1:0>
IRQ_ActH IRQ_PushP Remote_Det Remote_D RTC_Updat ADC_EndCo
igh
ull
2
et1
e
n
0
0
0
0
0
0
0
0
RTCV
VRTC<3:0>
For testing purpose
RTC_ON
OSC_ON
only, must be set to 0h
0
0
1
0
0
0
1
1
RTCT
IRQ_MIN
TRTC<6:0>
0
1
0
0
0
0
0
0
RTC_0
Qrtc<7:0>
0
0
0
0
0
0
0
0
RTC_1
Qrtc<15:8>
0
0
0
0
0
0
0
0
RTC_2
Qrtc<23:16>
0
0
0
0
0
0
0
0
RTC_3
Qrtc<31:24>
0
0
0
0
0
0
0
0
ADC_0
ADC_Source<3:0>
ADC<9:8>
0
0
0
0
0
0
X
X
ADC_1
ADC<7:0>
X
X
X
X
X
X
X
X
UID_0 .. 15
ID<7:0>
…
ID>127:120>
ch
2Ch
D<5>
al
id
16h
0
ADC_Mute
_off
0
0
ADC_on SUM_on
0
0
BIAS_off DITH_off
0
0
0
0
0
0
Design_Version<3:0>
lv
15h
D<6>
0
AD_FS2
am
lc s
on A
te G
nt
st
il
14h
D<7>
ca
11h
Name
ni
Addr
2Dh
Te
2Eh
2Fh
30-3F
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Revision 3.1
54 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
7 Electrical Specification
Table 57 Audio Parameter
Notes
Min
R L = 16Ω
A-weighted, no load, silence input
A-weighted, no load, -60dB FS 1kHz
input
no load, 1kHz FS input
SNR
DR
Signal to Noise Ratio
Dynamic Range
THD
Total Harmonic Distortion
SINAD
Pout=20mW, R L = 32Ω, f=1kHz FS input
Pout=40mW, R L = 16Ω, f=1kHz FS input
Signal to Noise and Distortion A-weighted, no load, 1kHz FS input
CS
Channel Separation
Signal to Noise Ratio
Dynamic Range
THD
Total Harmonic Distortion
ni
SNR
DR
R L = 32Ω, 1kHz 1V RMS (FS) input
R L = 16Ω, 1kHz 1V RMS (FS) input
A-weighted, no load, silence input
A-weighted, no load, -60dB FS 1kHz
(FS) input
no load, 1kHz 1V RMS input
ch
Pout=20mW, R=32Ω, 1kHz 1V RMS (FS)
input
Pout=40mW, R=16Ω, 1kHz 1V RMS (FS)
input
Signal to Noise and Distortion A-weighted, no load, 1kHz 1V RMS input
Te
CS
A-weighted,Pout=20mW, R L = 32Ω,
f=1kHz FS input
A-weighted,Pout=40mW, R L = 16Ω,
f=1kHz FS input
R L = 32Ω
R L = 16Ω
ca
Line Input to HP Output
FS
Full Scale Output
SINAD
Max
Channel Separation
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A-weighted, Pout=20mW, R=32Ω, 1kHz
1V RMS (FS) input
A-weighted, Pout=40mW, R=16Ω, 1kHz
1V RMS (FS) input
R L = 32Ω
R L = 16Ω
Revision 3.1
Unit
0.985
92
89
V RMS
dB
dB
-90
83
dB
dB
0.95
93
-85
80
89
V RMS
dB
dB
dB
dB
am
lc s
on A
te G
nt
st
il
1kHz FS input
A-weighted, no load, silence input
A-weighted, no load, -60dB FS 1kHz
input
THD
Total Harmonic Distortion
1kHz FS input
SINAD
Signal to Noise and Distortion A-weighted, 1kHz FS input
Line Input to Line Output
FS
Full Scale Output
1kHz 1V RMS (FS) input
SNR
Signal to Noise Ratio
A-weighted, no load, silence input
THD
Total Harmonic Distortion
1kHz 1V RMS (FS) input
SINAD
Signal to Noise and Distortion A-weighted, 1kHz FS input
CS
Channel Separation
DAC Input to HP Output
FS
Full Scale Output
R L = 32Ω
Typ
al
id
Parameter
DAC Input to Line Output
FS
Full Scale Output
SNR
Signal to Noise Ratio
DR
Dynamic Range
lv
Symbol
0.950
0.944
94
90
V RMS
V RMS
dB
dB
-90
-73
-66
84
73
dB
dB
dB
dB
dB
66
-60
dB
73
67
dB
dB
0.930
0.929
96
95
V RMS
V RMS
dB
dB
-85
-75
dB
dB
-68
-60
dB
84
73
dB
dB
68
dB
73
68
dB
dB
55 - 66
austriamicrosystems
SNR
THD
Signal to Noise Ratio
Total Harmonic Distortion
R L = 32Ω, 1kHz 1V RMS (FS) input
R L = 16Ω, 1kHz 1V RMS (FS) input
R L = 4Ω, 1kHz 1V RMS (FS) input
A-weighted, no load, silence input
no load, 1kHz 1V RMS (FS) input
V RMS
V RMS
V RMS
dB
dB
dB
dB
dB
-58
85
77
dB
dB
dB
71
dB
60
dB
60
dB
81
80
dB
dB
-62
61
dB
dB
83
82
dB
dB
-62
61
dB
dB
am
lc s
on A
te G
nt
st
il
R=32Ω, 1kHz 1V RMS (FS) input
R=16Ω, 1kHz 1V RMS (FS) input
R=4Ω, 1kHz 1V RMS (FS) input,
BVDD=5V
R=4Ω, 1kHz 0.7V RMS (FS) input,
BVDD=4V, bias reduction on
SINAD
Signal to Noise and Distortion A-weighted, no load, 1kHz 1V RMS (FS)
input
A-weighted, R=32Ω, 1kHz 1V RMS (FS)
input
A-weighted, R=16Ω, 1kHz 1V RMS (FS)
input
A-weighted, R=4Ω, 1kHz 1V RMS (FS)
input, BVDD=5V
CS
Channel Separation
R L = 32Ω
MIC Input to ADC Output
SNR
Signal to Noise Ratio
A-weighted, no load, silence input
DR
Dynamic Range
A-weighted, no load, -60dB FS 1kHz
input
THD
Total Harmonic Distortion
1kHz 27mV RMS (-3dB FS) input
SINAD
Signal to Noise and Distortion A-weighted, 1kHz 27mV RMS (-3dB FS)
input
Line Input to ADC Output
SNR
Signal to Noise Ratio
A-weighted, no load, silence input
DR
Dynamic Range
A-weighted, no load, -60dB FS 1kHz
input
THD
Total Harmonic Distortion
1kHz 1V RMS (-3dB FS) input
SINAD
Signal to Noise and Distortion A-weighted, 1kHz 1V RMS (-3dB FS) input
1.036
1.023
0.950
91
-88
-78
-71
-60
al
id
DAC to SP Output
FS
Full Scale Output
lv
AS3515 V15
Data Sheet, Confidential
Te
ch
ni
ca
BVDD = 3.3V, TA= 25oC, fs=48kHz, RL= 10kΩ unless otherwise mentioned
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Revision 3.1
56 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
8 Pinout and Packaging
8.1
Pin Description
Table 58 Pinlist CTBGA64 & LQFP64
Function
1
CVDD
Aout
ChargePump Output for CPU supply progr. 0.85-1.8V
2
VB1V
Supply
Battery supply input for single cell application
3
CP
Ai/o
ChargePump flying cap
4
CN
Ai/o
ChargePump flying cap
5
VSSCP
Supply
ChargePump Neg. Supply terminal
6
VSS3
Supply
DCDC3V Neg. Supply terminal
7
SW3
Aout
DCDC3V Switch terminal
8
SW15
Aout
DCDC15V Switch terminal
A1
B1
C3
C2
D2
C1
D1
D4
E1
D3
E2
E3
F1
F2
G1
G2
H1
H2
F3
9
VSS15
Supply
DCDC15V Neg. Supply terminal
10
ISINK
Aout
DCDC15V Load Current Sink terminal
G3
20
G4
21
H3
22
H4
23
E4
24
H5
F4
G5
F5
H6
G6
H7
G7
H8
G8
F6
F7
E7
F8
E8
E5
D8
E6
25
12
13
14
DVSS
Supply
Digital Circuit Neg. Supply terminal
BATTEMP
Ai/o
Charger Battery Temperature Sensor input (RNTC 100k)
VTRM
Aout
USB1.1 VTRM Regulator output 3.25V
USB1.1 USB supply input
am
lc s
on A
te G
nt
st
il
11
UVDD
Ain
CHGOUT
Aout
Charger Output prog. Ichg 50-400mA Vchg 3.9-4.25V
CHGIN
Ain
Charger Input
P_PVDD
Ain
5 State Prog Input of PVDD regulator
P_CVDD
Ain
5 State Prog Input of CVDD regulatro
PWR_UP
Power Up input
SDO
Din
Pull_dn
Di/o
pull_up
Din
pull_up
Din
pull_dn
Din
pull_dn
Din
pull_dn
Dout
PWGOOD
Dout
Goes high when power up sequence is completed (XRES)
IRQ
Dout
Interrupt Request Output
28
DVDD
Supply
Digital Circuit Pos. Supply terminal to be connected to QLDO2
29
XOUT
Ai/o
32kHz RTC Oscillator Crystal terminal
30
RVDD
Aout
RTC Supply Regulator Output prog. to 1.0-2.5V
31
XIN
Ai/o
32kHz RTC Oscillator Crystal terminal
32
RTCSUP
Supply
RTC Pos. Supply terminal 5.5V max
33
MIC1SUP
Ai/o
Microphone Supply 1 (2.95V) / Remote Input 1
34
MIC1N
Ain
Microphone Input 1N
35
MIC1P
Ain
Microphone Input 1P
15
16
17
18
19
CSDA
CSCL
LRCK
SCLK
SDI
ca
26
ch
ni
27
Te
al
id
PinName Type
lv
CTBGA64 LQFP64
ball #
pin #
Data I/O of two wire interface
Clock Input of two wire interface
I2S Left/Right Clock
I2S Shift Clock
I2S Data Input to DAC
I2S Data output from ADC
36
MIC2P
Ain
Microphone Input 2P
37
MIC2N
Ain
Microphone Input 2N
38
MIC2SUP
Ai/o
Microphone Supply 2 (2.95V) / Remote Input 2
39
LIN1R
Ain
Line Input 1 Right Channel
40
LIN1L
Ain
Line Input 1 Left Channel
41
LIN2R
Ain
Line Input 2 Right Channel
42
LIN2L
Ain
Line Input 2 Left Channel
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Revision 3.1
57 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
CTBGA64 LQFP64
ball #
pin #
PinName Type
Function
Ai/o
Analog Reference (AVDD/2) decoupling cap terminal (10uF)
43
AGND
44
VREF
Ai/o
Analog Reference ( filtered AVDD) decoupling cap terminal (10uF)
45
AVSS
Supply
Analog Circuit Neg Supply terminal
46
LOUT_R
Aout
Line Output Right Channel / Ear Piece diff output N
B8
B7
A8
A7
C6
B6
B5
A6
A5
D5
A4
C5
B4
C4
A3
B3
A2
B2
B2
47
LOUR_L
Aout
Line Output Left Channel / Ear Piece diff output P
48
AVDD
Supply
Analog Circuit Pos. Supply terminal
49
HPGND
Ai/o
Headphone Amplifier Reference decoupling cap terminal (100nF)
50
BVSS2
Supply
Headphone Amplifier Neg. Supply terminal
51
HPH_CM
Aout
Headphone Common GND Output for DC-coupled speakers
52
BVDD
Supply
Pos. Supply Terminal 5.5V max.
53
HPH_R
Aout
Headphone Output Right Channel
54
BVSS2
Supply
Headphone Amplifier Neg. Supply terminal
55
HPH_L
Aout
Headphone Output Left Channel
56
BGND
Ai/o
Loudspeaker Amplifier Reference decoupling cap terminal (100nF)
57
BVDD
Supply
Pos. Supply Terminal 5.5V max.
58
LSP_R
Aout
Loudspeaker Output Right Channel
59
BVSS
Supply
Loudspeaker Amplifier Neg. Supply terminal
LSP_L
Aout
Loudspeaker Output Left Channel
BVDD
Supply
Pos. Supply Terminal 5.5V max.
61
62
63
64
lv
QLDO2
Aout
LDO2 Regulator Output fixed 2.9V to be connected to DVDD
PVDD
Aout
LDO3 Regulator Output prog. to 1.7-3.3V
CPVDD
Aout
LDO4 Regulator Output limiter to 3.56V as ChargePump Input
CPVDD
Aout
LDO4 Regulator Output limiter to 3.56V as ChargePump Input
Te
ch
ni
ca
64
am
lc s
on A
te G
nt
st
il
60
al
id
D7
D6
C8
C7
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Revision 3.1
58 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
8.2
Ball & Pin Assignment
8.2.1
CTBGA64
Figure 19 Ball Assignment CTBGA64
2
3
4
5
6
7
8
A
CVDD
PVDD
BVDD
BVDD
HPH_L
BVSS2
BVSS2
HPGND
B
VB1V
CPVDD
QLDO2
BVSS
HPH_R
BVDD
AVDD
LOUT_L
C
VSS3
CN
CP
LSP_L
LSP_R
HPH_CM
LOUT_R
AVSS
D
SW3
VSSCP
ISINK
SW15
BGND
VREF
AGND
LIN2R
E
VSS15
DVSS
BATTEMP
SDI
LIN1L
LIN2L
MIC2N
LIN1R
F
VTRM
UVDD
PWR_UP
PWGOOD
DVDD
MIC1P
MIC2P
MIC2SUP
G
CHGOUT
CHGIN
CSDA
CSCL
IRQ
RVDD
RTCSUP
MIC1N
H
P_PVDD
P_CVDD
LRCK
SCLK
SDO
XOUT
XIN
MIC1SUP
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
1
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Revision 3.1
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austriamicrosystems
AS3515 V15
Data Sheet, Confidential
8.2.2
LQFP64
49
al
id
CPVDD
PVDD
QLDO2
BVDD
LSP_L
BVSS
LSP_R
BVDD
BGND
HPH_L
BVSS2
HPH_R
BVDD
HPH_CM
BVSS2
HPGND
Figure 20 Pin Assignment LQFP64
AVDD
LOUT_L
LOUT_R
AVSS
VREF
AGND
LIN2L
LIN2R
LIN1L
LIN1R
MIC2SUP
MIC2N
MIC2P
MIC1P
MIC1N
MIC1SUP
am
lc s
on A
te G
nt
st
il
lv
1
33
Te
ch
ni
ca
P_PVDD
P_CVDD
PWR_UP
CSDA
CSCL
LRCK
SCLK
SDI
SDO
PWGOOD
IRQ
DVDD
XOUT
RVDD
XIN
RTCSUP
17
CVDD
VB1V
CP
CN
VSSCP
VSS3
SW3
SW15
VSS15
ISINK
DVSS
BATTEMP
VTRM
UVDD
CHGOUT
CHGIN
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Revision 3.1
60 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
8.3
Package Drawings and Marking
8.3.1
CTBGA64
Table 59 Package Code AYWWZZZ
Y
Year
WW
Working week assembly/packaging
PZZ
Free choice
lv
A
A … for PB free
al
id
Figure 21 CTBGA64 Marking
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
Figure 22 CTBGA64 7x7mm 0.8mm pitch
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Revision 3.1
61 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
8.3.2
LQFP64
Table 60 Package Code AYWWZZZ
A
A … for PB free
Y
Year
WW
Working week assembly/packaging
SZZ
Free choice
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
Figure 24 LQFP 10x10mm 0.5mm pitch
al
id
Figure 23 LQFP64 Marking
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Revision 3.1
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austriamicrosystems
AS3515 V15
Data Sheet, Confidential
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Figure 25 Reel Specification
www.austriamicrosystems.com
Revision 3.1
63 - 66
www.austriamicrosystems.com
2.0
•See N ote 6
5.6
Ao =
Bo =
Ko =
K1 =
7.3 m m
7.3 m m
2.1 m m
1.25 m m
4.0
•See N ote 1
Ø 1.5 +0.1/-0.0
Revision 3.1
Ko
R 0.5
Ao
N otes:
1.10 sprockethole pitch cum ulative tolerance ±.02.
2.C am bernotto exceed 1m m in 100m m .
3.M aterial:PS + C .
4.Ao and Bo m easured on a plane 0.3m m above
the bottom ofthe pocket
5.Ko m easured from a plane on the inside bottom of
the pocketto the top surface ofthe carrier.
6.Pocketposition relative to sprockethole m easured as
true position ofpocket,notpockethole.
1.7
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NO .
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16.0 ± 0.3
D ESC R IPTIO N
DATE
D ATE
3:1
T-8152
11/16/98
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AS3515 V15
Data Sheet, Confidential
austriamicrosystems
Figure 26 CTBGA64 Tape Specification
64 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
9 Ordering Information
Description
Delivery Form
AS3515 V15 CTBGA64 LF T&R
Tape&Reel dry
pack
AS3515E-ELQP
AS3515 V15 LQFP64 LF T&R
Tape&Reel dry
pack
AS3515E-ECTS
AS3515 V15 CTBGA64 LF TRA
Tray dry pack
64-ball CTBGA
0.8mm pitch
(7mm x 7mm)
64-pin LQFP
0.5mm pitch
(10mm x 10mm)
64-ball CTBGA
0.8mm pitch
(7mm x 7mm)
pcs/reel
2250
1000
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AS3515E-ECTP
Package
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Model
www.austriamicrosystems.com
Revision 3.1
65 - 66
austriamicrosystems
AS3515 V15
Data Sheet, Confidential
10 Copyright
Copyright © 1997-2008, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks
Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner.
All products and companies mentioned are trademarks of their respective companies.
11 Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or
regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change
specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check
with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications
requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifesupport or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each
application.
am
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG
shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of
profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or
arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall
arise or flow out of austriamicrosystems AG rendering of technical or other services.
12 Contact Information
Headquarters:
austriamicrosystems AG
Business Unit Communications
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 0
F. +43 (0) 3136 5692
[email protected]
For Sales Offices, Distributors and Representatives, please visit:
ch
ni
ca
www.austriamicrosystems.com
– a leap ahead in analog
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austriamicrosystems
www.austriamicrosystems.com
Revision 3.1
66 - 66