16 Me g FPM DRAM Meg AS4LC4M4 Austin Semiconductor, Inc. 4M x 4 CMOS DRAM PIN ASSIGNMENT (Top View) WITH FAST PAGE MODE, 3.3V AVAILABLE AS MILITARY SPECIFICATIONS • MIL-STD-883 FEATURES • Fast Page Mode Operation • CAS\-before-RAS\ Refresh Capability • RAS\-only and Hidden Refresh Capability • Self-refresh Capability • Fast Parallel Test Mode Capability • TTL Compatible Inputs and Outputs • Early Write or Output Enable Controlled Write • JEDEC Standard Pinout • Single +3.3V (±10%) Power Supply OPTIONS • Timing 60ns access 70ns access • Package Plastic TSOP, 24-pin • Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) Vcc DQ0 DQ1 W\ RAS\ NC 1 2 3 4 5 6 24 23 22 21 20 19 Vss DQ3 DQ2 CAS\ OE\ A9 A10 A0 A1 A2 A3 Vcc 7 8 9 10 11 12 18 17 16 15 14 13 A8 A7 A6 A5 A4 Vss MARKINGS -6 -7 PIN ASSIGNMENT DG XT IT GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS4C4M4DG is a 4,194,304 x 4 bit Fast Page Mode CMOS DRAM offering high speed random access of memory cells within the same row. This device features a +5V (±10%) power supply, refresh cycle (2K), and fast access times (60 and 70ns). Other features include CAS\-before-RAS\, RAS\-only refresh, selfrefresh operation (128ms refresh period), and Hidden refresh capabilities. This 4M x 4 Fast Page Mode DRAM is fabricated using an advanced CMOS process to realize high bandwidth, low power consumption and high reliability. It may be used as main memory for high level computers, microcomputers and personal computers. PIN A0 - A10 FUNCTION Address Inputs DQ0 -DQ3 Data In/Out VSS Ground RAS\ Row Address Strobe CAS\ Column Address Strobe W\ Read/Write Input OE\ Data Output Enable VCC Power (+5V) NC No Connect ACTIVE POWER DISSIPATION SPEED -6 -7 2K 550 UNITS mW mW PERFORMANCE RANGE For more products and information please visit our web site at www.austinsemiconductor.com AS4LC4M4 Rev. 0.3 7/06 SPEED -6 -7 tRAC 60 tCAC 15 tRC 110 tPC 40 UNITS ns ns Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 16 Me g FPM DRAM Meg AS4LC4M4 Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM RAS\ CAS\ W\ VCC Control Clocks VSS VBB Generator Data In Buffer Row Decoder Refresh Timer Memory Array 4,194,304 x 4 Cells Refresh Counter (A0 - A10) (A0 - A10) Sense Amps & I/O Refresh Control Row Address Buffer Col. Address Buffer Data Out Buffer Column Decoder ABSOLUTE MAXIMUM RATINGS* DQ0 to DQ3 OE\ *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics). Voltage on any pin relative to VCC (VIN, VOUT) ..........-0.5V to +4.6V Voltage on VCC supply relative to VSS (VCC)................-0.5V to +4.6V Storage Temperature (Tstg).........................................-55°C to +150°C Power Dissipation (PD)....................................................................1W Short Circuit Output Current (IOS Address).............................50mA ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 3.3V +0.3V) PARAMETER SYMBOL MIN TYP MAX UNITS Supply Voltage VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.0 --- VCC + 0.3 Input Low Voltage VIL -0.3 --- 0.8 2 1 V V NOTES: 1. VCC + .13V/15ns, Pulse width is measured at VCC 2. -1.3V/15ns, Pulse width is measured at VSS AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 16 Me g FPM DRAM Meg AS4LC4M4 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 3.3V +0.3V) PARAMETER SYMBOL MIN MAX UNITS II(L) -5 5 uA IO(L) -5 5 uA Output High Voltage (IOH = -2mA) VOH 2.4 --- V Output Low Voltage (IOL = 2mA) VOL --- 0.4 V Input Leakage Current (any input 0<VIN<VIN+0.3V, all other input pins not under test = 0 Volt) Output Leakage Current (Data out is disabled, 0V<VOUT<VCC) MAX SYMBOL PARAMETERS -60 ICC1* Operating Current (RAS\ and CAS\, Address cycling @ tRC = MIN), Power = Don't Care ICC2 Standby Current (RAS\ = CAS\ = W\ = VIH) Power = Normal L ICC3* ICC4* ICC5 ICC6* ICC7 -70 UNITS 100 1 RAS\-only Refresh Current (CAS\ = VIH, RAS\, Address cycling @ tRC = MIN), Power = Don't Care Fast Page Mode Current (RAS\ = VIL, CAS\, Address cycling @ tPC = MIN), Power = Don't Care Standby Current (RAS\ = CAS\ = W\ = Vcc - 0.2V) Power = Normal L CAS\-BEFORE-RAS\ Refresh Current (RAS\ and CAS\ cycling @ tRC = MIN), Power = Don't Care Battery back-up current, Average power supply current, Battery backup mode, Input high voltage (VIH) = VCC - 0.2V, Input low voltage (VIL) = 0.2V, CAS\ = 0.2V, DQ = Don't care, TRC = 31.25us (4K/L- 100 80 200 100 250 ver), 62.5us (2K/L-ver), TRAS = TRAS min ~ 300ns ICCS Self Refresh Current, RAS\ = CAS\ = 0.2V, W\ = OE\ = A0 ~ A11 = VCC - 0.2V or 0.2V, DQ0 ~ DQ3 = VCC - 0.2V, 0.2V or Open 200 NOTES: *ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3, and ICC6 address can be changed maximum once while RAS\ = VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC. AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 16 Me g FPM DRAM Meg AS4LC4M4 Austin Semiconductor, Inc. CAPACITANCE (f = 1MHz ; Vcc = 3.3V ±0.3V) PARAMETER Input capacitance (A0 - A11) SYMBOL MAX UNITS CIN1 5 pF Input capacitance (RAS\, CAS\, W\, OE\) CIN2 7 pF Output capacitance (DQ0 - DQ3) CDQ 7 pF ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS1,2 (-55oC<TA<+125oC & -40oC<TA<+85oC; Vcc = 3.3V ±0.3V; VIH/VIL = 2.0/0.8V; VOH/VOL = 2.0/0.8V) -60 PARAMETER Random read or write cycle time MIN 110 tRWC Read-modify-write cycle time 155 tRAC Access time from RAS\ tCAC SYMBOL -70 MAX MIN MAX UNITS ns NOTES ns 3, 4, 10 60 ns 3, 4, 5 Access time from CAS\ 15 ns 3, 10 tAA Access time from column address 30 ns 3 tCLZ CAS\ to output in Low-Z 0 ns 6 tOFF Output buffer turn-off delay 0 15 ns 2 Transition time (raise and fall) 3 50 ns tRP RAS\ precharge time 40 tRAS RAS\ pulse width 60 tRSH RAS\ hold time 15 ns tCSH CAS\ hold time 60 ns tCAS CAS\ pulse width 15 10K ns tRCD RAS\ to CAS\ delay time 20 45 ns 4 tRAD RAS\ to column address delay time 15 30 ns 10 tCRP CAS\ to RAS\ precharge time 5 ns tASR Row address set-up time 0 ns tRAH Row address hold time 10 ns tASC Column address set-up time 0 ns tCAH Column address hold time 10 ns tRAL Column address to RAS\ lead time 30 ns tRCS Read command set-up time 0 ns tRCH Read command hold time referenced to CAS\ 0 ns 8 tRRH Read command hold time referenced to RAS\ 0 ns 8 tWCH Write command hold time 10 ns tWP Write command pulse width 10 ns tRWL Write command to RAS\ lead time 15 ns tCWL Write command to CAS\ lead time 15 ns tRC tT AS4LC4M4 Rev. 0.3 7/06 ns 10K ns Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 16 Me g FPM DRAM Meg AS4LC4M4 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS1,2 (CONTINUED) -60 SYMBOL PARAMETER MIN 0 -70 MAX MIN MAX UNITS NOTES ns 9 ns 9 tDS Data set-up time tDH Data hold time tREF Refresh period tWCS Write command set-up time 0 ns 7 tCWD CAS\ to W\ delay time 40 ns 7 tRWD RAS\ to W\ delay time 85 ns 7 tAWD Column address to W\ delay time 55 ns 7 tCPWD CAS\ precharge to W\ delay time 60 ns tCSR CAS\ set-up time (CAS\-before-RAS\ refresh) 5 ns tCHR CAS\ hold time (CAS\-before-RAS\ refresh) 10 ns tRPC RAS\ to CAS\ precharge time 5 ns tCPA Access time from CAS\ precharge tPC Fast Page cycle time 40 ns tPRWC Fast Page read-modify-write cycle time 85 ns tCP CAS\ precharge time (Fast Page Cycle) 10 ns tRASP RAS\ pulse width (Fast Page Cycle) 60 tRHCP RAS\ hold time from CAS\ precharge 35 tOEA OE\ access time tOED OE\ to data delay 15 tOEZ Output buffer turn off delay time from OE\ 0 tOEH OE\ command hold time 15 ns tWTS Write command set-up time (Test mode in) 10 ns 11 tWTH Write command hold time (Test mode in) 10 ns 11 tWRP W\ to RAS\ precharge time (C\-B-R\ refresh) 10 ns tWRH W\ to RAS\ hold time (C\-B-R\ refresh) 10 ns tRASS RAS\ pulse width (C\-B-R\ self refresh) 100 us 13, 14, 15 tRPS RAS\ precharge time (C\-B-R\ self refresh) 110 ns 13, 14, 15 tCHS CAS\ hold time (C\-B-R\ self refresh) -50 ns 13, 14, 15 AS4LC4M4 Rev. 0.3 7/06 10 128 35 200K ms ns 3 ns ns 15 ns ns 15 ns 6 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 16 Me g FPM DRAM Meg AS4LC4M4 Austin Semiconductor, Inc. TEST MODE CYCLE11 -60 -70 PARAMETER Random read or write cycle time MIN 115 UNITS ns tRWC Read-modify-write cycle time 160 ns tRAC Access time from RAS\ 65 ns 3, 4, 10, 12 tCAC Access time from CAS\ 20 ns 3, 4, 5, 12 tAA Access time from column address 35 ns 3, 10 ,12 tRAS RAS\ pulse width 65 10K ns tCAS CAS\ pulse width 20 10K ns tRSH RAS\ hold time 20 ns tCSH CAS\ hold time 65 ns tRAL Column address to RAS\ lead time 35 ns tCWD CAS\ to W\ delay time 45 ns 7 tRWD RAS\ to W\ delay time 90 ns 7 tAWD Column address to W\ delay time 60 ns 7 tCPWD CAS\ precharge to W\ delay time 65 ns Fast Page cycle time 45 ns tPRWC Fast Page read-modify-write time 90 ns tRASP RAS\ pulse width (Fast Page Cycle) 65 tCPA SYMBOL tRC tPC MAX MIN MAX 200K ns Access time from CAS\ precharge 40 ns tOEA OE\ access time 20 ns tOED OE\ to data delay 20 ns tOEH OE\ command hold time 20 ns NOTES 3 NOTES: 1. An initial pause of 200us is required after power-up followed by an 8 RAS\-only refresh or CAS\-before-RAS\ refresh cycles before proper device operation is achieved. 2. VIH(MIN) and VIL(MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH(MIN) and VIL(MAX) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(MAX) limit insures that tRAC(MAX) and be met. tRCD(MAX) is specified as a reference point only. If tRCD is greater than the specified tRCD(MAX) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD > tRCD(MAX). 6. tOFF(MIN) and tOEZ(MAX) define the time at which the output achieves the open circuit condition and are not referenced VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS(MIN), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD > tCWD(MIN), tRWD > tRWD(MIN) and tAWD > tAWD(MIN), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write cycles. 10. Operation within the tRAD(MAX) limit insures that tRAC(MAX) can be met. tRAD(MAX) is specified as a reference point only. If tRAD is greater than the specified tRAS(MAX) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. If tRASS > 100 us, then RAS\ precharge time must use tRPS instead of tRP. 14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within 32ms before and after self refresh, in order to meet refresh specification. 15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 READ CYCLE AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 WRITE CYCLE (EARLY WRITE) DOUT = OPEN AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 WRITE CYCLE (OE\ CONTROLLED WRITE) DOUT = OPEN AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 READ-MODIFY-WRITE CYCLE AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 FAST PAGE READ CYCLE AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 FAST PAGE WRITE CYCLE (EARLY WRITE) DOUT = OPEN AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 FAST PAGE READ-MODIFY-WRITE CYCLE AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 RAS\-ONLY REFRESH CYCLE (W\, OE\, DIN = DON’T CARE; DOUT = OPEN) CAS\-BEFORE-RAS\ REFRESH CYCLE (OE\, A = DON’T CARE) AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 HIDDEN REFRESH CYCLE (READ) AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 HIDDEN REFRESH CYCLE (WRITE) DOUT = OPEN AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 CAS\-BEFORE-RAS\ SELF REFRESH CYCLE (OE\, A = DON’T CARE) TEST MODE IN CYCLE (OE\, A = DON’T CARE) AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 16 Me g FPM DRAM Meg Austin Semiconductor, Inc. AS4LC4M4 MECHANICAL DEFINITIONS* Package Designator DG *All measurements are in inches (millimeters). AS4LC4M4 Rev. 0.3 7/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 16 Me g FPM DRAM Meg AS4LC4M4 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS4LC4M4DG-6/XT Device Number Package Type AS4LC4M4 AS4LC4M4 DG DG *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range AS4LC4M4 Rev. 0.3 7/06 Speed Process -6 -7 /* /* -40oC to +85oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19