ALSC AS7C164-12 5v 8k x 8 cmos sram Datasheet

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• Low power consumption: STANDBY
- 11 mW (AS7C164) / max CMOS I/O
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard package
- 300 mil SOJ
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• AS7C164 (5V version)
• Commercial temperature
• Organization: 8,192 words × 8 bits
• Center power and ground pins
• High speed
- 12/15/20 ns address access time
- 6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 550 mW (AS7C164) / max @ 12 ns
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28-pin PDIP, SOJ (300 mL)
VCC
128×64×8
Array
(65,536)
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O7
Sense amp
A1
A2
A3
A4
A10
A11
A12
Row decoder
Input buffer
I/O0
Column decoder
A A A AA A
0 5 6 7 8 9
Control
circuit
WE
OE
CE1
CE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AS7C164
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
CE2
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
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-12
-15
-20
Unit
Maximum address access time
12
15
20
ns
Maximum output enable access time
6
7
8
ns
Maximum operating current
110
100
90
mA
Maximum CMOS standby current
2.0
2.0
2.0
mA
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The AS7C164 is a high performance CMOS 65,536-bit Static Random Access Memory (SRAM) device organized as 8,192 words × 8 bits. It is
designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6/7/8 ns are ideal for high
performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems.
When CE1 is High or CE2 is Low the device enters standby mode. The standard AS7C164 is guaranteed not to exceed 11.0 mW power
consumption in standby mode, and typically requires only 250 µW; it offers 2.0V data retention with maximum power of 120 µW.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) High. The chip drives
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active,
output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C164 is packaged in 300 mil SOJ packages.
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Parameter
Device
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
AS7C164
Vt1
–0.50
+7.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC + 0.50
V
Power dissipation
PD
–
1.0
W
Storage temperature (plastic)
Tstg
–65
+150
oC
Ambient temperature with VCC applied
Tbias
–55
+125
oC
DC current into outputs (low)
Iout
–
20
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
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CE1
CE2
WE
OE
Data
H
X
X
X
High Z
Standby (ISB, ISB1)
X
L
X
X
High Z
Standby (ISB, ISB1)
L
H
H
H
High Z
Output disable (ICC)
L
H
H
L
Dout
Read (ICC)
L
H
L
X
Din
Write (ICC)
Mode
Key: X = Don’t Care, L = Low, H = High
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Parameter
Device
Supply voltage
AS7C164
Input voltage
AS7C164
Ambient operating temperature
Symbol
Min
Typical
Max
Unit
VCC
4.5
5.0
5.5
V
VIH
2.2
–
VCC+1
V
VIL
–0.5*
–
0.8
V
70
oC
AS7C164
TA
0
–
* VIL min = –3.0V for pulse width less than tRC/2.
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Parameter
Symbol
Test Conditions
Device
-15
-20
Min Max Min Max Min Max Unit
Input leakage current
|ILI|
VCC = Max,
VIN = GND to VCC
–
1
–
1
–
1
µA
Output leakage current
|ILO|
VCC = Max,
CE1 = VIH or CE2 = VIL,
VOUT = GND to VCC
–
1
–
1
–
1
µA
Operating power supply
current
ICC
VCC = Max,
CE1 = VIL, CE2 = VIH,
f = fMax, IOUT = 0 mA
AS7C164
–
110
–
100
–
90
mA
ISB
VCC = Max,
CE1 = VIH or CE2 = VIL,
f = fMax
AS7C164
–
30
–
25
–
25
mA
ISB1
VCC = Max,
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V,
VIN ≤ 0.2V or
VIN ≥ VCC–0.2V, f = 0
AS7C164
–
2.0
–
2.0
–
2.0
mA
VOL
IOL = 8 mA, VCC = Min
–
0.4
–
0.4
–
0.4
V
VOH
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
V
Standby power supply
current
Output voltage
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Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE1, CE2, WE, OE
Vin = 0V
5
pF
I/O capacitance
CI/O
I/O
Vin = Vout = 0V
7
pF
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Parameter
-15
-20
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read cycle time
tRC
12
–
15
–
20
–
ns
Address access time
tAA
–
12
–
15
–
20
ns
3
Chip enable (CE1) access time
tACE1
–
12
–
15
–
20
ns
3, 12
Chip enable (CE2) access time
tACE2
–
12
–
15
–
20
ns
3, 12
Output enable (OE) access time
tOE
–
6
–
7
–
8
ns
Output hold from address change
tOH
3
–
3
–
3
–
ns
5
CE1 Low to output in low Z
tCLZ1
3
–
3
–
3
–
ns
4, 5, 12
CE2 High to output in low Z
tCLZ2
3
–
3
–
3
–
ns
4, 5, 12
CE1 High to output in high Z
tCHZ1
–
3
–
4
–
5
ns
4, 5, 12
CE2 Low to output in high Z
tCHZ2
–
3
–
4
–
5
ns
4, 5, 12
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
ns
4, 5
OE High to output in high Z
tOHZ
–
3
–
4
–
5
ns
4, 5
Power up time
tPU
0
–
0
–
0
–
ns
4, 5, 12
Power down time
tPD
–
12
–
15
–
20
ns
4, 5, 12
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Rising input
Falling input
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Undefined/don’t care
tRC
Address
tAA
tOH
DOUT
Data valid
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tRC1
CE1
CE2
tOE
OE
tOLZ
tOHZ
tACE1, tACE2
tCHZ1, tCHZ2
DOUT
Data valid
tCLZ1, tCLZ2
Supply
current
Y
tPU
tPD
50%
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50%
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Parameter
-15
-20
Symbol
Min
Max
Min
Max
Min
Max
Unit
Write cycle time
tWC
12
–
15
–
20
–
ns
Chip enable (CE1) to write end
tCW1
9
–
10
–
12
–
ns
12
Chip enable (CE2) to write end
tCW2
9
–
10
–
12
–
ns
12
Address setup to write end
tAW
9
–
10
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
ns
Write pulse width
tWP
8
–
9
–
12
–
ns
Write recovery time
tWR
0
–
0
–
0
–
ns
Address hold from write end
tAH
0
–
0
–
0
–
ns
Data valid to write end
tDW
6
–
7
–
8
–
ns
Data hold time
tDH
0
–
0
–
0
–
ns
4, 5
Write enable to output in high Z
tWZ
–
5
–
5
–
5
ns
4, 5
Output active from write end
tOW
3
–
3
–
3
–
ns
4, 5
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Notes
12
tWC
tWR
tAH
tAW
Address
tWP
WE
tAS
tDW
DIN
tDH
Data valid
tWZ
tOW
DOUT
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tWC
tWR
tAH
tAW
Address
tAS
tCW1, tCW2
CE1
CE2
tWP
WE
tWZ
DIN
tDW
tDH
Data valid
DOUT
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Parameter
Symbol
VCC for data retention
VDR
Data retention current
ICCDR
Chip enable to data retention time
tCDR
Operation recovery time
tR
Test conditions
VCC = 2.0V
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
Min
Max
Unit
2.0
–
V
–
60
µA
0
–
ns
tRC
–
ns
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Data retention mode
VCC
VDR ≥ 2.0V
VCC
VCC
tCDR
CE1
VIH
CS2
VIH
tR
VDR
VIH
VIH
VDR
tCDR
tR
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Output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin Equivalent:
168Ω
DRXW
+1.728V (5V)
+5V
+5V
480Ω
+3.0V
GND
90%
10%
90%
2ns
10%
Figure A: Input pulse
DRXW
255Ω
C(14)
GND
Figure B: 5V Output loDG
320Ω
DRXW
255Ω
C(14)
GND
Figure C: 3.3V Output load
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
tCLZ and tCHZ are specified with CL = 5pF as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low and CE2 transition High.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE1 or WE must be High or CE2 Low during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
CE1 and CE2 have identical timing.
2V data retention applies to the commercial operating range only.
C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
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1.4
1.0
0.8
0.6
ISB
0.4
0.2
NOMINAL
Supply voltage (V)
0.6
ISB
0.4
1.2
1.1
1.0
0.9
0.8
MIN
NOMINAL
Supply voltage (V)
Output source current IOH
vs. output voltage VOH
140
1.3
1.2
1.1
1.0
0.9
Output sink current (mA)
VCC = VCC(NOMINAL)PL
Ta = 25°C
80
60
40
20
0
VCC
Output voltage (V)
Y
-10
35
80
125
Ambient temperature (°C)
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
1.2
VCC = VCC(NOMINAL)
1.0
Ta = 25°C
0.8
0.6
0.4
0.0
–10
35
80
125
Ambient temperature (°C)
0
25
50
75
Cycle frequency (MHz)
100
Typical access time change ∆tAA
vs. output capacitive loading
Output sink current IOL
vs. output voltage VOL
35
120
30
VCC = VCC(NOMINAL)
Ta = 25°C
100
80
60
40
20
VCC = VCC(NOMINAL)
25
20
15
10
5
0
0
0.2
0.2
140
120
100
VCC = VCC(NOMINAL)
0.8
–55
MAX
1
1.4
Normalized ICC
Normalized access time
1.3
5
-55
1.4
Ta = 25°C
VCC = VCC(NOMINAL)
25
–10
35
80
125
Ambient temperature (°C)
Normalized access time tAA
vs. ambient temperature Ta
1.5
1.4
625
0.04
0.0
–55
MAX
Normalized access time tAA
vs. supply voltage VCC
1.5
Normalized access time
0.8
0.2
0.0
MIN
Output source current (mA)
ICC
1.0
Normalized supply current ISB1
vs. ambient temperature Ta
Normalized ISB1 (log scale)
1.2
ICC
Normalized ICC, ISB
Normalized ICC, ISB
1.2
Normalized supply current ICC, ISB
vs. ambient temperature Ta
Change in tAA (ns)
1.4
Normalized supply current ICC, ISB
vs. supply voltage VCC
0
0
VCC
Output voltage (V)
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250
500
750
Capacitance (pF)
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1000
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Plane
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A
A1
A2
B
b
c
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E
E1
E2
e
28-pin SOJ in mil
Min
Max
0.140
0.025
0.095
0.105
0.028 TYP
0.018 TYP
0.010 TYP
0.730
0.245
0.285
0.295
0.305
0.327
0.347
0.050 BSC
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Package\
Access time
Volt/Temp
12 ns
15 ns
20 ns
Plastic SOJ\300 mL
5V commercial
AS7C164-12JC
AS7C164-15JC
AS7C164-20JC
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AS7C
164
X
–XX
X
Package code:
SRAM prefix
Device number
Blank = Standard power
Access time
J=SOJ 300 mil
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Commercial
temperature range,
0°C to 70°C
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of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
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