High Performance 32K×8 CMOS SRAM AS7C256 AS7C256L 32K×8 CMOS SRAM (Common I/O) FEATURES • Organization: 32,768 words × 8 bits • Equal access and cycle times • High speed • Easy memory expansion with CE and OE inputs – 10/12/15/20/25/35 ns address access time • TTL-compatible, three-state I/O – 3/3/4/5/6/8 ns output enable access time • 28-pin JEDEC standard packages • Low power consumption – 300 mil PDIP and SOJ Socket compatible with 7C512 and 7C1024 – Active: 660 mW max (10 ns cycle) – Standby: 11 mW max, CMOS I/O 2.75 mW max, CMOS I/O, L version – 330 mil SOIC – 8×13.4 TSOP – Very low DC component in active power • ESD protection > 2000 volts • 2.0V data retention (L version) • Latch-up current > 200 mA PIN ARRANGEMENT DIP, SOJ, SOIC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND Vcc GND I/O7 256×128×8 ARRAY (262,144) SENSE AMP A0 A1 A2 A3 A4 A5 A6 A14 ROW DECODER INPUT BUFFER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C256 LOGIC BLOCK DIAGRAM Vcc WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I/O0 COLUMN DECODER TSOP 8×13.4 WE CONTROL CIRCUIT OE CE A A A A A A A 7 8 9 10 11 12 13 AS7C256-01 SELECTION GUIDE OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 AS7C256 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 AS7C256-02 A1 A2 7C256-10 7C256-12 7C256-15 7C256-20 7C256-25 7C256-35 Unit Maximum Address Access Time 10 12 15 20 25 35 ns Maximum Output Enable Access Time 3 3 4 5 6 8 ns Maximum Operating Current 120 115 110 100 90 80 mA 2.0 2.0 2.0 2.0 2.0 2.0 mA 0.5 0.5 0.5 0.5 0.5 0.5 mA Maximum CMOS Standby Current L ALLIANCE SEMICONDUCTOR AS7C256 AS7C256L FUNCTIONAL DESCRIPTION The AS7C256 is a high performance CMOS 262,144-bit Static Random Access Memory (SRAM) organized as 32,768 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20/25/35 ns with output enable access times (tOE) of 3/3/4/5/6/8 ns are ideal for high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output drivers stay in high-impedance mode. When CE is HIGH the device enters standby mode. The standard AS7C256 is guaranteed not to exceed 11 mW power consumption in standby mode; the L version is guaranteed not to exceed 2.75 mW, and typically requires only 500 µW. The L version also offers 2.0V data retention, with maximum power consumption in this mode of 300 µW. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C256 is packaged in all high volume industry standard packages. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit Voltage on Any Pin Relative to GND Vt –0.5 +7.0 V Power Dissipation PD – 1.0 W Storage Temperature (Plastic) Tstg –55 +150 oC Temperature Under Bias Tbias –10 +85 oC DC Output Current Iout – 20 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. . TRUTH TABLE CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output Disable L H L Dout Read L L X Din Write Key: X = Don’t Care, L = LOW, H = HIGH 2 AS7C256 AS7C256L RECOMMENDED OPERATING CONDITIONS (Ta = 0°C to +70°C) Parameter Supply Voltage Input Voltage Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V GND 0.0 0.0 0.0 V VIH 2.2 – VCC+1 V VIL –0.5* – 0.8 V *VIL min = –3.0V for pulse width less than tRC/2. DC OPERATING CHARACTERISTICS1 (VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C) -10 -12 -15 -20 -25 -35 Parameter Symbol Test Conditions Input Leakage Current |ILI| VCC = Max, Vin = GND to VCC – 1 – 1 – 1 – 1 – 1 – 1 µA Output Leakage Current |ILO| CE = VIH, VCC = Max, Vout = GND to VCC – 1 – 1 – 1 – 1 – 1 – 1 µA Operating Power Supply Current ICC CE = VIL, f = fmax, Iout = 0 mA – 120 – 115 – 110 – 100 – 90 – 80 mA – 115 – 110 – 105 – 95 – 85 – 75 mA ISB CE = VIH, f = fmax – 45 – 40 – 30 – 30 – 25 – 25 mA – 40 – 35 – 25 – 25 – 20 – 20 mA CE > VCC–0.2V, f = 0, Vin ≤ 0.2V or Vin ≥ VCC–0.2V – 2.0 – 2.0 – 2.0 – 2.0 – 2.0 – 2.0 mA ISB1 – 0.5 – 0.5 – 0.5 – 0.5 – 0.5 – 0.5 mA VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 – 0.4 – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – 2.4 – 2.4 – 2.4 – V Standby Power Supply Current Output Voltage Min Max Min Max Min Max Min Max Min Max Min Max Unit L L L CAPACITANCE2 (f = 1 MHz, Ta = Room Temperature, VCC = 5V) Parameter Symbol Signals Test Conditions Max Unit Input Capacitance CIN A, CE, WE, OE Vin = 0V 5 pF I/O Capacitance CI/O I/O Vin = Vout = 0V 7 pF 3 AS7C256 AS7C256L READ CYCLE 3, 9 (VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C) -10 -12 -15 -20 -25 -35 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Read Cycle Time tRC 10 – 12 – 15 – 20 – 25 – 35 – ns Address Access Time tAA – 10 – 12 – 15 – 20 – 25 – 35 ns 3 Chip Enable (CE) Access Time tACE – 10 – 12 – 15 – 20 – 25 – 35 ns 3 Output Enable (OE) Access Time tOE – 3 – 3 – 4 – 5 – 6 – 8 ns Output Hold from Address Change tOH 2 – 3 – 3 – 3 – 3 – 3 – ns 5 CE LOW to Output in Low Z tCLZ 3 – 3 – 3 – 3 – 3 – 3 – ns 4, 5 CE HIGH to Output in High Z tCHZ – 3 – 3 – 4 – 5 – 6 – 8 ns 4, 5 OE LOW to Output in Low Z tOLZ 0 – 0 – 0 – 0 – 0 – 0 – ns 4, 5 OE HIGH to Output in High Z tOHZ – 3 – 3 – 4 – 5 – 6 – 8 ns 4, 5 Power Up Time tPU 0 – 0 – 0 – 0 – 0 – 0 – ns 4, 5 Power Down Time tPD – 10 – 12 – 15 – 20 – 25 – 35 ns 4, 5 TIMING WAVEFORM OF READ CYCLE 13, 6, 7, 9 Notes (Address Controlled) tRC Address tOH tAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA Dout Data Valid TIMING WAVEFORM OF READ CYCLE 23, 6, 8, 9 (CE Controlled) tRC1 CE AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tOE AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA OEAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAA A tACE Dout tOLZ AAAA AAAA AAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA tOHZ tCHZ Data Valid tCLZ Supply Current tPU tPD 50% 50% ICC ISB AS7C256-04 4 AS7C256 AS7C256L WRITE CYCLE 11 (VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C) -10 -12 -15 -20 -25 -35 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tWC 10 – 12 – 15 – 20 – 20 – 30 – ns Chip Enable to Write End tCW 9 – 10 – 12 – 12 – 15 – 20 – ns Address Setup to Write End tAW 9 – 10 – 12 – 12 – 15 – 20 – ns Address Setup Time tAS 0 – 0 – 0 – 0 – 0 – 0 – ns Write Pulse Width tWP 7 – 8 – 9 – 12 – 15 – 17 – ns Address Hold From End of Write tAH 0 – 0 – 0 – 0 – 0 – 0 – ns Data Valid to Write End tDW 6 – 6 – 8 – 10 – 10 – 15 – ns Data Hold Time tDH 0 – 0 – 0 – 0 – 0 – 0 – ns 4, 5 Write Enable to Output in High Z tWZ – 5 – 5 – 5 – 5 – 5 – 5 ns 4, 5 Output Active from Write End tOW 3 – 3 – 3 – 3 – 3 – 3 – ns 4, 5 TIMING WAVEFORM OF WRITE CYCLE 1 10, 11 (WE Controlled) tWC tAW tAH Address WE tWP AAAAAAAAAA AAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAA AA tAS tDW Din tDH Data Valid tWZ tOW Dout AS7C256-05 TIMING WAVEFORM OF WRITE CYCLE 2 10, 11 (CE Controlled) tWC tAW tAH Address tAS tCW CE tWP AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA WE AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA tWZ Din Dout tDW tDH Data Valid AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAA AAAA AAAA AAAA AAAAAAAAAAAAAAA AAA AS7C256-06 5 AS7C256 AS7C256L DATA RETENTION CHARACTERISTICS Parameter Symbol VCC for Data Retention VDR Data Retention Current ICCDR Chip Enable to Data Retention Time tCDR Operation Recovery Time tR Input Leakage Current | ILI | (L Version Only) Test Conditions VCC = 2.0V CE ≥ VCC–0.2V Vin ≥ VCC–0.2V or Vin ≤ 0.2V Min Max Unit 2.0 – V – 150 µA 0 – ns tRC – ns – 1 µA DATA RETENTION WAVEFORM (L Version Only) Data retention mode VCC VDR ≥ 2.0V 4.5V 4.5V tCDR tR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VDR AAAAAAAAAAAAAAAAAAAAAAAAAAA CE AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIH AAAAAAAAAAAAAAAAAAAAAAAAAAA VIH AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AS7C256-07 AC TEST CONDITIONS – Output load: see Figure B, except for tCLZ and tCHZ see Figure C. Thevenin Equivalent: 168Ω Dout +1.728V – Input pulse level: GND to 3.0V. See Figure A. – Input rise and fall times: 5 ns. See Figure A. +5V – Input and output timing reference levels: 1.5V. +5V 480Ω +3.0V GND Dout 90% 10% 90% 255Ω 30 pF* 10% Figure A: Input Waveform AS7C256-08 480Ω Dout GND Figure B: Output Load AS7C256-09 255Ω 5 pF* *including scope and jig capacitance GND Figure C: Output Load for tCLZ, tCHZ AS7C256-10 NOTES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed but not tested. WE is HIGH for read cycle. CE and OE are LOW for read cycle. Address valid prior to or coincident with CE transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be HIGH during address transitions. All write cycle timings are referenced from the last valid address to the first transitioning address. 6 AS7C256 AS7C256L Normalized supply current ICC, ISB vs. ambient temperature Ta 1.4 1.2 1.2 0.8 0.6 0.2 0.0 4.0 Normalized access time tAA vs. supply voltage VCC Normalized access time Ta = 25°C 1.0 0.9 4.5 5.0 5.5 Supply voltage (V) Output source current I OH vs. output voltage VOH VCC = 5.0V Ta = 25°C 60 40 20 1.25 2.5 3.75 Output voltage (V) 1.3 5.0 –10 35 80 125 Ambient temperature (°C) 5 1 0.2 1.4 -10 35 80 125 Ambient temperature (°C) Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC 1.2 VCC = 5.0V 1.0 0.9 VCC = 5.0V Ta = 25°C 1.0 0.8 0.6 0.4 0.2 0.0 –10 35 80 125 Ambient temperature (°C) 0 25 50 75 Cycle frequency (MHz) 100 Typical access time change ∆tAA vs. output capacitive loading Output sink current I OL vs. output voltage VOL 35 120 30 VCC = 5.0V Ta = 25°C 80 60 40 20 0 0.0 VCC = 5.0V 25 -55 Normalized access time t AA vs. ambient temperature Ta 1.1 100 625 0.04 1.2 140 80 0 0.0 ISB 1.4 0.8 –55 6.0 120 100 0.4 1.5 1.1 140 0.6 0.0 –55 6.0 1.2 0.8 4.0 Output source current (mA) 4.5 5.0 5.5 Supply voltage (V) 1.4 1.3 0.8 0.2 Output sink current (mA) Normalized access time 1.5 1.0 Normalized ICC 0.4 ISB ICC Change in tAA (ns) 1.0 ICC Normalized supply current ISB1 vs. ambient temperature Ta Normalized ISB1 (log scale) Normalized supply current ICC, ISB vs. supply voltage VCC 1.4 Normalized ICC, ISB Normalized ICC, ISB TYPICAL DC AND AC CHARACTERISTICS VCC = 4.5V 25 20 15 10 5 0 1.25 2.5 3.75 Output voltage (V) 5.0 0 250 500 750 Capacitance (pF) 1000 AS7C256-11 7 AS7C256 AS7C256L ORDERING CODES Package / Access Time 10 ns 12 ns 15 ns 20 ns 25 ns 35 ns Plastic DIP, 300 mil AS7C256-10PC AS7C256L-10PC AS7C256-12PC AS7C256L-12PC AS7C256-15PC AS7C256L-15PC AS7C256-20PC AS7C256L-20PC AS7C256-25PC AS7C256L-25PC AS7C256-35PC AS7C256L-35PC Plastic SOJ, 300 mil AS7C256-10JC AS7C256L-10JC AS7C256-12JC AS7C256L-12JC AS7C256-15JC AS7C256L-15JC AS7C256-20JC AS7C256L-20JC AS7C256-25JC AS7C256L-25JC AS7C256-35JC AS7C256L-35JC Plastic SOIC, 330 mil AS7C256-10SC AS7C256L-10SC AS7C256-12SC AS7C256L-12SC AS7C256-15SC AS7C256L-15SC AS7C256-20SC AS7C256L-20SC AS7C256-25SC AS7C256L-25SC AS7C256-35SC AS7C256L-35SC TSOP 8×13.4 AS7C256-10TC AS7C256L-10TC AS7C256-12TC AS7C256L-12TC AS7C256-15TC AS7C256L-15TC AS7C256-20TC AS7C256L-20TC AS7C256-25TC AS7C256L-25TC AS7C256-35TC AS7C256L-35TC PART NUMBERING SYSTEM AS7C 256 X SRAM Prefix Device Number Blank L = Standard Power = Low Power –XX X Access Time Package: C P = PDIP 300 mil J = SOJ 300 mil S = SOIC 330 mil T = TSOP 8×14 Commercial Temperature Range, 0°C to 70 °C REPRESENTATIVES, DISTRIBUTORS, AND SALES OFFICES DOMESTIC REPS INDIANA NEW HAMPSHIRE SOUTH CAROLINA CANADA PUERTO RICO ALABAMA CC Electro Sales (317) 921-5000 Kitchen & Kutchin Inc. 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ALLIANCE SEMICONDUCTOR Printed in U.S.A. 3099 North First Street San Jose, CA 95134 (408) 383-4900 Fax (408) 383-4999 Copyright © 1995 All rights reserved. May 1996