ALSC AS7C33128PFS32A-100TQI 3.3v 128k x 32/36 pipeline burst synchronous sram Datasheet

March 2002
AS7C33128PFS32A
AS7C33128PFS36A
®
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Features
•
•
•
•
•
•
•
•
Organization: 131,072 words × 32 or 36 bits
Fast clock speeds to 200 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns
Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns
Fully synchronous register-to-register operation
Single register “Flow-through” mode
Single-cycle deselect
Dual-cycle deselect also available (AS7C33128PFD32A/
AS7C33128PFD36A)
• Pentium®1 compatible architecture and timing
• Asynchronous output enable control
•
•
•
•
•
•
•
Economical 100-pin TQFP package
Byte write enables
Multiple chip enables for easy expansion
3.3 core power supply
2.5V or 3.3V I/O operation with separate VDDQ
30 mW typical standby power in power down mode
NTD™1 pipeline architecture available
(AS7C33128NTD32A/ AS7C33128NTD36A)
1 Pentium® is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Pin arrangement
Logic block diagram
17
A[16:0]
GWE
BWE
BWd
D
Address
CE register
CLK
D
DQd Q
Byte write
registers
CLK
15
128K × 32/36
Memory
array
17
36/32
DQPc/NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
FT
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd/NC
36/32
D
DQc Q
Byte write
registers
CLK
BWc
D
DQb Q
Byte write
registers
CLK
BWb
BWa
D
DQa Q
Byte write
registers
CLK
CE0
CE1
CE2
D
Power
down
OE
Output
registers
CLK
Input
registers
CLK
D Enable Q
delay
register
CLK
TQFP 14 × 20 mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
DQPa/NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
ZZ
Q
Enable
CE register
CLK
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Q0
Burst logic
Q1
17
Q
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CLK
CE
CLR
A6
A7
CE0
CE1
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
LBO
CLK
ADV
ADSC
ADSP
OE
FT
Note: Pins 1,30,51,80 are NC for ×32
36/32
DQ [a:d]
Selection guide
–200
–183
–166
–133
–100
Units
5
5.4
6
7.5
10
ns
200
183
166
133
100
MHz
3
3.1
3.5
4
5
ns
Maximum operating current
570
540
475
425
325
mA
Maximum standby current
160
140
130
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
30
30
mA
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
3/4/02; v.1.4
Alliance Semiconductor
P. 1 of 13
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128PFS32A
AS7C33128PFS36A
®
Functional description
The AS7C33128PFS32A and AS7C33128PFS36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given
technology.
Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 5.0/5.4/6.0/7.5/10 ns with clock access times (tCD) of 3.0/3.1/3.5/4.0/5.0 ns enable 200, 183, 166, 133 and 100 MHz
bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst
addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High.
Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium® count sequence. With
LBO driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to
the next burst address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33128PFS32A and AS7C33128PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate
at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
CI/O
Signals
Address and control pins
I/O pins
Test conditions
VIN = 0V
VIN = VOUT = 0V
Max
5
7
Unit
pF
pF
Write enable truth table (per byte)
GWE
L
H
H
H
BWE
X
L
H
L
BWn
X
L
X
H
WEn
T
T
F*
F*
.H\X = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE, WEn = internal write signal.
Burst Order
Starting Address
First increment
Second increment
Third increment
Interleaved Burst Order
LBO=1
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order
LBO=0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1 PowerPC™ is a trademark International Business Machines Corporation.
3/4/02; v.1.4
Alliance Semiconductor
P. 2 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
Signal descriptions
Signal
I/O
Properties
CLK
I
CLOCK
A0–A16
I
SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
I/O
SYNC
Data. Driven as output when the chip is enabled and OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
ADSC
I
SYNC
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
ADV
I
SYNC
Advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
BWE
I
SYNC
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
BW[a,b,c,d]
I
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
LBO
I
STATIC
default =
HIGH
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.18
FT
I
STATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to
VDD if unused or for pipelined operation.
ZZ
I
ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
DQ[a,b,c,d]
Description
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
VDD, VDDQ
–0.5
+4.6
V
Input voltage relative to GND (input pins)
VIN
–0.5
VDD + 0.5
V
Input voltage relative to GND (I/O pins)
VIN
–0.5
VDDQ + 0.5
V
Power dissipation
PD
–
1.8
W
DC output current
IOUT
–
50
mA
Storage temperature (plastic)
Tstg
–65
+150
oC
Temperature under bias
Tbias
–65
+135
o
Power supply voltage relative to GND
C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
3/4/02; v.1.4
Alliance Semiconductor
P. 3 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
Synchronous truth table
CE0
CE1
CE2
ADSP
ADSC
ADV
WEn1
OE
Address accessed
CLK
Operation
DQ
H
X
X
X
L
X
X
X
NA
L to H
Deselect
Hi−Z
L
L
X
L
X
X
X
X
NA
L to H
Deselect
Hi−Z
L
L
X
H
L
X
X
X
NA
L to H
Deselect
Hi−Z
L
X
H
L
X
X
X
X
NA
L to H
Deselect
Hi−Z
L
X
H
H
L
X
X
X
NA
L to H
Deselect
Hi−Z
L
H
L
L
X
X
X
L
External
L to H
Begin read
Hi−Z2
L
H
L
L
X
X
X
H
External
L to H
Begin read
Hi−Z
L
H
L
H
L
X
F
L
External
L to H
Begin read
Hi−Z2
L
H
L
H
L
X
F
H
External
L to H
Begin read
Hi−Z
X
X
X
H
H
L
F
L
Next
L to H
Cont. read
Q
X
X
X
H
H
L
F
H
Next
L to H
Cont. read
Hi−Z
X
X
X
H
H
H
F
L
Current
L to H
Suspend read
Q
X
X
X
H
H
H
F
H
Current
L to H
Suspend read
Hi−Z
H
X
X
X
H
L
F
L
Next
L to H
Cont. read
Q
H
X
X
X
H
L
F
H
Next
L to H
Cont. read
Hi−Z
H
X
X
X
H
H
F
L
Current
L to H
Suspend read
Q
H
X
X
X
H
H
F
H
Current
L to H
Suspend read
Hi−Z
L
H
L
H
L
X
T
X
External
L to H
Begin write
D3
X
X
X
H
H
L
T
X
Next
L to H
Cont. write
D
H
X
X
X
H
L
T
X
Next
L to H
Cont. write
D
X
X
X
H
H
H
T
X
Current
L to H
Suspend write
D
H
X
X
X
H
H
T
X
Current
L to H
Suspend write
D
1See “Write enable truth table” on page 2 for more information.
2
Q in flow through mode.
3For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time.
Key: X = Don’t Care, L = Low, H = High.
3/4/02; v.1.4
Alliance Semiconductor
P. 4 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
Recommended operating conditions
Parameter
Supply voltage
3.3V I/O supply voltage
2.5V I/O supply voltage
Input
Address and
control pins
voltages1
I/O pins
Ambient operating temperature
Symbol
Min
Nominal
Max
Unit
VDD
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VIH
VIL
VIH
VIL
TA
3.135
0.0
3.135
0.0
2.35
0.0
2.0
–0.52
2.0
–0.52
0
3.3
0.0
3.3
0.0
2.5
0.0
–
–
–
–
–
3.6
0.0
3.6
0.0
2.9
0.0
VDD + 0.3
0.8
VDDQ + 0.3
0.8
70
V
V
V
V
V
°C
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
2 VIL min. = –2.0V for pulse width less than 0.2 × tRC.
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)1
Thermal resistance
(junction to top of case)1
Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per EIA/
JESD51
Symbol
Typical
Units
θJA
46
°C/W
θJC
2.8
°C/W
1 This parameter is sampled.
3/4/02; v.1.4
Alliance Semiconductor
P. 5 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
DC electrical characteristics
–200
Parameter
–183
–166
–133
–100
Symbol
Test conditions
Input leakage
current1
|ILI|
VDD = Max, VIN = GND to VDD
–
2
–
2
–
2
–
2
–
2
µA
Output leakage
current
|ILO|
OE ≥ VIH, VDD = Max,
VOUT = GND to VDD
–
2
–
2
–
2
–
2
–
2
µA
Operating
power supply
current
ICC2
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA
–
570
–
540
–
475
–
425
–
325 mA
ISB
Deselected, f = fMax, ZZ ≤ VIL
–
160
–
140
–
130
–
100
–
90
ISB1
Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V
–
30
–
30
–
30
–
30
–
30
ISB2
Deselected, f = fMax, ZZ ≥ VDD – 0.2V
All VIN ≤ VIL or ≥ VIH
–
30
–
30
–
30
–
30
–
30
VOL
IOL = 8 mA, VDDQ = 3.465V
–
0.4
–
0.4
–
0.4
–
0.4
–
0.4
VOH
IOH = –4 mA, VDDQ = 3.135V
2.4
–
2.4
–
2.4
–
2.4
–
2.4
–
Standby power
supply current
Output voltage
Min Max Min Max Min Max Min Max Min Max Unit
mA
V
1 LBO pin has an internal pull-up and input leakage = ±10 µa.
2 ICC given with no output loading. ICC increases with faster cycles times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
–200
–183
–166
–133
–100
Parameter
Symbol
Test conditions
Output leakage
current
|ILO|
OE ≥ VIH, VDD = Max,
VOUT = GND to VDD
–1
1
–1
1
–1
1
–1
1
–1
1
VOL
IOL = 2 mA, VDDQ = 2.65V
–
0.7
–
0.7
–
0.7
–
0.7
–
0.7
VOH
IOH = –2 mA, VDDQ = 2.35V
1.7
–
1.7
–
1.7
–
1.7
–
1.7
–
Output voltage
3/4/02; v.1.4
Min Max Min Max Min Max Min Max Min Max Unit
Alliance Semiconductor
µA
P. 6 of 13
V
AS7C33128PFS32A
AS7C33128PFS36A
®
Timing characteristics over operating range
–200
Parameter
–183
–166
–133
–100
Max Unit Notes1
Sym
Min
Max
Min
Max
Min
Max
Min
Max
Min
Clock frequency
fMax
–
200
–
183
–
166
–
133
–
Cycle time (pipelined mode)
tCYC
5
–
5.4
–
6
–
7.5
–
10
–
ns
Cycle time (flow-through mode)
tCYCF
9
–
10
–
10
–
12
–
12
–
ns
Clock access time (pipelined mode)
tCD
–
3.0
–
3.1
–
3.5
–
4.0
–
5.0
ns
Clock access time (flow-through mode)
tCDF
–
8.5
–
9
–
9
–
10
–
12
ns
Output enable LOW to data valid
tOE
–
3.0
–
3.1
–
3.5
–
4.0
–
5.0
ns
Clock HIGH to output Low Z
tLZC
0
–
0
–
0
–
0
–
0
–
ns
2,3,4
Data output invalid from clock HIGH
tOH
1.5
–
1.5
–
1.5
–
1.5
–
1.5
–
ns
2
Output enable LOW to output Low Z
tLZOE
0
–
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable HIGH to output High Z
tHZOE
–
3.0
–
3.1
–
3.5
–
4.0
–
4.5
ns
2,3,4
Clock HIGH to output High Z
tHZC
–
3.0
–
3.1
–
3.5
–
4.0
–
5.0
ns
2,3,4
tOHOE
0
–
0
–
0
–
0
–
0
–
ns
Clock HIGH pulse width
tCH
2.2
–
2.4
–
2.4
–
2.5
–
3.5
–
ns
5
Clock LOW pulse width
tCL
2.2
–
2.4
–
2.4
–
2.5
–
3.5
–
ns
5
Address setup to clock HIGH
tAS
1.4
–
1.4
–
1.5
–
1.5
–
2.0
–
ns
6
Data setup to clock HIGH
tDS
1.4
–
1.4
–
1.5
–
1.5
–
2.0
–
ns
6
Write setup to clock HIGH
tWS
1.4
–
1.4
–
1.5
–
1.5
–
2.0
–
ns
6,7
Chip select setup to clock HIGH
tCSS
1.4
–
1.4
–
1.5
–
1.5
–
2.0
–
ns
6,8
Address hold from clock HIGH
tAH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock HIGH
tDH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock HIGH
tWH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock HIGH
tCSH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock HIGH
tADVS
1.4
–
1.4
–
1.5
–
1.5
–
2.0
–
ns
6
ADSP setup to clock HIGH
tADSPS
1.4
–
1.4
–
1.5
–
1.5
–
2.0
–
ns
6
ADSC setup to clock HIGH
tADSCS
1.4
–
1.4
–
1.5
–
1.5
–
2.0
–
ns
6
ADV hold from clock HIGH
tADVH
0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold from clock HIGH
tADSPH 0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock HIGH
tADSCH 0.5
–
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Output enable HIGH to invalid output
100 MHz
1 See “Notes” on page 11.
3/4/02; v.1.4
Alliance Semiconductor
P. 7 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Timing waveform of read cycle
tCH
tCYC
tCL
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
tAS
LOAD NEW ADDRESS
tAH
Address
A1
A2
A3
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tCD
tHZOE
tOH
ADV INSERTS WAIT STATES
tHZC
DOUT
(pipelined mode) t
OE
Q(A1)
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
tLZOE
DOUT
(flow-through mode)
Q(A1)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
tHZC
Note: Ý = XOR when LBO= HIGH/No Connect; Ý = ADD when LBO = LOW.
BW[a:d] is don’t care.
3/4/02; v.1.4
Alliance Semiconductor
P. 8 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
Timing waveform of write cycle
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
tAS
tAH
Address
A1
A3
A2
tWS
tWH
BWE
BW[a:d]
tCSS
tCSH
CE0, CE2
CE1
tADVS
ADV SUSPENDS BURST
tADVH
ADV
OE
tDS
tDH
Data In
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01)
D(A2Ý10)
D(A2Ý11)
D(A3)
D(A3Ý01)
D(A3Ý10)
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
3/4/02; v.1.4
Alliance Semiconductor
P. 9 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
Timing waveform of read/write cycle
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tAS
tAH
Address
A2
A1
A3
tWS
tWH
GWE
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tDS
tDH
D(A2)
DIN
tLZC
tHZOE
tCD
Q(A1)
DOUT
(pipeline mode)
tOH
tLZOE
tOE
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
tCDF
DOUT
(flow-through mode)
Q(A1)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
3/4/02; v.1.4
Alliance Semiconductor
P. 10 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
• Input and output timing reference levels: 1.5V.
+3.0V
90%
90%
10%
10%
GND
DOUT
Figure A: Input waveform
Z0 = 50Ω
50Ω
DOUT
VL = 1.5V
for 3.3V I/O; 353Ω / 1538Ω
30 pF* = V
DDQ/2
for 2.5V I/O
319Ω / 1667Ω
5 pF*
GND *including scope
and jig capacitance
Figure C: Output load (B)
Figure B: Output load (A)
Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet
the setup and hold times for all rising edges of CLK when chip is enabled.
7 Write refers to GWE, BWE, BW[a:d].
8 Chip select refers to CE0, CE1, CE2.
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
A1
Min
Max
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
Hd
D
b
e
0.65 nominal
Hd
15.90
16.10
He
21.90
22.10
L
0.45
0.75
L1
1.00 nominal
α
0°
He E
7°
Dimensions in millimeters
α
c
L1
L
3/4/02; v.1.4
Alliance Semiconductor
A1 A2
P. 11 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
3/4/02; v.1.4
Alliance Semiconductor
P. 12 of 13
AS7C33128PFS32A
AS7C33128PFS36A
®
Ordering information
Package
Width
–200 MHz
–183 MHz
–166 MHz
–133 MHz
–100 MHz
TQFP
x32
AS7C33128PFS32A200TQC
AS7C33128PFS32A183TQC
AS7C33128PFS32A166TQC
AS7C33128PFS32A133TQC
AS7C33128PFS32A100TQC
TQFP
x32
AS7C33128PFS32A200TQI
AS7C33128PFS32A183TQI
AS7C33128PFS32A166TQI
AS7C33128PFS32A133TQI
AS7C33128PFS32A100TQI
TQFP
x36
AS7C33128PFS36A200TQC
AS7C33128PFS36A183TQC
AS7C33128PFS36A166TQC
AS7C33128PFS36A133TQC
AS7C33128PFS36A100TQC
TQFP
x36
AS7C33128PFS36A200TQI
AS7C33128PFS36A183TQI
AS7C33128PFS36A166TQI
AS7C33128PFS36A133TQI
AS7C33128PFS36A100TQI
Part numbering guide
AS7C
33
128
PF
S
32/36
A
–XXX
TQ
C/I
1
2
3
4
5
6
7
8
9
10
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization: 128=128K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: S=Single cycle deselect
6.Organization: 32=x32; 36=x36
7.Production version: A=first production version
8.Clock speed (MHz)
9.Package type: TQ=TQFP
10.Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C)
3/4/02; v.1.4
Alliance Semiconductor
P. 13 of 13
© Copyright A lliance Sem iconductor Corporation. All rights reserved. O ur three-point logo, our nam e and Intelliw att are tradem arks or registered tradem arks of Alliance. All other brand and
product nam es m ay be the tradem arks of their respective com panies. A lliance reserves the right to m ake changes to this docum ent and its products at any tim e without notice. A lliance assum es no
responsibility for any errors that m ay appear in this docum ent. T he data contained herein represents A lliance’s best data and/or estim ates at the tim e of issuance. A lliance reserves the right to
change or correct this data at any tim e, without notice. If the product described herein is under developm ent, significant changes to these specifications are possible. The inform ation in this
product data sheet is intended to be general descriptive inform ation for potential custom ers and users, and is not intended to operate as, or provide, any guarantee or w arrantee to any user or
custom er. A lliance does not assum e any responsibility or liability arising out of the application or use of any product described herein, and disclaim s any express or im plied warranties related to
the sale and/or use of A lliance products including liability or warranties related to fitness for a particular purpose, m erchantability, or infringem ent of any intellectual property rights, except as
express agreed to in A lliance’s Term s and Conditions of Sale (w hich are available from A lliance). A ll sales of A lliance products are m ade exclusively according to Alliance’s Term s and
Conditions of Sale. T he purchase of products from A lliance does not convey a license under any patent rights, copyrights, m ask w orks rights, tradem arks, or any other intellectual property rights
of A lliance or third parties. A lliance does not authorize its products for use as critical com ponents in life-supporting system s where a m alfunction or failure m ay reasonably be expected to result
in significant injury to the user, and the inclusion of Alliance products in such life-supporting system s im plies that the m anufacturer assum es all risk of such use and agrees to indem nify A lliance
against all claim s arising from such use.