September 2004
Preliminary Information
AS9C25512M2018L
AS9C25256M2018L
®
2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
Features
• True Dual-Port memory cells that allow simultaneous access of the same memory location
• Organisation: 524,288/262,144 × 18[1]
• Fully Synchronous, independent operation on
both ports
• Selectable Pipeline or Flow-Through output
mode
• Fast clock speeds in Pipeline output mode: 250
MHz operation (9Gbps bandwidth)
• Fast clock to data access: 2.8ns for Pipeline output mode
• Asynchronous output enable control
• Fast OE access times: 2.8ns
• Double Cycle Deselect (DCD) for Pipeline Output Mode
• 19/18[1]-bit counter with Increment, Hold and
Repeat features on each port
•
•
•
•
•
•
•
•
Dual Chip enables on both ports for easy
depth expansion
Interrupt and Collision Detection Features
2.5 V power supply for the core
LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
Snooze modes for each port for standby
operation
15mA typical standby current in power
down mode
Available in 256-pin Ball Grid Array
(BGA), 144-pin Thin Quad Flatpack
(TQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
Supports JTAG features compliant with
IEEE 1149.1
Note:
1. AS9C25512M2018L/AS9C25256M2018L
Selection guide
Feature
-250
-200
-166
-133
Units
4
5
6
7.5
ns
Maximum Pipeline clock frequency
250
200
166
133
MHz
Maximum Pipeline clock access time
2.8
3.4
3.6
4.2
ns
Maximum flow-through clock frequency
150
133
100
83
MHz
Maximum flow-through clock access time
6.5
7.5
10
12
ns
TBD
350
300
260
mA
18
18
18
18
mA
Minimum cycle time
Maximum operating current
Maximum snooze mode current
9/24/04; v.1.2
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AS9C25512M2018L
AS9C25256M2018L
®
Dual port logic block diagram
R/W Control
BE1A-BE0A
REGISTER BANK
CE0A
D
R/W Control
REGISTER BANK
D
Q
Q
BE1B-BE0B
REGISTER BANK
REGISTER BANK
Q
D
Q
CE0B
D
CE1A
CE1B
R/WA
R/WB
O/P Control
O/P Control
O/P Control
1
PL/FT
0
1
0
O/P Control
PL/FT
PL/FTA
PL/FTB
QoutB<17:0>
QoutA<17:0>
OEA
OEB
PL/FT
PL/FT
0
Q
D
REGISTER BANK
True Dual Port
Memory Array
512/256K X 18
REGISTER BANK
DQ17A-DQ0A
D
Q
D
0
REGISTER BANK
1
Q
1
REGISTER BANK
DinA<17:0>
DinB<17:0>
Q
DQ17B-DQ0B
D
RPTA
RPTB
ADSA
ADSB
INCB
INCA
A18[1]A-A0A
Address
Decoding
Address
Decoding
REGISTER BANK
Increment
Logic
Mirror
Register
D
REGISTER BANK
Increment
Logic
Mirror
Register
D
Q
Q
Address Counter A
A18[1]B-A0B
Address Counter B
CE0B
CE0A
OPTA
CE1A
CLKA
R/WA
PL/FTA
CLKA
OPTA
Interrupt/Collision
Detection
Logic/Registers
CE1B
OPTB
R/WB
PL/FTB
CLKB
OPTB
CLKB
INTA
INTB
COLA
COLB
ZZA
TDI
Snooze
Logic
Snooze
Logic
ZZB
TCK
JTAG
TDO
TMS
TRST
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
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P. 2 of 30
AS9C25512M2018L
AS9C25256M2018L
®
General Description
The AS9C25512M2018L/AS9C25256M2018L is a high-speed CMOS 9/4.5-Mbit synchronous Dual-Port Static Random Access Memory
device, organized as 524,288/262,144 × 18 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clockto-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation.
Each port contains a 19/18 bit linear burst counter on the input address register that can loop through the whole address sequence. After
externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or
the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control,
data, and address inputs provide minimal setup and hold times.
The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write
to a certain location while another port is reading from the same location, but the validity of read data is not guaranteed. However, the
reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than
one port at the same time is undefined.
The Asynchronous Output Enable input pin allows asynchronous disabling of output buffers at any given time. The Byte Enable inputs
allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1,
permits the on-chip circuitry of each port to enter a very low standby power mode.
AS9C25512M2018L/AS9C25256M2018L can support an operating voltage of either 3.3V or 2.5V on either or both ports, which is
controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. This device is available in 256-pin Ball Grid
Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 144-pin Thin Quad Flatpack (TQFP)
Address Counter
The AS9C25512M2018L/AS9C25256M2018L carries an internal 19/18 bit address counter for each port which can loop through the entire
memory array. The Address counter features are discussed below:
Load: Any required external address can be loaded on to the counter. This feature is similar to normal address load in conventional
memories.
Increment: The address counter has the capability to internally increment the address value, potentially covering the entire memory array.
Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known
location has to be loaded before Increment operation.
Hold: The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs.
Repeat: The previously loaded address (loaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 19/18
bit register called “Mirror register” is used to hold the last loaded address.This register is not initialized on Power-up, hence a known
location has to be loaded before Repeat operation (Refer Counter control truth table for details).
9/24/04, v.1.2
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AS9C25512M2018L
AS9C25256M2018L
®
Ball Assignment - 256-ball BGA
AS9C25512M2018L/AS9C25256M2018L
B - 256
Top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
NC
TDI
NC
A17A
A14A
A11A
A8A
NC
CE1A
OEA
INCA
A5A
A2A
A0A
NC
NC
A
B
INTA
NC
TDO
A18[1]A
A15A
A12A
A9A
BE1A
CE0A
R/WA
RPTA
A4A
A1A
VDD
NC
NC
B
C
COLA
DQ9A
VSS
A16A
A13A
A10A
A7A
NC
BE0A
CLKA
ADSA
A6A
A3A
OPTA
NC
DQ8A
C
D
NC
DQ9B
NC
PL/FTA VDDQA VDDQA VDDQB VDDQB VDDQA VDDQA VDDQB VDDQB
VDD
NC
NC
DQ8B
D
E
DQ10B DQ10A
NC
VDDQA
VDD
VDD
NC
VSS
VSS
VSS
VDD
VDD
VDDQB
NC
DQ7A
DQ7B
E
F
DQ11A
NC
DQ11B VDDQA
VDD
NC
NC
VSS
VSS
VSS
VSS
VDD
VDDQB DQ6B
NC
DQ6A
F
G
NC
NC
DQ12A VDDQB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQA DQ5A
NC
NC
G
H
NC
DQ12B
VDDQB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQA
NC
DQ5B
H
DQ13A DQ14B DQ13B VDDQA
ZZB
VSS
VSS
VSS
VSS
VSS
VSS
ZZA
VDDQB DQ4B
DQ3B
DQ4A
J
NC
DQ3A
K
J
NC
NC
K
NC
NC
DQ14A VDDQA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQB
L
DQ15A
NC
DQ15B VDDQB
VDD
NC
NC
VSS
VSS
VSS
VSS
VDD
VDDQA DQ2A
NC
DQ2B
L
M
DQ16B DQ16A
VDD
VDD
NC
VSS
VSS
VSS
VDD
VDD
VDDQA DQ1B
DQ1A
NC
M
NC
VDDQB
PL/FTB VDDQB VDDQB VDDQA VDDQA VDDQB VDDQB VDDQA VDDQA
N
NC
DQ17B
NC
P
COLB
DQ17A
TMS
A16B
A13B
A10B
A7B
NC
BE0B
CLKB
ADSB
R
INTB
NC
TRST
A18[1]B
A15B
A12B
A9B
BE1B
CE0B
R/WB
T
NC
TCK
NC
A17B
A14B
A11B
A8B
NC
CE1B
1
2
3
4
5
6
7
8
9
NC
VDD
NC
DQ0B
NC
N
A6B
A3B
NC
NC
DQ0A
P
RPTB
A4B
A1B
OPTB
NC
NC
R
OEB
INCB
A5B
A2B
A0B
NC
NC
T
10
11
12
13
14
15
16
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
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AS9C25512M2018L
AS9C25256M2018L
®
Ball Assignment - 208-ball fpBGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
DQ9A
INTA
VSS
TDO
NC
A16A
A12A
A8A
NC
VDD
CLKA
INCA
A4A
A0A
OPTA
NC
VSS
A
B
NC
VSS
COLA
TDI
A17A
A13A
A9A
NC
CE0A
VSS
ADSA
A5A
A1A
NC
NC
B
VDDQA DQ9B VDDQB PL/FTA A18[1]
A14A
A
A10A
BE1A
CE1A
VSS
R/WA
A6A
A2A
VDD
VSS
C
A7A
BE0A
VDD
OEA
RPTA
A3A
VDD
NC
DQ7B
D
C
NC
D
NC
VSS
DQ10A
E
DQ11A
NC
VDDQB DQ10B
F
VDDQA DQ11B
NC
E
DQ6B
NC
VDDQB
F
NC
G
NC
H
VDD
NC
VDDQB DQ12B
J
VDDQA VDD
VSS
ZZB
K
DQ14B
DQ13B
VSS
L
NC
M
VDDQA
NC
DQ15B
VSS
N
NC
VSS
NC
DQ15A
AS9C25512M2018L/AS9C25256M2018L
F - 208
Top view
DQ14A VDDQB DQ13A
VDDQA DQ7A
VSS
NC
DQ12A
NC
NC
VSS
VSS
DQ8B
DQ6A
VSS
NC
P
A11A
NC
G
VSS
A15A
VDDQB DQ8A
VDDQA DQ5A
VDD
NC
VSS
DQ5B
H
ZZA
VDD
VSS
VDDQB
J
VSS
K
DQ4A
L
DQ3B VDDQA DQ4B
NC
DQ3A
VSS
NC
DQ1B VDDQA
DQ2B VDDQB
M
NC
DQ2A
N
VSS
NC
P
DQ16B DQ16A VDDQB COLB
TRST
A16B
A12B
A8B
NC
VDD
CLKB
INCB
A4B
NC
TCK
A17B
A13B
A9B
NC
CE0B
VSS
ADSB
A5B
A1B
NC
A18[1]B A14B
A10B
BE1B
CE1B
VSS
R/WB
A6B
A2B
VSS
NC
VSS
NC
T
U
NC
DQ17B
DQ1A
VSS
VDDQA DQ0B VDDQB
R
VSS
T
NC
U
VSS
INTB
PL/FTB
NC
A15B
A11B
A7B
BE0B
VDD
OEB
RPTB
A3B
A0B
VDD
OPTB
NC
DQ0A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DQ17A VDDQA TMS
R
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
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AS9C25512M2018L
AS9C25256M2018L
®
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PL/FTA
NC
NC
A18[1]A
A17A
A16A
A15A
A14A
A13A
A12A
A11A
A10A
A9A
A8A
A7A
BE1A
BE0A
CE1A
CE0A
VDD
VSS
CLKA
OEA
R/WA
ADSA
INCA
RPTA
A6A
A5A
A4A
A3A
A2A
A1A
A0A
VDD
NC
Pin Assignment - 144-pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AS9C25512M2018L/AS9C25256M2018L
T - 144
Top view
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
OPTA
VDDQB
VSS
DQ8A
DQ8B
DQ7A
DQ7B
DQ6A
DQ6B
VSS
VDDQA
DQ5A
DQ5B
VSS
VDDQB
VDD
VDD
VSS
VSS
ZZA
VDDQA
DQ4B
DQ4A
DQ3B
DQ3A
VSS
VDDQB
DQ2B
DQ2A
DQ1B
DQ1A
DQ0B
DQ0A
VSS
VDDQA
OPTB
PL/FTB
NC
NC
[1]
A18 B
A17B
A16B
A15B
A14B
A13B
A12B
A11B
A10B
A9B
A8B
A7B
BE1B
BE0B
CE1B
CE0B
VDD
VSS
CLKB
OEB
R/WB
ADSB
INCB
RPTB
A6B
A5B
A4B
A3B
A2B
A1B
A0B
VDD
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDDQB
VSS
DQ9A
DQ9B
DQ10A
DQ10B
DQ11A
DQ11B
VDDQA
VSS
DQ12A
DQ12B
VDDQB
ZZB
VDD
VDD
VSS
VSS
VDDQA
VSS
DQ13B
DQ13A
DQ14B
DQ14A
VDDQB
VSS
DQ15B
DQ15A
DQ16B
DQ16A
DQ17B
DQ17A
VSS
VDDQA
NC
Note:
1. Address A18 is a NC for AS9C25256M2018L
9/24/04, v.1.2
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AS9C25512M2018L
AS9C25256M2018L
®
Signal description
Signal
Port A
Port B
CLKA
CLKB
A0A - A18A
A0B - A18B
DQ0A - DQ17A DQ0B - DQ17B
CE0A, CE1A
CE0B, CE1B
R/WA
R/WB
BE0A - BE1A
BE0B - BE1B
ADSA
ADSB
INCA
INCB
RPTA
RPTB
OEA
OEB
ZZA
ZZB
PL/FTA
PL/FTB
OPTA
OPTB
INTA
INTB
COLA
COLB
VDDQA
VDDQB
VDD
VSS
TCK
TDI
TDO
TMS
TRST
I/O Properties
Description
Notes
Clock. Each port has an independent Clock input that can be of different frequencies. All
I
CLOCK inputs except OEx and ZZx are synchronous to the corresponding port’s clock and must meet
setup and hold time about the rising edge of the clock.
I
SYNC
External Address. Sampled on the rising edge of corresponding port clock
I/O
SYNC
Bidirectional data pins
Chip enable inputs. Active low and high, respectively. Sampled on the rising edge of
I
SYNC
corresponding port clock.
I
SYNC
Read/Write enable. Drive this pin LOW to write to, or HIGH to Read from the memory array.
Byte Enable Inputs. Active low. Asserting these signals enables Read and Write operations to
I
SYNC
the corresponding bytes of the memory array. (Refer Byte Control Truth Table)
Address Strobe Enable.Active low. Loads external address onto the counter. (Refer Counter
I
SYNC
Control Truth Table)
Address Counter Increment. Active low. Increments the counter value. (Refer Counter Control
I
SYNC
Truth Table)
Address Counter Repeat. Active low. Reloads the counter with the previously loaded external
I
SYNC
address.(Refer Counter Control Truth Table)
Asynchronous output enable. I/O pins are driven when the OE is low and the chip is in Read
I
ASYNC
mode. A high on OE tristates the I/O pins.
Snooze Mode Input. Places the device in low power mode. Data is retained. This pin has an
I
ASYNC
internal pull-down and can be floating.
Pipeline/Flow-Through Select. When low, enables single register flow-through mode. When
I
STATIC high, enables double register Pipeline mode. This pin has an internal pull-up and can be left
floating to operate in pipeline mode.
VDDQx Option. OPTx selects the operating voltage levels for the I/Os, addresses, clock, and
I
STATIC controls on that port. This pin has an internal pull-up and can be left floating to operate in 3.3V
mode.
Interrupt Flag. Used for message passing between two ports. (Refer Interrupt Logic Truth
O
SYNC
Table)
Collision Alert Flag. Used to indicate collision during simultaneous memory access to the
O
SYNC
same location by both the ports (Refer Collision Detection Truth Table)
I
POWER Power to I/O bus. Can be 3.3V or 2.5V depending on OPTx input.
I
POWER Power Inputs (To be connected to 2.5V Power supply)
I GROUND Ground Inputs (To be connected to Ground supply)
CLOCK
I
JTAG Test Clock Input. All JTAG signals except TRST are synchronous to this clock.
(JTAG)
SYNC
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
I
(JTAG)
SYNC
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
O
(JTAG)
tristated except when the captured data is shifted out of the JTAG TAP.
SYNC
JTAG Test Mode Select Input. It controls the JTAG TAP state machine. State machine
I
(JTAG)
transitions occur on the rising edge of TCK.
ASYNC
JTAG Test Reset Input. Asynchronous input used to initialize TAP controller.
I
(JTAG)
1
6
1,2,3
5
5
1,2,3
2
Notes:
1. Subscript 'x' represents 'A' for Port A and 'B' for Port B.
2. OPTx,VDDQx and VDD must be set to appropriate operating levels before applying inputs on the I/Os and controls for that port.
3. OPTx = VDD (2.5V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 3.3V level and VDDQx must be supplied at 3.3V.
OPTx = VSS (0V) implies that corresponding port's I/Os, addresses, clock, and controls will operate at 2.5V level and VDDQx must be supplied at 2.5V.
Each port can independently operate on either of the VDDQ levels.
4. If unused JTAG inputs may be left unconnected.
5. JTAG, Collision Detection & Interrupt features are not supported in TQFP package.
6. Address A18 is a NC for AS9C25256M2018L.
9/24/04, v.1.2
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4,5
4,5
5
4,5
4,5
AS9C25512M2018L
AS9C25256M2018L
®
Byte control truth table[1,2,3,4,5]
BE1
BE0
CLK
Mode
H
H
L to H
All Bytes Deselected - NOP
H
L
L to H
Read or Write Byte 0
L
H
L to H
Read or Write Byte 1
Notes:
1. L = low, H = high
2. CE0 = L, CE1 = H (Chip in Select mode)
3. R/W = H for a Read operation, R/W = L for a Write operation
4. Byte 1 - DQ[17:9], Byte 0 - DQ[8:0]
5. More than one byte enable may be simultaneously asserted
Read/write control truth table[1,4]
CE[2]
R/W
BEn[3]
CLK
DQn[0:8][3,7]
H
X
X
L to H
Chip Deselect
Hi-Z[5,9]
L
X
H
L to H
Byte Deselect
Hi-Z[5,9]
L
L
L
L to H
Byte Write
Din[6]
L
H
L
L to H
Byte Read
Qout[5,8]
Operation
Notes:
1. L = low, H = high, X = don't care
2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H)
3. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DQn refers to the corresponding Byte
4. Snooze de-asserted (ZZ=L)
5. True in flow-through mode. For Pipeline mode there will be a 1 cycle latency [refer timing diagrams]
6. For a write command issued before the completion of a read command, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.
7. All DQs are tristated on power-up
8. OE should be asserted (OE = L) (Refer Read timing waveform)
9. In pipeline mode the DQs are HighZ-ed in the same cycle if R/W=L
Counter control truth table[1,2,5,6]
CLK
ADS[3]
INC[3]
RPT[3]
External
Address
Previous
Address
Accessed
Mirror
Register
Content[4]
Address
Accessed
Operation
Load
[4]
L to H
L
X
H
An
X
An
An
L to H
H
L
H
X
An
Am
An + 1
L to H
H
H
H
X
An
Am
An
Hold
L to H
X
X
L
X
X
Am
Am
Repeat
Increment
Notes:
1. L = low, H = high, X = don't care
2. Cycle can be Read, Write or Deselect (Controlled by appropriate setting of R/W, CE0, CE1 and BEn)
3. ADS, INC, RPT are independent of all other memory controls including R/W, CE0,CE1 and BEn (i.e Counter works independent of R/W, CE0,CE1 and BEn)
4. The 'Mirror register' used for the Repeat operation is loaded with External address during every valid ADS access. “Am” refers to the mirror register content.
5. Clock to the counter is disabled during Snooze mode (True for both ports).
6. The counter and the mirror registers are not initialized on Power-up (refer Counter description).
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Package Thermal Resistance
Description
Conditions
Thermal Resistance (junction to
ambient)[1]
Thermal Resistance (junction to
top of case)[1]
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
Symbol
Typical
Units
BGA
θJA
TBD
°C/W
fpBGA
θJA
TBD
°C/W
TQFP
θJA
TBD
°C/W
θJC
TBD
°C/W
Notes:
1. This parameter is sampled.
Capacitance[1] (TA = +25 °C, F = 1.0 Mhz)[2]
Parameter
Input Capacitance
Symbol
Signals
Test Condition[3]
BGA
(Max)
fpBGA
(Max)
TQFP
(Max)
Unit
CIN
Address and
Control pins
VIN = L to H or H to L
TBD
TBD
TBD
pF
Output Capacitance
COUT
I/O Capacitance
CI/O
Flag Output pins VOUT = L to H or H to L
I/O pins
VI/O = L to H or H to L
TBD
TBD
TBD
pF
TBD
TBD
TBD
pF
Notes:
1. Sampled, not 100% tested
2. TA stands for 'Ambient temperature'.
3. L = 0V; H = 3V
Absolute maximum ratings[1]
Rating
Parameter
Symbol
Min
Max
Unit
VDD
-0.5
3.6
V
VDDQ
-0.3
3.9
V
Input and I/O voltage relative to VSS
VIN
-0.3
VDDQ + 0.3
V
Power Dissipation
PD
-
TBD
W
Short circuit output current
IOUT
-
TBD
mA
Storage Temperature
TSTG
-65
150
°C
Storage Temperature under Bias
TBIAS
-55
125
°C
TJN
-
TBD
°C
Core supply voltage relative to VSS
I/O supply voltage relative to VSS
Junction Temperature
Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating for extended
periods may affect reliability.
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Recommended operating Temperature
Grade
Ambient Temperature (TA)
Commercial
0°C to 70°C
Industrial
-40°C to 85°C
Recommended operating conditions
Parameter
Core Supply Voltage
I/O supply Voltage
Ground
VDDQ = 2.5V[1]
VDDQ = 3.3V[2]
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
VDD
2.4
2.5
2.6
2.4
2.5
2.6
V
VDDQ
2.4
2.5
2.6
3.15
3.3
3.45
V
VSS
0
0
0
0
0
0
V
Notes:
1. OPT pin for a given port must be set to VSS(0V) to operate at VDDQ = 2.5V levels on the I/Os, addresses, clock and controls of that port.
2. OPT pin for a given port must be set to VDD(2.5V) to operate at VDDQ = 3.3V levels on the I/Os, addresses, clock and controls of that port.
DC Electrical Characteristics (VDD = 2.5 V ± 100 mV)
VDDQ = 2.5V
Parameter
Symbol
Input Leakage
Current
|ILI|
PL/FT and ZZ Input
Leakage Current
|ILI|
Output Leakage
Current[1]
|ILO|
Input high (logic 1)
voltage
(Address, Control,
Clock & Data Inputs)
VIH
Test Conditions
VDDQ = Max;
Min
VDDQ = 3.3V
Max
Test Conditions
VDDQ = Max;
Min
Max
Units
-
2
µA
-
2
µA
-
2
µA
-
2
-
2
-
2
-
1.7
VDDQ + 0.1V
-
2
VDDQ + 0.15V
V
VIH
-
VDD - 0.2V
VDD + 0.1V
-
VDD - 0.2V
VDD + 0.1V
V
Input low (logic 0)
voltage (Address,
Control, Clock &
Data Inputs)
VIL
-
-0.3
0.7
-
-0.3
0.8
V
Input low voltage
(ZZ,OPT,PL/FT)
VIL
-
-0.3
0.2
-
-0.3
0.2
V
Output low voltage
VOL
-
0.4
-
0.4
V
Output high voltage
VOH
2.0
-
2.4
-
V
Input high voltage
(ZZ,OPT,PL/FT)
0V < VIN < VDDQ
VDD = Max;
0V < VIN < VDD
OE>=VIH;
0V < VOUT < VDDQ
IOL = +2mA;
VDDQ = Min
IOH = -2mA;
VDDQ = Min
0V < VIN < VDDQ
VDD = Max;
0V < VIN < VDD
OE>=VIH;
0V < VOUT < VDDQ
IOL = +4mA;
VDDQ = Min
IOH = -4mA;
VDDQ = Min
Notes:
1. Outputs disabled (High-Z condition).
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IDD operating conditions and maximum limits[4] (VDD = 2.5 V ± 100 mV)
Parameter
Symbol
Test Conditions
-250
-200
-166
-133
Units
Typ Max Typ Max Typ Max Typ Max
Operating current
(Both ports active)
Pipeline mode -(PL/FT > VIH)
Operating current
(Both ports active)
Both ports enabled (CEA = CEB = L[3]),
ICC
TBD
350
TBD
300
TBD
260
mA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
TBD
TBD
TBD
105
TBD
90
TBD
80
mA
TBD
TBD
TBD
265
TBD
225
TBD
190
mA
20
25
20
25
20
25
20
25
mA
TBD
TBD
TBD
265
TBD
225
TBD
190
mA
15
18
15
18
15
18
15
18
mA
f=fMax[1]
Both ports disabled (CEA = CEB = H),
ISB1
ZZA = ZZB < VIL,
f=fMax
[1]
One port enabled (CEA = L and CEB = H)[5],
Standby current
(One port)
ISB2
Full standby current
(Both ports)
ISB3
Full standby current
(One port)
TBD
Outputs disabled (IOUT = 0mA), ZZA = ZZB < VIL,
Flow-through mode
(PL/FT < VIL)
Standby current
(Both ports)
TBD
Active port's outputs disabled, ZZA = ZZB < VIL,
f=fMax
[1]
Both ports disabled (CEA = CEB = H),
ZZA = ZZB < VIL,
[2]
f=0
ISB4
One port in Snooze (ZZA > VIH, ZZB < VIL, and
CEB = L)[5],
Active port's outputs disabled,
f=fMax[1]
Snooze mode
current
IZZ
Both ports in Snooze (ZZA = ZZB > VIH),
f=fMax[1]
Notes:
1. f=fMax implies address and controls (except OE) are cycling at maximum clock frequency using AC test conditions (Refer AC test conditions).
2. f = 0 implies address and controls are static. Corresponding current numbers indicated are true for both CMOS (VIN > VDDQ - 0.2V or VIN < 0.2V)
and TTL (VIN > VIH or VIN < VIL) level inputs.
3. CEA and CEB are internal signals (CEx = L implies CE0x < VIL and CE1x > VIH, CEx = H implies CE0x > VIH or CE1x < VIL).
4. Subscript 'x' represents 'A' for Port A and 'B' for Port B.
5. “A” and “B” are interchangeable.
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AC timing characteristics[1,2,5,6] (VDD = 2.5 ± 100mV)
Parameter
Symbol
Clock
Cycle Time (Pipeline)
Clock High Pulse Width (Pipeline)
Clock Low Pulse Width (Pipeline)
Cycle Time (Flow-Through)
Clock High Pulse Width (Flow-Through)
Clock Low Pulse Width (Flow-Through)
Output
Clock access time (Pipeline)
Output Data Hold from Clock High (Pipeline)
Clock High to Output Low-Z (Pipeline)
Clock High to Output High-Z (Pipeline)
Clock access time (Flow-Through)
Output Data Hold from Clock High (Flow-Through)
Clock High to Output Low-Z (Flow-Through)
Clock High to Output High-Z (Flow-Through)
Output Enable to Data Valid
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Setup
Address Setup to Clock High
Chip Enable Setup to Clock High
Byte Enable Setup to Clock High
R/W Setup to Clock High
Input Data Setup to Clock High
ADS Setup to Clock High
INC Setup to Clock High
RPT Setup to Clock High
Hold
Address Hold from Clock High
Chip Enable Hold from Clock High
Byte Enable Hold from Clock High
R/W Hold from Clock High
Input Data Hold from Clock High
ADS Hold from Clock High
INC Hold from Clock High
RPT Hold from Clock High
Flag
Interrupt Flag Set Time
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
Port-to-Port Delay
Clock-to-Clock Delay
tCYCP
tCHP
tCLP
tCYCF
tCHF
tCLF
tCDP
tOHP
tLZCP
tHZCP
tCDF
tOHF
tLZCF
tHZCF
tOE
tLZOE
tHZOE
-250
Min. Max.
4
1.7
1.7
6.5
1.7
1.7
-
1
1
1
1
1
1
-
5
2
2
7.5
2
2
-
2.8
-
-
1
1
1
2.8
6.5
2.8
2.8
-
1
1
1
-
-166
Min. Max.
6
2.4
2.4
10
2.4
2.4
-
3.4
-
-
1
1
1
Notes
ns
ns
ns
ns
ns
ns
3
3
3
3
3
3
3.6
-
4.2
3
-
1
1
1
-
-
4.2
4.2
1
1
4.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
-
ns
ns
ns
ns
ns
ns
ns
ns
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
-
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
-
ns
ns
ns
ns
ns
ns
ns
ns
6
6
3.4
3.4
-
6
6
3.6
3.6
-
7
7
4.2
4.2
ns
ns
ns
ns
-
4
-
5
-
ns
3.4
7.5
3.4
3.4
-
1
1
1
-
3.6
10
3.6
3.6
-
2.8
3.4
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
-
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
-
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
-
tADSH
tINCH
tRPTH
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
-
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
-
tSINT
tRINT
tSCOL
tRCOL
-
6
6
2.8
2.8
-
tCCO
3.0
-
3.5
tAH
tCEH
tBH
tWH
tDH
Unit
-
1
1
tADSS
tINCS
tRPTS
-133
Min. Max.
7.5
3
3
12
3
3
1
1
tAS
tCES
tBS
tWS
tDS
1
1
-200
Min. Max.
3.6
1
1
1
4.2
12
-
-
3,8
3,8
3
3,8
3,8
4
4
4
7
Notes:
1. All timings are same for both ports.
2. These values are valid for either level of VDDQ (2.5V/3.3V)
3. A particular port will operate in Pipeline output mode if PL/FT = VDD and in flow-through output mode if PL/FT = 0V. Each port can independently operate in any of these
modes.
4. Output Enable (OE) is an asynchronous input.
5. PL/FT and OPT should be treated as DC signals and should reach steady state before normal operation.
6. Refer AC Test Conditions to view the test conditions used for these measurements.
7. This parameter has to be taken care to avoid collision during simultaneous memory access of the same location.
8. To avoid bus contention, at a given voltage and temperature tLZC is more than tHZC (True in both Pipeline and flow-through output mode).
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Timing waveform of read cycle[7]
Don’t care
tCYC[2]
tCL
tCH
Undefined
CLK
tCES
tCEH
CE[3]
tBS
tBH
BEn[4]
R/W
tWH
tWS
tAS
tAH
ADDRESS[5]
A2
A1
A6
A5
A4
A3
A7
A11
A10
A9
A8
A13
A12
tLZOE
OE[6]
[Pipeline Mode]
tOHP
DATA OUT[1]
tLZCP
Q1
Q1
[Pipeline Mode]
tHZCP
tHZOE
Q2
tOE
Q10
Q8
Q6
tLZOE
tCDP
tLZOE
OE[6]
[Flow-through Mode]
tOHF
tLZCF
DATA OUT[1]
Q1
Q1
[Flow-through Mode]
tHZCF
tHZOE
Q2
tOE
Q12
Q10
Q8
Q6
tLZOE
tCDF
Read
(A1)
Read
(A2)
Dsel
Read[8]
(A4)
Dsel
Read
(A6)
Read
(A7)
Read
(A8)
Dsel
Read
(A10)
Dsel
Read
(A12)
Notes:
1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters tCYC, tCH and tCL are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics).
3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1
4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte.
5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H).
6. OE is an asynchronous input.
7. All timings are similar for both ports.
8. Read with Byte disabled. Data is not read out.Bus in High-Z condition.
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Timing wave form read/write cycle[7]
tCYC[2]
tCL
tCH
CLK
Don’t care
Undefined
tCES
tCEH
CE[3]
tBS
tBH
BEn[4]
R/W
tWH
tWS
tAS
tAH
[5]
ADDRESS
A2
A1
A5
A4
A3
A3
A6
A8
A7
A10
A9
A11
A12
OE[6]
tDS
tDH
[Pipeline Mode]
[1]
DATA IN
D3
[Pipeline Mode]
tCDP
D6
tHZCP
[1]
DATA OUT
D8
tHZOE
Q9
Q1
[Pipeline Mode]
tLZCP
OE[6]
[Flow-through Mode]
[1]
DATA IN
[Flow-through Mode]
D3
[1]
DATA OUT
Q1
[Flow-through Mode]
D11
D6
tHZCF
tOHF
tCDF
tHZOE
Q4
Q2
tDS
tDH
Q9
Q7
tLZCF
Read
(A1)
Read
(A2)
Write[8] Write
(A3)
Read
(A4)
Read
(A5)
Write
(A6)
Read
(A7)
Write[9]
(A8)
Read
(A9)
Dsel
Write[9]
(A11)
Notes:
1. Both Flow-through and Pipeline Inputs/Outputs indicated.A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline modes of operation.(Refer AC Timing characteristics)
3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1
4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte.
5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H).
6. OE is an asynchronous input.
7. All timings are similar for both ports.
8. Invalid write. Memory Content of the selected location may get corrupted and should be re-written before future readback.
9. Write (A11) is invalid in Pipeline mode and Write (A8) is invalid in Flow-through mode. Memory Content of the selected location may get corrupted and should be re-written
before future readback.
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Timing waveform of address counter[6]
tCYC[2]
tCL
tCH
Don’t care
Undefined
CLK
tCES
tCEH
[4]
CE[3]
R/W
tWH
tWS
tAS
tAH
ADDRESS
A2
A1
INTERNAL
ADDRESS
A1+1
A1
A1+2
A1+2
A1+1
A1
A1+2
A1+2
A2+1
A2
A2+1
A2
Dsel
Hold
Dsel
Rept
tADSS
tADSH
ADS
tINCS
tINCH
INC
tRPTS
tRPTH
RPT
DATA IN
tDS
tDH
D1
D1+1
D1+2
D1+2
tCDP
tOHP
tHZCP
[5]
DATA OUT[1]
Q1
[Pipeline Mode]
tCDF
DATA OUT[1]
tLZCP
Q1
[Flow-through Mode]
Write
Load
(A1)
Write
Incr
Write
Incr
Write
Hold
Q4 Q4
Q3 Q1+2
Q1+1
tOHF
tHZCF
[5]
Q1+2
Q1+1
tLZCF
Read
Rept
Read
Incr
Read
Incr
Read
Hold
Dsel
Load
(A2)
Dsel
Incr
Notes:
1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,
and in Pipeline mode if PL/FT is driven high or left unconnected.
2. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline modes of operation (Refer AC Timing characteristics).
3. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
Timings indicated for CE hold good for CE0 and CE1.
4. These cycles indicate that Counter works independent of all memory controls including R/W,CE and BEn.
5. If a Hold operation is performed for a Read access, the Data-out is held valid for the subsequent clock cycle also.
6. All timings are similar for both ports.
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Mailbox Interrupts
The AS9C25512M2018L/AS9C25256M2018L has an Inbuilt Mailbox Logic that can be used for communication between the two ports.
One memory location is assigned as mail box (message center) for each port. The location 7FFFE (HEX) is assigned as the message center
for Port A and 7FFFF (HEX) for Port B (3FFFE and 3FFFF for AS9C25256M2018L). The port A interrupt flag (INTA) is asserted when the
port B writes to memory location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). The port A clears the interrupt flag by reading the
address location 7FFFE (HEX) (3FFFE for AS9C25256M2018L). Likewise, the port B interrupt flag (INTB) is asserted when the port A
writes to memory location 7FFFF (HEX) (3FFFF for AS9C25256M2018L) and to clear the interrupt flag (INTB), the port B must read the
memory location 7FFFF (3FFFF for AS9C25256M2018L).(Refer Interrupt Logic Truth Table).
The interrupt flag is asserted in a flow-through mode (i.e., it follows the clock edge of the writing port). Also, the flag is reset in a flowthrough mode (i.e., it follows the clock edge of the reading port). Each port can read the other port’s mailbox without de-asserting the
interrupt and each port can write to its own mailbox without asserting the interrupt. If an application does not require message passing, INT
pins can be ignored.
Interrupt logic truth table[1,4,5]
CLKA R/WA CEA[2] A18A-A0A[3,6] CLKB R/WB CEB[2] A18B-A0B[3,6]
Function
INTA
INTB
L to H
L
L
7FFFF
L to H
X
X
X
X
L
Assert Port B Interrupt Flag
L to H
X
X
X
L to H
H
L
7FFFF
X
H
De-assert Port B Interrupt Flag
L to H
X
X
X
L to H
L
L
7FFFE
L
X
Assert Port A Interrupt Flag
L to H
H
L
7FFFE
L to H
X
X
X
H
X
De-assert Port A Interrupt Flag
Notes:
1. L = low, H = high, X = don't care
2. CEx is an internal signal ('x' = 'A' or 'B'). CEx = H implies 'Chip is Deselected' (CE0x = H or CE1x =L), CEx = L implies 'Chip is Selected' (CE0x = L and CE1x =H)
3. Address specified here is the internal address (refer Counter control truth table).
4. Both Interrupt Flags are De-asserted on power-up.
5. Interrupt feature is not supported in TQFP package.
6. Address A18 is a NC for AS9C25256M2018L, hence Interrupt addresses are 3FFFF and 3FFFE
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Interrupt timing wave form[2]
tCYC[1]
Don’t care
CLKA
tCL[1]
tCH[1]
tWS
tWH
R/WA[2]
ADDRESSA[3]
tAS
tAH
[4]
Aa
7FFFF
7FFFF
Aa
[5]
Aa
Aa
Aa
7FFFE
tSINT
tRINT
INTA
tCYC[1]
CLKB
tCL[1]
tWS tCH[1]
tWH
R/WB[2]
[5]
ADDRESSB[3]
Ab
tSINT
tAS
tAH
[4]
Ab
7FFFF
7FFFE
7FFFE
Ab
Ab
Ab
tRINT
INTB
Notes:
1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).
2. Chip Selected (CE0 = L and CE1 =H). True for both ports.
3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.
4. 7FFFF (3FFFF for AS9C25256M2018L) is the Mailbox for port B and 7FFFE (3FFFE for AS9C25256M2018L) is the Mailbox for port A.
5. “Aa” and “Ab” refer to any other valid address other than 7FFFF or 7FFFE (3FFFF or 3FFFE for AS9C25256M2018L).
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Collision detection
Three different cases of collisions can be listed depending on the type of access from two ports:
Simultaneous Read: A true dual-ported memory cell allows data to be read simultaneously from both ports of the device. Hence no data is
corrupted, lost, or incorrectly output, and none of the collision alert flags is asserted.
Simultaneous Write: When both ports are writing simultaneously to the same location, both write operations would fail. Therefore, the
collision flag is asserted on both ports.
Simultaneous Read and Write: When one port is writing and the other port is reading from the same location in the memory, the data
written will be valid. However, the read operation would fail and hence the reading port's collision flag is asserted.
The alert flag (COLx) is asserted on the 3rd (for both pipe-lined and flow-through output mode) rising clock edge of the affected port
following the collision, and remains low for one cycle. On continuous collisions (one or both ports writing during each access), the collision
alert flag will be asserted and de-asserted every alternate cycle.
Collision detection truth table[1,2,4,5]
CLKA
R/WA
CLKB
R/WB
Port address[3]
COLA
Function
COLB
L to H
H
L to H
H
MATCH
H
H
Both ports reading. Not a valid collision. No
collision flag asserted on either port.
L to H
H
L to H
L
MATCH
L
H
Port A reading, Port B writing. Valid collision.
Collision flag asserted on port A.
L to H
L
L to H
H
MATCH
H
L
Port B reading, Port A writing. Valid collision.
Collision flag asserted on port B.
L to H
L
L to H
L
MATCH
L
L
Both ports writing. Valid collision. Collision
flag asserted on both ports.
L to H
L
L to H
H
NO MATCH
H
H
No match. No collision flag asserted on either
port.
Notes:
1. L = low, H = high, X = don't care
2. Chip Selected (CE0 = L and CE1 =H). True for both ports. Collision flag is not affected if any one or both ports are deselected.
3. “MATCH” indicates that internal addresses of both the ports are the same (refer Counter control truth table).
4. Both Collision Flags are De-asserted on power-up.
5. Collision detection feature is not supported in TQFP package.
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Collision timing waveform[2]
Don’t care
tCYC[1]
CLKA
tCH[1]
[5]
tCCO
tCL[1]
tWS
tWH
R/WA
tAS
tAH
[4]
ADDRESSA[3]
Aa
Am
Am
Aa
Aa
Am
tSCOL
Aa
Am
Am
Am
Am
Aa
tRCOL
COLA
tCYC[1]
CLKB
tCL[1]
tCH[1]
tWS
tWH
R/WB
tAS
tAH
ADDRESSB[3]
Am
Ab
[4]
Am
Ab
Ab
Am
Ab
Am
tSCOL
Am
Am
Am
Ab
tRCOL
COLB
Notes:
1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).
2. Chip Selected (CE0 = L and CE1 =H). True for both ports.
3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.
4. “Am” refers to matched address. “Aa” and “Ab” refer to any other valid address.
5. During address collision the data validity is guaranteed only if tCCO is greater than the minimum specified (Refer AC timing characteristics).
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Depth and Width expansion
AS9C25512M2018L/AS9C25256M2018L has two chipselects (one active high and other active low) for simple depth expansion. This
permits easy upgrade from 512/256K depth to 1M/512K depth without extra logic. Two such parts can also be combined to obtain an
expanded width of 36 bits or wider.
DQ<0:35>
Data
Address
Clock
CLK
512/256Kx18
DPSRAM
INC
RPT
CLK
DQ<0:17>
512/256Kx18
DPSRAM
R/W
BE<0:1>
OE
ADS
INC
RPT
BANK 1
DQ<18:35>
DQ<0:17>
A<0:18>[1]
A<0:18>[1]
CE0
CE1
R/W
BE<0:1>
OE
ADS
Controller
A<0:18>[1]
A<19>[3]
DQ<0:17>
CE0
CE1
DQ<18:35>
DQ<0:17>
A<0:18>[1]
Clock
A<0:18>[1]
A<19>[3]
Microprocessor
A<0:18>[1]
A<0:19>[2]
BANK 0
Notes:
1. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L
2. A<0:19> for AS9C25512M2018L, A<0:18> for AS9C25256M2018L
3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L
Timing waveform of multi device read[4,5,6]
tCYC[1]
tCL
tCH
CLK
Don’t care
Undefined
tWS
tWH
R/W
A[0:18][2]
tAS
tAH
A1
A2
A5
A4
A3
A6
A8
A7
A[19][3]
tCDP
DATA OUT [0:35]
(BANK 0)
tOHP
tCDP
tOHF
tCDF
Q1
tHZCF
tLZCP
Q2
Q4
tCDF
tLZCF
Q3
Read
(Bank0)
Read
(Bank1)
Read
(Bank0)
tLZCF
tHZCF
tOHF
Q5
[Flow-through Mode]
Read
(Bank0)
tHZCP
Q6
Q5
Q3
DATA OUT [0:35]
(BANK 0)
DATA OUT [0:35]
(BANK 1)
Q4
Q2
tLZCP
DATA OUT [0:35]
(BANK 1)
[Flow-through Mode]
tHZCP
Q1
[Pipeline Mode]
[Pipeline Mode]
tOHP
Read
(Bank1)
Q6
Read
(Bank1)
Read
(Bank0)
Notes:
1. Parameters tCYC, tCH and tCL are different in Flow-through and Pipeline mode of operation (Refer AC Timing characteristics).
2. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L
3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L
4. Refer to the above block diagram for the assumed setup.
5. One Bank is assumed to have two AS9C25512M2018L/AS9C25256M2018Ls combined to have an expanded width of 36 bits. Two such Banks are used for depth expansion.
6. All BEn's = L, Counter set in “Load” mode (ADS = L, INC = X, RPT = H), OE =L.
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Snooze mode
Snooze mode is a low-current, power-down mode in which the corresponding port is deselected and its current is reduced to a
very low value. Both ports are equipped with independent SNOOZE inputs (ZZ). During Snooze mode, all inputs of the port
except ZZ are internally disabled and all its Outputs go to High-Z.
ZZ is an asynchronous, active HIGH input that causes the selected port to enter Snooze mode. If both ports go into Snooze mode,
the device is deselected and current is reduced to IZZ. When ZZA and ZZB become a logic HIGH, IZZ is guaranteed after the
setup time tSCZZ is met.
Any READ or WRITE operation pending when the port enters Snooze mode is not guaranteed to complete. Therefore, Snooze
mode must not be initiated until valid pending operations are completed. Similarly during the time tRCZZ, when the port is
transitioning out of snooze mode, only DESELECT cycles should be given.
Snooze mode electrical characteristics
Description
Conditions
Symbol
Min
Max
Units
ZZA = ZZB >= VIH
IZZ
15
18
mA
ZZ active to input ignored
tSCZZ
-
2
cycle
SNOOZE MODE Current
ZZ inactive to input sampled
tRCZZ
2
-
cycle
ZZ active to enter Snooze Current
tSIZZ
-
2
cycle
ZZ inactive to exit Snooze Current
tRIZZ
0
-
cycle
Snooze mode timing waveform[1,3]
Don’t care
Undefined
tCYC
CLK
tCES
tCEH
tCH
tCL
CE[2,4]
ZZ
tSIZZ
ISupply
tSCZZ
INPUTS
(Except ZZ)
OUTPUTS[5]
(Qout)
tRIZZ
IZZ
tRCZZ
ZZ recovery cycles
ZZ setup cycles
Valid
Valid
tHZC
tLZC
High-Z
Notes:
1. During Snooze mode, all dynamic inputs are disabled (except JTAG inputs). During JTAG operations, ZZx must be held Low in order to capture the parallel inputs of the boundary scan register. All static inputs (i.e. PL/FTx,OPTx) and ZZx themselves are not affected during snooze mode.
2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).
3. All timings are same for Port A and Port B.
4. Minimum of two deselect cycles should be given before asserting snooze and minimum of two deselect cycles should be given after de-asserting snooze to guarantee data
integrity.
5. Select cycles indicated before and after Snooze are Read cycles. They can also be Write cycles.
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AC test conditions
Input Pulse Level (Address and Controls)
GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.4V
Input Rise/Fall Times
2V/ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference levels
1.5V/1.25V
Output Load (for tLZC, tHZC, tLZOE, tHZOE)
Fig. C
Output Load (for all other measurements)
Fig. B
Thevenin equivalent:
+3.0/2.4 V
90%
GND
10%
Z0 = 50 Ω
90%
10%
+3.3/2.5 V;
50 Ω
DOUT
Figure A: Input Waveform
319Ω / 1667Ω
VL = 1.5/1.25 V
10 pF*
Figure B: Output Load (A)
353Ω / 1538Ω
5 pF*
GND
Figure C: Output Load (B)
* Including scope and jig capacitance
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IEEE 1149.1 Serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan Test Access Port (TAP). All JTAG pins operate using JEDEC standard 2.5V I/O logic levels.
In order to operate the device without using the JTAG feature, all JTAG pins may be left unconnected. On power-up, the device will start in
a reset state which will not interfere with normal device operation.
TAP Controller block diagram
0
Bypass Register
Selection
Circuitry
TDI
3 2 1 0
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . . 2 1 0
Identification Register
x[1]
. . . . . 2 1 0
Boundary Scan Register1
TCK
TAP Controller
TMS
Note:
1. x = 111
JTAG timing waveform
tJCYC
tJCH
Don’t care
tJCL
Undefined
TEST CLK
TCK
tJIS tJIH
TMS/TDI
tJCD
TDO
tJRS
tJOH
tJRR
TRST
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TAP AC electrical characteristics[2]
Description
Symbol
Min
Max
Units
Clock cycle time
tJCYC
100
-
ns
Clock frequency
fJTAG
-
10
MHz
Clock high time
tJCH
40
-
ns
Clock low time
tJCL
40
-
ns
TCK low to TDO unknown
tJOH
0
-
ns
TCK low to TDO valid
tJCD
-
20
ns
tJIS
10
-
ns
10
-
ns
Clock
Output Times
Setup Times
TMS/TDI setup
Capture setup
tJCS
[1]
Hold Times
TMS/TDI hold
tJIH
10
-
ns
tJCH[1]
10
-
ns
JTAG Reset
tJRS
50
-
ns
JTAG Reset Recovery
tJRR
50
-
ns
Capture hold
Reset Times
Notes:
1. tJCS and tJCH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in the figure TAP AC output load equivalent.
TAP AC test conditions & output load equivalent
Input pulse levels
Vss to 2.5V
Input rise and fall times
1V/ns
Input timing reference levels
1.25V
Output reference levels
1.25V
Test load termination supply voltage
1.25V
1.25V
50Ω
TDO
20pF
ZO=50Ω
TAP DC electrical characteristics and operating conditions (VDD=2.5V ± 100 mV)
Description
Symbol
Input high (logic 1) voltage
VIH
Conditions
Min
Max
Units
1.7
VDD + 0.3
V
Input low (logic 0) voltage
VIL
-0.3
0.7
V
Input leakage current
|ILI|
VDD = Max; 0V < VIN < VDD
0
10
µA
Output leakage current
|ILO|
Outputs disabled, 0V < VOUT < VDDQ (DQx)
0
10
µA
Output low voltage
VOLC
IOLC = 100µA
0.2
V
Output low voltage
VOLT
IOLT = 2mA
Output high voltage
VOHC
IOHC = -100µA
2.1
V
Output high voltage
VOHT
IOHT = -2mA
1.7
V
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Identification register definitions
Instruction field
Value
Description
Revision number (31:28)
TBD
Version Number
Device depth (27:12)
TBD
ALSC part number
JEDEC ID code (11:1)
00001010010
Manufacturer Identity Code
(ALSC)
Indicator Bit (0)
1
ID Register presence indicator
Scan register sizes
Register name
Bit size
Instruction Register (IR)
4
Bypass Register (BYR)
1
Identification Register (IDR)
32
Boundary Scan Register (BSR)
112
Instruction codes
Instruction
Code
Description
Selected Reg
EXTEST
0000
Forces contents of the BSR onto the device outputs.
BSR
SAMPLE/PRELOAD
0001
Samples the I/O ring contents. Preloads test data into the
BSR.
BSR
IDCODE
0010
Loads the IDR with the vendor ID code and places the
register between TDI and TDO.
IDR
CLAMP
0011
Forces contents of the BSR onto the device outputs.
BYR
HIGHZ
0100
Forces all device 2-state and 3-state outputs to High-Z.
BYR
RESERVED
BYPASS
9/24/04, v.1.2
0101 - 1110 Reserved states. Do not use.
1111
Places the BYR between TDI and TDO.
Alliance Semiconductor
BYR
BYR
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Package Diagram: 256-ball Ball Grid Array (BGA)
All measurements are in
mm.
Min
Typ
Max
A
1.00
B
16.95 17.00 17.05
C
15.00
D
16.95 17.00 17.05
E
15.00
F
0.36
G
0.35
0.50
H
I
1.60
0.40
0.50
J
A1
0.60
0.70
corner
index
Top View
Bottom View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
oooooooooooooooo
+
oooooooooooooooo
oooooooooooooooo
+
oooooooooooooooo
+
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooooo
+
+
++
A
B
C
A
D
E
J
0.35 Z
1.60 MAX
G
0.20 Z
0.35 ~ 0.50
0.36
0.70
oooooooooooooooo
F
H
Side View
9/24/04, v.1.2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
D
oo
oo
I
/ 0.50±0.10 (256X)
Ø 0.25 M Z X Y
Ø 0.15 M Z
Detail of Solder Ball
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Package Diagram: 208-ball fine pitch Ball Grid Array (fpBGA)
All measurements are in
mm.
Min
Typ
Max
A
0.80
B
14.95 15.00 15.05
C
12.80
D
14.95 15.00 15.05
E
12.80
F
G
0.26
0.25
0.40
H
I
1.40
0.40
0.45
J
A1
0.50
0.70
corner
index
Bottom View
Top View
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
ooooooooooooooooo
+
ooooooooooooooooo
ooooooooooooooooo
+
ooooooooooooooooo
+
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
oooo
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
ooooooooooooooooo
+
++
+
A
B
C
A
D
E
0.20 Z
G
0.15 Z
F
0.25 ~ 0.40
0.26
0.70
ooooooooooooooooo
1.40 MAX
J
H
oo
oo
D
I
/ 0.45±0.05 (208X)
Ø 0.15 M Z X Y
Ø 0.08 M Z
Detail of Solder Ball
Side View
9/24/04, v.1.2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
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Package Diagram: 144-pin Thin Quad Flat Pack (TQFP)
TQFP
Min
Typ
Max
A1
0.05
0.15
A2
1.35
1.40
1.45
b
0.17
0.20
0.27
c
0.09
0.20
D
20.00 nominal
E
20.00 nominal
e
0.50 nominal
Hd
22.00 nominal
He
22.00 nominal
L
0.45
0.60
0.75
L1
1.00 nominal
α
0°
3.5°
7°
Dimensions in millimeters
Hd
D
b
e
He E
c
α
9/24/04, v.1.2
L1
L
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Ordering Information
Package & Width
-250
-200
-166
-133
AS9C25512M2018L - 250BC
AS9C25512M2018L - 200BC
AS9C25512M2018L -166BC
AS9C25512M2018L - 133BC
AS9C25512M2018L - 250BI
AS9C25512M2018L - 200BI
AS9C25512M2018L - 166BI
AS9C25512M2018L - 133BI
AS9C25512M2018L - 250FC
AS9C25512M2018L - 200FC
AS9C25512M2018L - 166FC
AS9C25512M2018L - 133FC
AS9C25512M2018L - 250FI
AS9C25512M2018L - 200FI
AS9C25512M2018L - 166FI
AS9C25512M2018L - 133FI
AS9C25512M2018L - 250TC
AS9C25512M2018L - 200TC
AS9C25512M2018L - 166TC
AS9C25512M2018L - 133TC
AS9C25512M2018L - 250TI
AS9C25512M2018L - 200TI
AS9C25512M2018L - 166TI
AS9C25512M2018L - 133TI
AS9C25256M2018L - 250BC
AS9C25256M2018L - 200BC
AS9C25256M2018L -166BC
AS9C25256M2018L - 133BC
512K X 18
BGA X 18
fpBGA X 18
TQFP X 18
256K X 18
BGA X 18
fpBGA X 18
TQFP X 18
AS9C25256M2018L - 250BI
AS9C25256M2018L - 200BI
AS9C25256M2018L - 166BI
AS9C25256M2018L - 133BI
AS9C25256M2018L - 250FC
AS9C25256M2018L - 200FC
AS9C25256M2018L - 166FC
AS9C25256M2018L - 133FC
AS9C25256M2018L - 250FI
AS9C25256M2018L - 200FI
AS9C25256M2018L - 166FI
AS9C25256M2018L - 133FI
AS9C25256M2018L - 250TC
AS9C25256M2018L - 200TC
AS9C25256M2018L - 166TC
AS9C25256M2018L - 133TC
AS9C25256M2018L - 250TI
AS9C25256M2018L - 200TI
AS9C25256M2018L - 166TI
AS9C25256M2018L - 133TI
Part Numbering Guide
AS
9C
25
512/256
M20
18
L
-XXX
T or B or F
C/I
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor prefix
2. Speciality Memory
3. Operating Voltage: 25 - VDD = 2.5V
4. Device depth: 512 - 512K; 256 - 256K
5. M20 - Multiport - 2port, SSRAM, DCD
6. I/O width - 18
7. I/O interface: L - LVTTL
8. Clock speed (MHz)
9. Package Type: T - TQFP, B - BGA, F - fpBGA
10. Operating Temperature: C - Commercial (00C to 700C); I -Industrial (-400C to 850C)
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®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: AS9C25512M2018L/
AS9C25256M2018L
Document Version: v.1.2
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related
to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and
Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of
Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such lifesupporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.