Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) – Data Sheet Describes Mode 0 Operation • Low-voltage and Standard-voltage Operation • • • • • • • • • – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V) 20 MHz Clock Rate (5V) 8-byte Page Mode Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms max) High Reliability – Endurance: One Million Write Cycles – Data Retention: 100 Years Automotive Devices Available 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3) and 8lead TSSOP Packages Die Sales: Wafer Form, Waffle Pack, Bumped Wafers Description The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically erasable programmable read-only memory (EEPROM) organized as 128/256/512 words of 8 bits each. The device is optimized for use in many industrial and commercial applic a t i o n s w h e r e l ow - p ow e r a n d l ow - vo l t a g e o p e ra t i o n a r e e s s e n t i a l . T h e AT25010A/020A/040A is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), and 8-lead TSSOP packages. SPI Serial EEPROM 1K (128x8) 2K (256x8) 4K (512x8) AT25010A AT25020A AT25040A The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write. Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate Program Enable and Program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Table 1. Pin Configuration Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input 8-lead SOIC 8-lead PDIP CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI C S SO W P G N D 8-lead Ultra Thin mini-MAP (MLP 2x3) VCC HOLD SCK SI 8 7 6 5 1 2 3 4 CS SO WP GND 1 2 3 4 8 7 6 5 V H S S C C O L C K I V H S S C C O L C K I 8-lead TSSOP C S SO W P G N D 1 2 3 4 8 7 6 5 Bottom view 3348J–SEEPR–8/06 Absolute Maximum Ratings* Operating Temperature.................................... −40°C to + 125°C Storage Temperature ....................................... −65°C to + 150°C Voltage on Any Pin with Respect to Ground ....................................... −1.0V to + 7.0V Maximum Operating Voltage .......................................... 6.25V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Figure 1. Block Diagram STATUS REGISTER MEMORY ARRAY 128/256/512 X 8 ADDRESS DECODER DATA REGISTER OUTPUT BUFFER MODE DECODE LOGIC CLOCK GENERATOR 2 AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A Table 2. Pin Capacitance (1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions COUT CIN Note: Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. Table 3. DC Characteristics(1) Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V, (unless otherwise noted) Symbol Parameter VCC1 Supply Voltage VCC2 Max Units 1.8 5.5 V Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5.0V at 20 MHz, SO = Open, Read 8.5 10.0 mA ICC2 Supply Current VCC = 5.0V at 10 MHz, SO = Open, Read, Write 4.5 5.0 mA ICC3 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read, Write 2.0 3.0 mA ISB1 Standby Current VCC = 1.8V, CS = VCC 0.1 0.5 µA ISB2 Standby Current VCC = 2.7V, CS = VCC 0.2 1.0 µA ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 3.5 µA IIL Input Leakage VIN = 0V to VCC −3.0 IOL Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C −3.0 3.0 µA VIL(1) Input Low-voltage −0.6 VCC x 0.3 V VIH(1) Input High-voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low-voltage 0.4 V VOH1 Output High-voltage VOL2 Output Low-voltage VOH2 Output High-voltage Note: Test Condition 3.6V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 3.6V Min IOL = 3.0 mA IOH = −1.6 mA µA VCC − 0.8 IOL = 0.15 mA IOH = −100 µA Typ V 0.2 VCC − 0.2 V V 1. VIL min and VIH max are reference only and are not tested. 3 3348J–SEEPR–8/06 Table 4. AC Characteristics Applicable over recommended operating range from TAI = −40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 0 0 0 20 10 5 MHz tRI Input Rise Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 2 2 2 µs tFI Input Fall Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 2 2 2 µs tWH SCK High Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 20 40 80 ns tWL SCK Low Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 20 40 80 ns tCS CS High Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 100 100 200 ns tCSS CS Setup Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 100 100 200 ns tCSH CS Hold Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 100 100 200 ns tSU Data In Setup Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 20 40 80 ns tH Data In Hold Time 4.5 − 5.5 2.7 - 5.5 1.8 - 5.5 20 40 80 ns tHD Hold Setup Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 20 40 80 ns tCD Hold Hold Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 20 40 80 ns tV Output Valid 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 0 0 0 tHO Output Hold Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 0 0 0 4 20 40 80 ns ns AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A Table 4. AC Characteristics (Continued) Applicable over recommended operating range from TAI = −40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted) Symbol Parameter Voltage Min Max Units tLZ Hold to Output Low Z 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 0 0 0 25 50 100 ns tHZ Hold to Output High Z 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 25 50 100 ns tDIS Output Disable Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 25 50 100 ns tWC Write Cycle Time 4.5 − 5.5 2.7 − 5.5 1.8 − 5.5 5 5 5 ms Endurance(1) Note: 5.0V, 25°C, Page Mode 1M Write Cycles 1. This parameter is characterized and is not 100% tested. 5 3348J–SEEPR–8/06 Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the serial clock pin (SCK) is always an input, the AT25010A/020A/040A always operates as a slave. TRANSMITTER/RECEIVER: The AT25010A/020A/040A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. The op-code also contains address bit A8 in both the read and write instructions. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25010A/020A/040A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25010A/020A/040A is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the SO pin will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25010A/020A/040A. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low, all write operations are inhibited. WP going low while CS is still low will interrupt a write to the AT25010A/020A/040A. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation. 6 AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A Figure 2. SPI Serial Interface AT25010A/020A/040A 7 3348J–SEEPR–8/06 Functional Description The AT25010A/020A/040A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25010A/020A/040A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Figure 5. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 5. Instruction Set for the AT25010A/020A/040A Instruction Name Instruction Format WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 A011 Read Data from Memory Array WRITE 0000 A010 Write Data to Memory Array Note: Operation “A” represents MSB address bit A8. WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during a WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The read/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 6. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X BP1 BP0 WEN RDY Table 7. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = “0” indicates the device is not write enabled. Bit 1 = “1” indicates the device is write enabled. Bit 2 (BP0) See Table 8. Bit 3 (BP1) See Table 8. Bits 4–7 are “0”s when device is not in an internal write cycle. Bits 0–7 are “1”s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25010A/020A/040A is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any of 8 AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A the data within any selected segment will therefore be read only. The block write protection levels and corresponding status register control bits are shown in Table 8. Bits BP1 and BP0 are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, tWC, RDSR). Table 8. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BP0 AT25010A AT25020A AT25040A 0 0 0 None None None 1 (1/4) 0 1 60−7F C0−FF 180−1FF 2 (1/2) 1 0 40−7F 80−FF 100−1FF 3 (All) 1 1 00−7F 00−FF 000−1FF READ SEQUENCE (READ): Reading the AT25010A/020A/040A via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the read op-code (including A8) is transmitted via the SI line followed by the byte address to be read (A7−A0). Upon completion, any data on the SI line will be ignored. The data (D7−D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25010A/020A/040A, the Write Protect pin (WP) must be held high and two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code (including A8) is transmitted via the SI line followed by the byte address (A7−A0) and the data (D7−D0) to be programmed. Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The ready/busy status of the device can be determined by initiating a Read Status Register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle. The AT25010A/020A/040A is capable of an 8-byte page write operation. After each byte of data is received, the three low-order address bits are internally incremented by one; the six high-order bits of the address will remain constant. If more than 8 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25010A/020A/040A is automatically returned to the write disable state at the completion of a write cycle. NOTE: If the WP pin is brought low or if the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication. 9 3348J–SEEPR–8/06 Timing Diagrams Figure 3. Synchronous Data Timing (for Mode 0) t CS VIH CS VIL t CSH t CSS VIH t WH SCK t WL VIL tH t SU VIH SI VALID IN VIL tV VOH SO HI-Z t HO t DIS HI-Z VOL Figure 4. WREN Timing Figure 5. WRDI Timing 10 AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A Figure 6. RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK INSTRUCTION SI SO DATA OUT HIGH IMPEDANCE 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 7 6 5 4 2 1 0 MSB Figure 7. WRSR Timing CS 0 1 2 3 4 5 6 7 SCK INSTRUCTION SI SO DATA IN 3 HIGH IMPEDANCE Figure 8. READ Timing 11 3348J–SEEPR–8/06 Figure 9. WRITE Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK INSTRUCTION SI BYTE ADDRESS 8 7 6 5 4 3 2 1 DATA IN 0 7 6 5 4 3 2 1 0 9TH BIT OF ADDRESS SO HIGH IMPEDANCE Figure 10. HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ 12 AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A AT25010A Ordering Information(1) Ordering Code (2) AT25010A-10PU-2.7 AT25010A-10PU-1.8(2) AT25010AN-10SU-2.7(2) AT25010AN-10SU-1.8(2) AT25010A-10TU-2.7(2) AT25010A-10TU-1.8(2) AT25010AY1-10YU-1.8(2) (Not recommended for new designs) AT25010AY6-10YH-1.8(3) AT25010A-W1.8-11(4) Notes: Package Operation Range 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (−40 to 85°C) Die Sale Industrial Temperature (−40 to 85°C) 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in Table on page 3 and Table 4 on page 4. 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) Options −2.7 Low Voltage (2.7 to 5.5V) −1.8 Low Voltage (1.8 to 5.5V) 13 3348J–SEEPR–8/06 AT25020A Ordering Information(1) Ordering Code Package Operation Range 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (−40 to 85°C) Die Sale Industrial Temperature (−40 to 85°C) (2) AT25020A-10PU-2.7 AT25020A-10PU-1.8(2) AT25020AN-10SU-2.7(2) AT25020AN-10SU-1.8(2) AT25020A-10TU-2.7(2) AT25020A-10TU-1.8(2) AT25020AY1-10YU-1.8(2) (Not recommended for new designs) AT25020AY6-10YH-1.8(3) AT25020A-W1.8-11(4) Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in Table on page 3 and Table 4 on page 4. 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) Options −2.7 Low Voltage (2.7 to 5.5V) −1.8 Low Voltage (1.8 to 5.5V) 14 AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A AT25040A Ordering Information Ordering Code (2) AT25040A-10PU-2.7 AT25040A-10PU-1.8(2) AT25040AN-10SU-2.7(2) AT25040AN-10SU-1.8(2) AT25040A-10TU-2.7(2) AT25040A-10TU-1.8(2) AT25040AY1-10YU-1.8(2) (Not recommended for new designs) AT25040AY6-10YH-1.8(3) AT25040A-W1.8-11(4) Notes: Package Operation Range 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 Lead-free/Halogen-free/ Industrial Temperature (−40 to 85°C) Die Sale Industrial Temperature (−40 to 85°C) 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in Table on page 3 and Table 4 on page 4. 2. “U” designates Green Package + RoHS compliant. 3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8Y6 8-lead, 2.00mm x 3.00mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) Options −2.7 Low Voltage (2.7 to 5.5V) −1.8 Low Voltage (1.8 to 5.5V) 15 3348J–SEEPR–8/06 Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A b2 b3 b 4 PLCS Side View L SYMBOL NOM MAX NOTE 2 A – – 0.210 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 – – 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC L Notes: MIN 0.115 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A 8S1 – JEDEC SOIC C 1 E E1 L N ∅ Top View End View e B COMMON DIMENSIONS (Unit of Measure = mm) A A1 D Side View SYMBOL MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B 17 3348J–SEEPR–8/06 8A2 – TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D A b MIN 2.90 E e A2 D 3.00 3.10 2, 5 3, 5 4.30 4.40 4.50 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 L 4 0.65 BSC 0.45 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 18 NOTE E1 L1 Notes: MAX 6.40 BSC e Side View NOM 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A 8Y1 − MAP PIN 1 INDEX AREA A 1 3 2 4 PIN 1 INDEX AREA E1 D1 D L 8 Bottom View COMMON DIMENSIONS (Unit of Measure = mm) A Side View 5 e End View Top View 6 b A1 E 7 SYMBOL MIN NOM MAX A – – 0.90 A1 0.00 – 0.05 D 4.70 4.90 5.10 E 2.80 3.00 3.20 D1 0.85 1.00 1.15 E1 0.85 1.00 1.15 b 0.25 0.30 0.35 e L NOTE 0.65 TYP 0.50 0.60 0.70 2/28/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 DRAWING NO. REV. 8Y1 C 19 3348J–SEEPR–8/06 8Y6 - Mini-Map D2 A b (8X) E E2 Pin 1 Index Area Pin 1 ID L (8X) D A2 e (6X) A1 1.50 REF. A3 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN D 1.50 1.60 E2 - - 1.40 A - - 0.60 A1 0.0 0.02 0.05 A2 - - 0.55 L 0.20 REF 0.20 e b NOTE 3.00 BSC 1.40 A3 Notes: MAX 2.00 BSC E D2 NOM 0.30 0.40 0.50 BSC 0.20 0.25 0.30 2 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 8/26/05 R 20 2325 Orchard Parkway San Jose, CA 95131 DRAWING NO. TITLE 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, 8Y6 Dual No Lead Package (DFN) ,(MLP 2x3) REV. C AT25010A/020A/040A 3348J–SEEPR–8/06 AT25010A/020A/040A Revision History Doc. Rev. Comments 3348J Revision History implemented; Added ordering codes for At25020A and AT25040A. 21 3348J–SEEPR–8/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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