Features • Single 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 • 33 MHz Maximum Clock Frequency • Flexible, Uniform Erase Architecture • • • • • • • • • • – 4-Kbyte Blocks – 32-Kbyte Blocks – 64-Kbyte Blocks – Full Chip Erase Optimized Physical Sectoring for Code Shadowing and Code + Data Storage Applications – One 16-Kbyte Top Boot Sector – Two 8-Kbyte Sectors – One 32-Kbyte Sector – Seven 64-Kbyte Sectors Individual Sector Protection for Program/Erase Protection Hardware Controlled Locking of Protected Sectors Byte Program Architecture with Sequential Byte Program Mode Capability – Sequential Byte Program Mode Improves Throughput for Programming Multiple Bytes JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation – 7 mA Active Read Current (Typical) – 15 µA Deep Power-down Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC – 8-lead MLF 4-megabit 2.7-volt Only Serial Firmware DataFlash® Memory AT26F004 1. Description The AT26F004 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT26F004, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT26F004 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. 3588C–DFLASH–04/06 The AT26F004 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. Specifically designed for use in 3-volt systems, the AT26F004 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. 2. Pin Descriptions and Pinouts Table 2-1. Asserted State Type CS CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally placed in standby mode (not Deep Power-down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. Low Input SCK SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. – Input SI SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. – Input SO SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. – Output WP WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Refer to section “Protection Commands and Features” on page 13 for more details on protection features and the WP pin. The WP pin is not internally pulled-high and cannot be left floating. If hardware controlled locking will not be used, then the WP pin must be externally connected to VCC. Low Input HOLD HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold” on page 27 for additional details on the Hold operation. The HOLD pin is not internally pulled-high and cannot be left floating. If the Hold function will not be used, then the HOLD pin must be externally connected to VCC. Low Input Symbol 2 Pin Descriptions Name and Function VCC DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. – Power GND GROUND: The ground reference for the power supply. GND should be connected to the system ground. – Power AT26F004 3588C–DFLASH–04/06 AT26F004 Figure 2-1. 8-SOIC Top View CS SO WP GND 1 2 3 4 Figure 2-2. 8 7 6 5 8-MLF Top View CS SO WP GND VCC HOLD SCK SI VCC HOLD 6 SCK 5 SI 1 8 2 7 3 4 3. Block Diagram CS CONTROL LOGIC I/O BUFFERS AND LATCHES INTERFACE CONTROL AND LOGIC SI SO WP HOLD ADDRESS LATCH SCK Y-DECODER Y-GATING X-DECODER FLASH MEMORY ARRAY 4. Memory Array To provide the greatest flexibility, the memory array of the AT26F004 can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into physical sectors of various sizes, of which each sector can be individually protected from program and erase operations. The sizes of the physical sectors are optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. 3 3588C–DFLASH–04/06 Figure 4-1. Memory Architecture Diagram Block Erase Detail 64KB 32KB 4KB Block Erase Block Erase Block Erase (D8h Command) (52h Command) (20h Command) 16KB (Sector 10) 8KB (Sector 9) 8KB (Sector 8) 32KB 64KB 32KB (Sector 7) 32KB 32KB 64KB (Sector 6) 64KB ••• ••• ••• 32KB 32KB 64KB (Sector 0) 64KB 32KB 4 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB Block Address Range 7FFFFh 7EFFFh 7DFFFh 7CFFFh 7BFFFh 7AFFFh 79FFFh 78FFFh 77FFFh 76FFFh 75FFFh 74FFFh 73FFFh 72FFFh 71FFFh 70FFFh 6FFFFh 6EFFFh 6DFFFh 6CFFFh 6BFFFh 6AFFFh 69FFFh 68FFFh 67FFFh 66FFFh 65FFFh 64FFFh 63FFFh 62FFFh 61FFFh 60FFFh – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 7F000h 7E000h 7D000h 7C000h 7B000h 7A000h 79000h 78000h 77000h 76000h 75000h 74000h 73000h 72000h 71000h 70000h 6F000h 6E000h 6D000h 6C000h 6B000h 6A000h 69000h 68000h 67000h 66000h 65000h 64000h 63000h 62000h 61000h 60000h 0FFFFh 0EFFFh 0DFFFh 0CFFFh 0BFFFh 0AFFFh 09FFFh 08FFFh 07FFFh 06FFFh 05FFFh 04FFFh 03FFFh 02FFFh 01FFFh 00FFFh – – – – – – – – – – – – – – – – 0F000h 0E000h 0D000h 0C000h 0B000h 0A000h 09000h 08000h 07000h 06000h 05000h 04000h 03000h 02000h 01000h 00000h ••• Internal Sectoring for Sector Protection Function 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB AT26F004 3588C–DFLASH–04/06 AT26F004 5. Device Operation The AT26F004 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT26F004 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT26F004 supports the two most common modes, SPI modes 0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. Figure 5-1. SPI Mode 0 and 3 CS SCK SI MSB SO LSB MSB LSB 6. Commands and Addressing A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT26F004 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deasserted before all eight bits of an opcode are sent to the device, then the device will simply return to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23 - A0. Since the upper address limit of the AT26F004 memory array is 07FFFFh, address bits A23 - A19 are always ignored by the device. 5 3588C–DFLASH–04/06 Table 6-1. Command Listing Command Opcode Address Bytes Dummy Bytes Data Bytes Read Commands Read Array 0Bh 0000 1011 3 1 1+ Read Array (Low Frequency) 03h 0000 0011 3 0 1+ Block Erase (4 KBytes) 20h 0010 0000 3 0 0 Block Erase (32 KBytes) 52h 0101 0010 3 0 0 Block Erase (64 KBytes) D8h 1101 1000 3 0 0 60h 0110 0000 0 0 0 C7h 1100 0111 0 0 0 02h 0000 0010 3 0 1 0 1 Program and Erase Commands Chip Erase Byte Program Sequential Byte Program Mode (1) AFh 1010 1111 3, 0 Write Enable 06h 0000 0110 0 0 0 Write Disable 04h 0000 0100 0 0 0 Protect Sector 36h 0011 0110 3 0 0 Unprotect Sector 39h 0011 1001 3 0 0 Read Sector Protection Registers 3Ch 0011 1100 3 0 1+ Read Status Register 05h 0000 0101 0 0 1+ Write Status Register 01h 0000 0001 0 0 1 Read Manufacturer and Device ID 9Fh 1001 1111 0 0 1 to 4 Deep Power-down B9h 1011 1001 0 0 0 Resume from Deep Power-down ABh 1010 1011 0 0 0 Protection Commands Status Register Commands Miscellaneous Commands Notes: 6 1. Three address bytes are only required for the first operation to designate the address at which to start the programming. Afterwards, the internal address counter automatically increments, so subsequent Sequential Program Mode operations only require clocking in of the opcode and the data byte until the Sequential Program Mode has been exited. AT26F004 3588C–DFLASH–04/06 AT26F004 7. Read Commands 7.1 Read Array The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the SCK signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every clock cycle. Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the device. The 0Bh opcode can be used at any SCK frequency up to the maximum specified by fSCK. The 03h opcode can be used for lower frequency read operations up to the maximum specified by fRDLF. To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. If the 0Bh opcode is used, then one don't care byte must also be clocked in after the three address bytes. After the three address bytes (and the one don't care byte if using opcode 0Bh) have been clocked in, additional clock cycles will result in serial data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (07FFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array - 0Bh Opcode CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK OPCODE SI 0 0 0 0 1 ADDRESS BITS A23-A0 0 1 A 1 MSB A A A A A A DON'T CARE A A MSB X X X X X X X X MSB DATA BYTE 1 HIGH-IMPEDANCE SO D D D D D D D D MSB Figure 7-2. D D MSB Read Array - 03h Opcode CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 MSB 1 1 A A A A A A A A A MSB DATA BYTE 1 SO HIGH-IMPEDANCE D MSB D D D D D D D D D MSB 7 3588C–DFLASH–04/06 8. Program and Erase Commands 8.1 Byte Program The Byte Program command allows a single byte of data to be programmed into a previously erased memory location. An erased memory location is one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte Program command can be started, the Write Enable command must have been previously issued to the device (see “Write Enable” on page 13) to set the Write Enable Latch (WEL) bit of the Status Register to a logical “1” state. To perform a Byte Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting which byte location of the memory array to program. After the address bytes have been clocked in, the next byte of data clocked into the device will be latched internally. If more than one byte of data is clocked in, then only the first byte of data sent on the SI pin will be stored in the internal latches and all subsequent bytes will be ignored. When the CS pin is deasserted, the device will take the one byte stored in the internal latches and program it into the memory array location specified by A23 - A0. The programming of the byte is internally self-timed and should take place in a time of tBP. The three address bytes and a complete byte of data must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by A23 - A0 points to a memory location within a sector that is in the protected state (see “Protect Sector” on page 15), then the Byte Program command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, or because the memory location to be programmed is protected. While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP time to determine if the byte has finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. The Byte Program mode is the default programming mode after the device powers-up or resumes from a device reset. Figure 8-1. Byte Program CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 MSB SO 8 1 0 A MSB A A A A A A DATA IN A A D D D D D D D D MSB HIGH-IMPEDANCE AT26F004 3588C–DFLASH–04/06 AT26F004 8.2 Sequential Byte Program Mode The Sequential Byte Program mode improves throughput over the single Byte Program operation when programming multiple bytes of data into consecutive address locations. When using the Sequential Byte Programming mode, an internal address counter keeps track of the byte location to program, thereby eliminating the need to supply an address sequence to the device for every byte to program. All address locations to be programmed using the Sequential Byte Program mode must be in the erased state. Before the Sequential Byte Program mode can first be entered, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. To start the Sequential Byte Program mode, the CS pin must first be asserted, and the opcode of AFh must be clocked into the device. For the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. After the address bytes have been clocked in, the next byte of data clocked into the device will be latched internally. Deasserting the CS pin will start the internally self-timed program operation, and the first byte will be programmed into the memory location specified by A23 - A0. After the first byte has been successfully programmed, a second byte can be programmed by simply reasserting the CS pin, clocking in the AFh opcode, and then clocking in the next byte of data. When the CS pin is deasserted, the second byte of data will be programmed into the next sequential memory location. The process would be repeated for any additional bytes. There is no need to reissue the Write Enable command once the Sequential Byte Program mode has been entered. When the last desired byte has been programmed into the memory array, the Sequential Byte Program mode operation can be terminated by reasserting the CS pin and sending the Write Disable command to the device to reset the WEL bit in the Status Register back to the logical “0” state. If more than one byte of data is ever clocked in during each program cycle, then only the first byte of data sent on the SI pin will be stored in the internal latches and all subsequent bytes will be ignored. The programming of each byte is internally self-timed and should take place in a time of tBP. For each program cycle, a complete byte of data must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation, the byte of data will not be programmed into the memory array, and the WEL bit in the Status Register will be reset back to the logical “0” state. If the address initially specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Sequential Byte Program mode command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will also be reset back to the logical “0” state. There is no address wrapping when using the Sequential Byte Program mode. Therefore, when the last byte (07FFFFh) of the memory array has been programmed, the device will automatically exit the Sequential Byte Program mode and reset the WEL bit in the Status Register back to the logical “0” state. In addition, the Sequential Byte Program mode will not automatically skip over protected sectors; therefore, once the highest unprotected memory location in a programming sequence has been programmed, the device will automatically exit the Sequential Byte Program mode and reset the WEL bit in the Status Register. For example, if Sector 1 was protected and Sector 0 was currently being programmed, once the last byte of Sector 0 was programmed, the Sequential Byte Program mode would automatically end. To continue programming with Sector 2, the Sequential Byte Program mode would have to be restarted by supplying the AFh opcode, the three address bytes, and the first byte of Sector 2 to program. 9 3588C–DFLASH–04/06 While the device is programming a byte, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled at the end of each program cycle rather than waiting the tBP time to determine if the byte has finished programming before starting the next Sequential Byte Program mode cycle. Figure 8-2. Sequential Byte Program Mode – Status Register Polling CS Status Register Read Seqeuntial Program Mode Command Command Seqeuntial Program Mode Command SI AFh A23-16 A15-8 A7-0 Data 05h AFh Data Seqeuntial Program Mode Write Disable Command Command 05h AFh Data 04h 05h First Address to Program STATUS REGISTER DATA STATUS REGISTER DATA STATUS REGISTER DATA HIGH-IMPEDANCE SO Note: Each transition Figure 8-3. shown for SI represents one byte (8 bits) Sequential Byte Program Mode – Waiting Maximum Byte Program Time CS tBP Seqeuntial Program Mode Command SI AFh A23-16 A15-8 A7-0 Data tBP tBP Seqeuntial Program Mode Command Seqeuntial Program Mode Command Write Disable Command AFh AFh 04h Data Data First Address to Program SO HIGH-IMPEDANCE Note: Each transition 10 shown for SI represents one byte (8 bits) AT26F004 3588C–DFLASH–04/06 AT26F004 8.3 Block Erase A block of 4 Kbytes, 32 Kbytes, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h or D8h) must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4-Kbyte, 32-Kbyte, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-timed and should take place in a time of tBLKE. Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11 - A0 will be ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14 - A0 will be ignored, and for a 64-Kbyte erase, address bits A15 - A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation and no erase operation will be performed. If the address specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. In addition, with the larger Block Erase sizes of 32 Kbytes and 64 Kbytes, more than one physical sector may be erased (e.g. sectors 10, 9 and 8) at one time. Therefore, in order to erase a larger block that may span more than one sector, all of the sectors in the span must be in the unprotected state. If one of the physical sectors within the span is in the protected state, then the device will ignore the Block Erase command and will return to the idle state once the CS pin is deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. Figure 8-4. Block Erase CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI C C C C C C MSB SO ADDRESS BITS A23-A0 C C A A A A A A A A A A A A MSB HIGH-IMPEDANCE 11 3588C–DFLASH–04/06 8.4 Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE. The complete opcode must be clocked into the device before the CS pin is deasserted; otherwise, no erase will be performed. In addition, if any sector of the memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if a sector is in the protected state. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. Figure 8-5. Chip Erase CS 0 1 2 3 4 5 6 7 SCK OPCODE SI C C C C C C C C MSB SO 12 HIGH-IMPEDANCE AT26F004 3588C–DFLASH–04/06 AT26F004 9. Protection Commands and Features 9.1 Write Enable The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command can be executed. This makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the issuance of one of these commands, then the command will not be executed. To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. Write Enable CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 0 0 0 0 1 1 0 MSB SO HIGH-IMPEDANCE 13 3588C–DFLASH–04/06 9.2 Write Disable The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical “0” state. With the WEL bit reset, all program, erase, Protect Sector, Unprotect Sector, and Write Status Register commands will not be executed. The Write Disable command is also used to exit the Sequential Program mode. Other conditions can also cause the WEL bit to be reset; for more details, refer to the “WEL Bit” on page 20. To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-2. Write Disable CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 0 0 0 0 1 0 0 MSB SO 14 HIGH-IMPEDANCE AT26F004 3588C–DFLASH–04/06 AT26F004 9.3 Protect Sector Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Upon device power-up or after a device reset, each Sector Protection Register will default to the logical “1” state indicating that all sectors are protected and cannot be programmed or erased. Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection Register to the logical “1” state. The following table outlines the two states of the Sector Protection Registers. Table 9-1. Sector Protection Register Values Value Sector Protection Status 0 Sector is unprotected and can be programmed and erased. 1 Sector is protected and cannot be programmed or erased. This is the default state. Before the Protect Sector command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Protect Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be locked. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector addressed by A23 - A0 will be set to the logical “1” state, and the sector itself will then be protected from program and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state. The complete three address bytes must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”. As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status Register (refer to “Status Register Commands” on page 19 for more details). If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-3. Protect Sector CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI 0 0 1 1 0 ADDRESS BITS A23-A0 1 MSB SO 1 0 A A A A A A A A A A A A MSB HIGH-IMPEDANCE 15 3588C–DFLASH–04/06 9.4 Unprotect Sector Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector Protection Register to the logical “0” state (see Table 9-1 for Sector Protection Register values). Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Before the Unprotect Sector command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Unprotect Sector command, the CS pin must first be asserted and the opcode of 39h must be clocked into the device. After the opcode has been clocked in, the three address bytes designating any address within the sector to be unlocked must be clocked in. Any additional data clocked into the device after the address bytes will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the sector addressed by A23 - A0 will be reset to the logical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state. The complete three address bytes must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”. As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status Register (refer to “Status Register Commands” on page 19 for more details). If the Sector Protection Registers are locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-4. Unprotect Sector CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE SI 0 0 1 1 1 ADDRESS BITS A23-A0 0 MSB SO 16 0 1 A A A A A A A A A A A A MSB HIGH-IMPEDANCE AT26F004 3588C–DFLASH–04/06 AT26F004 9.5 Read Sector Protection Registers The Sector Protection Registers can be read to determine the current software protection status of each sector. Reading the Sector Protection Registers, however, will not determine the status of the WP pin. To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address within the sector must be clocked in. After the last address byte has been clocked in, the device will begin outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote the value of the appropriate Sector Protection Register. Table 9-2. Output Data Read Sector Protection Register – Output Data Sector Protection Register Value 00h Sector Protection Register value is 0 (sector is unprotected). FFh Sector Protection Register value is 1 (sector is protected). Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are software protected (refer “Status Register Commands” on page 19 for more details). Figure 9-5. Read Sector Protection Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 1 1 1 ADDRESS BITS A23-A0 1 MSB 0 0 A A A A A A A A A MSB DATA BYTE SO HIGH-IMPEDANCE D MSB D D D D D D D D D MSB 17 3588C–DFLASH–04/06 9.6 Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware locking to be active, two conditions must be met-the WP pin must be asserted and the SPRL bit must be in the logical “1” state. When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked. Therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the protection status of a sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be reset back to the logical “0” state. If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”, the only way to reset the bit back to the logical “0” state is to power-cycle or reset the device. This allows a system to power-up with all sectors software protected but not hardware locked. Therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the SPRL bit in the Status Register. When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit in the Status Register can still be set to a logical “1” to lock the Sector Protection Registers. This provides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector commands from being processed. Tables 9-3 and 9-4 detail the various protection and locking states of the device. Table 9-3. Software Protection WP Sector Protection Register n(1) Sector n(1) 0 Unprotected 1 Protected X (Don't Care) Note: 1. “n” represents a sector number Table 9-4. 18 Hardware and Software Locking WP SPRL Locking SPRL Sector Protection Registers 0 0 – Can be modified from 0 to 1 Unlocked and modifiable using the Protect and Unprotect Sector commands 0 1 Hardware locked Locked Locked in current state. Protect and Unprotect Sector commands will be ignored. 1 0 – Can be modified from 0 to 1 Unlocked and modifiable using the Protect and Unprotect Sector commands 1 1 Software locked Can be modified from 1 to 0 Locked in current state. Protect and Unprotect Sector commands will be ignored. AT26F004 3588C–DFLASH–04/06 AT26F004 10. Status Register Commands 10.1 Read Status Register The Status Register can be read to determine the device's ready/busy status, as well as the status of many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the device. After the last bit of the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin during every subsequent clock cycle. After the last bit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 10-1. Bit (1) Status Register Format Type(2) Name Description 7 SPRL Sector Protection Registers Locked R/W 0 1 Sector Protection Registers are unlocked (default). Sector Protection Registers are locked. 6 SPM Sequential Program Mode Status R 0 1 Byte programming mode (default). Sequential Programming mode entered. 5 RES Reserved for future use R 0 Reserved for future use. 4 WPP Write Protect (WP) Pin Status R 0 1 WP is asserted. WP is deasserted. 00 01 10 11 All sectors are software unprotected. Some sectors are software protected. Read Sector Protection Registers. Reserved for future use. All sectors are software protected (default). 3:2 SWP 1 WEL 0 RDY/BSY Notes: Software Protection Status R Write Enable Latch Status R 0 1 Device is not write enabled (default). Device is write enabled. Ready/Busy Status R 0 1 Device is ready. Device is busy with an internal operation. 1. Bit 7 of the Status Register is the only bit that can be user modified 2. R/W = Readable and writable R = Readable only 19 3588C–DFLASH–04/06 10.1.1 SPRL Bit The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect Sector and Unprotect Sector commands (the device will ignore these commands). Any sectors that are presently protected will remain protected, and any sectors that are presently unprotected will remain unprotected. When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and can be modified (the Protect Sector and Unprotect Sector commands will be processed as normal). The SPRL bit defaults to the logical “0” state after a power-up or a device reset. The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then the SPRL bit may only be changed from a logical “0” (Sector Protection Registers are unlocked) to a logical “1” (Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical “0” using the Write Status Register command, the WP pin will have to first be deasserted. The SPRL bit is the only bit of the Status Register than can be user modified via the Write Status Register command. 10.1.2 SPM Bit The SPM bit indicates whether the device is in the Byte Program mode or the Sequential Program mode. The default state after power-up or device reset is the Byte Program mode. 10.1.3 WPP Bit The WPP bit can be read to determine if the WP pin has been asserted or not. 10.1.4 SWP Bits The SWP bits provide feedback on the software protection status for the device. There are three possible combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using the Protect Sector command. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. 10.1.5 WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automatically under the following conditions: • Write Disable operation completes successfully • Write Status Register operation completes successfully or aborts • Protect Sector operation completes successfully or aborts • Unprotect Sector operation completes successfully or aborts • Byte Program operation completes successfully or aborts • Sequential Program Mode reaches highest unprotected memory location • Sequential Program Mode reaches the end of the memory array • Sequential Program Mode aborts 20 AT26F004 3588C–DFLASH–04/06 AT26F004 • Block Erase operation completes successfully or aborts • Chip Erase operation completes successfully or aborts If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command must have been clocked into the device. 10.1.6 RDY/BSY Bit The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a logical “0”. Figure 10-1. Read Status Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK OPCODE SI 0 0 0 0 0 1 0 1 MSB STATUS REGISTER DATA SO HIGH-IMPEDANCE D MSB D D D D D D D STATUS REGISTER DATA D MSB D D D D D D D D D MSB 21 3588C–DFLASH–04/06 10.2 Write Status Register The Write Status Register command is used to modify the SPRL bit of the Status Register. Before the Write Status Register command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Write Status Register command, the CS pin must first be asserted and the opcode of 01h must be clocked into the device. After the opcode has been clocked in, one byte of data comprised of the SPRL bit value and seven don't care bits must be clocked in. Any additional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be reset back to a logical “0”. The complete one byte of data must be clocked into the device before the CS# pin is deasserted; otherwise, the device will abort the operation, the state of the SPRL bit will not change, and the WEL bit in the Status Register will be reset back to the logical “0” state. If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register command will be ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Figure 10-2. Write Status Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK OPCODE SI 0 0 0 0 0 STATUS REGISTER IN 0 MSB SO 22 0 1 D X X X X X X X MSB HIGH-IMPEDANCE AT26F004 3588C–DFLASH–04/06 AT26F004 11. Other Commands and Functions 11.1 Read Manufacturer and Device ID Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information. To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00h indicating that no Extended Device Information follows. After the Extended Device Information String Length byte is output, the SO pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional. Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 11-1. Byte No. Manufacturer and Device ID Information Data Type Value 1 Manufacturer ID 1FH 2 Device ID (Part 1) 04H 3 Device ID (Part 2) 00H 4 Extended Device Information String Length 00H 23 3588C–DFLASH–04/06 Table 11-2. Manufacturer and Device ID Details Data Type Manufacturer ID Device ID (Part 1) Device ID (Part 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 JEDEC Assigned Code 0 0 0 1 1 Family Code 0 0 Density Code 0 0 0 MLC Code 0 0 1 1 0 0 Product Version Code 0 0 0 0 0 0 Hex Value Details 1FH JEDEC Code: 0001 1111 (1FH for Atmel) 04H Family Code: Density Code: 000 (AT26Fxxx series) 00100 (4-Mbit) 00H MLC Code: 000 (1-bit/cell technology) Product Version: 00000 (Initial version) Figure 11-1. Read Manufacturer and Device ID CS 0 6 7 8 14 15 16 22 23 24 30 31 32 38 SCK OPCODE SI 9Fh HIGH-IMPEDANCE SO Note: Each transition 24 1Fh 04h 00h 00h MANUFACTURER ID DEVICE ID BYTE 1 DEVICE ID BYTE 2 EXTENDED DEVICE INFORMATION STRING LENGTH shown for SI and SO represents one byte (8 bits) AT26F004 3588C–DFLASH–04/06 AT26F004 11.2 Deep Power-down During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep Power-down command offers the ability to place the device into an even lower power consumption state called the Deep Power-down mode. When the device is in the Deep Power-down mode, all commands including the Read Status Register command will be ignored with the exception of the Resume from Deep Power-down command. Since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. Entering the Deep Power-down mode is accomplished by simply asserting the CS pin, clocking in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Deep Power-down mode within the maximum time of tEDPD. The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device will abort the operation and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle or a device reset. The Deep Power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-down mode. Figure 11-2. Deep Power-down CS tEDPD 0 1 2 3 4 5 6 7 SCK OPCODE SI 1 0 1 1 1 0 0 1 MSB SO HIGH-IMPEDANCE Active Current ICC Standby Mode Current Deep Power-Down Mode Current 25 3588C–DFLASH–04/06 11.3 Resume from Deep Power-down In order exit the Deep Power-down mode and resume normal device operation, the Resume from Deep Power-down command must be issued. The Resume from Deep Power-down command is the only command that the device will recognize while in the Deep Power-down mode. To resume from the Deep Power-down mode, the CS pin must first be asserted and opcode of ABh must be clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Powerdown mode within the maximum time of tRDPD and return to the standby mode. After the device has returned to the standby mode, normal command operations such as Read Array can be resumed. If the complete opcode is not clocked in before the CS pin is deasserted, then the device will abort the operation and return to the Deep Power-down mode. Figure 11-3. Resume from Deep Power-down CS tRDPD 0 1 2 3 4 5 6 7 SCK OPCODE SI 1 0 1 0 1 0 1 1 MSB SO HIGH-IMPEDANCE Active Current ICC Deep Power-Down Mode Current 26 Standby Mode Current AT26F004 3588C–DFLASH–04/06 AT26F004 11.4 Hold The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until it is finished. The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are asserted. While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode. To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won't end until the beginning of the next SCK low pulse. If the CS pin is deasserted while the HOLD pin is still asserted, then the Hold mode will abort and the device may abort the current operation depending on whether or not a complete opcode, address bytes, or data byte was already clocked into the device before the Hold mode was entered. The WEL bit in the Status Register will be reset back to a logical “0” if a program, erase, Protect Sector, Unprotect Sector, or Write Status Register operation aborts as a result of the Hold mode aborting. Figure 11-4. Hold Mode CS SCK HOLD Hold Hold Hold 27 3588C–DFLASH–04/06 12. Electrical Specifications 12.1 Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground .....................................-0.6V to +4.1V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.5V 12.2 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC and AC Operating Range AT26F004 Operating Temperature (Case) Industrial -40°C to 85°C VCC Power Supply 12.3 2.7V to 3.6V DC Characteristics Symbol Parameter Condition ISB Standby Current IDPD Deep Power-down Current ICC1 Active Current, Read Operation Min Typ Max Units CS, WP, HOLD = VCC, all inputs at CMOS levels 25 35 µA CS, WP, HOLD = VCC, all inputs at CMOS levels 20 25 µA f = 33 MHz; IOUT = 0 mA; CS = VIL, VCC = Max 8 12 f = 20 MHz; IOUT = 0 mA; CS = VIL, VCC = Max 7 10 mA ICC2 Active Current, Program Operation CS = VCC, VCC = Max 9 12 mA ICC3 Active Current, Erase Operation CS = VCC, VCC = Max 9 12 mA ILI Input Leakage Current VIN = CMOS levels 1 µA ILO Output Leakage Current VOUT = CMOS levels 1 µA VIL Input Low Voltage 0.3 x VCC V VIH Input High Voltage VOL Output Low Voltage IOL = 1.6 mA; VCC = Min VOH Output High Voltage IOH = -100 µA 28 0.7 x VCC V 0.4 VCC - 0.2V V V AT26F004 3588C–DFLASH–04/06 AT26F004 12.4 AC Characteristics Symbol Parameter fSCK Max Units Serial Clock (SCK) Frequency 33 MHz fRDLF SCK Frequency for Read Array (Low Frequency – 03h opcode) 20 MHz tSCKH SCK High Time 13 20(1) ns tSCKL SCK Low Time 13 20(1) ns tSCKR(2) SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tSCKF(2) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns tCSH Chip Select High Time 50 ns tCSLS Chip Select Low Setup Time (relative to SCK) 5 ns tCSLH Chip Select Low Hold Time (relative to SCK) 5 12(3) ns tCSHS Chip Select High Setup Time (relative to SCK) 5 ns tCSHH Chip Select High Hold Time (relative to SCK) 5 ns tDS Data In Setup Time 3 ns tDH Data In Hold Time 3 ns tOH Output Hold Time 0 ns tDIS(2) Output Disable Time tV Output Valid Time tHLS HOLD Low Setup Time (relative to SCK) 5 ns tHLH HOLD Low Hold Time (relative to SCK) 5 ns tHHS HOLD High Setup Time (relative to SCK) 5 ns tHHH HOLD High Hold Time (relative to SCK) 5 ns tHLQZ(2) HOLD Low to Output High-Z 9 ns tHHQX(2) HOLD High to Output Low-Z 9 ns tWPS(2)(4) Write Protect Setup Time 20 ns Write Protect Hold Time 100 ns tWPH (2)(4) Min 10 ns 12 18(1) ns tSECP(2) Sector Protect Time (from Chip Select High) 20 ns tSECUP(2) Sector Unprotect Time (from Chip Select High) 20 ns tEDPD(2) Chip Select High to Deep Power-down 3 µs tRDPD(2) Chip Select High to Standby Mode 3 µs Notes: 1. Specification only applies when using the 03h Read Array (Low Frequency) command. 2. Not 100% tested (value guaranteed by design and characterization). 3. Specification only applies when using the SPI Mode 3 timing. 4. Only applicable as a constraint for the Write Status Register command when SPRL = 1. 29 3588C–DFLASH–04/06 12.5 Program and Erase Characteristics Symbol Parameter tBP Byte Program Time tPP Page Program Time (256 Bytes Using Sequential Program Mode) tBLKE Units µs ms 4-Kbyte 0.1 0.35 32-Kbyte 0.38 0.65 64-Kbyte 0.75 1.0 6 10 sec. 200 ns Write Status Register Time Note: 1. Not 100% tested (value guaranteed by design and characterization). 12.6 Power-Up Conditions Parameter Min Minimum VCC to Chip Select Low Time Max 50 Power-up Device Delay Before Program or Erase Allowed Power-on Reset Voltage 12.7 Max 5 Chip Erase Time (1) Typ 15 Block Erase Time tCHPE tWRSR Min 1.5 sec. Units µs 10 ms 2.5 V Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 2.4V 1.5V 0.45V AC MEASUREMENT LEVEL tR, tF < 2 ns (10% to 90%) 12.8 Output Test Load DEVICE UNDER TEST 30 pF 30 AT26F004 3588C–DFLASH–04/06 AT26F004 13. AC Waveforms Figure 13-1. Serial Input Timing tCSH CS tCSLH tSCKL tCSLS tSCKH tCSHH tCSHS SCK tDS SI SO tDH MSB LSB MSB HIGH-IMPEDANCE Figure 13-2. Serial Output Timing CS tSCKH tSCKL tDIS SCK SI tOH tV tV SO Figure 13-3. HOLD Timing – Serial Input CS SCK tHHH tHLS tHLH tHHS HOLD SI SO HIGH-IMPEDANCE 31 3588C–DFLASH–04/06 Figure 13-4. HOLD Timing – Serial Output CS SCK tHHH tHLS tHLH tHHS HOLD SI tHLQZ tHHQX SO Figure 13-5. WP Timing for Write Status Register Command When SPRL = 1 CS tWPH tWPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE SO 32 0 0 X MSB LSB OF WRITE STATUS REGISTER DATA BYTE MSB OF NEXT OPCODE HIGH-IMPEDANCE AT26F004 3588C–DFLASH–04/06 AT26F004 14. Ordering Information 14.1 Green Package Options (Pb/Halide-free/RoHS Compliant) fSCK (MHz) 33 Note: Ordering Code Package AT26F004-SSU 8S1 AT26F004-SU 8S2 AT26F004-MU(1) 8M1-A Operation Range Industrial (-40°C to 85°C) 1. Contact Atmel for availability. Package Type 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8M1-A 8-lead, 6 x 5 mm Very Thin Micro Lead-frame Package (MLF) 33 3588C–DFLASH–04/06 15. Packaging Information 15.1 8S1 – JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 SYMBOL MIN NOM MAX A1 0.10 – 0.25 NOTE D SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 R 34 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. 8S1 C AT26F004 3588C–DFLASH–04/06 AT26F004 15.2 8S2 – EIAJ SOIC C 1 E E1 L N θ TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW NOM MAX NOTE A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 θ 0° 8° e Notes: 1. 2. 3. 4. 5. MIN 1.27 BSC 2, 3 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 4/7/06 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. 8S2 REV. D 35 3588C–DFLASH–04/06 15.3 8M1-A – MLF D D1 0 Pin 1 ID E E1 SIDE VIEW TOP VIEW A3 A2 A1 A 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) D2 Pin #1 Notch (0.20 R) e E2 SYMBOL MIN NOM A – 0.85 1.00 A1 – – 0.05 A2 b L K BOTTOM VIEW 0.20 TYP 0.35 0.40 D 6.00 TYP D1 5.75 TYP D2 3.20 3.40 E 5.00 TYP E1 4.75 TYP E2 3.80 4.00 e L 0.48 3.60 4.20 1.27 0.50 0.60 0 K NOTE 0.65 TYP A3 b MAX 0.75 12o 1.30 REF 12/6/04 R 36 2325 Orchard Parkway San Jose, CA 95131 TITLE 8M1-A, 8-pad, 6 x 5 x 1.00 mm Body, Very Thin Dual Flat Package No Lead (MLF) DRAWING NO. 8M1-A REV. A AT26F004 3588C–DFLASH–04/06 AT26F004 16. Revision History Revision Level – Release Date History A – October 2005 Initial release B – January 2006 Changed tCSLH parameter for SPI Mode 3 timing C – April 2006 Changed Note 5 of 8S2 package drawing to generalize terminal plating comment 37 3588C–DFLASH–04/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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