Features
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Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time - 120 ns
Internal Program Control and Timer
16K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte-By-Byte Programming - 30 µs/Byte Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
- 25 mA Active Current
- 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Small Packaging
- 8 x 14 mm CBGA
Description
The AT49BV/LV080 are 3-volt-only in-system Flash Memory devices. Their 8 megabits of memory are organized as 1,024,576 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 120
ns with power dissipation of just 90 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 50 µA.
The device contains a user-enabled "boot block" protection feature. Two versions of
the feature are available: the AT49BV/LV080 locates the boot block at lowest order
addresses ("bottom boot"); the AT49BVLV080T locates it at highest order addresses
("top boot").
(continued)
TSOP Top View
Pin Configurations
Pin Name
Function
A0 - A19
Addresses
Type 1
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
RDY/BUSY
Ready/Busy Output
I/O0 - I/O7
Data Inputs/Outputs
CBGA Top View
1
2
3
4
5
6
AT49BV080
AT49BV080T
AT49LV080
AT49LV080T
SOIC
7
A
A5
A8 A11 NC A12 A15 A17
A4
A7 A10 VCC A13 NC A18
A6
A9 RST CE A14 A16 A19
B
C
D
A3 I/O1 NC VCC I/O4 I/O7 NC
E
A2
8-Megabit
(1M x 8)
Single 2.7-volt
Battery-Voltage
Flash Memory
A0 I/O3 GND I/O6 OE NC
F
A1 I/O0 I/O2 GND I/O5 RY/BY WE
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O3
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE
OE
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
0812A–8/97
Description (Continued)
To allow for simple in-system reprogrammability, the
AT49BV/LV080 does not require high input voltages for
programming. 3-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV080 is performed by erasing the entire 8 megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can
be optionally detected by the DATA polling feature. Once
Block Diagram
AT49BV/LV080T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
OE, CE, AND WE
LOGIC
8
DATA LATCH
DATA LATCH
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
Y-GATING
Y DECODER
ADDRESS
INPUTS
The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure
code, and when the feature is enabled, the boot sector is
permanently protected from being reprogrammed.
AT49BV/LV080
VCC
GND
OE
WE
CE
the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000
cycles.
Y-GATING
FFFFFH
MAIN MEMORY
(1008K BYTES)
X DECODER
FFFFFH
OPTIONAL BOOT
BLOCK (16K BYTES)
03FFFH
FC000H
MAIN MEMORY
(1008K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
00000H
00000H
Device Operation
READ: The AT49BV/LV080 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus
contention.
ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can
be erased at one time by using a 6-byte software code.
The software chip erase code consists of 6-byte load commands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the in-
2
AT49BV/LV080
ternal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table).
The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming
lockout feature. This feature prevents programming of
data in the designated block once the feature has been
enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address
range of the AT49BV/LV080 boot block is 00000H to
03FFFH while the address range of the AT49BV/LV080T
boot block is FC000H to FFFFFH.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must
AT49BV/LV080
Device Operation (Continued)
be performed. Please refer to the Command Definitions
table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identification exit code should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming
lockout by taking the RESET pin to 12 + 0.5 volts. By doing
this, protected boot block data can be altered through a
chip erase, or byte programming. When the RESET pin is
brought back to TTL levels the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49BV/LV080 features DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
RDY/BUSY: An open drain READY/BUSY output pin provides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection allows for OR - tying of several devices to the same
RDY/BUSY line.
RESET: A RESET input pin is provided to ease some
system applications. When RESET is at a logic high level,
the device is in its standard operating mode. A low level on
the RESET input halts the present device operation and
puts the outputs of the device in a high impedance state.
If the RESET pin makes a high to low transition during a
program or erase operation, the operation may not be successfully completed, and the operation will have to be repeated after a high level is applied to the RESET pin.
When a high level is reasserted on the RESET pin, the
device returns to the read or standby mode, depending
upon the state of the control inputs. By applying a 12V +
0.5V input signal to the RESET pin the boot block array
can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming
Lockout Override section).
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV/LV080 in the following ways: (a) VCC sense: if
VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
TOGGLE BIT: I n a d d i t i o n t o DATA po ll in g, t he
AT49BV/LV080 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
3
Command Definition (in Hex)
Command Bus
Sequence Cycles
1st Bus
Cycle
Addr
Data
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
10
2AAA
55
5555
40
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte
Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block
(1)
Lockout
6
5555
AA
2AAA
55
5555
80
5555
AA
Product ID
Entry
3
5555
AA
2AAA
55
5555
90
Product ID
(2)
Exit
3
5555
AA
2AAA
55
5555
F0
Product ID
(2)
Exit
1
XXXX
F0
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV080 and FC000H to FFFFFH for the
AT49BV/LV080T.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V CC + 0.6V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
4
AT49BV/LV080
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
AT49BV/LV080
DC and AC Operating Range
AT49BV/LV080-12
AT49BV/LV080-15
AT49BV/LV080-20
0°C - 70°C
0°C - 70°C
0°C - 70°C
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
2.7V - 3.6V / 3.0V - 3.6V
2.7V - 3.6V / 3.0V - 3.6V
2.7V - 3.6V / 3.0V - 3.6V
Operating Modes
Mode
Read
Program
(2)
CE
OE
WE
RESET
Ai
I/O
RDY/BUSY
VIL
VIL
VIH
VIH
Ai
DOUT
VOH
VIL
VIH
VIL
VIH
Ai
DIN
VOL
Standby/Write
Inhibit
VIH
X (1)
X
VIH
X
High Z
VOH
Program Inhibit
X
X
VIH
VIH
VOH
Program Inhibit
X
VIL
X
VIH
Output Disable
X
VIH
X
VIH
VOH
RESET
X
X
X
VIL
X
VIH
A1 - A19 = VIL, A9 = VH, (3)
A0 = VIL
A1 - A19 = VIL, A9 = VH, (3)
A0 = VIH
High Z
VOH
High Z
Product
Identification
Hardware
VIL
VIL
VIH
Software (5)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
Manufacturer Code (4)
Device Code (4)
A0 = VIL, A1 - A19 = VIL
Manufacturer Code (4)
A0 = VIH, A1 - A19 = VIL
Device Code (4)
4. Manufacturer Code: 1FH,
Device Code: 23H (AT49BV/LV080), 27H (AT49BV/LV080T)
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Max
Units
ILI
Symbol
Input Load Current
Parameter
VIN = 0V to VCC
Condition
Min
1
µA
ILO
Output Leakage Current
VI/O = 0V to VCC
1
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
50
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
1
mA
ICC (1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA, VCC = 3.6V
25
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6 mA, VCC = 3.0V
VOH
Output High Voltage
IOH = -100 µA, VCC = 3.0V
Note:
2.0
V
0.45
2.4
V
V
1. ICC in the erase mode is 50 mA.
5
AC Read Characteristics
AT49BV/LV080-12 AT49BV/LV080-15 AT49BV/LV080-20
Symbol
Parameter
tACC
Min
Max
Min
Max
Min
Max
Units
Address to Output Delay
120
150
200
ns
tCE
(1)
CE to Output Delay
120
150
200
ns
tOE
(2)
OE to Output Delay
0
50
0
70
0
100
ns
tDF
(3, 4)
CE or OE to Output Float
0
30
0
40
0
50
ns
Output Hold from OE, CE or
Address, whichever occurred first
0
tOH
0
0
ns
AC Read Waveforms (1,2,3,4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
CIN
COUT
Note:
6
Typ
Max
Units
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
AT49BV/LV080
Conditions
AT49BV/LV080
AC Byte Load Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Set-up Time
tAH
Address Hold Time
tCS
Min
Max
Units
0
ns
100
ns
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
200
ns
tDS
Data Set-up Time
100
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
200
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
7
Program Cycle Characteristics
Symbol
Parameter
tBP
Byte Programming Time
tAS
Address Set-up Time
tAH
Min
Max
Units
30
50
µs
0
ns
Address Hold Time
100
ns
tDS
Data Set-up Time
100
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
200
ns
tWPH
Write Pulse Width High
200
ns
tEC
Erase Cycle Time
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note:
8
Typ
OE must be high only when WE and CE are both low.
AT49BV/LV080
10
seconds
AT49BV/LV080
Data Polling Characteristics
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
(1)
Min
Typ
Max
10
ns
10
ns
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Units
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
(1)
Min
OE to Output Delay
tOEHP
OE High Pulse
tWR
Write Recovery Time
Max
Units
10
ns
10
ns
(2)
tOE
Typ
ns
150
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms (1, 2, 3)
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit. The tOEHP specification must be
met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address
should not vary.
9
Software Product (1)
Identification Entry
Boot Block Lockout
(1)
Feature Enable Algorithm
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE (2, 3, 5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product (1)
Identification Exit
LOAD DATA AA
TO
ADDRESS 5555
OR
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE (4)
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE (4)
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A19 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 23H (AT49BV/LV080), 27H (AT49BV/LV080T)
10
AT49BV/LV080
PAUSE 1 second (2)
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
AT49BV/LV080
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
120
25
150
200
120
150
200
Ordering Code
Package
Operation Range
0.05
AT49BV080-12CC
AT49BV080-12RC
AT48BV080-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49BV080-12CI
AT49BV080-12RI
AT49BV080-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49BV080-15CC
AT49BV080-15RC
AT49BV080-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49BV080-15CI
AT49BV080-15RI
AT49BV080-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49BV080-20CC
AT49BV080-20RC
AT49BV080-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49BV080-20CI
AT49BV080-20RI
AT49BV080-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49BV080T-12CC
AT49BV080T-12RC
AT48BV080T-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49BV080T-12CI
AT49BV080T-12RI
AT49BV080T-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49BV080T-15CC
AT49BV080T-15RC
AT49BV080T-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49BV080T-15CI
AT49BV080T-15RI
AT49BV080T-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49BV080T-20CC
AT49BV080T-20RC
AT49BV080T-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49BV080T-20CI
AT49BV080T-20RI
AT49BV080T-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
Package Type
42C2
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44R
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40T
40-Lead, Thin Small Outline Package (TSOP)
11
Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
120
25
150
200
120
150
200
Ordering Code
Package
0.05
AT49LV080-12CC
AT49LV080-12RC
AT48LV080-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49LV080-12CI
AT49LV080-12RI
AT49LV080-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49LV080-15CC
AT49LV080-15RC
AT49LV080-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49LV080-15CI
AT49LV080-15RI
AT49LV080-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49LV080-20CC
AT49LV080-20RC
AT49LV080-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49LV080-20CI
AT49LV080-20RI
AT49LV080-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49LV080T-12CC
AT49LV080T-12RC
AT48LV080T-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49LV080T-12CI
AT49LV080T-12RI
AT49LV080T-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49LV080T-15CC
AT49LV080T-15RC
AT49LV080T-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49LV080T-15CI
AT49LV080T-15RI
AT49LV080T-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
25
0.05
AT49LV080T-20CC
AT49LV080T-20RC
AT49LV080T-20TC
42C2
44R
40T
Commercial
(0° to 70°C)
25
0.05
AT49LV080T-20CI
AT49LV080T-20RI
AT49LV080T-20TI
42C2
44R
40T
Industrial
(-40° to 85°C)
Package Type
12
42C2
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44R
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40T
40-Lead, Thin Small Outline Package (TSOP)
AT49BV/LV080
Operation Range