Features • Single Voltage Read/Write Operation: 2.65V to 3.6V • Fast Read Access Time – 70 ns • Sector Erase Architecture • • • • • • • • • • • • • – Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout – Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout Fast Word Program Time – 10 µs Fast Sector Erase Time – 100 ms Suspend/Resume Feature for Erase and Program – Supports Reading and Programming from Any Sector by Suspending Erase of a Different Sector – Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending Programming of Any Other Byte/Word Low-power Operation – 10 mA Active – 15 µA Standby Data Polling, Toggle Bit, Ready/Busy for End of Program Detection RESET Input for Device Initialization Sector Lockdown Support TSOP and CBGA Package Options Top or Bottom Boot Block Configuration Available 128-bit Protection Register Minimum 100,000 Erase Cycles Common Flash Interface (CFI) Green (Pb/Halide-free) Packaging 16-megabit (1M x 16/2M x 8) 3-volt Only Flash Memory AT49BV163D AT49BV163DT 1. Description The AT49BV163D(T) is a 2.7-volt 16-megabit Flash memory organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 39 sectors for erase operations. The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see “Sector Lockdown” on page 5). To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the toggle bit. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to VCC. Erase, 3590A–FLASH–12/05 Erase Suspend/Resume and Program Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. The BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic “1”, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated, and the I/O15 pin is used as an input for the LSB (A-1) address function. 2. Pin Configurations Pin Name Function A0 - A19 Addresses CE Chip Enable OE Output Enable WE Write Enable RESET Reset RDY/BUSY READY/BUSY Output I/O0 - I/O14 Data Inputs/Outputs I/O15 (A-1) I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) BYTE Selects Byte or Word Mode NC No Connect 2.1 48-lead TSOP (Type 1) Top View A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RESET NC NC RDY/BUSY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0 2.2 48-ball CBGA Top View (Ball Down) 1 2 3 4 5 6 A3 A7 RDY/BUSY WE A9 A13 A4 A17 NC RST A8 A12 A2 A6 A18 NC A10 A14 A1 A5 NC A19 A11 A15 A0 I/O0 I/O2 I/O5 I/O7 A16 CE I/O8 I/O10 I/O12 I/O14 BYTE OE I/O9 I/O11 VCC I/O13 I/015/A-1 VSS I/O1 I/O3 I/O4 I/O6 VSS A B C D E F G H 2 AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 3. Block Diagram I/O0 - I/O15/A-1 INPUT BUFFER INPUT BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA REGISTER A0 - A19 OUTPUT MULTIPLEXER OUTPUT BUFFER CE WE OE RESET BYTE COMMAND REGISTER ADDRESS LATCH DATA COMPARATOR Y-DECODER Y-GATING X-DECODER MAIN MEMORY RDY/BUSY WRITE STATE MACHINE PROGRAM/ERASE VOLTAGE SWITCH VCC GND 4. Device Operation 4.1 Command Sequences When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the “Command Definition Table” on page 11 (I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. 4.2 Read The AT49BV163D(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the out-puts. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention. 4.3 Reset A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. 3 3590A–FLASH–12/05 4.4 Erase Before a byte/word can be reprogrammed, it must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase command. 4.4.1 Chip Erase The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that has been locked out; it will erase only the unprotected sectors. After the chip erase, the device will return to the read or standby mode. 4.4.2 Sector Erase As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. The maximum time to erase a sector is tSEC. When the sector programming lockdown feature is not enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a sector that has been protected will result in the operation terminating immediately. 4.5 Byte/Word Programming Once a memory block is erased, it is programmed (to a logical “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the erase or program operation was performed successfully. 4.6 Program/Erase Status The device provides several bits to determine the status of a program or erase operation: I/O2, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 10 and the following four sections describe the function of these bits. To provide greater flexibility for system designers, the AT49BV163D(T) contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, “00” or “01”. If the configuration register is set to “00”, the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a “01”, a Product ID Exit command must be given after a successful program or erase operation before the part will return to the read mode. It is important to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the configuration register is “00”. Using the four-bus cycle Set Configuration Register command as shown in the “Command Definition Table” on page 11, the value 4 AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) of the configuration register can be changed. Voltages applied to the RESET pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as described below. 4.6.1 DATA Polling The AT49BV163D(T) features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a “00”, during a program cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. Please see “Status Bit Table” on page 10 for more details. If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked. The Data Polling status bit must be used in conjunction with the erase/program status bit as shown in the algorithm in Figures 4-1 and and 4-2 on page 8. 4.6.2 Toggle Bit In addition to Data Polling the AT49BV163D(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see “Status Bit Table” on page 10 for more details. The toggle bit status bit should be used in conjunction with the erase/program status bit as shown in the algorithm in Figures 4-3 and and 4-4 on page 9. 4.6.3 4.7 Erase/Program Status Bit The device offers a status bit on I/O5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to verify that an erase or a byte/word program operation has been successfully performed. If a program (Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a “0” while the erase or program operation is still in progress. Please see “Status Bit Table” on page 10 for more details. Sector Lockdown Each sector has a programming lockdown feature. This feature prevents programming of data in the designated sectors once the feature has been enabled. These sectors can contain secure code that is used to bring up the system. Enabling the lockdown feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; any sector’s usage as a write-protected region is optional to the user. 5 3590A–FLASH–12/05 At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down, the contents of the sector is read-only and cannot be erased or programmed. 4.7.1 Sector Lockdown Detection A software method is available to determine if programming of a sector is locked down. When the device is in the software product identification mode (see “Software Product Identification Entry/Exit” sections on page 21), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and the sector cannot be programmed. The software product identification exit code should be used to return to standard operation. 4.7.2 Sector Lockdown Override The only way to unlock a sector that is locked down is through reset or power-up cycles. After power-up or reset, the content of a sector that is locked down can be erased and reprogrammed. 4.8 Erase Suspend/Erase Resume The Erase Suspend command allows the system to interrupt a sector or chip erase operation and then program or read data from a different sector within the memory. After the Erase Suspend command is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same. 4.9 Program Suspend/Program Resume The Program Suspend command allows the system to interrupt a programming operation and then read data from a different byte/word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 µs to suspend the programming operation. After the programming operation has been suspended, the system can then read data from any other byte/word that is not contained in the sector in which the programming operation was suspended. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. 4.10 Product Identification The product identification mode identifies the device and manufacturer as Atmel. It is accessed using a software operation. For details, see “Operating Modes” on page 15 or “Software Product Identification Entry/Exit” sections on page 21. 6 AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 4.11 128-bit Protection Register The AT49BV163D(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the “Command Definition Table” on page 11. To lock out block B, the four-bus cycle Lock Protection Register command must be used as shown in the “Command Definition Table” . Data bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To determine whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protection Register Addressing Table” on page 12 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not, or reading the protection register, the Product ID Exit command must be given prior to performing any other operation. 4.12 RDY/BUSY An open-drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open-drain connection allows for ORtying of several devices to the same RDY/BUSY line. Please see “Status Bit Table” on page 10 for more details. 4.13 Common Flash Interface (CFI) CFI is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in “Common Flash Interface Definition Table” on page 22. To exit the CFI Query mode, the product ID exit command must be given. 4.14 Hardware Data Protection The Hardware Data Protection feature protects against inadvertent programs to the AT49BV163D(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. 4.15 Input Levels While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V. 7 3590A–FLASH–12/05 Figure 4-1. Data Polling Algorithm (Configuration Register = 00) Figure 4-2. START START Read I/O7 - I/O0 Addr = VA Read I/O7 - I/O0 Addr = VA I/O7 = Data? YES I/O7 = Data? NO NO I/O5 = 1? I/O5 = 1? YES YES Read I/O7 - I/O0 Addr = VA I/O7 = Data? Read I/O7 - I/O0 Addr = VA YES I/O7 = Data? NO Program/Erase Operation Not Successful, Write Product ID Exit Command YES NO Program/Erase Operation Not Successful, Write Product ID Exit Command Program/Erase Operation Successful, Device in Read Mode 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. 8 YES NO NO Notes: Data Polling Algorithm (Configuration Register = 01) Notes: Program/Erase Operation Successful, Write Product ID Exit Command 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) Figure 4-3. Toggle Bit Algorithm (Configuration Register = 00) Figure 4-4. START START Read I/O7 - I/O0 Read I/O7 - I/O0 Read I/O7 - I/O0 Read I/O7 - I/O0 Toggle Bit = Toggle? NO Toggle Bit = Toggle? NO YES YES NO NO I/O5 = 1? I/O5 = 1? YES YES Read I/O7 - I/O0 Twice Toggle Bit = Toggle? Read I/O7 - I/O0 Twice NO Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command Note: Toggle Bit Algorithm (Configuration Register = 01) NO YES Program/Erase Operation Successful, Device in Read Mode 1. The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”. Program/Erase Operation Not Successful, Write Product ID Exit Command Note: Program/Erase Operation Successful, Write Product ID Exit Command 1. The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop toggling as I/O5 changes to “1”. 9 3590A–FLASH–12/05 5. Status Bit Table Status Bit I/O7 I/O7 I/O6 I/O5(1) I/O2 RDY/BUSY 00 01 00/01 00/01 00/01 00/01 I/O7 0 TOGGLE 0 1 0 Erasing 0 0 TOGGLE 0 TOGGLE 0 Erase Suspended & Read Erasing Sector 1 1 1 0 TOGGLE 1 Erase Suspended & Read Non-erasing Sector DATA DATA DATA DATA DATA 1 Erase Suspended & Program Non-erasing Sector I/O7 0 TOGGLE 0 TOGGLE 0 Erase Suspended & Program Suspended and Reading from Non-suspended Sectors DATA DATA DATA DATA DATA 1 Program Suspended & Read Programming Sector I/O7 1 1 0 TOGGLE 1 Program Suspended & Read Non-programming Sector DATA DATA DATA DATA DATA 1 Configuration Register Programming Notes: 10 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 6. Command Definition Table Command Sequence 1st Bus Cycle Bus Cycles Addr Data Read 1 Addr DOUT Chip Erase 6 555 AA 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data AAA(2) 55 555 80 555 AA AAA 55 555 10 Sector Erase 6 555 AA AAA 55 555 80 555 AA Byte/Word Program 4 555 AA AAA 55 555 A0 Addr DIN Enter Single Pulse Program Mode 6 555 AA AAA 55 555 80 555 Single Pulse Byte/Word Program 1 Addr DIN Sector Lockdown 6 555 AA AAA(2) 55 555 80 Erase/Program Suspend 1 XXX B0 Erase/Program Resume 1 XXX 30 Product ID Entry 3 555 AA AAA 55 555 90 (5) Product ID Exit 3 555 AA AAA 55 555 F0(6) Product ID Exit(5) 1 XXX F0(6) Program Protection Register 4 555 AA AAA 55 555 Lock Protection Register - Block B 4 555 AA AAA 55 Status of Block B Protection 4 555 AA AAA Set Configuration Register 4 555 AA AAA CFI Query(10) 1 X55 98 Notes: 5th Bus Cycle (3)(4) AAA 55 SA AA AAA 55 555 A0 555 AA AAA 55 SA(3)(4) 60 C0 Addr(7) DIN 555 C0 080 X0 55 555 90 80 DOUT(8) 55 555 D0 XXX 00/01(9) 30 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are don’t care in the word mode. Address A19 through A11 and A-1 are don’t care in the byte mode. 2. Since A11 is a Don’t Care, AAA can be replaced with 2AA. 3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 13 - 14 for details). 4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled. 5. Either one of the Product ID Exit commands can be used. 6. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used. 7. Any address within the user programmable register region. Address locations are shown on “Protection Register Addressing Table” on page 12. 8. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed. 9. The default state (after power-up) of the configuration register is “00”. 10. When accessing the data in the CFI table, the address format is A15 - A0 (Hex) in the word mode, A14 - A0 (Hex), and A-1 = 0 in the byte mode. 11 3590A–FLASH–12/05 7. Absolute Maximum Ratings* *NOTICE: Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8. Protection Register Addressing Table Word Use Block A7 A6 A5 A4 A3 A2 A1 A0 0 Factory A 1 0 0 0 0 0 0 1 1 Factory A 1 0 0 0 0 0 1 0 2 Factory A 1 0 0 0 0 0 1 1 3 Factory A 1 0 0 0 0 1 0 0 4 User B 1 0 0 0 0 1 0 1 5 User B 1 0 0 0 0 1 1 0 6 User B 1 0 0 0 0 1 1 1 User B 1 0 0 0 1 0 0 0 7 Notes: 1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0. 2. The addressing shown above should be used when the device is operating in the word (x16) mode. 3. In the byte (x8) mode, A-1 should be used when addressing the protection register: with A-1 = 0, the LSB of the address location can be accessed; and with A-1 = 1, the MSB of the address location can be accessed 12 AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 9. AT49BV163D – Sector Address Table x8 x16 Size (Bytes/Words) Address Range (A19 - A-1) Address Range (A19 - A0) SA0 8K/4K 000000 - 001FFF 00000 - 00FFF SA1 8K/4K 002000 - 003FFF 01000 - 01FFF SA2 8K/4K 004000 - 005FFF 02000 - 02FFF SA3 8K/4K 006000 - 007FFF 03000 - 03FFF SA4 8K/4K 008000 - 009FFF 04000 - 04FFF SA5 8K/4K 00A000 - 00BFFF 05000 - 05FFF SA6 8K/4K 00C000 - 00DFFF 06000 - 06FFF SA7 8K/4K 00E000 - 00FFFF 07000 - 07FFF SA8 64K/32K 010000 - 01FFFF 08000 - 0FFFF SA9 64K/32K 020000 - 02FFFF 10000 - 17FFF SA10 64K/32K 030000 - 03FFFF 18000 - 1FFFF SA11 64K/32K 040000 - 04FFFF 20000 - 27FFF SA12 64K/32K 050000 - 05FFFF 28000 - 2FFFF SA13 64K/32K 060000 - 06FFFF 30000 - 37FFF SA14 64K/32K 070000 - 07FFFF 38000 - 3FFFF SA15 64K/32K 080000 - 08FFFF 40000 - 47FFF SA16 64K/32K 090000 - 09FFFF 48000 - 4FFFF SA17 64K/32K 0A0000 - 0AFFFF 50000 - 57FFF SA18 64K/32K 0B0000 - 0BFFFF 58000 - 5FFFF SA19 64K/32K 0C0000 - 0CFFFF 60000 - 67FFF SA20 64K/32K 0D0000 - 0DFFFF 68000 - 6FFFF SA21 64K/32K 0E0000 - 0EFFFF 70000 - 77FFF SA22 64K/32K 0F0000 - 0FFFFF 78000 - 7FFFF SA23 64K/32K 100000 - 10FFFF 80000 - 87FFF SA24 64K/32K 110000 - 11FFFF 88000 - 8FFFF SA25 64K/32K 120000 - 12FFFF 90000 - 97FFF SA26 64K/32K 130000 - 13FFFF 98000 - 9FFFF SA27 64K/32K 140000 - 14FFFF A0000 - A7FFF SA28 64K/32K 150000 - 15FFFF A8000 - AFFFF SA29 64K/32K 160000 - 16FFFF B0000 - B7FFF SA30 64K/32K 170000 - 17FFFF B8000 - BFFFF SA31 64K/32K 180000 - 18FFFF C0000 - C7FFF SA32 64K/32K 190000 - 19FFFF C8000 - CFFFF SA33 64K/32K 1A0000 - 1AFFFF D0000 - D7FFF SA34 64K/32K 1B0000 - 1BFFFF D8000 - DFFFF SA35 64K/32K 1C0000 - 1CFFFF E0000 - E7FFF SA36 64K/32K 1D0000 - 1DFFFF E8000 - EFFFF SA37 64K/32K 1E0000 - 1EFFFF F0000 - F7FFF SA38 64K/32K 1F0000 - 1FFFFF F8000 - FFFFF Sector 13 3590A–FLASH–12/05 10. AT49BV163DT – Sector Address Table Sector Size (Bytes/Words) x8 x16 Address Range (A19 - A-1) Address Range (A19 - A0) SA0 64K/32K 000000 - 00FFFF 00000 - 07FFF SA1 64K/32K 010000 - 01FFFF 08000 - 0FFFF SA2 64K/32K 020000 - 02FFFF 10000 - 17FFF SA3 64K/32K 030000 - 03FFFF 18000 - 1FFFF SA4 64K/32K 040000 - 04FFFF 20000 - 27FFF SA5 64K/32K 050000 - 05FFFF 28000 - 2FFFF SA6 64K/32K 060000 - 06FFFF 30000 - 37FFF SA7 64K/32K 070000 - 07FFFF 38000 - 3FFFF SA8 64K/32K 080000 - 08FFFF 40000 - 47FFF SA9 64K/32K 090000 - 09FFFF 48000 - 4FFFF SA10 64K/32K 0A0000 - 0AFFFF 50000 - 57FFF SA11 64K/32K 0B0000 - 0BFFFF 58000 - 5FFFF SA12 64K/32K 0C0000 - 0CFFFF 60000 - 67FFF SA13 64K/32K 0D0000 - 0DFFFF 68000 - 6FFFF SA14 64K/32K 0E0000 - 0EFFFF 70000 - 77FFF SA15 64K/32K 0F0000 - 0FFFFF 78000 - 7FFFF SA16 64K/32K 100000 - 10FFFF 80000 - 87FFF SA17 64K/32K 110000 - 11FFFF 88000 - 8FFFF SA18 64K/32K 120000 - 12FFFF 90000 - 97FFF SA19 64K/32K 130000 - 13FFFF 98000 - 9FFFF SA20 64K/32K 140000 - 14FFFF A0000 - A7FFF SA21 64K/32K 150000 - 15FFFF A8000 - AFFFF SA22 64K/32K 160000 - 16FFFF B0000 - B7FFF SA23 64K/32K 170000 - 17FFFF B8000 - BFFFF SA24 64K/32K 180000 - 18FFFF C0000 - C7FFF SA25 64K/32K 190000 - 19FFFF C8000 - CFFFF SA26 64K/32K 1A0000 - 1AFFFF D0000 - D7FFF SA27 64K/32K 1B0000 - 1BFFFF D8000 - DFFFF SA28 64K/32K 1C0000 - 1CFFFF E0000 - E7FFF SA29 64K/32K 1D0000 - 1DFFFF E8000 - EFFFF SA30 64K/32K 1E0000 - 1EFFFF F0000 - F7FFF SA31 8K/4K 1F0000 - 1F1FFF F8000 - F8FFF SA32 8K/4K 1F2000 - 1F3FFF F9000 - F9FFF SA33 8K/4K 1F4000 - 1F5FFF FA000 - FAFFF SA34 8K/4K 1F6000 - 1F7FFF FB000 - FBFFF SA35 8K/4K 1F8000 - 1F9FFF FC000 - FCFFF SA36 8K/4K 1FA000 - 1FBFFF FD000 - FDFFF SA37 8K/4K 1FC000 - 1FDFFF FE000 - FEFFF SA38 8K/4K 1FE000 - 1FFFFF FF000 - FFFFF 14 AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 11. DC and AC Operating Range AT49BV163D(T)-70 Operating Temperature (Case) Ind. -40°C - 85°C VCC Power Supply 2.65V to 3.6V 12. Operating Modes Mode Read Program/Erase (2) Standby/Program Inhibit CE OE WE RESET Ai I/O VIL VIL VIH VIH Ai DOUT VIL VIH VIL VIH Ai DIN VIH X(1) X VIH X High-Z X X VIH VIH X VIL X VIH Program Inhibit X X X VIH Output Disable X VIH X VIH Reset X X X VIL Product Identification Software(5) Notes: High-Z VIH X High-Z A0 = VIL, A1 - A19 = VIL Manufacturer Code(3) A0 = VIH, A1 - A19 = VIL Device Code(3)(4) 1. X can be VIL or VIH. 2. Refer to AC programming waveforms on page 19. 3. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: C0H (x8)-AT49BV163D; 01C0H (x16)-AT49BV163D; C2H (x8)-AT49BV163DT; 01C2H (x16)-AT49BV163DT. 4. Additional device code: 01H (x8) – AT49BV163D(T); 001H (x16) – AT49BV163D(T). 5. See details under “Software Product Identification Entry/Exit” on page 21. 13. DC Characteristics Symbol Parameter Condition ILI Input Load Current ILO Min Typ Max Units VIN = 0V to VCC 2 µA Output Leakage Current VI/O = 0V to VCC 2 µA ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC 15 25 µA ICC (1) VCC Active Read Current f = 5 MHz; IOUT = 0 mA 10 15 mA ICC1 VCC Programming Current 25 mA VIL Input Low Voltage 0.6 V VIH Input High Voltage 2.0 V VOL1 Output Low Voltage IOL = 2.1 mA 0.45 V VOL2 Output Low Voltage IOL = 1.0 mA 0.20 V VOH1 Output High Voltage IOH = -400 µA 2.4 V Output High Voltage IOH = -100 µA 2.5 V VOH2 Note: 1. In the erase mode, ICC is 25 mA. 15 3590A–FLASH–12/05 14. Input Test Waveforms and Measurement Level 2.0V 0.6V tR, tF < 5 ns 15. Output Test Load 16. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 16 1. This parameter is characterized and is not 100% tested. AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 17. AC Read Characteristics AT49BV163D(T)-70 Symbol Parameter Min Max tRC Read Cycle Time tACC Address to Output Delay 70 ns tCE(1) CE to Output Delay 70 ns tOE(2) OE to Output Delay 0 20 ns tDF(3)(4) CE or OE to Output Float 0 25 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 tRO RESET to Output Delay 70 Units ns ns 100 ns 18. AC Read Waveforms(1)(2)(3)(4) tRC ADDRESS ADDRESS VALID CE tCE tOE OE tDF tOH tACC tRO RESET OUTPUT Notes: HIGH Z OUTPUT VALID 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 17 3590A–FLASH–12/05 19. AC Byte/Word Load Characteristics Symbol Parameter Min Max Units tAS, tOES Address, OE Setup Time 0 ns tAH Address Hold Time 25 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 25 ns tWPH Write Pulse Width High 15 ns tDS Data Setup Time 25 ns tDH, tOEH Data, OE Hold Time 0 ns 20. AC Byte/Word Load Waveforms 20.1 WE Controlled 20.2 CE Controlled 18 AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 21. Program Cycle Characteristics Symbol Parameter Min Typ Max Units tBP Byte/Word Programming Time 10 120 µs tAS Address Setup Time 0 ns tAH Address Hold Time 25 ns tDS Data Setup Time 25 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 25 ns tWPH Write Pulse Width High 15 ns tWC Write Cycle Time 70 ns tRP Reset Pulse Width 500 ns tEC Chip Erase Cycle Time 16 tSEC1 Sector Erase Cycle Time (4K Word Sectors) 0.1 2.0 seconds tSEC2 Sector Erase Cycle Time (32K Word Sectors) 0.5 6.0 seconds tES Erase Suspend Time 15 µs tPS Program Suspend Time 10 µs tERES Delay between Erase Resume and Erase Suspend seconds 500 µs 22. Program Cycle Waveforms PROGRAM CYCLE OE CE tWP tBP tWPH WE tAS tAH A0 - A19 tDH 555 555 AAA tWC 555 ADDRESS tDS DATA 55 AA INPUT DATA A0 AA 23. Sector or Chip Erase Cycle Waveforms OE (1) CE tWP tWPH WE tAS A0-A19 tAH Notes: 555 555 AAA tWC DATA tDH 555 Note 2 AAA tEC /tSEC1/2 tDS AA 55 80 AA 55 Note 3 WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note 3 under “Command Definition Table” on page 11.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 19 3590A–FLASH–12/05 24. Data Polling Characteristics(1) Symbol Parameter Min tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns Max (2) tOE OE to Output Delay tWR Write Recovery Time Notes: Typ Units ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in “AC Read Characteristics” on page 17. 25. Data Polling Waveforms WE CE tOEH OE tDH I/O7 tOE A0-A19 tWR HIGH Z An An An An An 26. Toggle Bit Characteristics(1) Symbol Parameter Min tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) tOEHP OE High Pulse 50 ns tWR Write Recovery Time 0 ns Notes: Typ Max Units ns 1. These parameters are characterized and not 100% tested. 2. See tOE spec in “AC Read Characteristics” on page 17. 27. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 20 AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 28. Software Product Identification Entry(1) 30. Sector Lockdown Enable Algorithm(1) LOAD DATA AA TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 55 TO ADDRESS AAA LOAD DATA 90 TO ADDRESS 555 LOAD DATA 80 TO ADDRESS 555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA AA TO ADDRESS 555 29. Software Product Identification Exit(1)(6) LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA OR LOAD DATA 55 TO ADDRESS AAA LOAD DATA F0 TO ANY ADDRESS LOAD DATA 60 TO SECTOR ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4) LOAD DATA F0 TO ADDRESS 555 EXIT PRODUCT IDENTIFICATION MODE(4) Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) PAUSE 200 µs(2) Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don’t Care). 2. Sector Lockdown feature enabled. Address Format: A11 - A0 (Hex), A-1, and A11 - A19 (Don’t Care). 2. A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. Additional Device Code is read from address 0003H. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH(x8); 001FH(x16) Device Code:C0H (x8) - AT49BV163D; 01C0H (x16) - AT49BV163D; C2H (x8) - AT49BV163DT; 01C2H (x16) - AT49BV163DT. Additional Device Code: 01H(x8) – AT49BV163D(T); 0001H(x16) – AT49BV163D(T) 6. Either one of the Product ID Exit commands can be used. 21 3590A–FLASH–12/05 31. Common Flash Interface Definition Table 22 Address [x16 Mode] Address [x8 Mode] Data 10h 20h 0051h “Q” 11h 22h 0052h “R” 12h 24h 0059h “Y” 13h 26h 0002h 14h 28h 0000h 15h 2Ah 0041h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 0000h 19h 32h 0000h 1Ah 34h 0000h 1Bh 36h 0027h VCC min write/erase 1Ch 38h 0036h VCC max write/erase 1Dh 3Ah 0000h VPP min voltage 1Eh 3Ch 0000h VPP max voltage 1Fh 3Eh 0004h Typ word write – 10 µs 20h 40h 0000h 21h 42h 0009h Typ sector erase: 500 ms 22h 44h 000Eh Typ chip erase: 16,000 ms 23h 46h 0004h Max word write/typ time 24h 48h 0000h N/A 25h 4Ah 0004h Max sector erase/typ sector erase 26h 4Ch 0004h Max chip erase/typ chip erase 27h 4Eh 0015h Device size 28h 50h 0002h x8/x16 device 29h 52h 0000h x8/x16 device 2Ah 54h 0000h Multiple byte write not supported 2Bh 56h 0000h Multiple byte write not supported 2Ch 58h 0002h 2 regions, X = 2 2Dh 5Ah 0007h 8K bytes, Y = 7 2Eh 5Ch 0000h 8K bytes, Y = 7 2Fh 5Eh 0020h 8K bytes, Z = 32 30h 60h 0000h 8K bytes, Z = 32 31h 62h 001Eh 64K bytes, Y = 30 32h 64h 0000h 64K bytes, Y = 30 33h 66h 0000h 64K bytes, Z = 256 34h 68h 0001h 64K bytes, Z = 256 Comments AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 31. Common Flash Interface Definition Table (Continued) Address [x16 Mode] Address [x8 Mode] Data Comments Vendor Specific Extended Query 41h 82h 0050h “P” 42h 84h 0052h “R” 43h 86h 0049h “I” 44h 88h 0031h Major version number, ASCII 45h 8Ah 0030h Minor version number, ASCII Bit 0 – chip erase supported, 0 – no, 1 – yes Bit 1 – erase suspend supported, 0 – no, 1 – yes Bit 2 – program suspend supported, 0 – no, 1 – yes Bit 3 – simultaneous operations supported, 0 – no, 1 – yes Bit 4 – burst mode read supported, 0 – no, 1 – yes Bit 5 – page mode read supported, 0 – no, 1 – yes Bit 6 – queued erase supported, 0 – no, 1 – yes Bit 7 – protection bits supported, 0 – no, 1 – yes 46h 8Ch 0087h 47h 8Eh 0000h (top) or 0001h (bottom) Bit 8 – top (“0”) or bottom (“1”) boot block device undefined bits are “0” 48h 90h 0000h Bit 0 – 4-word linear burst with wrap around, 0 – no, 1 – yes Bit 1 – 8-word linear burst with wrap around, 0 – no, 1 – yes Bit 2 – continuos burst, 0 – no, 1 – yes Undefined bits are “0” 49h 92h 0000h Bit 0 – 4-word page, 0 – no, 1 – yes Bit 1 – 8-word page, 0 – no, 1 – yes Undefined bits are “0” 4Ah 94h 0080h Location of protection register lock byte, the section’s first byte 4Bh 96h 0003h # of bytes in the factory prog section of prot register – 2*n 4Ch 98h 0003h # of bytes in the user prog section of prot register – 2*n 23 3590A–FLASH–12/05 32. Ordering Information 32.1 tACC (ns) Green Package (Pb/Halide-free) ICC (mA) Active Standby Ordering Code Package Operation Range AT49BV163D-70CU 48C19 AT49BV163DT-70CU 70 15 Industrial (-40° to 85° C) 0.025 AT49BV163D-70TU 48T AT49BV163DT-70TU Package Type 48C19 48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 48T 48-lead, Plastic Thin Small Outline Package (TSOP) 24 AT49BV163D(T) 3590A–FLASH–12/05 AT49BV163D(T) 33. Packaging Information 33.1 48C19 – CBGA E A1 Ball ID D A1 Top View A Side View E1 1.0 REF e A1 Ball Corner 1.20 REF A COMMON DIMENSIONS (Unit of Measure = mm) B C SYMBOL D D1 E E F E1 G D MIN NOM MAX 5.90 6.00 6.10 NOTE 4.0 TYP 7.90 8.00 8.10 H e 6 5 4 3 2 1 Øb Bottom View D1 5.6 TYP A – – 1.0 A1 0.22 – – e b Ø 0.80 BSC 0.40 TYP 7/2/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 48C19, 48-ball (6 x 8 Array), 0.80 mm Pitch, 6.0 x 8.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 48C19 REV. A 25 3590A–FLASH–12/05 33.2 48T – TSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 Note 2 E 11.90 12.00 12.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-142, Variation DD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e NOTE 0.50 BASIC 10/18/01 R 26 2325 Orchard Parkway San Jose, CA 95131 TITLE 48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. REV. 48T B AT49BV163D(T) 3590A–FLASH–12/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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