ATMEL AT49BV6416-70TI 64-megabit (4m x 16) page mode 2.7-volt flash memory Datasheet

Features
• 64-megabit (4M x 16) Flash Memory
• 2.7V - 3.6V Read/Write
• High Performance
•
•
•
•
•
•
•
•
•
•
•
•
•
•
– Asynchronous Access Time – 70 ns
– Page Mode Read Time – 20 ns
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 200 ms
Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not Being
Programmed/Erased
– Memory Plane A: 16M of Memory Including Eight 4K Word Sectors
– Memory Plane B: 16M of Memory Consisting of 32K Word Sectors
– Memory Plane C: 16M of Memory Consisting of 32K Word Sectors
– Memory Plane D: 16M of Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 35 µA Standby
2.2V I/O Option Reduces Overall System Power
Data Polling and Toggle Bit for End of Program Detection
VPP Pin for Write Protection and Accelerated Program Operations
RESET Input for Device Initialization
TSOP Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
Green (Pb/Halide-free) Packaging Option
64-megabit
(4M x 16)
Page Mode
2.7-volt Flash
Memory
AT49BV6416
AT49BV6416T
1. Description
The AT49BV6416(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided
into multiple sectors and planes for erase operations. The device can be read or
reprogrammed off a single 2.7V power supply, making it ideally suited for in-system
programming. The output voltage can be separately controlled down to 2.2V through
the VCCQ supply pin. The device can operate in the asynchronous or page read
mode.
The AT49BV6416(T) is divided into four memory planes. A read operation can occur
in any of the three planes which is not being programmed or erased. This concurrent
operation allows improved system performance by not requiring the system to wait for
a program or erase operation to complete before a read is performed. To further
increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time
and let the user read data from or program data to any of the remaining sectors. There
is no reason to suspend the erase or program operation if the data to be read is in
another memory plane. The end of program or erase is detected by Data Polling or
toggle bit.
3451C–FLASH–2/05
The VPP pin provides data protection and faster programming times. When the VPP input is
below 0.7V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 10.0V, the program (dualword program command) operation is accelerated.
A six-byte command (Enter Single Pulse Program Mode) to remove the requirement of entering
the three-byte program sequence is offered to further improve programming time. After entering
the six-byte code, only single pulses on the write control lines are required for writing into the
device. This mode (Single Pulse Word Program) is exited by powering down the device, by taking the RESET pin to GND or by a high-to-low transition on the V PP input. Erase, Erase
Suspend/Resume, Program Suspend/Resume and Read Reset commands will not work while in
this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external
programming code.
2. Pin Configurations
2.1
Pin Name
Pin Function
I/O0 - I/O15
Data Inputs/Outputs
A0 - A21
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
WP
Write Protect
VPP
Write Protection and Power Supply for Accelerated Program
Operations
VCCQ
Output Power Supply
TSOP Top View (Type 1)
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE
RESET
VPP
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
3. Device Operation
3.1
Command Sequences
The device powers on in the read mode. Command sequences are used to place the device in
other operating modes such as program and erase. After the completion of a program or an
erase cycle, the device enters the read mode. The command sequences are written by applying
a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the
CE input with WE low and OE high. The address is latched on the falling edge of the WE or CE
pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,
whichever occurs first. The addresses used in the command sequences are not affected by
entering the command sequences.
3.2
Asynchronous Read
The AT49BV6416(T) is accessed like an EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins are asserted on the outputs.
The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
3.3
Page Read
The page read operation of the device is controlled by CE and OE inputs. The page size is four
words. The first word access of the page read is the same as the asynchronous read. The first
word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1
will result in subsequent reads within the page being output at a speed of 20 ns. The “Page
Read Cycle Waveform” is shown on page 21.
3.4
Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET pin halts the
present device operation and puts the outputs of the device in a high-impedance state. When a
high level is reasserted on the RESET pin, the device returns to read or standby mode, depending upon the state of the control pins.
3.5
Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The entire memory can be erased by using the Chip Erase command or individual
planes or sectors can be erased by using the Plane Erase or Sector Erase commands.
3.5.1
Chip Erase
Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the
last WE pulse. Chip Erase does not alter the data of the protected sectors. After the full chip
erase the device will return back to the read mode. The hardware reset during Chip Erase will
stop the erase but the data will be of unknown state. Any command during Chip Erase except
Erase Suspend will be ignored.
3
3451C–FLASH–2/05
3.5.2
Plane Erase
As a alternative to a full chip erase, the device is organized into four planes that can be individually erased. The plane erase command is a six-bus cycle operation. The plane whose address is
valid at the sixth falling edge of WE will be erased. The plane erase command does not alter the
data in protected sectors.
3.5.3
Sector Erase
As an alternative to a full chip erase or a plane erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a six-bus cycle operation.
The sector whose address is valid at the sixth falling edge of WE will be erased provided the
given sector has not been protected.
3.6
Word Programming
The device is programmed on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The programming address
and data are latched in the fourth cycle. The device will automatically generate the required
internal programming pulses. Please note that a “0” cannot be programmed back to a “1”; only
erase operations can convert “0”s to “1”s.
3.7
Flexible Sector Protection
The AT49BV6416(T) offers two sector protection modes, the Softlock and the Hardlock. The
Softlock mode is optimized as sector protection for sectors whose content changes frequently.
The Hardlock protection mode is recommended for sectors whose content changes infrequently.
Once either of these two modes is enabled, the contents of the selected sector is read-only and
cannot be erased or programmed. Each sector can be independently programmed for either the
Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled.
3.7.1
Softlock and Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a six-bus cycle Softlock command must be issued to the
selected sector.
3.7.2
Hardlock and Write Protect (WP)
The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin.
The Hardlock sector protection mode can be enabled by issuing a six-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the
Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
4
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
Table 3-1.
Hardlock and Softlock Protection Configurations in Conjunction with WP
Softlock
Erase/
Prog
Allowed?
VPP
WP
Hardlock
VCC
0
0
0
Yes
No sector is locked
VCC
0
0
1
No
Sector is Softlocked. The Unlock command can unlock the sector.
VCC
0
1
1
No
Hardlock protection mode is enabled. The sector cannot be
unlocked.
VCC
1
0
0
Yes
No sector is locked.
VCC
1
0
1
No
Sector is Softlocked. The Unlock command can unlock the sector.
VCC
1
1
0
Yes
Hardlock protection mode is overridden and the sector is not locked.
VCC
1
1
1
No
Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
VIL
x
x
x
No
Erase and Program Operations cannot be performed.
Figure 3-1.
Comments
Sector Locking State Diagram
UNLOCKED
[000]
LOCKED
A
B
[001]
C
Power-Up/Reset
Default
C
WP = VIL = 0
Hardlocked
[011]
A
[110]
B
C
WP = VIH = 1
[100]
A
B
Hardlocked is disabled by
WP = VIH
[111]
C
Power-Up/Reset
Default
[101]
A = Unlock Command
B = Softlock Command
C = Hardlock Command
Note:
1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP
and the two bits of the sector-lock status D[1:0].
3.7.3
Sector Protection Detection
A software method is available to determine if the sector protection Softlock or Hardlock features
are enabled. When the device is in the software product identification mode a read from the I/O0
and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked.
5
3451C–FLASH–2/05
Table 3-2.
3.8
Sector Protection Status
I/O1
I/O0
Sector Protection Status
0
0
Sector Not Locked
0
1
Softlock Enabled
1
0
Hardlock Enabled
1
1
Both Hardlock and Softlock Enabled
Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2,
I/O3, I/O5, I/O6, and I/O7. All other status bits are don’t care. The “Status Bit Table” on page 11
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the AT49BV6416(T) contains a programmable configuration register. The
configuration register allows the user to specify the status bit operation. The configuration register can be set to one of two different values, “00” or “01”. If the configuration register is set to
“00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be given
after a successful program or erase operation before the part will return to the read mode. It is
important to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID Exit command to return the
device to read mode. The default value (after power-up) for the configuration register is “00”.
Using the four-bus cycle set configuration register command as shown in the “Command Definition Table” on page 12, the value of the configuration register can be changed. Voltages applied
to the reset pin will not alter the value of the configuration register. The value of the configuration
register will affect the operation of the I/O7 status bit as described below.
3.8.1
Data Polling
The AT49BV6416(T) features Data Polling to indicate the end of a program cycle. If the status
configuration register is set to a “00”, during a program cycle an attempted read of the last word
loaded will result in the complement of the loaded data on I/O7. Once the program cycle has
been completed, true data is valid on all outputs and the next cycle may begin. During a chip or
sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program
or erase cycle has completed, true data will be read from the device. Data Polling may begin at
any time during the program cycle. Please see “Status Bit Table” on page 11 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed
a program or erase operation. Once I/O7 has gone high, status information on the other pins can
be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 3-2 and 3-3 on page 9.
3.8.2
Toggle Bit
In addition to Data Polling, the AT49BV6416(T) provides another method for determining the
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the memory will result in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle. Please see “Status Bit Table” on page 11 for
more details.
6
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit
as shown in the algorithm in Figures 3-4 and 3-5 on page 10.
3.8.3
Erase/Program Status Bit
The device offers a status bit on I/O5 that indicates whether the program or erase operation has
exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to
verify that an erase or a word program operation has been successfully performed. The device
may also output a “1” on I/O5 if the system tries to program a “1” to a location that was previously programmed to a “0”. Only an erase operation can change a “0” back to a “1”. If a program
(Sector Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be set
high, indicating the program (erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see “Status Bit Table” on page 11 for more details.
3.8.4
VPP Status Bit
The AT49BV6416(T) provides a status bit on I/O3 that provides information regarding the voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is
not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”.
Once the VPP status bit has been set to a “1”, the system must write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to
perform a program or erase operation successfully, the VPP status bit will output a “0”. Please
see “Status Bit Table” on page 11 for more details.
3.9
Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase operation and then
program or read data from a different sector within the same plane. Since this device has a multiple plane architecture, there is no need to use the erase suspend feature while erasing a sector
when you want to read data from a sector in another plane. After the Erase Suspend command
is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the
erase operation has been suspended, the plane that contains the suspended sector enters the
erase-suspend-read mode. The system can then read data or program data to any other sector
within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the
system must write the Erase Resume command. The Erase Resume command is a one-bus
cycle command, which does require the plane address. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from
any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase suspend are the same.
3.10
Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To resume
the programming operation, the system must write the Program Resume command. The
program suspend and resume are one-bus cycle commands. The command sequence for the
7
3451C–FLASH–2/05
erase suspend and program suspend are the same, and the command sequence for the erase
resume and program resume are the same.
3.11
128-Bit Protection Register
The AT49BV6416(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can be
locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 12. To lock out block B, the four-bus cycle
lock protection register command must be used as shown in the Command Definition table. Data
bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are
don’t cares. To determine whether block B is locked out, the status of Block B Protection command is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be
reprogrammed. Please see the “Protection Register Addressing Table” on page 13 for the
address locations in the protection register. To read the protection register, the Product ID Entry
command is given followed by a normal read operation from an address within the protection
register. After determining whether block B is protected or not or reading the protection register,
the Product ID Exit command must be given prior to performing any other operation.
3.12
Common Flash Interface (CFI)
Common Flash Interface (CFI) is a published, standardized data structure that may be read from
a Flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is
used to allow the system to learn how to interface to the Flash device most optimally. The two
primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h
to address 55h. The CFI Query command can be written when the device is ready to read data
or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the
system can read CFI data at the addresses given in the “Common Flash Interface Definition
Table” on page 25. To exit the CFI Query mode, the product ID exit command must be given.
3.13
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV6416(T) in the following
ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC
power-on delay: once VCC has reached the VCC sense level, the device will automatically timeout 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high
or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP.
3.14
Input Levels
While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.
The I/O lines can be driven from 0 to VCCQ + 0.6V.
3.15
Output Levels
For the AT49BV6416(T), output high levels are equal to VCCQ - 0.1V (not VCC). For 2.7V to 3.6V
output levels, VCCQ must be tied to VCC.
8
AT49BV6416(T)
3451C–FLASH–2/05
Figure 3-2.
Data Polling Algorithm
(Configuration Register = 00)
Figure 3-3.
START
START
Read I/O7 - I/O0
Addr = VA
Read I/O7 - I/O0
Addr = VA
NO
YES
I/O7 = 1?
I/O7 = Data?
YES
NO
NO
I/O3, I/O5 = 1?
I/O3, I/O5 = 1?
YES
Notes:
9
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
NO
YES
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
Data Polling Algorithm
(Configuration Register = 01)
Note:
Program/Erase
Operation
Successful,
Device in
Read Mode
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
Figure 3-4.
Toggle Bit Algorithm
(Configuration Register = 00)
Figure 3-5.
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
Toggle?
NO
Toggle Bit =
Toggle?
NO
I/O3, I/O5 = 1?
Read I/O7 - I/O0
Twice
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
Note:
NO
YES
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
I/O3, I/O5 = 1?
YES
YES
Toggle Bit =
Toggle?
NO
YES
YES
NO
Toggle Bit Algorithm
(Configuration Register = 01)
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Device in
Read Mode
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
10
3451C–FLASH–2/05
AT49BV6416(T)
4. Status Bit Table
I/O7
Configuration
Register:
I/O6
I/O2
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
Plane A
Plane B
Plane C
Plane D
Plane A
Plane B
Plane C
Plane D
Plane A
Plane B
Plane C
Plane D
Programming
in Plane A
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
1
DATA
DATA
DATA
Programming
in Plane B
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
1
DATA
DATA
Programming
in Plane C
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
1
DATA
Programming
in Plane D
DATA
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
1
Erasing in
Plane A
0/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
Erasing in
Plane B
DATA
0/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
Erasing in
Plane C
DATA
DATA
0/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
Erasing in
Plane D
DATA
DATA
DATA
0/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
Erase
Suspended &
Read Erasing
Sector
1
1
1
1
1
1
1
1
TOGGLE
TOGGLE
TOGGLE
TOGGLE
Erase
Suspended &
Read Nonerasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Erase
Suspended &
Program Nonerasing Sector
in Plane A
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
Erase
Suspended &
Program Nonerasing Sector
in Plane B
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
Erase
Suspended &
Program Nonerasing Sector
in Plane C
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
Erase
Suspended &
Program Nonerasing Sector
in Plane D
DATA
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
Erase
Suspended &
Program
Suspended &
Read from
Nonsuspended
Sectors
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Read Address
In
While
11
3451C–FLASH–2/05
5. Command Definition Table
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
555
AA
Command Sequence
Plane Erase
6
Sector Erase
6
555
555
AA
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AAA(2)
55
555
80
555
AA
AAA
55
555
10
AAA
AAA
55
55
555
555
80
80
555
555
AA
AA
AAA
55
AAA
55
PA
(6)
20
(4)
30
SA
Word Program
4
555
AA
AAA
55
555
A0
Addr
DIN
Dual-Word Program(8)
5
555
AA
AAA
55
555
A1
Addr0
DIN0
Addr1
DIN1
Enter Single-pulse Program
Mode
6
555
AA
AAA
55
555
80
555
AA
AAA
55
555
A0
Single-pulse Word Program
Mode
1
Addr
DIN
Sector Softlock
6
555
AA
AAA
55
555
80
555
AA
AAA
55
SA(4)
40
Sector Unlock
2
555
AA
SA(4)
70
Sector Hardlock
6
555
AA
AAA
55
555
80
555
AA
AAA
55
SA(4)(5)
60
Erase/Program Suspend
1
xxx
B0
(6)
30
Erase/Program Resume
1
PA
Product ID Entry(7)
3
555
AA
AAA
55
PA+00555
90
(3)
3
555
AA
AAA
55
555
F0
(3)
Product ID Exit
1
xxx
FX
Program Protection
Register – Block B
4
555
AA
AAA
55
555
C0
xxxx(12)8x(11)
DIN
Lock Protection
Register – Block B
4
555
AA
AAA
55
555
C0
xxxx80(12)
X0
Status of Block B
Protection
4
555
AA
AAA
55
555
90
xxxx80(13)
DOUT(9)
Set Configuration Register
4
555
AA
AAA
55
555
E0
xxx
00/01(10)
CFI Query
1
X55
98
Product ID Exit
Notes:
12
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in
each bus cycle is as follows: A11 - A0 (Hex), A11 - A21 (Don’t Care).
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 17
for details).
5. Once a sector is in the Hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled.
6. PA is the plane address (A21 - A20).
7. During the fourth bus cycle, the manufacturer code is read from address PA+00000H, the device code is read from address
PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H. PA (A21 - A20) must specify the same plane address as specified in the third bus cycle.
8. The fast programming option enables the user to program two words in parallel only when VPP = 10V. The addresses, Addr0
and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used for manufacturing
purpose only.
9. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
10. The default state (after power-up) of the configuration register is “00”.
11. Any address within the user programmable register region. Please see “Protection Register Addressing Table” on page 13.
12. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 3F80H.
13. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 0F80H.
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
6. Absolute Maximum Ratings*
*NOTICE:
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages Except VPP
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
VPP Input Voltage
with Respect to Ground ......................................... 0V to 10.0V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
All Output Voltages
with Respect to Ground ...........................-0.6V to VCCQ + 0.6V
7. Protection Register Addressing Table
Word
Use
Block
A7
A6
A5
A4
A3
A2
A1
A0
0
Factory
A
1
0
0
0
0
0
0
1
1
Factory
A
1
0
0
0
0
0
1
0
2
Factory
A
1
0
0
0
0
0
1
1
3
Factory
A
1
0
0
0
0
1
0
0
4
User
B
1
0
0
0
0
1
0
1
5
User
B
1
0
0
0
0
1
1
0
6
User
B
1
0
0
0
0
1
1
1
7
User
B
1
0
0
0
1
0
0
0
13
3451C–FLASH–2/05
AT49BV6416(T)
8. Memory Organization –
AT49BV6416
8. Memory Organization –
AT49BV6416 (Continued)
x16
6416
Plane
Sector
x16
Size
(Words)
Address Range
(A21 - A0)
6416
Plane
Sector
Size
(Words)
Address Range
(A21 - A0)
A
SA0
4K
00000 - 00FFF
A
SA33
32K
D0000 - D7FFF
A
SA1
4K
01000 - 01FFF
A
SA34
32K
D8000 - DFFFF
A
SA2
4K
02000 - 02FFF
A
SA35
32K
E0000 - E7FFF
A
SA3
4K
03000 - 03FFF
A
SA36
32K
E8000 - EFFFF
A
SA4
4K
04000 - 04FFF
A
SA37
32K
F0000 - F7FFF
A
SA5
4K
05000 - 05FFF
A
SA38
32K
F8000 - FFFFF
A
SA6
4K
06000 - 06FFF
B
SA39
32K
100000 - 107FFF
A
SA7
4K
07000 - 07FFF
B
SA40
32K
108000 - 10FFFF
A
SA8
32K
08000 - 0FFFF
B
SA41
32K
110000 - 117FFF
A
SA9
32K
10000 - 17FFF
B
SA42
32K
118000 - 11FFFF
A
SA10
32K
18000 - 1FFFF
B
SA43
32K
120000 - 127FFF
A
SA11
32K
20000 - 27FFF
B
SA44
32K
128000 - 12FFFF
A
SA12
32K
28000 - 2FFFF
B
SA45
32K
130000 - 137FFF
A
SA13
32K
30000 - 37FFF
B
SA46
32K
138000 - 13FFFF
A
SA14
32K
38000 - 3FFFF
B
SA47
32K
140000 - 147FFF
A
SA15
32K
40000 - 47FFF
B
SA48
32K
148000 - 14FFFF
A
SA16
32K
48000 - 4FFFF
B
SA49
32K
150000 - 157FFF
A
SA17
32K
50000 - 57FFF
B
SA50
32K
158000 - 15FFFF
A
SA18
32K
58000 - 5FFFF
B
SA51
32K
160000 - 167FFF
A
SA19
32K
60000 - 67FFF
B
SA52
32K
168000 - 16FFFF
A
SA20
32K
68000 - 6FFFF
B
SA53
32K
170000 - 177FFF
A
SA21
32K
70000 - 77FFF
B
SA54
32K
178000 - 17FFFF
A
SA22
32K
78000 - 7FFFF
B
SA55
32K
180000 - 187FFF
A
SA23
32K
80000 - 87FFF
B
SA56
32K
188000 - 18FFFF
A
SA24
32K
88000 - 8FFFF
B
SA57
32K
190000 - 197FFF
A
SA25
32K
90000 - 97FFF
B
SA58
32K
198000 - 19FFFF
A
SA26
32K
98000 - 9FFFF
B
SA59
32K
1A0000 - 1A7FFF
A
SA27
32K
A0000 - A7FFF
B
SA60
32K
1A8000 - 1AFFFF
A
SA28
32K
A8000 - AFFFF
B
SA61
32K
1B0000 - 1B7FFF
A
SA29
32K
B0000 - B7FFF
B
SA62
32K
1B8000 - 1BFFFF
A
SA30
32K
B8000 - BFFFF
B
SA63
32K
1C0000 - 1C7FFF
A
SA31
32K
C0000 - C7FFF
B
SA64
32K
1C8000 - 1CFFFF
A
SA32
32K
C8000 - CFFFF
B
SA65
32K
1D0000 - 1D7FFF
14
3451C–FLASH–2/05
8. Memory Organization –
AT49BV6416 (Continued)
8. Memory Organization –
AT49BV6416 (Continued)
x16
6416
Plane
15
Sector
x16
Size
(Words)
Address Range
(A21 - A0)
6416
Plane
Sector
Size
(Words)
Address Range
(A21 - A0)
B
SA66
32K
1D8000 - 1DFFFF
C
SA100
32K
2E8000 - 2EFFFF
B
SA67
32K
1E0000 - 1E7FFF
C
SA101
32K
2F0000 - 2F7FFF
B
SA68
32K
1E8000 - 1EFFFF
C
SA102
32K
2F8000 - 2FFFFF
B
SA69
32K
1F0000 - 1F7FFF
D
SA103
32K
300000 - 307FFF
B
SA70
32K
1F8000 - 1FFFFF
D
SA104
32K
308000 - 30FFFF
C
SA71
32K
200000 - 207FFF
D
SA105
32K
310000 - 317FFF
C
SA72
32K
208000 - 20FFFF
D
SA106
32K
318000 - 31FFFF
C
SA73
32K
210000 - 217FFF
D
SA107
32K
320000 - 327FFF
C
SA74
32K
218000 - 21FFFF
D
SA108
32K
328000 - 32FFFF
C
SA75
32K
220000 - 227FFF
D
SA109
32K
330000 - 337FFF
C
SA76
32K
228000 - 22FFFF
D
SA110
32K
338000 - 33FFFF
C
SA77
32K
230000 - 237FFF
D
SA111
32K
340000 - 347FFF
C
SA78
32K
238000 - 23FFFF
D
SA112
32K
348000 - 34FFFF
C
SA79
32K
240000 - 247FFF
D
SA113
32K
350000 - 357FFF
C
SA80
32K
248000 - 24FFFF
D
SA114
32K
358000 - 35FFFF
C
SA81
32K
250000 - 257FFF
D
SA115
32K
360000 - 367FFF
C
SA82
32K
258000 - 25FFFF
D
SA116
32K
368000 - 36FFFF
C
SA83
32K
260000 - 267FFF
D
SA117
32K
370000 - 377FFF
C
SA84
32K
268000 - 26FFFF
D
SA118
32K
378000 - 37FFFF
C
SA85
32K
270000 - 277FFF
D
SA119
32K
380000 - 387FFF
C
SA86
32K
278000 - 27FFFF
D
SA120
32K
388000 - 38FFFF
C
SA87
32K
280000 - 287FFF
D
SA121
32K
390000 - 397FFF
C
SA88
32K
288000 - 28FFFF
D
SA122
32K
398000 - 39FFFF
C
SA89
32K
290000 - 297FFF
D
SA123
32K
3A0000 - 3A7FFF
C
SA90
32K
298000 - 29FFFF
D
SA124
32K
3A8000 - 3AFFFF
C
SA91
32K
2A0000 - 2A7FFF
D
SA125
32K
3B0000 - 3B7FFF
C
SA92
32K
2A8000 - 2AFFFF
D
SA126
32K
3B8000 - 3BFFFF
C
SA93
32K
2B0000 - 2B7FFF
D
SA127
32K
3C0000 - 3C7FFF
C
SA94
32K
2B8000 - 2BFFFF
D
SA128
32K
3C8000 - 3CFFFF
C
SA95
32K
2C0000 - 2C7FFF
D
SA129
32K
3D0000 - 3D7FFF
C
SA96
32K
2C8000 - 2CFFFF
D
SA130
32K
3D8000 - 3DFFFF
C
SA97
32K
2D0000 - 2D7FFF
D
SA131
32K
3E0000 - 3E7FFF
C
SA98
32K
2D8000 - 2DFFFF
D
SA132
32K
3E8000 - 3EFFFF
C
SA99
32K
2E0000 - 2E7FFF
D
SA133
32K
3F0000 - 3F7FFF
D
SA134
32K
3F8000 - 3FFFFF
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
9. Memory Organization –
AT49BV6416T
9. Memory Organization –
AT49BV6416T (Continued)
x16
6416T
Plane
Sector
x16
Size
(Words)
Address Range
(A21 - A0)
6416T
Plane
Sector
Size
(Words)
Address Range
(A21 - A0)
D
SA0
32K
00000 - 07FFF
C
SA36
32K
120000 - 127FFF
D
SA1
32K
08000 - 0FFFF
C
SA37
32K
128000 - 12FFFF
D
SA2
32K
10000 - 17FFF
C
SA38
32K
130000 - 137FFF
D
SA3
32K
18000 - 1FFFF
C
SA39
32K
138000 - 13FFFF
D
SA4
32K
20000 - 27FFF
C
SA40
32K
140000 - 147FFF
D
SA5
32K
28000 - 2FFFF
C
SA41
32K
148000 - 14FFFF
D
SA6
32K
30000 - 37FFF
C
SA42
32K
150000 - 157FFF
D
SA7
32K
38000 - 3FFFF
C
SA43
32K
158000 - 15FFFF
D
SA8
32K
40000 - 47FFF
C
SA44
32K
160000 - 167FFF
D
SA9
32K
48000 - 4FFFF
C
SA45
32K
168000 - 16FFFF
D
SA10
32K
50000 - 57FFF
C
SA46
32K
170000 - 177FFF
D
SA11
32K
58000 - 5FFFF
C
SA47
32K
178000 - 17FFFF
D
SA12
32K
60000 - 67FFF
C
SA48
32K
180000 - 187FFF
D
SA13
32K
68000 - 6FFFF
C
SA49
32K
188000 - 18FFFF
D
SA14
32K
70000 - 77FFF
C
SA50
32K
190000 - 197FFF
D
SA15
32K
78000 - 7FFFF
C
SA51
32K
198000 - 19FFFF
D
SA16
32K
80000 - 87FFF
C
SA52
32K
1A0000 - 1A7FFF
D
SA17
32K
88000 - 8FFFF
C
SA53
32K
1A8000 - 1AFFFF
D
SA18
32K
90000 - 97FFF
C
SA54
32K
1B0000 - 1B7FFF
D
SA19
32K
98000 - 9FFFF
C
SA55
32K
1B8000 - 1BFFFF
D
SA20
32K
A0000 - A7FFF
C
SA56
32K
1C0000 - 1C7FFF
D
SA21
32K
A8000 - AFFFF
C
SA57
32K
1C8000 - 1CFFFF
D
SA22
32K
B0000 - B7FFF
C
SA58
32K
1D0000 - 1D7FFF
D
SA23
32K
B8000 - BFFFF
C
SA59
32K
1D8000 - 1DFFFF
D
SA24
32K
C0000 - C7FFF
C
SA60
32K
1E0000 - 1E7FFF
D
SA25
32K
C8000 - CFFFF
C
SA61
32K
1E8000 - 1EFFFF
D
SA26
32K
D0000 - D7FFF
C
SA62
32K
1F0000 - 1F7FFF
D
SA27
32K
D8000 - DFFFF
C
SA63
32K
1F8000 - 1FFFFF
D
SA28
32K
E0000 - E7FFF
B
SA64
32K
200000 - 207FFF
D
SA29
32K
E8000 - EFFFF
B
SA65
32K
208000 - 20FFFF
D
SA30
32K
F0000 - F7FFF
B
SA66
32K
210000 - 217FFF
D
SA31
32K
F8000 - FFFFF
B
SA67
32K
218000 - 21FFFF
C
SA32
32K
100000 - 107FFF
B
SA68
32K
220000 - 227FFF
C
SA33
32K
108000 - 10FFFF
B
SA69
32K
228000 - 22FFFF
C
SA34
32K
110000 - 117FFF
B
SA70
32K
230000 - 237FFF
C
SA35
32K
118000 - 11FFFF
B
SA71
32K
238000 - 23FFFF
16
3451C–FLASH–2/05
9. Memory Organization –
AT49BV6416T (Continued)
9. Memory Organization –
AT49BV6416T (Continued)
x16
6416T
Plane
17
Sector
x16
Size
(Words)
Address Range
(A21 - A0)
6416T
Plane
Sector
Size
(Words)
Address Range
(A21 - A0)
B
SA72
32K
240000 - 247FFF
A
SA104
32K
340000 - 347FFF
B
SA73
32K
248000 - 24FFFF
A
SA105
32K
348000 - 34FFFF
B
SA74
32K
250000 - 257FFF
A
SA106
32K
350000 - 357FFF
B
SA75
32K
258000 - 25FFFF
A
SA107
32K
358000 - 35FFFF
B
SA76
32K
260000 - 267FFF
A
SA108
32K
360000 - 367FFF
B
SA77
32K
268000 - 26FFFF
A
SA109
32K
368000 - 36FFFF
B
SA78
32K
270000 - 277FFF
A
SA110
32K
370000 - 377FFF
B
SA79
32K
278000 - 27FFFF
A
SA111
32K
378000 - 37FFFF
B
SA80
32K
280000 - 287FFF
A
SA112
32K
380000 - 387FFF
B
SA81
32K
288000 - 28FFFF
A
SA113
32K
388000 - 38FFFF
B
SA82
32K
290000 - 297FFF
A
SA114
32K
390000 - 397FFF
B
SA83
32K
298000 -29FFFF
A
SA115
32K
398000 - 39FFFF
B
SA84
32K
2A0000 - 2A7FFF
A
SA116
32K
3A0000 - 3A7FFF
B
SA85
32K
2A8000 - 2AFFFF
A
SA117
32K
3A8000 - 3AFFFF
B
SA86
32K
2B0000 - 2B7FFF
A
SA118
32K
3B0000 - 3B7FFF
B
SA87
32K
2B8000 - 2BFFFF
A
SA119
32K
3B8000 - 3BFFFF
B
SA88
32K
2C0000 - 2C7FFF
A
SA120
32K
3C0000 - 3C7FFF
B
SA89
32K
2C8000 - 2CFFFF
A
SA121
32K
3C8000 - 3CFFFF
B
SA90
32K
2D0000 - 2D7FFF
A
SA122
32K
3D0000 - 3D7FFF
B
SA91
32K
2D8000 - 2DFFFF
A
SA123
32K
3D8000 - 3DFFFF
B
SA92
32K
2E0000 - 2E7FFF
A
SA124
32K
3E0000 - 3E7FFF
B
SA93
32K
2E8000 - 2EFFFF
A
SA125
32K
3E8000 - 3EFFFF
B
SA94
32K
2F0000 - 2F7FFF
A
SA126
32K
3F0000 - 3F7FFF
B
SA95
32K
2F8000 - 2FFFFF
A
SA127
4K
3F8000 - 3F8FFF
A
SA96
32K
300000 - 307FFF
A
SA128
4K
3F9000 - 3F9FFF
A
SA97
32K
308000 - 30FFFF
A
SA129
4K
3FA000 - 3FAFFF
A
SA98
32K
310000 - 317FFF
A
SA130
4K
3FB000 - 3FBFFF
A
SA99
32K
318000 - 31FFFF
A
SA131
4K
3FC000 - 3FCFFF
A
SA100
32K
320000 - 327FFF
A
SA132
4K
3FD000 - 3FDFFF
A
SA101
32K
328000 - 32FFFF
A
SA133
4K
3FE000 - 3FEFFF
A
SA102
32K
330000 - 337FFF
A
SA134
4K
3FF000 - 3FFFFF
A
SA103
32K
338000 - 33FFFF
AT49BV6416(T)
3451C–FLASH–2/05
10. DC and AC Operating Range
AT49BV6416(T) - 70
Operating Temperature (Case)
Industrial
-40°C - 85°C
VCC Power Supply
2.7V - 3.6V
11. Operating Modes
Mode
CE
Read
Burst Read
(3)
Program/Erase
Standby/Program Inhibit
OE
WE
RESET
VPP(4)
Ai
I/O
VIL
VIL
VIH
VIH
X
Ai
DOUT
VIL
VIL
VIH
VIH
X
Ai
DOUT
VIL
VIH
VIHPP(5)
Ai
DIN
X
High Z
VIL
VIH
(1)
VIH
X
X
VIH
X
X
X
VIH
VIH
X
X
VIL
X
VIH
X
X
X
X
X
VILPP(6)
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
Program Inhibit
Product Identification
Software
Notes:
18
1.
2.
3.
4.
5.
6.
VIH
High Z
X
High Z
A0 = VIL, A1 - A21 = VIL
Manufacturer Code(3)
A0 = VIH, A1 - A21 = VIL
Device Code(3)
X can be VIL or VIH.
Refer to AC programming waveforms.
Manufacturer Code: 001FH; Device Code: 00D6H - AT49BV6416; 00D2H - AT49BV6416T.
The VPP pin can be tied to VCC. For faster program operations, VPP can be set to 9.5V ± 0.5V.
VIHPP (min) = 1.65V.
VILPP (max) = 0.7V.
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
12. DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
1
µA
Output Leakage Current
VI/O = 0V to VCC
1
µA
ISB1
VCC Standby Current CMOS
CE = VCCQ - 0.3V to VCC
35
µA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
30
mA
ICCRE
VCC Read While Erase Current
f = 5 MHz; IOUT = 0 mA
60
mA
ICCRW
VCC Read While Write Current
f = 5 MHz; IOUT = 0 mA
60
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -100 µA; VCCQ = 2.2V - 3.6V
Note:
Min
VCCQ - 0.6
V
0.45
V
VCCQ - 0.1
V
1. In the erase mode, ICC is 35 mA.
13. Input Test Waveforms and Measurement Level
2.0V
AC
DRIVING
LEVELS
1.5V
AC
MEASUREMENT
LEVEL
0.6V
tR, tF < 5 ns
14. Output Test Load
VCCQ
1.8K
OUTPUT
PIN
1.3K
30 pF
15. Pin Capacitance
f = 1 MHz, T = 25°C(1)
CIN
COUT
Note:
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
19
3451C–FLASH–2/05
16. AC Asynchronous Read Timing Characteristics
Symbol
Parameter
Min
Max
Units
tRC
Read Cycle Time
70
tACC
Access, Address to Data Valid
70
ns
tCE
Access, CE to Data Valid
70
ns
tOE
OE to Data Valid
20
ns
tDF
CE, OE High to Data Float
25
ns
tOH
Output Hold from OE, CE or Address, whichever Occurs First
tRO
RESET to Output Delay
ns
0
ns
150
ns
17. Asynchronous Read Cycle Waveform(1)(2)(3)
tRC
A0 - A21
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
I/O0 - I/O15
Notes:
20
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
18. AC Asynchronous Read Timing Characteristics
Symbol
Parameter
tACC
Min
Max
Units
Access, Address to Data Valid
70
ns
tCE
Access, CE to Data Valid
70
ns
tOE
OE to Data Valid
20
ns
tDF
CE, OE High to Data Float
25
ns
tRO
RESET to Output Delay
150
ns
tPAA
Page Address Access Time
20
ns
19. Page Read Cycle Waveform
tCE
CE
tDF
I/O0-I/O15
DATA VALID
tACC
tDF
A2 -A21
tPAA
tACC
A0 -A1
tOE
OE
tRO
RESET
21
3451C–FLASH–2/05
20. AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS
Address Setup Time to WE and CE Low
0
ns
tAH
Address Hold Time
20
ns
tDS
Data Setup Time
20
ns
tDH
Data Hold Time
0
ns
tWP
CE or WE Low Pulse Width
35
ns
tWPH
CE or WE High Pulse Width
25
ns
21. AC Word Load Waveforms
21.1
WE Controlled
CE
I/O0-I/O15
DATA VALID
A0 -A21
tDS
tDH
tAH
tAS
tWP
WE
21.2
CE Controlled
WE
I/O0-I/O15
DATA VALID
A0 -A21
tDS
tAS
CE
22
tDH
tAH
tWP
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
22. Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
tBP
Word Programming Time
15
µs
tSEC1
Sector Erase Cycle Time (4K word sectors)
200
ms
tSEC2
Sector Erase Cycle Time (32K word sectors)
700
ms
tES
Erase Suspend Time
15
µs
tPS
Program Suspend Time
10
µs
tERES
Delay between Erase Resume and Erase Suspend
500
Units
µs
23. Program Cycle Waveforms
OE(1)
CE
XXAA
I/O0 -I/O15
XX55
555
A0 -A21
AAA
INPUT
DATA
XXA0
555
ADDR
WE
24. Sector, Plane or Chip Erase Cycle Waveforms
OE(1)
CE
XXAA
I/O0 -I/O15
A0 -A21
555
XX55
AAA
555
555
Note3
XX55
XXAA
XX80
AAA
Note2
WE
Notes:
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For plane or sector erase, the address depends on what plane or sector is to be
erased. (See note 4 and 6 under “Command Definition Table” on page 12.)
3. For chip erase, the data should be XX10H, for plane erase, the data should be XX20H, and for sector erase, the data should
be XX30H
4. The waveforms shown above use the WE controlled AC Word Load Waveforms.
23
3451C–FLASH–2/05
25. Data Polling Characteristics
Symbol
Parameter
Min
tDH
Data Hold Time
tOEH
OE Hold Time
Max
OE to Output Delay
tWR
Write Recovery Time
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec on page 20.
26. Data Polling Waveforms
WE
CE
OE
I/O7
A0-A21
27. Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Typ
Max
Units
10
ns
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
50
ns
tWR
Write Recovery Time
0
ns
Notes:
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec on page 20.
28. Toggle Bit Waveforms(1)(2)(3)
Notes:
24
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
29. Common Flash Interface Definition Table
Address
AT49BV6416(T)
Comments
10h
0051h
“Q”
11h
0052h
“R”
12h
0059h
“Y”
13h
0002h
14h
0000h
15h
0041h
16h
0000h
17h
0000h
18h
0000h
19h
0000h
1Ah
0000h
1Bh
0027h
VCC min write/erase
1Ch
0036h
VCC max write/erase
1Dh
0009h
VPP min voltage
1Eh
000Ah
VPP max voltage
1Fh
0004h
Typ word write – 16 µs
20h
0000h
21h
0009h
Typ block erase – 500 ms
22h
0010h
Typ chip erase – 64,300 ms
23h
0004h
Max word write/typ time
24h
0000h
n/a
25h
0003h
Max block erase/typ block erase
26h
0003h
Max chip erase/ typ chip erase
27h
0017h
Device size
28h
0001h
x16 device
29h
0000h
x16 device
2Ah
0000h
Multiple byte write not supported
2Bh
0000h
Multiple byte write not supported
2Ch
0002h
2 regions, x = 2
2Dh
007Eh
64K bytes, Y = 126
2Eh
0000h
64K bytes, Y = 126
2Fh
0000h
64K bytes, Z = 256
30h
0001h
64K bytes, Z = 256
31h
0007h
8K bytes, Y = 7
32h
0000h
8K bytes, Y = 7
33h
0020h
8K bytes, Z = 32
34h
0000h
8K bytes, Z = 32
25
3451C–FLASH–2/05
29. Common Flash Interface Definition Table (Continued)
Address
AT49BV6416(T)
Comments
VENDOR SPECIFIC EXTENDED QUERY
26
41h
0050h
“P”
42h
0052h
“R”
43h
0049h
“I”
44h
0031h
Major version number, ASCII
45h
0030h
Minor version number, ASCII
46h
00AFh
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported, 0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
47h
0000h AT49BV6416T or
0001h AT49BV6416
Bit 0 – top (“0”) or bottom (“1”) boot block device
Undefined bits are “0”
48h
0000h
Bit 0 – 4 word linear burst with wrap around, 0 – no, 1 – yes
Bit 1 – 8 word linear burst with wrap around, 0 – no, 1 – yes
Bit 2 – continuos burst, 0 – no, 1 – yes
Undefined bits are “0”
49h
0001h
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
4Ah
0080h
Location of protection register lock byte, the section's first byte
4Bh
0003h
# of bytes in the factory prog section of prot register – 2*n
4Ch
0003h
# of bytes in the user prog section of prot register – 2*n
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
30. Ordering Information
30.1
Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
30
0.035
AT49BV6416-70TI
48T
Industrial
(-40° to 85°C)
70
30
0.035
AT49BV6416T-70TI
48T
Industrial
(-40° to 85°C)
30.2
Green Package Option (Pb/Halide-free)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
30
0.035
AT49BV6416-70TU
48T
Industrial
(-40° to 85°C)
Package Type
48T
48-lead, Plastic Thin Small Outline Package (TSOP)
27
3451C–FLASH–2/05
31. Packaging Information
31.1
48T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
NOTE
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
11.90
12.00
12.10
Note 2
L
0.50
0.60
0.70
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
0.50 BASIC
10/18/01
R
28
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
48T
B
AT49BV6416(T)
3451C–FLASH–2/05
AT49BV6416(T)
32. Revision History
Revision No.
History
Revision A – March 2004
•
Initial Release
Revision B – November 2004
•
•
•
•
•
•
Removed “Preliminary” from the datasheet.
Modified Plane Erase text on page 3.
Modified note 7 and added notes 11, 12, and 13 on page 11.
Removed note 1 on page 12.
Changed SA102 from plane D to plane C on page 14.
Changed the ISB1 spec to 35 µA.
Revision C – January 2005
•
•
Converted datasheet to New Template.
Changed the VPP value to 9.5 ± 0.5V in the text, table
on page 12, and CFI table. VPP text also changed to show
that a high voltage on VPP improves only the programming time.
Added Green Package (Pb/Halide-free) Option in the
Ordering Information section.
•
29
3451C–FLASH–2/05
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Atmel Operations
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not
intended, authorized, or warranted for use as components in applications intended to support or sustain life.
© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, and others, are registered trademarks, and
Everywhere You AreSM and others are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be
trademarks of others.
Printed on recycled paper.
3451C–FLASH–2/05
xM