Features • Clock Controller • • • • • • • • • • • • – 80C51 core with 6 clocks per instruction – 8 MHz On-Chip Oscillator – PLL for generating clock to supply CPU core, USB and Smart Card Interfaces – Programmable CPU clock from 500 KHz / X1 to 48 MHz / X1 Reset Controller – Power On Reset (POR) feature avoiding an external reset capacitor – Power Fail Detector (PFD) – Watch-Dog Timer Power Management – Two power saving modes : Idle and Power Down – Four Power Down Wake-up Sources : Smart Card Detection, Keyboard Interrupt, USB Resume, External Interrupt – Input Voltage Range : 3.0V - 5.5V – Core’s Power Consumption (Without Smart Card and USB) : •30 mA Maximum Operating Current @ 48 MHz / X1 •200 μA Maximum Power-down Current @ 5.5V Interrupt Controller – up to 9 interrupt sources – up to 4 Level Priority Memory Controller – Internal Program memory : •up to 32KB of Flash or CRAM or ROM for AT8xC5122 or ROM for AT83R5122 •up to 30KB of ROM for AT83C5123 – Internal Data Memory : 768 bytes including 256 bytes of data and 512 bytes of XRAM – Optional : internal data E2PROM 512 bytes Two 16-bit Timer/Counters USB 2.0 Full Speed Interface – 48 MHz DPLL – On-Chip 3.3V USB voltage regulator and transceivers – Software detach feature – 7 endpoints programmable with In or out directions and ISO, Bulk or Interrupt Transfers : •Endpoint 0: 32 Bytes Bidirectionnal FIFO for Control transfers •Endpoints 1,2,3: 8 bytes FIFO •Endpoints 4,5: 64 Bytes FIFO •Endpoint 6: 2*64 bytes FIFO with Pin-Pong feature ISO 7816 UART Interface Fully Compliant with EMV, GIE-CB and WHQL Standards – Programmable ISO clock from 1 MHz to 4.8 MHz – Card insertion/removal detection with automatic deactivation sequence – Programmable Baud Rate Generator from 372 to 11.625 clock pulses – Synchronous/Asynchronous Protocols T=0 and T=1 with Direct or Inverse Convention – Automatic character repetition on parity errors – 32 Bit Waiting Time Counter – 16 Bit Guard Time Counter – Internal Step Up/Down Converter with Programmable Voltage Output: •VCC = 4.0V to 5.5V, 1.8V-30 mA, 3V-60 mA and 5V-60 mA •VCC = 3.0V, 1.8V-30 mA, 3V-30 mA and 5V-30 mA – Current overload protection – 6 kV ESD (MIL/STD 833 Class 3) protection on whole Smart Card Interface Alternate Smart Card Interface with CLK, IO and RST UART Interface with Integrated Baud Rate Generator (BRG) Keyboard interface with up to 20x8 matrix management capability Master/Slave SPI Interface Four 8 bit Ports, one 6 bit port, one 3-bit port – Up to Seven LED outputs with 3 level programmable current source : 2, 4 and 10 mA – Two General Purpose I/O programmable as external interrupts – Up to 8 input lines programmable as interrupts – Up to 30 output lines C51 Microcontroller with USB and Smart Card Reader Interfaces AT83C5122 AT83R5122 AT85C5122 AT89C5122 AT89C5122DS AT83C5123 Rev. 4202F–SCR–07/2008 1 Reference Documents 2 The user must get the following additionnal documents which are not included but which complete this product datasheet • Product Errata Sheet • Bootloader Datasheet AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Product Description AT8xC5122/23 products are high-performance CMOS derivatives of the 80C51 8-bit microcontrollers designed for USB smart card reader applications. The AT8xC5122 is proposed in four versions : - ROM version referenced AT83R5122 is only factory programmable. - CRAM version without internal data E2PROM. The CRAM device implements a volatile program memory which is programmed by means of an embedded ROMed bootloader which transfers the code from a remote software programming tool called FLIP through UART or USB interfaces. - Flash version without internal data E2PROM. At power-up, the program located in the flash memory is transferred into the CRAM then executed. The AT83C5123 is a low pin count of the AT8xC5122 and is proposed in ROM version with or without internal data E2PROM. The ROM device is only factory programmable. The AT8xC5122DS is a secure version of the AT8xC5122 on which the external program memory access mode is disabled. Table 1. Product versions AT83C5122 Features AT83R5122 AT85C5122 AT89C5122 AT89C5122DS VQFP64 VQFP64 QFN64 QFN64 AT83C5123 VQFP64 PLCC68 QFN64 VQFP64 Die Form Die Form 32KB ROM 32KB CRAM 32KB E2PROM 32KB E2PROM 30KB ROM Internal Data E2PROM No No No No No Embedded bootloader No Yes Yes Yes No Packages Program memory VQFP32 QFN32 Die Form Features not available : - Keyboard Interface - Master/Slave SPI Interface VQFP32, - External Program Memory Access QFN32 packages Reduced features : - Only 12 I/O with up to 4 LED Outputs with Programmable Current Features PLCC68, VQFP64,QFN64 packages All features are available All features are available except External Program Memory Access 3 4202F–SCR–07/2008 RST 256 x 8 RAM 512 x 8 XRAM UART Interf ace PLL WATCH-DOG POR PFD RESET CVSS LI Alternate Card CVCC CIO1 Interrupt Controller CRST1 16-BIT TIMERS CCLK1 INT[0-1] 256 x 8 RAM DC/DC Conv erter CPRES CRST ISO 7816 Interface PLLF 8 MHz Oscillator T[0-1] XTAL2 80C518-BIT CORE XTAL1 RxD 3.3 V Regulator TxD VCC VSS AT8xC5122/AT83R5122 Block Diagram INTERNALADDRESSAND DATABUS CCLK CIO CC4 CC8 32K x 8 ROM (1) 32K x 8 CRAM (1) 32K x 8 E2PROM(1) SPI Interf ace ExternalMemory Controller USB Interf ace 3.3V Regulator 3-BIT PORT 8-BIT PORT 8-BIT PORT 6-BIT PORT 8-BIT PORT LED's DVCC AVCC AVSS D- VREF D+ RD WR A[8-15] ALE ParallelI/OPorts 8-BIT PORT AD[0-7] PSEN SS EA SCK MOSI MISO 512 x 8 E2PROM(1) KBD Interf ace KB[0-7] LED[0-6] P5[0-7] P4[0-5] P3[0-7] P2[0-7] P1[2,6-7] P0[0-7] Note 1 : the implementation of these f eatures depends on product v ersions Alternate Card CVSS CVCC LI CIO1 CCLK1 CRST1 Interrupt Controller DC/DC Conv erter CPRES CRST CCLK CIO INTERNALADDRESSAND DATABUS CC4 CC8 USB Interf ace 1-BIT PORT D+ ParallelI/OPorts 8-BIT PORT LED's 3.3V Regulator DVCC 512 x 8 E2PROM(1) AVSS 30K x 8 ROM 3-BIT PORT 16-BIT TIMERS ISO 7816 Interface UART Interf ace INT[0-1] 512 x 8 XRAM AVCC WATCH-DOG POR PFD RESET 256 x 8 RAM VREF RST PLL 256 x 8 RAM D- PLLF 8 MHz Oscillator T[0-1] XTAL2 80C518-BIT CORE XTAL1 RxD 3.3 V Regulator TxD VSS VCC AT83C5123 Block Diagram 4 LED[0-3] P5.0 P3[0-7] P1[2,6-7] Note 1 : the implementation of these f eatures depends on product v ersions AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Pinout High Pin Count Package Description P2.6/A14 P2.3/A11 P2.4/A12 P2.5/A13 AVSS P2.2/A10 AVCC PLLF P2.0/A8 P2.1/A9 D+ D- P1.7/CCLK1 VREF EA Figure 1. VQFP64 Package Pinout CIO AT8xC5122/AT83R5122 version 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P1.2/CPRES 1 2 CC8 P5.7/KB7 3 48 47 46 P3.1/TxD P1.6/SS P2.7/A15 4 5 45 P3.0/RxD P5.6/KB6 44 P3.5/T1/CRST1 CRST 6 P5.5/KB5 7 8 43 42 P3.2/INT0/LED0/CIO1 P4.0/MISO 41 P3.3/INT1 40 39 38 37 P4.1/MOSI P3.4/T0/LED1 36 35 34 P3.6/WR/LED2 P4.4/LED5 P5.4/KB4 CC4 P5.3/KB3 P5.2/KB2 CCLK P5.1/KB1 P5.0/KB0 PSEN VSS VQFP64 9 10 11 12 13 14 15 16 33 P4.2/SCK P4.3/LED4 RST P4.5/LED6 XTAL2 P0.1/AD1 P0.0/AD0 XTAL1 P0.3/AD3 P0.2/AD2 P0.4/AD4 P3.7/RD/LED3 P0.5/AD5 P0.6/AD6 ALE P0.7/AD7 VCC CVCC LI CVSS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 5 4202F–SCR–07/2008 9 8 7 6 DVCC P1.2/CPRES CC8 P5.7/KB7 P5.6/KB6 CRST P5.5/KB5 19 NC P2.5/A13 P2.6/A14 N/A AVSS P2.3/A11 P2.4/A12 PLLF P2.2/A10 AVCC 15 16 P5.3/KB3 P5.2/KB2 VSS P2.0/A8 P2.1/A9 11 12 13 14 17 P5.0/KB0 PSEN 5 4 3 2 1 68 67 66 65 64 63 62 61 10 P5.4/KB4 CC4 CCLK P5.1/KB1 D+ D- CIO EA P1.7/CCLK1 VREF Figure 2. PLCC68 Package Pinout (for engineering purpose only) 60 59 58 N/A P3.1/TxD 57 P2.7/A15 56 P3.0/RxD 55 P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P4.0/MISO 54 53 PLCC68 18 52 51 50 49 20 21 22 48 47 46 45 44 23 24 25 26 P1.6/SS P3.3/INT1 P4.1/MOSI P3.4/T0/LED1 P4.2/SCK P4.3/LED4 P3.6/WR/LED2 P4.4/LED5 RST P4.5/LED6 6 XTAT1 XTAL2 P0.1/AD1 P0.0/AD0 P0.4/AD4 P3.7/RD/LED3 P0.3/AD3 P0.2/AD2 P0.5/AD5 P0.6/AD6 P0.7/AD7 ALE VCC NC CVCC LI CVSS 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC : not connected N/A : not available AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 P2.6/A14 P2.3/A11 P2.4/A12 P2.5/A13 AVSS P2.2/A10 AVCC PLLF P2.0/A8 P2.1/A9 D+ D- P1.7/CCLK1 VREF EA CIO Figure 3. QFN64 Package Pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P1.2/CPRES 1 2 CC8 P5.7/KB7 3 48 47 46 P3.1/TxD P1.6/SS P2.7/A15 4 5 45 P3.0/RxD P5.6/KB6 44 P3.5/T1/CRST1 CRST 6 P5.5/KB5 7 43 42 P5.4/KB4 8 P3.2/INT0/LED0/CIO1 P4.0/MISO P3.3/INT1 CC4 P5.3/KB3 9 10 P5.2/KB2 CCLK 11 P5.1/KB1 P5.0/KB0 PSEN VSS 41 QFN64 12 13 14 15 16 40 39 38 37 P4.1/MOSI P3.4/T0/LED1 36 35 34 P3.6/WR/LED2 P4.4/LED5 33 P4.2/SCK P4.3/LED4 RST P4.5/LED6 XTAL2 P0.1/AD1 P0.0/AD0 XTAL1 P0.3/AD3 P0.2/AD2 P0.4/AD4 P3.7/RD/LED3 P0.5/AD5 P0.6/AD6 ALE P0.7/AD7 VCC CVCC LI CVSS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 7 4202F–SCR–07/2008 P2.6/A14 P2.3/A11 P2.4/A12 P2.5/A13 AVSS P2.2/A10 AVCC PLLF P2.0/A8 P2.1/A9 D+ D- P1.7/CCLK1 VREF CIO Figure 4. VQFP64 Package Pinout VCC AT89C5122DS version 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P1.2/CPRES 1 2 CC8 P5.7/KB7 3 48 47 46 P3.1/TxD P1.6/SS P2.7/A15 4 5 45 P3.0/RxD P5.6/KB6 44 P3.5/T1/CRST1 CRST 6 P5.5/KB5 7 43 42 P5.4/KB4 8 P3.2/INT0/LED0/CIO1 P4.0/MISO P3.3/INT1 CC4 P5.3/KB3 9 10 P5.2/KB2 CCLK 11 P5.1/KB1 P5.0/KB0 PSEN VSS 41 VQFP64 12 13 14 15 16 40 39 38 37 P4.1/MOSI P3.4/T0/LED1 36 35 34 P3.6/WR/LED2 P4.4/LED5 33 P4.2/SCK P4.3/LED4 RST P4.5/LED6 8 XTAL2 P0.1/AD1 P0.0/AD0 XTAL1 P0.3/AD3 P0.2/AD2 P0.4/AD4 P3.7/RD/LED3 P0.5/AD5 P0.6/AD6 ALE P0.7/AD7 VCC CVCC LI CVSS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 P2.6/A14 P2.3/A11 P2.4/A12 P2.5/A13 AVSS P2.2/A10 AVCC PLLF P2.0/A8 P2.1/A9 D+ D- P1.7/CCLK1 VREF CIO VCC Figure 5. QFN64 Package Pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC P1.2/CPRES 1 2 CC8 P5.7/KB7 3 48 47 46 P3.1/TxD P1.6/SS P2.7/A15 4 5 45 P3.0/RxD P5.6/KB6 44 P3.5/T1/CRST1 CRST 6 P5.5/KB5 7 43 42 P5.4/KB4 8 P3.2/INT0/LED0/CIO1 P4.0/MISO P3.3/INT1 CC4 P5.3/KB3 9 10 P5.2/KB2 CCLK 11 P5.1/KB1 P5.0/KB0 PSEN VSS 41 QFN64 12 13 14 15 16 40 39 38 37 P4.1/MOSI P3.4/T0/LED1 36 35 34 P3.6/WR/LED2 P4.4/LED5 33 P4.2/SCK P4.3/LED4 RST P4.5/LED6 XTAL2 P0.1/AD1 P0.0/AD0 XTAL1 P0.3/AD3 P0.2/AD2 P0.4/AD4 P3.7/RD/LED3 P0.5/AD5 P0.6/AD6 ALE P0.7/AD7 VCC CVCC LI CVSS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 4202F–SCR–07/2008 Low Pin Count Package Description AVSS DAVCC PLLF D+ VREF Figure 6. VQFP32 Package Pinout CIO P1.7/CCLK1 AT83C5123 version 32 31 30 29 28 27 26 25 DVCC P1.2/CPRES CC8 CRST CC4 CCLK P5.0 VSS 1 2 3 4 5 6 7 8 VQFP32 24 23 22 21 20 19 18 17 P3.1/TxD P1.6 P3.0/RxD P3.5/T1/CRST1 24 23 22 21 20 19 18 17 P3.1/TxD P1.6 P3.2/INT0/LED0/CIO1 P3.3/INT1 P3.4/T0/LED1 P3.6/LED2 P3.7/LED3 XTAL1 XTAL2 RST VCC LI CVSS CVCC 9 10 11 12 13 14 15 16 AVSS DAVCC PLLF D+ VREF CIO P1.7/CCLK1 Figure 7. QFN32 Package Pinout 32 31 30 29 28 27 26 25 DVCC P1.2/CPRES CC8 CRST CC4 CCLK P5.0 VSS 1 2 3 4 5 6 7 8 QFN32 P3.0/RxD P3.5/T1/CRST1 P3.2/INT0/LED0/CIO1 P3.3/INT1 P3.4/T0/LED1 P3.6/LED2 10 P3.7/LED3 XTAL1 XTAL2 RST VCC LI CVSS CVCC 9 10 11 12 13 14 15 16 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Pin Description QFN32 I/O Reset Level Alt Reset Config 30 - VCC 2KV I/O Float AD0 29 - VCC 2KV I/O Float - 28 - VCC 2KV I/O 38 - 27 - VCC 2KV - 36 - 25 - VCC 24 - 35 - 24 - P0.6 23 - 34 - 23 P0.7 22 - 33 - 22 PLCC28 ESD PLCC68 Supply Port VQFP32 Internal VQFP64 QFN64 Table 2. Pin Description P0.0 30 - 41 - P0.1 29 - 40 - P0.2 28 - 39 P0.3 27 - P0.4 25 P0.5 Power Conf 1 Conf 2 Conf 3 P0 KB_OUT Push-pull AD1 P0 KB_OUT Push-pull Float AD2 P0 KB_OUT Push-pull I/O Float AD3 P0 KB_OUT Push-pull 2KV I/O Float AD4 P0 KB_OUT Push-pull VCC 2KV I/O Float AD5 P0 KB_OUT Push-pull - VCC 2KV I/O Float AD6 P0 KB_OUT Push-pull - VCC 2KV I/O Float AD7 P0 KB_OUT Push-pull Led CVCC inactive at reset. ESD tested with a 10μF on CVCC CIO 64 32 9 4 64 32 CVCC 6KV I/O 0 Port51 CC4 3 3 12 7 3 3 CVCC 6KV I/O 0 Port51 P1.2 2 2 11 6 2 2 VCC 2KV I/O 1 CC4 9 5 18 9 9 5 CVCC 6KV I/O 0 Port51 CCLK 12 6 21 10 12 6 CVCC 6KV O 0 Push-pull CRST 6 4 15 8 6 4 CVCC 6KV O 0 Push-pull P1.6 47 23 58 - 47 23 VCC 2KV I/O 1 SS Port51 P1.7 62 31 7 - 62 31 VCC 2KV I/O 1 CCLK1 Port51 P2.0 58 - 3 - 58 - VCC 2KV I/O 1 A8 Port51 Push-pull KB_OUT Input WPU P2.1 57 - 2 - 57 - VCC 2KV I/O 1 A9 Port51 Push-pull KB_OUT Input WPU P2.2 56 - 1 - 56 - VCC 2KV I/O 1 A10 Port51 Push-pull KB_OUT Input WPU P2.3 52 - 65 - 52 - VCC 2KV I/O 1 A11 Port51 Push-pull KB_OUT Input WPU P2.4 51 - 64 - 51 - VCC 2KV I/O 1 A12 Port51 Push-pull KB_OUT Input WPU P2.5 50 - 63 - 50 - VCC 2KV I/O 1 A13 Port51 Push-pull KB_OUT Input WPU CPRES Port51 An external pull-up of 10K is recommended to support ICC’s with too weak internal pull-ups. CVCC inactive at reset ESD tested with a 10μF on CVCC Weak & medium pull-up can be disconnected CVCC inactive at reset ESD tested with a 10μF on CVCC CVCC inactive at reset ESD tested with a 10μF on CVCC CVCC inactive at reset ESD tested with a 10μF on CVCC 11 4202F–SCR–07/2008 QFN32 I/O Reset Level Alt Reset Config Conf 1 Conf 2 Conf 3 49 - VCC 2KV I/O 1 A14 Port51 Push-pull KB_OUT Input WPU 46 - VCC 2KV I/O 1 A15 Port51 Push-pull KB_OUT Input WPU 24 45 22 VCC 2KV I/O 1 RxD Port51 Push-pull KB_OUT Input WPU 59 25 48 24 VCC 2KV I/O 1 TxD Port51 Push-pull KB_OUT Input WPU 20 54 23 43 20 VCC 2KV I/O 1 INT0 Port51 41 19 52 22 41 19 VCC 2KV I/O 1 INT1 Port51 Push-pull KB_OUT Input WPU P3.4 39 18 50 21 39 18 VCC 2KV I/O 1 T0 Port51 Push-pull KB_OUT Input WPU P3.5 44 21 55 - 44 21 VCC 2KV I/O 1 T1 Port51 P3.6 36 17 47 20 36 17 VCC 2KV I/O 1 WR Port51 LED2 P3.7 26 13 37 16 26 13 VCC 2KV I/O 1 RD Port51 LED3 P4.0 42 - 53 - 42 - VCC 2KV I/O 1 MISO Port51 P4.1 40 - 51 - 40 - VCC 2KV I/O 1 MOSI Port51 P4.2 38 - 49 - 38 - VCC 2KV I/O 1 SCK Port51 P4.3 37 - 48 - 37 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input MPU LED4 P4.4 35 - 46 - 35 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input MPU LED5 P4.5 33 - 44 - 33 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input MPU LED6 P5.0 14 7 23 - 14 7 VCC 2KV I/O 1 KB0 Port51 Push-pull Input MPU Input WPU P5.1 13 - 22 - 13 - VCC 2KV I/O 1 KB1 Port51 Push-pull Input MPU Input WPU P5.2 11 - 20 - 11 - VCC 2KV I/O 1 KB2 Port51 Push-pull Input MPU Input WPU P5.3 10 - 19 - 10 - VCC 2KV I/O 1 KB3 Port51 Push-pull Input WPD Input WPU P5.4 8 - 17 - 8 - VCC 2KV I/O 1 KB4 Port51 Push-pull Input WPD Input WPU PLCC28 ESD PLCC68 Supply Port VQFP32 Internal VQFP64 QFN64 Table 2. Pin Description (Continued) P2.6 49 - 62 - P2.7 46 - 57 - P3.0 45 22 56 P3.1 48 24 P3.2 43 P3.3 12 Power Led LED0 LED1 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 PLCC68 PLCC28 7 - 16 - P5.6 5 - 14 - P5.7 4 - 13 - QFN32 VQFP32 P5.5 QFN64 Port VQFP64 Table 2. Pin Description (Continued) Internal Supply ESD I/O Reset Level Alt Reset Config Conf 1 Conf 2 Conf 3 7 - VCC 2KV I/O 1 KB5 Port51 Push-pull Input WPD Input WPU 5 - VCC 2KV I/O 1 KB6 Port51 Push-pull Input WPD Input WPU 4 - VCC 2KV I/O 1 KB7 Port51 Push-pull Input WPD Input WPU Power Led Reset Input The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. RST 34 16 45 19 34 16 VCC I/0 This pin has an internal 10K pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and VSS. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. The output is active for at least 12 oscillator periods when an internal reset occurs. USB Positive Data Upstream Port This pin requires an external serial resistor of 27Ω (AT8xC122) or 33Ω (AT83C5123) and a 1.5 KΩ pull-up to VREF for full speed configuration. D+ 60 29 5 2 60 29 DVCC I/O D- 59 28 4 1 59 28 DVCC I/O VREF 61 30 6 3 61 30 AVCC O XTAL 1 31 14 42 17 31 14 VCC I Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal or an external oscillator must be connected to this pin. XTAL 2 32 15 43 18 32 15 VCC O Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal circuit must be connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. USB Negative Data Upstream Port This pin requires an external serial resistor of 27Ω (AT8xC122) or 33Ω (AT83C5123) USB Voltage Reference: 3.0 < VREF < 3.6 V VREF can be connected to D+ through a 1.5 KΩ resistor. The VREF voltage is controlled by software. External Access Enable (Only AT8xC5122) EA must be strapped to ground in order to enable the device to fetch code from external memory locations 0000h to FFFFh. EA/ VCC 63 - 8 - 63 - VCC I If security level 1 is programmed, EA will be latched on reset. Warning : EA pin cannot be left floating. If the External Access Enable mode is not used, EA pin must be strapped to VCC. If this last condition is not met,the MCU may have an unpredictable behaviour. VCC (Only AT89C5122DS) ALE 21 - 32 - 21 - VCC O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches 13 4202F–SCR–07/2008 QFN32 QFN64 PLCC28 PLCC68 VQFP32 Port VQFP64 Table 2. Pin Description (Continued) Internal Power Supply ESD I/O Reset Level Alt Reset Config Conf 1 Conf 2 Conf 3 Led PSEN 15 - 24 - 15 - VCC O Program Strobe Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. PLLF 54 26 67 27 54 26 AVCC O PLL Low Pass Filter input Receives the RC network of the PLL low pass filter. AVCC 55 27 68 28 55 27 PWR VCC 20 12 31 15 20 12 PWR Analog Supply Voltage AVCC is used to supply the internal 3.3V analog regulator which supplies the internal USB driver Supply Voltage VCC is used to supply the internal 3.3V digital regulator which supplies the PLL, CPU core and internal I/O’s DC/DC Input LI supplies the current for the charge pump of the DC/DC converter. LI 18 10 29 13 18 10 PWR - LI tied directly to VCC : the DC/DC converter must be configured in regulator mode. - LI tied to VCC through an external 10μH coil : the DC/DC converter can be configured either in regulator or in pump mode. Card Supply Voltage CVCC 17 9 28 12 17 9 PWR CVCC is the ouput of internal DC/DC converter which supplies the Smart Card Interface. It must be connected to an external decoupling capacitor of 10 μF with the lowest ESR as this parameter influences on the CVCC noise Digital Supply Voltage DVCC 1 1 10 5 1 1 PWR DVCC is the output of the internal analog 3.3V regulator which supplies the USB driver. This pin must be connected to an external 680nF decoupling capacitor if the USB interface is used. This output can be used by the application with a maximum of 10 mA. DC/DC Ground CVSS 19 11 30 14 19 11 GND VSS 16 8 25 11 16 8 GND Digital Ground VSS is used to supply the PLL, buffer ring and the digital core AVSS 53 25 66 26 53 25 GND Analog Ground AVSS is used to supply the USB driver. 14 CVSS is used to sink high shunt currents from the external coil AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Typical Applications Recommended External components All the external components described in the figure and table below must be implemented as close as possible from the microcontroller package. Table 3. External Components Bill Of Materials Reference Description R1 USB Full Speed Pull-up R2 USB pad serial resistor R3 USB pad serial resistor Value Comments 1.5 KΩ +/-10% All product versions 27 Ω +/-10% For AT8xC5122 versions 33 Ω +/-10% For AT83C5123 versions 27 Ω +/-10% For AT8xC5122 versions 33 Ω +/-10% For AT83C5123 versions R4 PLL filter resistor 1.8 KΩ +/-10% All product versions R5 CIO Pull-up resistor 10 KΩ +/10% All product versions C1 Power Supply filter capacitor 100 nF +80/-20% All product versions C2 PLL filter capacitor 33 pF +/-10% All product versions C3 PLL filter capacitor 150 pF +/-10% All product versions C4 USB pad decoupling capacitor 680 nF +/-30% C5 Smart Card clock filter capacitor 27 pF +/-10% All product versions. C6 DC/DC Converter decoupling capacitor 10 μF +/-10% All product versions. Low ESR This capacitor does not impact the USB Inrush Current C7 DC/DC Converter filter capacitor 100 nF +80/-20% All product versions C8 Power Supply decoupling capacitor 4.7 μF +/-10% This capacitor impacts the USB Inrush Current. Maximum application capacitance allowed by the USB standard is 10 μF. C9 Power Supply filter capacitor 100 nF +80/-20C All product versions C10 Reset capacitor 10 μF +/-10% Optional capacitor for all product versions 10 μH +/- 10% All product versions. Min rated current : 200 mA Qualified component : Murata LQH32CN100K21L Min rated freq. : 4 MHz If DC/DC converter is not used at 5V, this inductance is optional. 8.0000 Mhz +/- 2500 ppm only All product versions All product versions. If USB interface is not used, this capacitor is optional All products versions L1 Q1 DC/DC converter input inductance Crystal ESR max : 100 Ω 15 4202F–SCR–07/2008 USB Keyboard with Smart Card Reader Using AT83R5122, AT8xC5122/AT89C5122DS VCC C9 C8 GND VCC GND VCC EA/VCC (1) 10mA Max VCC C1 GND VCC AVCC LEDx VCC DVCC L1 C4 LI GND USB R1 VCC VBUS D+ R2 CVCC D+ CVSS D- CRST C6 Smart Card C7 C1 VCC 15pF GND R3 DGND VREF CCLK CC4 CIO CC8 CPRES GND R00 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 C0 C1 C2 C3 C4 C5 C6 C7 KB0 KB1 KB2 KB3 KB4 KB5 KB6 KB7 C2 180Ohms RST CLK C4 I/O C8 S1 S2 GND VCC VCC RST CLK I/O GND GND RST C10 PLLF AVSS VSS Alternate Card C1 C2 C3 C7 C5 CRST1 CCLK1 CIO1 Keyboard Matrix C2 C3 C4 C7 C8 S1 R5 P3[0-1,3-4] P2[0-7] P0[0-7] R4 C5 GND XTAL1 XTAL2 Optional Capacitor GND C3 GND GND Q1 Notes : 1 - Pin configuration depends on product versions 16 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 USB Smart Card Reader Using the AT83C5123 Version VCC VCC C9 C1 C8 GND GND VCC GND VCC AVCC LEDx 10mA Max VCC DVCC L1 C4 LI Smart Card GND USB R1 VCC VBUS D+ C7 C1 VCC C5 GND CVSS R2 D+ R3 DGND CVCC VREF C6 CRST CCLK CC4 CIO CC8 CPRES D- GND GND C2 C3 C4 C7 C8 S1 RST CLK C4 I/O C8 S1 S2 R5 GND VCC Alternate Card C1 C2 C3 C7 C5 CRST1 CCLK1 CIO1 VCC RST CLK I/O GND GND PLLF R4 C2 RST AVSS VSS XTAL1 XTAL2 C10 Optional Capacitor GND C3 GND GND Q1 17 4202F–SCR–07/2008 Memory Organization The AT83R5122, AT8xC5122/23 devices have separated address spaces for Program and Data Memory, as shown in Figure 12 on page 27, Figure 13 on page 29 and Figure 14 on page 30. The logical separation of Program and Data memory allows the Data Memory to be accessed by 8-bit addresses, which can be more quickly stored and manipulated by an-bit CPU. Nevertheless, 16-bit Data Memory addresses can also be generated through the DPTR register. Program Memory Managament Depending on the state of EA pin, the MCU fetches the code from internal or external program memory (ROMless mode) Warning : the EA pin can not be left floating, otherwise MCU may have an unpredictable behaviour. If EA is strapped to VCC, the MCU fetches the code from the internal program memory. The way the MCU works in this mode depends on the device version. See next paragraphs for further details. If the EA is strapped to GND, the MCU fetches the code from external program memory. This mode is common for all device versions wich supports it. After reset, the CPU begins the execution from location 0000h. There can be up to 64 KBytes of program memory. In this mode, the internal program memories are disabled. The hardware configuration for external program execution is shown in Figure 8. Figure 8. Executing from External Program Memory EXTERNAL PROGRAM MEMORY AT8xC5122 A15:8 P2 A15:8 ALE AD7:0 P0 Latch A7:0 A7:0 D7:0 PSEN# OE Note that the 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external Program Memory fetches. Port 0 serves as a multiplexed address/dat bus. It emits the low byte of the Program Counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the Program Memory. During the time that the low byte of the Program Counter is valid on P0, the signal ALE (Address Latch Enable) clocks the byte into an address latch. Meanwhile, Port 2 emits the high byte of the Program Counter (PCH). Then PSEN strobes the External Program Memory and the code byte is read into the MCU. PSEN is not activated and Ports P0 and P2 are not affected during internal program fetches. 18 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Data Memory Managament All device versions implements : - 256 Bytes of RAM to increase data parameter handling and high level language usage - 512 bytes of XRAM (Extended RAM) to store program data. RAM Achitecture The internal RAM is mapped into three separate segments : • The Lower 128 bytes (addresses 00h to 7Fh) are directly and indirectly addressable. • The Upper 128 bytes (addresses 80h to FFh) are indirectly addressable only. • The Special Function Registers (SFRs) (addresses 80h to FFh) are directly addressable only. The Upper 128 bytes and SFR’s have the same address space but are physically separated. When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is in the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. • Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timings. If M0 is set, the read and write pulses are extended from 6 to 30 clock periods. This is useful to access external slow peripherals. XRAM Achitecture Depending on the state of EXTRAM bit in AUXR register (See Table 5 on page 22), the MCU fetches data from internal or external XRAM. If EXTRAM=0 (reset condition), the MCU fetches the data from internal XRAM. The size of internal XRAM is configured by the bit XRS0 in AUXR register (See Table 5 on page 22). Table 4. XRAM Size Configuration Address XRS0 0 1 XRAM size 256 Bytes (Reset condition) 512 bytes Start End 000h 0FFh 000h 1FFh The XRAM logically occupies the first bytes of external data memory. The bit XRS0 can be used to hide a part of the available XRAM . This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. The XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. For example, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. 19 4202F–SCR–07/2008 An access to external XRAM memory locations higher than the accessible size of the memory (roll-over feature) will be performed with the MOVX DPTR instructions, with P0 and P2 as data/address busses, WR and RD as respectively write and read signals. Accesses above XRAM size can only be done by the use of DPTR. If EXTRAM=1 the MCU fetches the data from external XRAM Memory. There can be up to 64 KBytes of external XRAM Memory. The hardware configuration for external Data Memory Access is shown in Figure 9 Figure 9. Accessing to External XRAM Memory EXTERNAL XRAM MEMORY AT83R5122, A15:8 P2 A15:8 ALE AD7:0 P0 Latch A7:0 A7:0 D7:0 RD# WR# OE WR MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port 2 outputs the highorder eight address bits (DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on WR and RD. Ports P0, P2 are not affected and RD, WR signals are not activated during access to internal XRAM. Note that external XRAM Memory access is only available on High Pin Count Packages. External Program Memory and external XRAM Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the ouput of the gate as the read strobe to the external program/data memory. RD STROBE PSEN Dual Data Pointer Register (DDPTR) The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 7) that allow the program code to switch between them (Figure 10). 20 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 10. Use of Dual Pointer External Data Memory 7 0 DPS AUXR1(A2H) DPTR1 DPTR0 DPH(83H) DPL(82H) a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3. Assembly Language ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 QU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ;increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. For example, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. 21 4202F–SCR–07/2008 Registers Table 5. Auxiliary Register - AUXR (8Eh) 7 6 5 4 DPU - - - Bit Number 3 2 1 0 XRS0 EXTRAM AO Bit Mnemonic Description Disable weak Pull-up 7 DPU 6-3 - 2 XRS0 0 weak pull-up is enabled 1 weak pull-up is disabled Reserved The value read from this bit is indeterminate. Do not change these bits. XRAM Size 0 256 bytes (default) 1 512 bytes EXTRAM bit Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR. 1 EXTRAM Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting , XRAM selected. ALE Output bit 0 AO Cleared , ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used)(default). Set , ALE is active only when a MOVX or MOVC instruction is used. Reset Value = 0XXX X000b 22 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 6. Auxiliary Register 1 AUXR1- (0A2h) for AT8xC5122 7 6 5 4 3 2 1 0 - - ENBOOT - GF3 0 - DPS Bit Number 7-6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. - Enable Boot ROM (CRAM / E2PROM version only) 5 ENBOOT Set this bit to map the Boot ROM from 8000h to FFFFh. If the PC increments beyond 7FFFh address, the code is fetch from internal ROM Clear this bit to disable Boot ROM. If the PC increments beyond 7FFFh address, the code is fetch from external code memory (C51 standard roll over function) This bit is forced to 1 at reset Reserved The value read from this bit is indeterminate. Do not change this bit. 4 - 3 GF3 2 0 Always cleared. 1 - Reserved The value read from this bit is indeterminate. Do not change this bit. 0 DPS This bit is a general-purpose user flag. Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1. Reset Value = XX1X XX0X0b (Not bit addressable) Table 7. Auxiliary Register 1 AUXR1- (0A2h) for AT83C5123 7 6 5 4 3 2 1 0 - - - - GF3 0 - DPS Bit Number 7-6 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not change these bits. Reserved The value read from this bit is indeterminate. Do not change these bits. 5 Reserved The value read from this bit is indeterminate. Do not change this bit. 4 - 3 GF3 2 0 Always cleared. 1 - Reserved The value read from this bit is indeterminate. Do not change this bit. 0 DPS This bit is a general-purpose user flag. Data Pointer Selection Cleared to select DPTR0. Set to select DPTR1. Reset Value = XXXX XX0X0b (Not bit addressable) 23 4202F–SCR–07/2008 Table 8. CRAM Configuration Register - RCON (D1h) 7 6 5 4 3 2 1 0 - - - - RPS - - - Bit Bit Number Mnemonic 7-4 - Description Reserved The value read from this bit is indeterminate. Do not change these bits. CRAM Memory Mapping Bit 3 RPS Set to map the CRAM memory during MOVX instructions Clear to map the XRAM memory during MOVX. This bit has priority over the EXTRAM bit. 2-0 - Reserved The value read from this bit is indeterminate. Do not change these bits. Reset Value = XXXX 0XXXb AT8xC5122’s CRAM and E2PROM Versions The AT8xC5122’s CRAM and E2PROM versions implements : - 32 KB of ROM mapped from 8000 to FFFF in which is embedded a bootloader for InSystem Programming feature - 32 KB of CRAM (Code RAM) , a volatile program memory mapped from 0000 to 7FFF In CRAM versions only : - 512 bytes of E2PROM can be optionally implemented to store permanent data In E2PROM version : - 32KB of E2PROM are implemented to store permanent code Warnings : 24 – some bytes of user program memory space are reserved for bootloader configuration. Depending on the configuration, up to 256 bytes of code may be not available for the user code from 7F00h location. Refer to bootloader datasheet for further details. – Port P3.7 may be used by the bootloader as a hardware condition at reset to select the In-System Programming mode. Once the bootloader has started, the P3.7 Port is no more used. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 AT8xC5122 Microcontroller FFFFh P3.7 Bootloader 7FFFh 7F00h 7EFFh Reserved User code 0000h When pin EA =1 and after the reset, the MCU begins the execution of the embedded bootloader from location F800h of the ROM. The bootloader implements an In-System Programming (ISP) mode which manages the transfer of the code in the volatile Program Memory (CRAM). For CRAM version, the code is supplied by the ATMEL’s FLexible In-system Programming software (FLIP) through USB or UART interface For E2PROM version, the code is supplied from the internal code E2PROM or by FLIP. The state of pin P3.7 at reset determines the code source. If P3.7=1 (reset condition) the source is the internal E2PROM and the transfer takes about 1.5 seconds. If P3.7=0 the source is FLIP and the transfer time depends mainly on external conditions not related to bootloader. Once the code is running in CRAM, the roll-over condition (code fetched beyond address 7FFFh) depends on the state of ENBOOT bit of AUXR1 register (Table 6 on page 23). If ENBOOT=1 (reset condition) the MCU fetches the code from bootloader ROM. If ENBOOT=0, the MCU fetches the code from the external Program Memory. In this last case, PSEN is activated and Ports P0 and P2 are used to emit data and address signals. Warning : external Program Memory access is not allowed on Low Pin Count Packages. 25 4202F–SCR–07/2008 Using CRAM Memory The CRAM is a read / write volatile memory that is mapped in the program memory space. Then when the power is switched off the code is lost and needs to be reload at each power up. In return, the CRAM enables a lot of flexibility in the code development as it can be programmed indefinitely. The user code running in the CRAM can perform read operations in CRAM itself by means of MOVC instructions like any C51 microcontroller does. Although the writing operations in CRAM are usually handled by the bootloader, it is possible for the user code to handle its own writing operations in CRAM as well. The user code must call API functions provided by the bootloader in the ROM memory. Refer to bootloader datasheet for further details about the use of these API functions. These API functions use a mechanism provided by the AT8xC5122 microcontroller. When the bit RPS is set in RCON register (Table 8 on page 24), the MOVX intructions are configured to write in CRAM instead of XRAM memory. However, due to C51 architecture, it is not possible for the user code to write directly in CRAM when it is itself running in CRAM. This is why the API functions must be called in order to have the code executing in ROM while the CRAM is written. Figure 11. Read / Write Mechanisms in CRAM Memory API functions BOOTLOADER RPS=1 MOVX CRAM API Call Writing operation User code Read operation MOVC 26 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 12. AT8xC5122’s CRAM and E2PROM Versions (E2PROM version) EA = 0 EA = 1 FFFF ENBOOT=0 ENBOOT=1 32K INTERNAL E2PROM (Read/Write) FFFF FFFF Reset@ <F800> 8000 32K EXTERNAL PROGRAM MEMORY 32K INTERNAL ROM (Read Only) 8000 8000 Roll-Over PROGRAM MEMORY EXTERNAL PROGRAM MEMORY PSEN 7FFF 32K INTERNAL CRAM (Read/Write) Reset@ <0000> 0000 PSEN EXTRAM=1 EXTRAM=0 FFFF 01FF EXTERNAL XRAM 512 Bytes INTERNAL E2PROM 0000 On-Chip 256 bytes RAM 0200 DATA MEMORY (Read / Write) Optional (applicable only to CRAM version) Roll-Over 01FF FF 01FF On-chip 512 bytes XRAM 0000 Indirect Addressing EXTERNAL XRAM 0000 80 7F 00 RD Upper 128 Bytes RAM Direct Addressing FF 80 SFR Space Lower 128 Bytes RAM WR 27 4202F–SCR–07/2008 AT83R5122, AT8xC5122’s The AT83R5122, AT8xC5122’s ROM version implements : ROM Version - 32 K of ROM mapped from 0000h to 7FFFh in which is embedded the user code. The ROM device is only factory programmable. - 512 bytes of E2PROM can be optionally implemented to store permanent data. With this option, the size of ROM is reduced to 30K. After the reset, the MCU begins the execution of the user code from location 0000h of the ROM. Access to external Program Memory is not allowed. Security Level There are two security levels (applicable to High Pin Count packages only) : Table 9. Security Levels Description Security Level 1 2 Protection description No protection lock enabled MOVC instruction executed from external Program Memory is disabled when fetching code bytes from internal Program Memory EA is sampled and latched on reset. External code execution is enabled. The security level 2 can be used to protect the user code from piracy. This option is configured at factory and must be requested by the customer at order time. 28 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 13. AT83R5122, AT8xC5122’s ROM Version EA=1 EA=0 FFFF EXTERNAL PROGRAM MEMORY (Read only) 8000 Roll-Over 7FFF INTERNAL 32K ROM EXTERNAL RESET@ <0000> 0000 PSEN EXTRAM=1 EXTRAM=0 FFFF 01FF EXTERNAL XRAM 0200 DATA MEMORY (Read / Write) Optional 512 Bytes INTERNAL E2PROM 0000 On-Chip 256 bytes RAM Roll-Over FF 01FF 01FF On-chip 512 bytes XRAM 0000 Indirect Addressing EXTERNAL XRAM 0000 80 7F 00 RD Upper 128 Bytes RAM Direct Addressing FF 80 SFR Space Lower 128 Bytes RAM WR 29 4202F–SCR–07/2008 The AT83C5123 device is a low pin count version of the AT8xC5122. AT83C5123 Version The ROM version implements : - 30 KB of ROM mapped from 0000 to 77FF in which is embedded the user code. The ROM device is only factory programmable. - 512 bytes of E2PROM can be optionally implemented to store permanent data Figure 14. AT83C5123’s Device 7FFF INTERNAL 30K ROM PROGRAM MEMORY (Read only) RESET@ <0000> OPTIONAL On-Chip 256 bytes RAM 01FF DATA MEMORY (Read / Write) 512 Bytes INTERNAL E2PROM Indirect Addressing FF 0000 80 01FF On-chip 512 bytes XRAM 7F 00 Upper 128 Bytes RAM Direct Addressing FF 80 SFR Space Lower 128 Bytes RAM 0000 30 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Special Function Registers (SFR’s) Introduction The Special Function Registers (SFRs) of the AT8xC5122/23 can be ranked into the following categories: • C51 Core Registers: ACC, B, DPH, DPL, PSW, SP • System Configuration Registers: PCON, CKRL, CKCON0, CKCON1, CKSEL, PLLCON, PLLDIV, AUXR, AUXR1, RCON • I/O Port Registers: P0, P1, P2, P3, P4, P5, PMOD1, PMOD2 • Timer Registers: TCON, TH0, TH1, TMOD, TL0, TL1 • Watchdog (WD) Registers: WDTRST, WDTPRG • Serial I/O Port Registers: SADDR, SADEN, SBUF, SCON • Baud Rate Generator (BRG) Registers: BRL, BDRCON • System Interrupt Registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1 • Smart Card Interface (SCI) Registers: SCSR, SCCON/SCETU0, SCISR/SCETU1, SCIER/SCIIR, SCIBUF, SCGT0/SCWT0, SCGT1/SCWT1, SCICR/SCWT2, SCICLK • DC/DC Converter Registers: DCCKPS • Keyboard Interface Registers: KBE, KBF, KBLS • Serial Port Interface (SPI) Registers: SPCON, SPSTA, SPDAT • Universal Serial Bus (USB) Registers:USBCON, USBADDR, USBINT, USBIEN, UEPNUM, UEPCONX, UEPSTAX, UEPRST, UEPINT, UEPIEN, UEPDATX, UBYCTX, UFNUML, UFNUMH • LED Controller Registers: LEDCON0, LEDCON1 31 4202F–SCR–07/2008 AT8xC5122 Version Bit addressable 0/8 F8h UEPINT 0000 0000 F0h B 0000 0000 E8h E0h Not bit addressable 1/9 2/A 3/B 4/C 5/D UEPCONX 1000 0000 UEPRST 0000 0000 6/E 7/F UEPSTAX 0000 0000 UEPDATX 0000 0000 LEDCON0 0000 0000 P5 1111 1111 LEDCON1 ACC 0000 0000 XX00 0000 PSW 0000 0000 XXXX 0XXX UBYCTX 0000 0000 D8h D0h RCON C8h S 1 C R S 0 SCICLK (1) C0h S 1 C R S 0 1111 1111 0X10 1111 SCWT3 (1) B0h A8h A0h 98h 90h 88h 80h IPL0 SADEN X000 000 0000 0000 P3 1111 1111 IEN1 XXXX X000 IEN0 SADDR 0000 0000 0000 0000 SPCON SPSTA SPDAT 0001 0100 0000 0000 1111 1111 USBADDR 1000 0000 UEPNUM 0000 0000 UFNUML 0000 0000 UFNUMH 0000 0000 USBCON 0000 0000 USBINT 0000 0000 USBIEN 0000 0000 0000 0000 SCGT0 (1) 0000 1100 SCGT1(1) XXXX XXX0 SCICR (1) 0000 0000 IPH0 SCWT0(1) SCWT1 (1) SCWT2 (1) X000 0000 1000 0000 0010 0101 0000 0000 SCETU0 (1) SCETU1 (1) SCIER 0111 0100 XXXX X001 0X00 0000 IPL1 IPH1 00XX 00X0 00XX 00X0 SCIBUF XXXX XXXX P2 ISEL AUXR1 1111 1111 0000 0100 XX1X 0XX0 SCSR X000 1000 PLLCON XXXX X000 SCCON (1) SCISR (1) SCIIR (1) 0000 0000 10X0 0000 0X00 0000 PLLDIV 0000 0000 WDTRST WDTPRG XXXX XXXX XXXX X000 SCON SBUF BRL BDRCON KBLS KBE KBF XXXX XXXX 0000 0000 XXX0 0000 0000 0000 0000 0000 0000 0000 P1 PMOD0(2) 0000 0000 1111 1111 DCCKPS (1) 0000 0000 CKRL XXXX 1111 TCON TMOD TL0 TL1 TH0 TH1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 P0 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 PMOD1 CKSEL PCON 0000 0000 XXXX XXX0 00X1 0000 1111 1111 Notes: 32 UEPIEN 0000 0000 0000 0000 B8h S 1 C R S 0 P4 AUXR 0XXX X000 CKCON0 X0X0 X000 1. Mapping is done using SCRS bit in SCSR register. 2. Grey areas : do not write in. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 AT83C5123 Version Bit addressable 0/8 F8h UEPINT 0000 0000 F0h B 0000 0000 E8h E0h Not bit addressable 1/9 2/A 3/B 4/C 5/D UEPCONX 1000 0000 UEPRST 0000 0000 6/E 7/F UEPSTAX 0000 0000 UEPDATX 0000 0000 USBADDR 1000 0000 UEPNUM 0000 0000 0000 0000 LEDCON0 0000 0000 P5 XXXX XXX1 ACC 0000 0000 UBYCTX 0000 0000 D8h D0h PSW 0000 0000 C8h S 1 C R S 0 SCICLK (1) C0h S 1 C R S 0 11XX XXXX 0X10 1111 SCWT3 (1) UEPIEN 0000 0000 0000 0000 B8h S 1 C R S 0 P4 B0h A8h IPL0 SADEN X000 000 0000 0000 P3 1111 1111 IEN0 SADDR 0000 0000 0000 0000 A0h 98h 90h 88h IEN1 X0XX 0XXX UFNUML 0000 0000 DCCKPS UFNUMH 0000 0000 USBCON 0000 0000 USBINT 0000 0000 USBIEN 0000 0000 IPH1 SCGT1(1) XXXX XXX0 SCICR (1) IPL1 SCGT0 (1) 0000 1100 0000 0000 IPH0 X0XX 0XXX X0XX 0XXX SCWT0(1) SCWT1 (1) SCWT2 (1) X000 0000 1000 0000 0010 0101 0000 0000 SCETU0 (1) SCETU1 (1) SCIER SCSR 0111 0100 XXXX X001 0X00 0000 CKCON1 X000 1000 SCCON (1) SCISR (1) SCIIR (1) XXXX XXX0 0000 0000 10X0 0000 0X00 0000 SCIBUF XXXX XXXX ISEL AUXR1 0000 0100 XXXX 0XX0 PLLCON XXXX X000 SCON SBUF BRL BDRCON 0000 0000 XXXX XXXX 0000 0000 XXX0 0000 PLLDIV 0000 0000 (1) WDTRST WDTPRG XXXX XXXX XXXX X000 P1 PMOD0 CKRL 1111 1111 00XX 0XXX XXXX 1111 TCON TMOD TL0 TL1 TH0 TH1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 PMOD1 CKSEL PCON XXXX 00XX XXXX XXX0 00X1 0000 80h Notes: AUXR 0XXX X000 CKCON0 X0X0 X000 1. Mapping is done using SCRS bit in SCSR register. 2. Grey areas : do not write in. 33 4202F–SCR–07/2008 SFR’s Description Table 10. C51 Core SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word RS0 OV F1 P SP 81h Stack Pointer DPL 82h Data Pointer Low byte (LSB of DPTR) DPL DPH 83h Data Pointer High byte (MSB of DPTR) DPH 4 3 2 1 0 GF1 GF0 PD IDL T1X2 T0X2 X2 ACC B CY AC F0 RS1 SP Table 11. Clock SFRs Mnemonic Add Name PCON 87h Power Controller CKCON0 8Fh Clock Controller 0 CKCON1 AFh Clock Controller 1 CKSEL 85h Clock Selection CKRL 97h Clock Reload Register PLLCON A3h PLL Controller Register PLLDIV A4h PLL Divider register AUXR 8Eh Auxiliary Register 0 AUXR1 A2h Auxiliary Register 1 RCON (1) D1h 7 6 5 SMOD1 SMOD0 POF WDX2 SIX2 SPIX2 CKS CKREL 3-0 EXT48 R3-0 PLLEN PLOCK EXTRAM A0 N3-0 DPU XRS0 ENBOOT(1) GF3 CRAM memory Configuration DPS RPS Note: 1. Only for AT8xC5122 Table 12. I/O Port SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 P0(1) 80h Port 0 P0 P1 90h Port 1 P1 P2(1) A0h Port 2 P2 P3 B0h Port 3 P3 P4(1) C0h Port 4 P4 P5 E8h Port 5 P5 (only P5.0 for AT8xC5122) PMOD0 91h Port Mode Register 0 P3C1 P3C0 P2C1(1) P2C0(1) CPRESRES - P0C1(1) P0C0(1) PMOD1 84h Port Mode Register 1 P5HC1(1) P5HC0(1) P5MC1(1) P5MC0(1) P5LC1 P5LC0 P4C1(1) P4C0(1) Note: 34 1. Only for AT8xC5122 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 13. Timers SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 TH0 8Ch Timer/Counter 0 High byte TH0 TL0 8Ah Timer/Counter 0 Low byte TL0 TH1 8Dh Timer/Counter 1 High byte TH1 TL1 8Bh Timer/Counter 1 Low byte TL1 TCON 88h Timer/Counter 0 and 1 control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 7 6 5 4 3 2 1 0 Table 14. Watchdog SFRs Mnemonic Add Name WDTRST A6h Watchdog Timer Reset WDTPRG A7h Watchdog Timer Program WDTRST S2-0 Table 15. Serial I/O Ports SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI 3 2 1 0 BRR TBCK RBCK SPD M0SRC 4 3 2 1 0 ES ET1 EX1 ET0 EX0 ESCI ESPI(1) PT1L PX1L SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADEN SADDR A9h Slave Address SADDR SBUF Table 16. Baud Rate Generator SFRs Mnemonic Add Name BRL 9Ah Baud Rate Reload BDRCON 9Bh Baud Rate Control 7 6 5 4 BRL Table 17. Interrupt SFRs Mnemonic Add Name 7 IEN0 A8h Interrupt Enable Control 0 EA IEN1 B1h Interrupt Enable Control 1 IPL0 B8h Interrupt Priority Control Low 0 6 5 EUSB PSL EKB(1) PT0L PX0L 35 4202F–SCR–07/2008 Table 17. Interrupt SFRs Mnemonic Add Name 7 IPH0 B7h Interrupt Priority Control High 0 IPL1 B2h Interrupt Priority Control Low 1 IPH1 B3h Interrupt Priority Control High 1 ISEL A1h Interrupt Enable Register Note: 6 5 4 3 2 1 0 PSH PT1H PX1H PT0H PX0H PUSBL PSCIL PSPIL(1) PKBL(1) PUSBH PSCIH PSPIH(1) PKBH(1) RXIT OELEV OEEN PRESEN RXEN 4 3 2 1 0 CPLEV PRESIT 1. Only for AT8xC5122 Table 18. SCIB SFRs Mnemonic Add Name SCGT0 B4h Smart Card Transmit Guard Time Register 0 SCGT1 B5h Smart Card Transmit Guard Time Register 1 SCWT0 B4h Smart Card Character/ Block Waiting Time Register 0 WT7 - 0 SCWT1 B5h Smart Card Character/ Block Waiting Time Register 1 WT15-8 SCWT2 B6h Smart Card Character/ Block Waiting Time Register 2 WT23-16 SCWT3 C1h Smart Card Character/ Block Waiting Time Register 3 WT31-24 SCICR B6h Smart Card Interface Control Register SCCON ACh Smart Card Interface Contacts Register SCETU0 ACh Smart Card ETU Register 0 SCETU1 ADh Smart Card ETU Register 1 COMP SCISR ADh Smart Card UART Interface Status Register (Read only) SCTBE SCIIR Smart Card UART Interrupt AEh Identification Register (Read only) SCIER AEh Smart Card UART Interrupt Enable Register SCSR ABh Smart Card Selection Register SCIBUF 36 AAh Smart Card Buffer Register 7 6 5 GT7 - 0 GT8 RESET CARDDET VCARD1-0 CLK CARDC8 UART CARDC4 CARDIO WTEN CREP CONV CARDCLK CARDRST CARDVCC ETU7 - 0 ETU10-8 CARDIN ICARDOVF VCARDOK SCWTO SCTC SCRC SCPE SCTBI ICARDERR VCARDERR SCWTI SCTI SCRI SCPI ESCTBI ICARDER EVCARDER ESCWTI ESCTI ESCRI ESCPI SCCLK1 SCRS BGTEN CREPSEL ALTKPS1-0 Can store a new byte to be transmitted on the I/O pin when SCTBE is set. Bit ordering on the I/O pin depends on the convention Provides the byte received from the I/O pin when SCRI is set. Bit ordering on the I/O pin depends on the convention. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 18. SCIB SFRs Mnemonic Add Name SCICLK C1h 7 Smart Card Frequency Prescaler Register Note: 6 5 4 3 XTSCS(1) 2 1 0 1 0 SCICLK5-0 1. Only for AT8xC5122 Table 19. DC/DC SFRs Mnemonic Add Name DCCKPS BFh DC/DC Converter Reload Register 7 6 MODE OVFADJ 7 6 5 4 3 2 BOOST[1-0] DCCKPS3-0 Table 20. Keyboard SFRs Mnemonic Add Name KBF(1) 9Eh Keyboard Flag Register KBE(1) 9Dh Keyboard Input Enable Register KBLS(1) 9Ch Keyboard Level Selector Register Note: 5 4 3 2 1 0 KBE7 - 0 KBF7 - 0 KBLS7 - 0 1. Only for AT8xC5122 Table 21. SPI SFRs Mnemonic SPCON (1) Add Name 7 6 5 4 3 2 1 0 C3h Serial Peripheral Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 Serial Peripheral StatusControl SPIF WCOL SPSTA(1) C4h SPDAT(1) C5h Serial Peripheral Data Notes: MODF R7 - 0 1. Only for AT8xC5122 Table 22. USB SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 USBCON BCh USB Global Control USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN USBADDR C6h USB Address USBINT BDh USB Global Interrupt USBIEN BEh UEPNUM C7h USB Endpoint Number UEPCONX D4h USB Endpoint X Control EPEN NAKIEN NAKOUT NAKIN DTGL EPDIR EPTYPE1 EPTYPE0 UEPSTAX CEh USB Endpoint X Status DIR RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP RXOUTB0 TXCMP UEPRST D5h USB Endpoint Reset EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST UEPINT F8h USB Endpoint Interrupt EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT FEN UADD6-0 WUPCPU USB Global Interrupt Enable EORINT EWUPCPU EEORINT SOFINT SPINT ESOFINT ESPINT EPNUM3-0 37 4202F–SCR–07/2008 Table 22. USB SFRs Mnemonic Add Name 7 UEPIEN C2h UEPDATX CFh USB Endpoint X Fifo Data UBYCTX E2h UFNUML BAh USB Frame Number Low UFNUMH BBh USB Frame Number High USB Endpoint Interrupt Enable 6 5 4 3 2 1 0 EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE FDAT7 - 0 USB Byte Counter Low BYCT6-0 (EPX) FNUM7 - 0 CRCOK CRCERR 5 4 FNUM10-8 Table 23. LED SFRs Mnemonic Add Name LEDCON0 F1h LED Control 0 LEDCON1(1) E1h LED Control 1 7 LED3 Note: 38 6 3 2 1 0 LED2 LED1 LED0 LED6 LED5 LED4 1. Only for AT8xC5122 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Clock Controller The clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the CPU core and peripherals are generated by this controller. On-Chip Oscillator The on-chip oscillator is composed of a single-stage inverter and a parallel feedback resistor. The XTAL1 and XTAL2 pins are respectively the input and the output of the inverter, which can be configured with off-chip components as a Pierce oscillator (see Figure 15). The on-chip oscillator has been designed and optimized to work with an external 8 MHz crystal and very few load capacitance. Then external load capacitors are not needed given that : – the internal capacitance of the microcontroller and the stray capacitance of circuit board are enough to ensure a stable oscillation – a very high accuracy on the oscillation frequency is not needed The circuit works on its fundamental frequency at 8 MHz. Figure 15. Oscillator Schematic Microcontroller To internal clock circuitry Feedback Resistor XTAL1 XTAL2 8 MHz C1 C2 GND GND C1 and C2 represents the internal capacitance of the microcontroller and the stray capacitance of the circuit board. It is recommended to implement the crystal as close as possible from the microcontroller package. Quartz Specification The equivalent circuit of a crystal is represented on the figure below : L1 C1 R1 C0 The Equivalent Serial Resistance R1 must be lower than 100 Ohm with a tolerance of +/- 2500 ppm only. 39 4202F–SCR–07/2008 Phase Lock Loop (PLL) PLL Description The AT83R5122, AT8xC5122/23’s PLL is used to generate internal high frequency clock synchronized with an external low-frequency. Figure 16 shows the internal structure of the PLL. The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the clock generation. When the PLL is locked, the bit PLOCK in PLLCON register is set. The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the external filter connected on PLLF pin (see Figure 17). Value of the filter components are detailed in the Section “DC Characteristics”. The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF produced by the charge pump. It generates a square wave signal: the PLL clock. The CK_PLL frequency is defined by the follwing formula: FCK_PLL = FCK_XTAL1 * (R+1) / (N+1) Figure 16. PLL Block Diagram and Symbol PLLF PLLCON.1 PLLEN N Divider CK_XTAL1 Up N3:0 PFLD CHP VREF VCO CK_PLL Down PLOCK PLLCON.0 R divider R3:0 Figure 17. PLL Filter Value PLLF 1,8 KΩ 33 pF 150 pF VSS PLL Programming 40 VSS The PLL must be programmed to work at 96 MHz frequency by means of PLLCON and PLLDIV registers. As soon as the PLL is enabled, the firmware must wait for the lock bit status to ensure that the PLL is ready. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 18. PLL Programming Flow PLL Programming Configure Dividers N3:0= xxxxb R3:0= xxxxb Enable PLL PLLEN= 1 PLL Locked? PLOCK= 1? Clock Tree Architecture The clock controller outputs several different clocks as shown in Figure 19: • a clock for the CPU core • a clock for the peripherals which is used to generate the timers, watchdog, SPI, UART, and ports sampling clocks. This divided clock will be used to generate the alternate card clock. • a clock for the USB • a clock for the SCIB controller • a clock for the DC/DC converter These clocks are enabled or not depending on the power reduction mode as detailed in Section “Power Management”, page 178. These clocks are generated using four presacalers defined in the table below: Prescaler Register Reload Factor Function PR1 CKRL CKRL[0:3] CPU & Peripheral clocks PR2 SCICLK SCICLK[0:5] Smart card PR3 SCSR ALTKPS[0:1] Alternate card PR4 DCCKPS DCCKPS[3:0] DC/DC 41 4202F–SCR–07/2008 Figure 19. Clock Tree Diagram CK_DCDC PR4 DC/DC Converter DCCKPS[3:0] CKCON0.X or CKCON1.0 PeriphX2 CKCON0.0 Peripherals X2 1 1/2 CK_XTAL1 CK_PLL 0 1 PERIPH = T0, T1, SI, WD or SPI 0 1 PR1 0 CKRL[3:0] 1 CPU PLL 96 MHz XTAL2 IDL X2 PCON.0 CKCON0.0 CK_XTAL1 CK_CPU CK_IDLE CKS CKSEL.0 XTAL1 CK_PERIPH 0 CK_T0 CK_T1 CK_SI CK_WD CK_SPI Alternate Card PR3 CK_PLL SCSR[3:2] PLLEN CK_PLL PLLCON.1 CK_XTAL1 CK_IDLE 0 PR2 1 SCICLK[5:0] PD <48 CK_ISO SCIB =48 PCON.1 SCICLK[5:0] XTSCS SCICLK.7 EXT48 PLLCON.2 CK_IDLE 1/2 0 CK_XTAL1 CPU and Peripheral Clocks CK_USB USB 1 Two clocks sources are available for CPU and peripherals: – on-chip oscillator – a derivative of the PLL clock. These clock sources are configured by the PR1 prescaler to generate the CPU core CK_CPU and the peripheral clocks: 42 – CK_IDLE for alternate card and peripherals registers access – CK_T0 for Timer 0 – CK_T1 for Timer 1 – CK_SI for the UART – CK_WD for the Watchdog Timer – CK_SPI for SPI AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 The CPU and peripherals clocks frequencies are defined in the table below. X1 and X2 Modes CKS X2 FCK_IDLE 0 0 FCK_XTAL1/(2*(16-CKRL)) 0 1 FCK_XTAL1 1 0 FCK_PLL/(2*(16-CKRL)) 1 1 Not allowed Use of on-chip oscillator When the CPU and Peripherals clocks are fed by the on-chip oscillator, the CPU and Peripherals can be configured independently in X1 or X2 mode depending on the frequencies wanted by the user. There is however one exception : the periperals can be configured in X2 mode while the CPU remains in X1 mode. This exception is handled by the hardware and the user does not need to take care of. Table 1. X1 and X2 Mode Selection CPU Peripherals X1 mode X1 mode X1 mode X2 mode Status Frequenci Allowed (default configuration at reset) FCK_IDLE = FCK_PERIPH Not Allowed by the hardware Allowed X2 mode X1 mode X2 mode X2 mode Once the CPU is switched to X2 mode, the user is free to switch any of the peripherals to X1 mode FCK_IDLE = 2*FCK_PERIPH Allowed Default configuration when CPU is switched to X2 mode FCK_IDLE = FCK_PERIPH The X1 or X2 modes can be individually selected for the CPU and each peripheral by means of CKCON0 and CKCON1 registers. At reset, the CPU and Peripherals are set all by default to X1 mode. In this mode, changing any peripheral to X2 mode has no effect. When X2 bit is set in CKCON0 register, CPU and All peripherals are automatically switched to X2 mode. It is then possible for the user to individually switch any peripheral back to X1 mode. In X1 mode (X2 bit cleared in CKCON0 regsiter), the PR1 prescaler is active while it is bypassed in X2 mode (X2 bit set in CKCON0 register). The X1 mode is true only when the prescaler PR1 is set to 1/2 (default condition at reset). 43 4202F–SCR–07/2008 Figure 20. X1 mode Crystal PR1 prescaler 8 MHz 1/2 CPU frequency 4 MHz Peripheral frequency 4 MHz When the X1 mode is selected, the CPU and Peripherals work at 8Mhz / X1 Figure 21. X2 mode CPU frequency (X2 Mode) Crystal 8 MHz 8 MHz Peripheral frequency (X2 mode) 8 MHz Internal Prescaler 1/2 Peripheral frequency (X1 mode) 4 MHz When the X2 mode is selected, the CPU works at 8 MHz / X2. The Peripherals can work at 8 MHz / X2 or 8 MHz / X1. When the PR1 prescaler is different from 1/2, the usual X1 mode can not be defined. In this case, it is necessary to define a X1 or X2 equivalent mode from equivalent clock circuits. Example : PR1=1/8, X2=0. In this configuration, the CPU works at 1 MHz. This frequency could also be obtained by an equivalent clock circuit where the on-chip oscillator would run at 2 MHz in X1 mode or at 1 MHz in X2 mode. So we can say that the CPU works at 2 MHz / X1 or 1MHz / X2. As the X2 bit is cleared in CKCON0 register, we have FCK_IDLE = FCK_PERIPH. 44 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Crystal 8 MHz PR1 Prescaler CPU frequency 1/8 1 MHz PERIPH frequency 1 MHz (Equivalent to) External Clock 2 MHz X1 mode selected CPU frequency 1/2 1 MHz PERIPH frequency 1 MHz (Equivalent to) External Clock 1 MHz X2 mode selected CPU frequency 1 MHz PERIPH frequency 1 MHz Use of PLL Clock When the CPU clock is fed by the PLL, the X2 mode is forbidden. The bit X2 must always remain cleared in CKCON0 register. As the PR1 prescaler is always different from 1/2, the usual X1 mode can not be defined. So it is necessary to define an equivalent X1 or X2 mode from equivalent clock circuits, as in previous section. Example: PR1=1/4, PLL feeds the CPU. The CPU works in this case at 24 MHz. This frequency could also be obtained by an equivalent clock circuit where the on-chip oscillator would run at 48 MHz in X1 mode or at 24 Mhz in X2 mode. So we can say that in this configuration, the CPU works at 48 MHz / X1 or 24 MHz / X2 (See figures below). As the X2 bit is cleared in CKCON0 register, we have always FCK_IDLE = FCK_PERIPH. 45 4202F–SCR–07/2008 PLL Prescaler CPU frequency 1/4 96 MHz 24 MHz PERIPH frequency 24 MHz (Equivalent to) External Clock X1 mode selected CPU frequency 1/2 48 MHz 24 MHz PERIPH frequency 24 MHz (Equivalent to) External Clock 24 MHz X2 mode selected CPU frequency 24 MHz PERIPH frequency 24 MHz SCIB Clock The Smart Card Interface Block (SCIB) uses two clocks : – The first one, CK_IDLE, is the peripheral clock used for the interface with the microcontroller. – The second one, CK_ISO, is independant from the CPU clock and is generated from the PLL or XTAL1 output. PR2, a 6-bit prescaler, will be used to generate: 12/9.6/8/6.85/6/5.33/4.8/4.36/ ..../1MHz frequencies. SCIB clock frequency must be lower than CPU clock frequency. During SCIB Reset, the CK_ISO input must be in the range 1 - 5 MHz according to ISO 7816. The SCIB clocks frequency is defined in Figure 41 on page 72 and Table 42 on page 72. Two conditions must be met for a correct use of the SCIB: 46 • CK_CPU > 4/3 * CK_ISO and • CK_CPU < 6 * CK_ISO. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 If the CK_CPU <= 4/3 * CK_ISO, the SCIB doesn’t work. If the CK_CPU >= 6* CK_ISO, the programmer must take care of three cases: • Read (or write) operation on a SCIB register followed immediatly with an other Read (or write) operation on the same register. • Read (or write) operation on a SCIB register followed immediatly with an other Read (or write) operation on a linked register. The list of linked registers is in the table below. Linked registers Write in SCICR and after read of SCETU0-1 Write in SCIBUF and after read of SCISR • Write operation on a register of the list below followed immediatly with a read operation on a SCIB register. Wait after Write operation on this registers SCICR, SCIER, SCETU0-1,SCGT0-1, SCWT0-3,SCCON To avoid any trouble, a delay must be added between the two accesses on the SCIB register. The SCIB must complete the first read (or write) operation before to receive the second. A solution is to add NOP (no operation) instructions. The number of NOP to add depends of the rate between CK_CPU and CK_ISO (see table below). Min CLK_CPU Max CLK_CPU Number of CPU cycles to add CLK_CPU >= 6 * CLK_ISO CLK_CPU <= 12 * CLK_ISO 6 ( example1 NOP) CLK_CPU >= 12* CLK_ISO CLK_CPU <= 16 * CLK_ISO 12 ( example 2 NOP) Alternate Card Clock The alternate Card uses the peripheral clock divided by the PR3 prescaler. (1; 1/2; 1/4; 1/8 division ratio). See Section "Alternate Card", page 76 for the definition of the alternate clock. DC/DC Converter Clock The DC/DC block needs a clock with a 50% duty cycle. The frequency must also be included in the range 3.68 MHz and 6 MHz. The PR4 prescaler is used to configure the DC/DC frequency. XTAL1 (MHz) DCCKPS3:0 value Prescaler Factor DC/DC converter CLK (MHz) 8 0 2 4 47 4202F–SCR–07/2008 USB Interface Clock The USB Interface uses two clocks : – The first one is the CPU clock used for the interface with the microcontroller, CK_IDLE. – The second one is the CK_USB supplied from the PLL through a divider by 2. Registers Table 24. Clock Selection Register - CKSEL (S:85h) 7 6 5 4 3 2 1 0 - - - - - - - CKS Bit Number Bit Mnemonic Description 7:1 - 0 CKS Reserved The value read from this bit is indeterminate. Do not set this bit. CPU Oscillator Select Bit Set this bit to connect CPU and Peripherals to PLL output. Clear this to to connect CPU and Peripherals to XTAL1 clock input. Reset Value = XXXX XXX0b Table 25. Clock Reload Register - CKRL (S:97h) 7 6 5 4 3 2 1 0 - - - - CKRL3 CKRL2 CKRL1 CKRL0 Bit Number Bit Mnemonic Description 7-4 - 3:0 CKRL3:0 Reserved The value read from this bit is indeterminate. Do not set this bit. Clock Reload register Prescaler1 value Fck_cpu =[ 1 / 2*(16-CKRL)] * Fck_XTAL1 Reset Value = XXXX 1111b 48 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 26. Clock Configuration Register 0 - CKCON0 (S:8Fh) 7 6 5 4 3 2 1 0 - WDX2 - SIX2 - T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. Watchdog clock 6 WDX2 This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. Enhanced UART clock (Mode 0 and 2) 4 SIX2 This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 1 clock 2 T1X2 This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. Timer 0 clock 1 T0X2 This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. System clock Control bit 0 X2 Cleared to select the PRT output for CPU and all the peripherals . Set to bypass the PRT prescaler and to enable the individual peripherals ‘X2’ bits. Reset Value = X0X0 X000b 49 4202F–SCR–07/2008 Table 27. Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122 7 6 5 4 3 2 1 0 - - - - - - - SPIX2 Bit Number Bit Mnemonic Description 7-4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. SPI clock 0 SPIX2 This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Cleared to bypass the 1/2 prescaler. Set to select the 1/2 output for this peripheral. Reset Value = XXXX XXX0b Table 28. PLL Control Register - PLLCON (S:A3h) 7 6 5 4 3 2 1 0 - - - - - EXT48 PLLEN PLOCK Bit Number Bit Mnemonic Description 7-3 - Reserved The value read from these bits is always 0. Do not set this bits. External 48 MHz Enable Bit 2 EXT48 Set this bit to select XTAL1 as USB clock. Clear this bit to select PLL as USB clock. SCIB clock is controlled by EXT48 bit and XTSCS bit. PLL Enable bit 1 PLLEN Set to enable the PLL. Clear to disable the PLL. PLL Lock Indicator 0 PLOCK Set by hardware when PLL is locked Clear by hardware when PLL is unlocked Reset Value = 0000 0000b Table 29. PLL Divider Register - PLLDIV (S:A4h) 7 6 5 4 3 2 1 0 R3 R2 R1 R0 N3 N2 N1 N0 Bit Number Bit Mnemonic Description 7-4 R3:0 PLL R Divider Bits 3-0 N3:0 PLL N Divider Bits Reset Value = 0000 0000b 50 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 I/O Port Definition Ports vs Packages Port 0 Table 30. I/O Number vs Packages P0 P1 P2 P3 P4 P5 Total VQFP64 QFN64 8 8 8 8 6 8 46 VQFP32 QFN32 - 8 - 8 - 1 17 PLCC28 - 6 - 6 - 1 13 Port 0 has the following functions: – Default function: Port 0 is an 8-bit I/O port. – Alternate function: Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application, it uses strong internal pull-ups when emitting 1’s and it can drive CMOS inputs without external pull-ups. Port 0 has the following configurations: – Default configuration: open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state they can be used as highimpedance inputs. – Configuration 2: Low speed output, “KB_OUT” – Configuration 3: Push-pull output 51 4202F–SCR–07/2008 Port 1 has the following functions: Port 1 – Default function : Only Port 1.2, P1.6 and P1.7 are standard I/O’s; the other ports can be activated only with the SCIB function. – Alternate function and configuration: see Table 31. Table 31. Port 1 Description. Port Alternate Function Configuration Signal Description Mode Smart card interface function Quasi-bidirectional port supplied by DC/DC converter CIO CC8 P1.2 CPRES CC4 CCLK CRST P1.6 SS Card I/O Smart card interface function Card contact 8 Smart card interface function Card presence Smart card interface function Card contact 4 Quasi-bidirectional port supplied by DC/DC converter CCLK1 Quasi-bidirectional port supplied by DC/DC converter Caution : if DPU bit is set in AUXR register, the weak-pull of the port is disabled Low level at reset Caution : if DPU bit is set in AUXR register, the weak-pull of the port is disabled Low level at reset Caution : if DPU bit is set in AUXR register, the weak-pull of the port is disabled Push-Pull port supplied by DC/DC converter Low level at reset Card reset Push-Pull port supplied by DC/DC converter Low level at reset SS pin of the SPI function Quasi-bidirectional supplied by VCC Smart card interface function Card clock Smart card interface function Alternate Card Clock function disabled Alternate Smart Card Clock enabled Alternate Card Clock output Quasi-bidirectional supplied by VCC Port 2 Low level at reset. Weak & medium pull-up’s can be disconnected Quasi-bidirectional port supplied by VCC by CPRESRES bit in PMOD0 regsiter High Level at reset Quasi-bidirectional supplied by VCC P1.7 Comments Switched automatically to Push-pull (see Table 47 on page 80 ) Port 2 has the following functions: – Default function: Port 2 is an 8-bit I/O port. – Alternate function 1: Port 2 is also the multiplexed high-order address during accesses to external Program and Data Memory. In this application, it uses strong internal pull-ups when emitting 1’s and it can drive CMOS inputs without external pull-ups. Port 2 has the following configurations: 52 – Default configuration: Pseudo bi-directional “Port51” digital input/output with internal pull-ups. – Configuration 1: Push-pull output – Configuration 2: Low speed output, “KB_OUT – Configuration 3: Input with weak pull-up, “WPU input” AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Port 3 has the following functions: Port 3 – Default function: Port 3 is an 8-bit I/O port. – Alternate functions: see table below Port 3 has the following configurations: – Default configuration: Pseudo bi-directional “Port51” digital input/output with internal pull-ups. – Alternate configurations: See Table 32. Table 32. Port 3 Description Alternate Functions Configurations Port Signal Description Mode 1 Mode 2 Mode 3 Mode 4 P3.0 RxD Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface Push-pull KB_OUT Input WPU P3.1 TxD Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface Push-pull KB_OUT Input WPU P3.2 INT0 External interrupt 0 input/timer 0 gate control input P3.3 INT1 External interrupt 1input/timer 1 gate control input Push-pull KB_OUT Input WPU P3.4 T0 Timer 0 counter input Push-pull KB_OUT Input WPU P3.5 T1 Timer 1 counter input P3.6 WR External Data Memory write strobe; latches the data byte from port 0 into the external data memory LED2 P3.7 RD External Data Memory read strobe; Enables the external data memory. Port 3 can drive CMOS inputs without external pull-ups LED3 LED0 LED1 53 4202F–SCR–07/2008 Port 4 Port 4 has the following functions: – Default function: Port 4 is an 6-bit I/O port. – Alternate functions: see table below Port 4 has the following configurations: – Default configuration: Pseudo bi-directional “Port51” digital input/output with internal pull-ups. – Alternate configurations: See Table 33. Table 33. Port 4 Description Alternate Functions Port 5 Configurations Port Signal Description Mode 1 Mode 2 Mode 3 P4.0 MISO SPI Master In Slave Out I/O P4.1 MOSI SPI Master Out Slave In I/O P4.2 SCK SPI clock P4.3 Push-pull KB_OUT Input MPU P4.4 Push-pull KB_OUT Input MPU P4.5 Push-pull KB_OUT Input MPU Port 5 has the following functions: – Default function: Port 5 is an 8-bit I/O port. – Alternate function 1: Port 5 is an 8-bit keyboard port KB0 to KB7. Port 5 has the following configurations: – Default configuration: Pseudo bi-directional “Port51” digital input/output with internal pull-ups. – Alternate configuration: see Table 34. Table 34. Port 5 Description Configurations 54 Port Mode 1 Mode 2 Mode 3 P5.0 Push-pull Input MPU Input WPU P5.1 Push-pull Input MPU Input WPU P5.2 Push-pull Input MPU Input WPU P5.3 Push-pull Input WPD Input WPU P5.4 Push-pull Input WPD Input WPU P5.5 Push-pull Input WPD Input WPU P5.6 Push-pull Input WPD Input WPU P5.7 Push-pull Input WPD Input WPU Comments First cluster Second cluster Third cluster AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Port Configuration Standard I/O P0 The P0 port is described in Figure 22. Figure 22. Standard Input/Output Port ADDR/DATA CONTROL Vcc PMOS 1 Port latch Data NMOS Pin 0 MUX Vss Input Data Quasi Bi-directional Port The default port output configuration for standard I/O ports is the quasi-bi-directional output that is common on the 80C51 and most of its derivatives. The “Port51” output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the port outputs a logic low state, it is driven strongly and is able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bi-directional output that serve different purposes. One of these pull-ups, called the weak pull-up, is turned on whenever the port latch for the pin contains a logic 1. The weak pull-up sources a very small current that will pull the pin high if it is left floating. The weak pull-up can be turned off by the DPU bit in AUXR register. A second pull-up, called the medium pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bi-directional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external device, the medium pull-up turns off, and only the weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the medium pull-up and take the voltage on the port pin below its input threshold. Note: for CIO, CC4, CC8 ports of SCIB interface , in input mode when the ICC (smart card) is driving the port pin : – if 0 < Vin < CVCC/2 : weak pull-up is active (~100KOhm) – if CVCC/2 < Vin < CVCC : weak (~100KOhm) and medium (~12KOhm) pullup’s are active 55 4202F–SCR–07/2008 The “Port51” is described in Figure 23. Figure 23. Quasi Bi-directional Port DPU (AUXR.7) 2 CPU CLOCK DELAY vcc P Strong Port Latch Data vcc vcc P P Weak Medium Pin N Vss Input Data Push-pull Output Configuration The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bi-directional output modes, but provides a continuous strong pullup when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. The Push-pull port configuration is shown in Figure 24. Figure 24. Push-pull Output P PMOS Strong Pin Port latch Data Input with Medium or Weak Pull-up Configuration 56 N NMOS The input with pull-up (Input MPU and Input WPU) configuration is shown in Figure 25. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 25. Input with Pull-up P Stuck to 0 if Medium Medium P Stuck to 0 if Weak Weak Input Data Pin Input with Weak Pull-down Configuration The input with pull-down (input WPD) configuration is shown in Figure 26 Figure 26. Input with Pull-down Input Data N 1 Low Speed Output Configuration Pin Weak The low speed output with low speed tFALL and tRISE can drive keyboard. The current limitation of the LED2CTRL block requires a polarisation current of about 250 μA. This block is automatically disabled in power-down mode. The low speed output configuration (KB_OUT) is shown in Figure 27. Figure 27. Low-speed Output PWEAKCTRL P Weak Pin Port latch Data PCON.1 LED Source Current NMOS LED2CTRL N N The LED configuration is shown in Figure 28. 57 4202F–SCR–07/2008 Figure 28. LED Source Current Pin NMOS N LEDx.0 N Port Latch Data LEDx.1 Notes: LEDCTRL 1. When switching a low level, LEDCTRL device has a permanent current of about N mA/15 (N is 2, 4 or 8). 2. The port must be configured as standard C51 port by means of PMOD0 and PMOD1 registers and the level of current must be programmed by means of LEDCON0 and LEDCON1 registers before switching the led on. Table 35. LED Source Current LEDx.1 LEDx.0 Port Latch Data NMOS PIN 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 1 0 1 Comments LED control disabled LED mode 2 mA LED mode 4 mA LED mode 10 mA 58 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Registers Table 36. Port Mode Register 0 - PMOD0 (91h) for AT8xC5122 7 6 5 4 3 2 1 0 P3C1 P3C0 P2C1 P2C0 CPRESRES - P0C1 P0C0 Bit Number Bit Mnemonic Description Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only) 00 Quasi bi-directional 7-6 P3C1-P3C0 01 Push-pull 10 Output Low Speed 11 Input with weak pull-up Port 2 Configuration bits 00 Quasi bi-directional 5-4 P2C1-P2C0 01 Push-pull 10 Output Low Speed 11 Input with weak pull-down Card Presence Pull-up resistor 3 CPRESRES Cleared to connect the internal 100K pull-up Set to disconnect the internal pull-up 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. Port 0 Configuration bits 00 C51 Standard P0 1-0 P0C1-P0C0 01 Reserved 10 Output Low Speed 11 Push-pull Reset Value = 0000 0x00b Table 37. Port Mode Register 0 - PMOD0 (91h) for AT83C5123 7 6 5 4 3 2 1 0 P3C1 P3C0 - - CPRESRES - - - Bit Number Bit Mnemonic Description Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only) 00 Quasi bi-directional 7-6 P3C1-P3C0 01 Push-pull 10 Output Low Speed 11 Input with weak pull-up Reserved The value read from these bits are indeterminate. Do not set these bit. 5-4 Card Presence Pull-up resistor 3 CPRESRES Cleared to connect the internal 100K pull-up Set to disconnect the internal pull-up 2-0 - Reserved The value read from these bits are indeterminate. Do not set these bit. Reset Value = 00xx 0xxxb 59 4202F–SCR–07/2008 Table 38. Port Mode Register 1 - PMOD1 (84h) for AT8xC5122 7 6 5 4 3 2 1 0 P5HC1 P5HC0 P5MC1 P5MC0 P5LC1 P5LC0 P4C1 P4C0 Bit Number Bit Mnemonic Description Port 5 High Configuration bits (Applicable from P5.6 to P5.7 only) 00 Quasi bi-directional 7-6 P5HC1-P5HC0 01 Push-pull 10 Input with weak pull-down 11 Input with weak pull-up Port 5 Medium Configuration bits (Applicable from P5.3 to P5.5 only) 00 Quasi bi-directional 5-4 P5MC1-P5MC0 01 Push-pull 10 Input with weak pull-down 11 Input with weak pull-up Port 5 Low Configuration bits (Applicable from P5.0 to P5.2 only) 00 Quasi bi-directional 3-2 P5LC1-P5LC0 01 Push-pull 10 Input with medium pull-up 11 Input with weak pull-up Port 4 Configuration bits (Applicable from P4.3 to P4.5 only) 00 Quasi bi-directional 1-0 P4C1-P4C0 01 Push-pull 10 Output Low Speed 11 Input with medium pull-up Reset Value = 0000 0000b Table 39. Port Mode Register 1 - PMOD1 (84h) for AT83C5123 7 6 5 4 3 2 1 0 - - - - P5LC1 P5LC0 - - Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7-4 Port 5 Low Configuration bits (Applicable from P5.0 to P5.2 only) 00 Quasi bi-directional 3-2 P5LC1-P5LC0 01 Push-pull 10 Input with medium pull-up 11 Input with weak pull-up 1-0 Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = xxxx 00xxb 60 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 40. LED Port Control Register 0 - LEDCON0 (F1h) 7 6 5 4 3 2 1 0 LED3.1 LED3.0 LED2.1 LED2.0 LED1.1 LED1.0 LED0.1 LED0.0 Bit Number Bit Mnemonic Description Port LED3 Configuration bits 7-6 LED3 00 01 10 11 LED control disabled 2 mA current source when P3.7 is configured as Quasi-bi-directional mode 4 mA current source when P3.7 is configured as Quasi-bi-directional mode 10 mA current source when P3.7 is configured as Quasi-bidirect. mode Port LED2 Configuration bits 5-4 LED2 00 01 10 11 LED control disabled 2 mA current source when P3.6 is configured as Quasi-bi-directional mode 4 mA current source when P3.6 is configured as Quasi-bi-directional mode 10 mA current source when P3.6 is configured as Quasi-bidirect. mode Port LED1 Configuration bits 3-2 LED1 00 01 10 11 LED control disabled 2 mA current source when P3.4 is configured as Quasi-bi-directional mode 4 mA current source when P3.4 is configured as Quasi-bi-directional mode 10 mA current source when P3.4 is configured as Quasi-bidirect. mode Port LED0 Configuration bits 1-0 LED0 00 01 10 11 LED control disabled 2 mA current source when P3.2 is configured as Quasi-bi-directional mode 4 mA current source when P3.2 is configured as Quasi-bi-directional mode 10 mA current source when P3.2 is configured as Quasi-bidirect. mode Reset Value = 0000 0000b Table 41. LED Port Control Register 1- LEDCON1 (F1h) only for AT8xC5122 7 6 5 4 3 2 1 0 - - LED6.1 LED6.0 LED5.1 LED5.0 LED4.1 LED4.0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7-6 Port LED6 Configuration bits 5-4 LED6 00 01 10 11 LED control disabled 2 mA current source when P4.5 is configured as Quasi-bi-directional mode 4 mA current source when P4.5 is configured as Quasi-bi-directional mode 10 mA current source when P4.5 is configured as Quasi-bidirect. mode Port LED5 Configuration bits 3-2 LED5 00 01 10 11 LED control disabled 2 mA current source when P4.4 is configured as Quasi-bi-directional mode 4 mA current source when P4.4 is configured as Quasi-bi-directional mode 10 mA current source when P4.4 is configured as Quasi-bidirect. mode Port LED0 Configuration bits 1-0 LED4 00 01 10 11 LED control disabled 2 mA current source when P4.3 is configured as Quasi-bi-directional mode 4 mA current source when P4.3 is configured as Quasi-bi-directional mode 10 mA current source when P4.3 is configured as Quasi-bidirect. mode Reset Value = 0000 0000b 61 4202F–SCR–07/2008 Smart Card Interface Block (SCIB) The SCIB provides all signals to interface directly with a smart card. The compliance with the ISO7816, EMV’2000, GSM and WHQL standards has been certified. Both synchronous (e.g. memory card) and asynchronous smart cards (e.g. microprocessor card) are supported. The component supplies the different voltages requested by the smart card. The power off sequence is directly managed by the SCIB. The card presence switch of the smart card connector is used to detect card insertion or card removal. In case of card removal, the SCIB de-activates the smart card using the de-activation sequence. An interrupt can be generated when a card is inserted or removed. Any malfunction is reported to the microcontroller (interrupt + control register). The different operating modes are configured by internal registers. • 62 Support of ISO/IEC 7816 • character mode • one transmit/receive buffer • 11 bits ETU counter • 9 bits guard time counter • 32 bits waiting time counter • Auto character repetition on error signal detection in transmit mode • Auto error signal generation on parity error detection in receive mode • Power on and power off sequence generation • Manual mode to drive directly the card I/O AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Block Diagram The Smart Card Interface Block diagram is shown Figure 29: Figure 29. SCIB Block Diagram Barrel shifter IO (in) Clk_iso IO (out) Clk_cpu CLK I/O mux Etu counter Guard time counter Scart fsm Waiting time counter RST C4 (out) C8 (out) C4 (in) SCI Registers C8 (in) INT Interrupt generator Power on Power off VCARD fsm Definitions This paragraph introduces some of the terms used in ISO 7816-3 and EMV recommendations. Please refer to the full recommendations for a complete list of terms. Terminal and ICC Terminal is the reader, ICC is the Integrated Circuit Card ETU Elementary Timing Unit (Bit time) T=0 Character oriented half duplex protocol T=0 T=1 Block oriented half duplex protocol T=1 Activation: Cold Reset Reset initiated by the Terminal with Vcc power-up. The card will answer with ATR (see below) Activation: Warm Reset Reset initiated by the Terminal with Vcc already powered-up, and after a prior ATR or Warm Reset De-Activation Deactivation by the Terminal as a result of : unresponsive ICC, or ICC removal. 63 4202F–SCR–07/2008 ATR Answer To Reset. Response from the ICC to a Reset initiated by the Terminal F and D F = Clock Rate Conversion Factor, D = Bit rate adjustment factor. ETU is defined as : ETU = F/(D*f) with f = Card Clock frequency. If f is in Hertz, ETU is in second. F and D are available in the ATR (byte TA1). The default values are F=372, D=1. Guard Time The time between 2 leading edges of the start bit of 2 consecutive characters is comprised of the character duration (10) plus the guard time. Be aware that the Guard Time counter and the Guard Time registers in the AT8xC5122/23 consider the time between 2 consecutive characters. So the equation is Guard Time Counter = Guard Time + 10. In other words, the Guard Time is the number of Stop Bits between 2 characters sent in the same direction. Extra Guard Time ISO IEC 7816-3 and EMV introduce the Extra Guard time to be added to the minimum Guard Time. Extra Guard Time only apply to consecutive characters sent by the terminal to the ICC. The TC1 byte in the ATR define the number N. For N=0 the character to character duration is 12 ETUs. For N=254 the character to character duration is 266. For N=255 (special case) The minimum character to character duration is to be used : 12 for T=0 protocol and 11 for T=1 protocol. Block Guard Time The time between the leading edges of 2 consecutive characters sent in opposit direction. ISO IEC 7816-3 and EMV recommend a fixed Block Guard Time of 22 ETUs. Work Waiting Time (WWT) In T=0 protocol WWT is the interval between the leading edge of any character sent by the ICC, and the leading edge of the previous character sent either by the ICC or the Terminal. If no character is received by the terminal after WWTmax time, the Terminal initiates a De-Activation Sequence. Character Waiting Time (CWT) In T=1 protocol CWT is the interval between the leading edge of 2 consecutive characters sent by the ICC. If the next character is not received by the Terminal after CWTmax time, the Terminal initiates a De-Activation Sequence. Block Waiting Time (BWT) In T=1 protocol BWT is the interval between the leading edge of the start bit of the last character sent by the Terminal that gives the right to sent to the ICC, and the leading edge of the start bit of the first character sent by the ICC. If the first character from the ICC is not received by the Terminal after BWTmax time, the Terminal initiates a De-Activation Sequence. Waiting Time Extention (WTX) In T=1 protocol the ICC can request a Waiting Time Extension with a S(WTX request) request. The Terminal should acknowlege it. The Waiting time between the leading edge of the start bit of the last character sent by the Terminal that gives the right to sent to the ICC, and the leading edge of the start bit of the first character sent by the ICC will be BWT*WTX ETUs. Parity error in T=0 protocol In T=0 protocol, a Terminal (respectively an ICC) detecting a parity error while receiving a character shall force the Card IO line at 0 starting at 10.5 ETUs, thus reducing the first Guard bit by half the time. The Terminal (respectively an ICC) shall maintain a 0 for 1 ETU min and 2 ETUs max (according to ISO IEC) or to 2 ETUs (according to EMV). The ICC (respectively a Terminal) shall monitor the Card IO to detect this error signal then attempt to repeat the character. According to EMV, following a parity error the character can be repeated one time, if parity error is detected again this procedure can be repeated 3 more times. The same character can be transmitted 5 times in total. ISO 64 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 IEC7816-3 says this procedure is mandatory in ATR for card supporting T=0 while EMV says this procedure is mandatory for T=0 but does not apply for ATR. Functional Description The architecture of the Smart Card Interface Block can be detailed as follows: Barrel Shifter The Barrel Shifter performs the translation between 1 bit serial data and 8 bits parallel data The barrel function is useful for character repetition since the character is still present in the shifter at the end of the character transmission. This shifter is able to shift the data in both directions and to invert the input or output value in order to manage both direct and inverse ISO7816-3 convention. Coupled with the barrel shifter is a parity checker and generator. There are 2 registers connected to this barrel shifter, one for the transmission and one for the reception. They act as buffers to relieve the CPU of timing constraints. SCART FSM (Smart Card Asynchronous Receiver Transmitter Finite State Machine) This is the core of the block. Its purpose is to control the barrel shifter. To sequence correctly the barrel shifter for a reception or a transmission, it uses the signals issued by the different counters. One of the most important counters is the guard time counter that gives time slots corresponding to the character frame. The SCART FSM is enabled only in UART mode. The transition from the receipt mode to the transmit mode is done automatically. Priority is given to the transmission. Transmission refers to Terminal transmission to the ICC. Reception refers to reception by the Terminal from the ICC. ETU Counter The ETU (Elementary Timing Unit) counter controls the working frequency of the barrel shifter, in fact it generates the enable signal of the barrel shifter. It receives the Card Clock, and generates the ETU clock. The Card Clock frequency is called “f” below. The ETU counter is 11 bit wide. A special compensation mode can be activated. It accomodates situations where the ETU is not an integer number of Card Clock (CK_ISO). The compensation mode is controlled by the COMP bit in SCETU1 register bit position 7. With COMP=1 the ETU of every character even bits is reduced by 1 Card Clock period. As a result, the average ETU is : ETU_average = (ETU - 0.5). One should bear in mind that the ETU counter should be programmed to deliver a faster ETU which will be reduced by the COMP mechanism, not the other way around. This allows to reach the required precision of the character duration specified by the ISO7816-3 standard. Example1 : F=372, D=32 => ETU= F/D = 11.625 clock cycles. We select ETU[10-0] = 12 , COMP=1. ETUaverage= 12 - (0.5*COMP) = 11.5 The result will be a full character duration (10 bit) = (10 - 0.107)*ETU. The EMV specification is (10 +/- 0.2)*ETU Guard Time Counter The minimum time between the leading edge of the start bit of 2 consecutive characters transmitted by the Terminal is controlled by the Guard Time counter, as described in Figure 32. 65 4202F–SCR–07/2008 The Guard Time counter is an 9 bit counter It is initialized at 001h at the start of a transmission by the Terminal. It then increments itself at each ETU until it reach the 9 bit value loaded into the SCGT1[0] concatenated with SCGT0[7:0]. At this time a new Terminal transmission is enabled and the Guard Time Counter stop incrementing. As soon as a new transmission start, the Guard Time Counter is re-initialized at 1 decimal value. It should be noted that the value of the Guard Time Counter cannot be red. Reading SCGT1,0 only gives the minimum time between 2 characters that the Guard Time Counter will allow. Care must be taken with the Guard Time Counter which counts the duration between the leading edges of 2 consecutive characters. This correspond to the character duration (10 ETU) plus the Guard Time as defined by the ISO and EMV recommendations. To program Guard Time = 2 : 2 stop bits between 2 characters which is equivalent to the minimum delay of 12 ETUs between the leading edges of 2 consecutive characters, SCGT1[0],SCGT0[7:0] should be loaded with the value 12 decimal. See Figure 30 Figure 30. Guard Time. TRANSMISSION to ICC CHAR n+1 CHAR n+2 CHAR n+3 >= SCGT Block Guard Time Counter The Block Guard Time counter provides a way to program a minimum time between the leading edge of the start bit of a character received from the ICC and the leading edge of the start bit of a character sent by the terminal. ISO IEC 7816-3 and EMV recommend a fixed Block Guard Time of 22 ETUs. The AT8xC5122/23 offer the possibility to extend this delay up to 512 ETUs. The Block Guard Time is a 9 bit counter. When the Block Guard Time mode is enabled (BGTEN=1 in SCSR register) The Block Guard Time counter is initialized at 000h at the start of each character transmissions from the ICC. It then increments at each ETU until it reach the 9 bit value loaded into shadow SCGT1,0 registers, or until it is re-initialized by the start of an new transmission from the ICC. If the Block Guard Time counter reaches the 9 bit value loaded into shadow SCGT1,0 registers, a transmission by the TERMINAL is enabled, and the Block Guard Time counter stop incrementing. The Block Guard Time counter is re-initialized at the start of each TERMINAL transmission. The SCGT1 SCGT0 shadow registers are loaded with the content of GT[8-0] contained in the registers SCGT1[0),SCGT0(7:0] with the rising edge of the bit BGTEN in the SCSR register. See Figure 32. 66 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 31. Block Guard Time. TRANSMISSION to ICC RECEPTION from ICC Write SCGT1,0 with a value for Guard Time CHAR 1 CHAR 2 CHAR n CHAR n+1 CHAR n+2 CHAR n+3 >= SCGT >= Block Guard Time Write “Block Guard Time” in SCGT1,0 and set BGTEN to transfer the value to the shadow SCGT1,0 registers Figure 32. Guard Time and Block Guard Time counters ETU Counter Guard Time Counter Block Guard Time Counter 9 bits Enable transmit 9 bits Comparator Comparator 9 bits 9 bits Enable transmit Shadow SCGT1 ,Shadow SCGT0 GT[8:0] SCGT1 SCGT0 To illustrate the use of Guard Time and Block Guard Time, let us consider the ISO/IEC7816-3 recommendation : Guard Time = 2 (minimum delay between 2 consecutive characters sent by the Terminal = 12 ETUs), and Block Guard Time = 22 ETUs. After A smart Card Reset – Write 00decimal in SCGT1, Write 21decimal in SCGT0 – Set BGTEN in SCSR (BGTEN was 0 before as a result of the smart card reset) – Write 12decimal in SCGT0 Now the Guard Time and Block Guard Time are properly initialized. The TERMINAL will insure a minimun 12 ETUs between 2 leading edges of 2 consecutive characters transmitted. The TERMINAL will also insure a minimum of 22 ETUs between the leading edge of a character sent by the ICC, and the leading edge of a character sent by the TERMINAL. There is no need to write SCGT1,0 again and again. Waiting Time (WT) Counter The WT counter is a 32 bits down counter which can be loaded with the value contained in the SCWT3, SCWT2, SCWT1, SCWT0 registers. Its main purpose is timeout signal generation. It is 32 bits wide and is decremented at the ETU rate. see Figure 33. 67 4202F–SCR–07/2008 When the WT counter times out, an interrupt is generated and the SCIB function is locked: reception and emission are disabled. It can be enabled by resetting the macro or reloading the counter. The Waiting Time Counter can be used in T=0 protocol for the Work Waiting Time. It can be used in T=1 protocol for the Character Waiting Time and for the Block Waiting Time. See the detailed explanation below. Figure 33. Waiting Time Counter ETU Counter WTEN WT Counter Timeout Load Write_SCWT2 WT[31:0] UART Start Bit SCWT3 SCWT2 SCWT1 SCWT0 In the so called manuel mode, the counter is loaded, if WTEN = 0, during the write of SCWT2 register. The counter is loaded with a 32 bit word built with SCWT3 SCWT2 SCWT1 SCWT0 registers (SCWT0 contain WT[7-0] byte. WTEN is located in the SCICR register. When WTEN=1 and in UART mode, the counter is re-loaded at the occurence of a start bit. This mode will be detailed below in T=0 protocol and T=1 protocol. In manual mode, the WTEN signal controls the start of the counter (rising edge) and the stop of the counter (falling edge). After a timeout of the counter, a falling edge on WTEN, a reload of SCWT2 and a rising edge of WTEN are necessary to start again the counter and to release the SCIB macro. The reload of SCWT2 transfers all SCWT0, SCWT1, SCWT2 and SCWT3 registers to the WT counter. In UART mode there is an automatic load on the start bit detection. This automatic load is very useful for changing on-the-fly the timeout value since there is a register to hold the load value. This is the case for T=1 protocol. In T=0 protocol the maximun interval between the start leading edge of any character sent by the ICC and the start of the previous character sent by either the ICC or the Terminal is the maximum Work Waiting Time. The Work Waiting Time shall not exceed 960*D*WI ETUs with D and WI parameters are returned by the field TA1 and TC2 respectively in the Answer To Reset (ATR). This is the value the user shall write in the SCWT0,1,2,3 register. This value will be reloaded in the Waiting Time counter every start bit. 68 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 34. T=0 mode > GT CHAR 2 CHAR 1 < WT In T=1 protocol : The maximum interval between the leading edge of the start bit of 2 consecutive characters sent by the ICC is called maximum Character Waiting Time. The Character Waiting Time shall not exceed (2**CWI + 11) ETUs with 0 =< BWI =< 5. Consequently 12 ETUs =< CWT =< 43 ETUs. T=1 protocol also specify the maximum Block Waiting Time. This is the time between the leading edge of the last character sent by the Terminal giving the right to send to the ICC, and the leading edge of the start bit of the first character sent by the ICC. The Block Waiting Time shall not exceed (2**BWI*960 + 11) ETUs with 0 =< BWI =< 4. Consequently 971 ETUs =< BWT =< 15371 ETUs. In T=1 protocol it is possible to extend the Block Waiting Time with the Waiting Time Extension (WTX). When selected the waiting time becomes BWT*WTX ETUs. The Waiting Time counter is 32 bit wide to accomodate this feature. It is possible to take advantage of the automatic reload of the Waiting Time counter with a start bit in UART mode (T=1 protocol use UART mode) . If the Terminal sends a block of N characters, and the ICC is supposed to respond immediately after, then the following sequence can be used. While sending the (N-1)th character of the block, the Terminal can write the SCWT0,1,2,3 with BWImax. At the start bit of the Nth character, the BWImax is loaded in the Waiting Time counter During the transmission of the Nth character, the Terminal can write SCWT0,1,2,3 with the CWImax. At the start bit of the first character sent by the ICC, the CWImax will be loaded in the Waiting Time counter. Figure 35. T=1 Mode RECEPTION TRANSMISSION BLOC 2 BLOC 1 CHAR 1 CHAR 2 CHAR n CHAR n+1 < BWT CHAR n+2 CHAR n+3 < CWT 69 4202F–SCR–07/2008 Power-on and Power-off FSM The Power-on Power-off Finite State Machine (FSM) applies the signals on the smart card in accordance with ISO7816-3 standard. It conducts the Activation (Cold Reset and Warm Reset as well as De-Activation) it also manages the exception conditions such as overcurrent (see DC/DC Converter) To be able to power on the SCIB, the card presence is mandatory. Upon detectection of a card presence, the Terminal initiate a Cold Reset Activation. The Cold Reset Activation Terminal procedure is as follow and the Figure 36. Timing indications are given according to ISO IEC 7816 – RESET= Low , I/O in the receive state – Power Vcc (see DC/DC Converter) – Once Vcc is established, apply Clock at time Ta – Maintain Reset Low until time Ta+tb (tb< 400 clocks) – Monitor The I/O line for the Answer To Reset (ATR) between 400 and 40000 clock cycles after Tb. ( 400 clocks < tc < 40000clocks) Figure 36. SCIB Activation Cold Reset Sequence after a Card Insertion CVCC CRST CCLK CIO Undefined Ta Data Ta+tb Tb+tc The Warm Reset Activation Terminal procedure is as follow and the Figure 37 – Vcc active, Reset = High, CLK active – Terminal drive Reset low at time T to initiate the warm Reset. Reset=0 maintained for at least 400 clocks until time Td = T+te (400 clocks < te) – Terminal keep the IO line in receive state – Terminal drive Reset high after at least 400 clocks at time Td – ICC shall respond with an ATR within 40000 clocks (tf<40000 clocks) Figure 37. SCIB Activation Warm Reset Sequence CVCC CRST CCLK CIO Undefined T 70 Data Td=T + te Td + tf AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Removal of the smart card will automatically start the power off sequence as described in Figure 38. The SCIB deactivation sequence after a reset of the CPU or after a lost of power supply is ISO7816-3 compliant. The switching order of the signals is the same as in Figure 38 but the delay between signals is analog and not clock dependant. Figure 38. SCIB Deactivation Sequence after a Card Extraction CVCC CRST CCLK 8 Clock Cycles CIO Interrupt Generator There are several sources of interruption but the SCIB macro-cell issues only one interrupt signal: SCIBIT. Figure 39. SCIB Interrupt Sources Transmit buffer copied to shift register Output current out of range Output voltage out of range Timeout on WT counter Complete transmission Complete reception Parity error detected SCTBI ESCTBI ICARDERR ICARDER VCARDERR EVCARDER SCWTI ESCWTI SCTI ESCTI SCRI ESCRI SCPI ESCPI SCIB IT This signal is high level active. Each of the sources is able to activate the SCIB interruption which is cleared when the Smart Card Interrupt register is read by the microcontroller. If during the read of the Smart Card Interrupt register another interrupt occurs, the activation of the corresponding bit in the Smart Card Interrupt register and the new SCIB interruption is delayed until the interrupt register is read by the microcontroller. Warning : Each bit of the SCIIR register is irrelevant while the corresponding interruption is disabled in SCIER register. When the interruption mode is not used, the bits of the SCISR register must be used instead of the bits of the SCIIR register. 71 4202F–SCR–07/2008 Additional Features The CK_ISO input must be in the range 1 - 5 MHz according to ISO 7816. Clock The CK_ISO can be programmed up to 12 MHz. In this case, the timing specification of the output buffer will not comply to ISO 7816. Figure 40. Clock Diagram of the SCIB Block CK_IDLE Ck_cpu CK_PLL or CK_XTAL1 Ck_ISO PR2 SCIB Figure 41. Prescaler 2 Description PR2 CK_PLL 0 CK_XTAL1 1 1/(2*(48 - SCICLK[5-0])) XTSCS <48 CK_ISO =48 SCICLK.7 SCICLK[5:0] EXT48 PLLCON.2 The division factor SCICLK must be smaller than 49. If it is greater or equal to 49, the PR2 prescaler is locked. See Figure 17 clock tree diagram in the clock controller chapter. Table 42. Examples of Clock settings XTAL1 (MHz) EXT48 SCICLK CK_ ISO 8 0 36 4 8 0 44 12 8 0 42 8 8 0 40 6 8 0 24 2 8 0 0 1 Card Presence Input The internal pull-up (weak pull-up) on Card Presence input can be disconnected in order to reduce the consumption (CPRESRES, bit 3 in PMOD0). In this case, an external resistor (typically 1 MΩ) must be externally tied to Vcc. CPRES input can generate an interrupt (see Interrupt system section). The detection level can be selected. 72 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Transmit / Receive Buffer The contents of the SCIBUF Transmit / Receive Buffer is transferred or received into / from the Shift Register. The Shift Register is not accessible by microcontroller. Its role is to prepare the byte to be copied on the I/O pin for a transmission or in the SCIBUF buffer after a reception. During a character transmission process, as soon as the contents of the SCIBUF buffer is transferred to the shift register, the SCTBE bit is set in SCISR register to indicate that the SCIBUF buffer is empty and ready to accept a new byte. This mechanism avoids to wait for the complete transmission of the previous byte before writing a new byte in the buffer and enables to speed up the transmission. – If the Character repetition mode is not selected (bit CREP=0 in SCICR), as soon as the contents of the Shift Register is transferred to I/O pin, the SCTC bit is set in SCISR register to indicate that the byte has been transmitted. – If the Character repetition mode is selected (bit CREP=1 in SCICR) The TERMINAL will be able to repeat characters as requested by the ICC (See the Parity Error in T=0 protocol description in the definition paragraph above). The SCTC bit in SCISR register will be set after a successful transmission (no retry or no further retry requested by the ICC). If the number of retries is exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last retry is still unsuccessful, the SCTC bit in SCISR will not be set and the SCPE bit in SCISR register will be set instead. During a character reception process, the contents of the Shift Register is transferred in the SCIBUF buffer. – If the Character repetition mode is not selected (bit CREP=0 in SCICR), as soon as the contents of the Shift Register is transferred to the SCIBUF the SCRC bit is set in SCISR register to indicate that the byte has been received, and the SCIBUF contains a valid character ready to be red by the microcontroller. – If the Character repetition mode is selected (bit CREP=1 in SCICR) The TERMINAL will be able to request repetition if the received character exhibit a parity error. Up to 4 retries can be requested depending on CREPSEL bit in SCSR. The SCRC bit will be set in SCISR register after a successful reception, first reception or after retry(ies). If the number of retries is exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last retry is still unsuccessful, the SCRC bit and the SCPE bit in SCISR register will be set. It will be possible to read the erroneous character. Warning : the SCTBI, SCTI SCRI and SCPI bits have the same function as SCTBE, SCTC, SCRC and SCPE bits. The first ones are able to generate interruptions if the interruptions are enabled in SCIER register while the second ones are only status bits to be used in pulling mode. If the interruption mode is not used, the status bits must be used. The SCTBI, SCTI and SCRI bits do not contain valid information while their respective interrupt enable bits ESCTBI, EXCTI, ESCRI are cleared. 73 4202F–SCR–07/2008 Figure 42. CharacterTransmission Diagram SCISR register SCTC SCTBE Transmitted Character SCIBUF SCPE Parity error Shift Register I/O pin SCIER Register ESCTBI SCTBI ESCTI Parity error SCTI SCPI SCIIR register 74 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 43. Character Reception Diagram SCISR register SCTC SCTBE Shift Register SCRC Parity error SCIBUF I/O pin SCPE Received Character SCIER Register ESCTBI SCTBI ESCTI ESCRI Parity error SCTI SCRI SCPI SCIIR register SCIB Reset The SCICR register contains a reset bit. If set, this bit generates a reset of the SCIB and its registers. Table 43 defines the SCIB registers that are reset and their reset values. Table 43. Reset Values for SCI Registers Register Name SCIB Reset Value (Binary) SCICR 0000 0000 SCCON 0X00 0000 SCISR 1000 0000 SCIIR 0X00 0000 SCIER 0X00 0000 SCSR X000 1000 SCIBUF 0000 0000 SCETU1, SCETU0 XXXX X001, 0111 0100 (372) SCGT1, SCGT0 0000 0000, 0000 1100 (12) SCWT3, SCWT2, SCWT1, SCWT0 0000 0000, 0000 0000, 0010 0101, 1000 0000 (9600) SCICLK 0X10 1111 75 4202F–SCR–07/2008 Alternate Card A second card named ‘Alternate Card’ can be controlled. The Clock signal CCLK1 can be adapted to the XTAL frequency. Thanks to the clock prescaler which can divide the frequency by 1, 2, 4 or 8. The bits ALTKPS0 and ALTKPS1 in SCSR Register are used to set this factor. Figure 44. Alternate Card CVCC CRST CIO CCLK SMART CARD Main card CPRES CK_IDLE PR3 1, 1/2, 1/4 or 1/8 ALTKPS0,1 SCSR Reg. P1.7 1 0 CCLK1 SIM, SAM CARD Alternate card SCCLK1 SCSR Reg. Registers There are fifteen registers to control the SCIB macro-cell. They are described from Table 58 to Table 45. Some of the register widths are greater than a byte. Despite the 8 bits access provided by the BIU, the address mapping of this kind of register respects the following rule : The Low significant byte register is implemented at the higher address. This implementation makes access to these registers easier when using high level programming languages (C,C++). 76 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 44. Smart Card Interface Control Register - SCICR (S:B6h, SCRS = 1) 7 6 5 4 3 2 1 0 RESET CARDDET VCARD1 VCARD0 UART WTEN CREP CONV Bit Number Bit Mnemonic 7 RESET Description Reset Set this bit to reset and deactivate the Smart Card Interface. Clear this bit to activate the Smart Card Interface. This bit acts as an active high software reset. 6 CARDDET Card Presence Detector Sense Clear this bit to indicate the card presence detector is open when no card is inserted (CPRES is high). Set this bit to indicate the card presence detector is closed when no card is inserted (CPRES is low). Card Voltage Selection: VCARD[1] VCARD[0] 5-4 3 VCARD[1:0] UART CVCC 0 0 0V 0 1 1.8 V 1 0 3.0 V 1 1 5.0 V Card UART Selection Clear this bit to use the CARDIO bit (P1.0) bit to drive the Card I/O (P1.0) pin. Set this bit to use the Smart Card UART to drive the Card I/O pin (P1.0 pin). Controls also the Waiting Time Counter as described in Section “Waiting Time (WT) Counter”, page 67 Waiting Time Counter Enable Clear this bit to stop the counter and enable the load of the Waiting Time counter hold registers. 2 WTEN The hold registers are loaded with SCWT0, SCWT1, SCWT2 and SCWT3 values when SCWT2 is written. Set this bit to start the Waiting Time Counter. The counters stop when it reaches the timeout value. If the UART bit is set, the Waiting Time Counter automatically reloads with the hold registers whenever a start bit is sent or received. Character Repetition Clear this bit to disable parity error detection and indication on the Card I/O pin in receive mode and to disable character repetition in transmit mode. Set this bit to enable parity error indication on the Card I/O pin in receive mode and to set automatic character repetition when a parity error is indicated in transmit mode. 1 CREP Depending upon CREPSET bit is SCSR register, the receiver can indicate parity error up to 4times (3 repetitions) or up to 5times (4 repetitions) after which it will raise the parity error bit SCPE bit in the SCISR register. If parity interrupt is enabled, the SCPI bit in SCIIR register will be set too. Alternately, the transmitter will detect ICC character repetition request. After 3 or 4 unsuccessful repetitions (depending on CREPSEL bit in SCSR register), the transmitter will raise the parity error bit SCPE bit in the SCISR register. If parity interrupt is enabled, the SCPI bit in SCIIR register will be set too. Note : Character repetition mode is specified for T=0 protocol only and should not be used in T=1 protocol (block oriented protocol) 0 CONV ISO Convention Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the parity bit is added after b7 bit and a low level on the Card I/O pin represents a’0’. Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the parity bit is added after b0 bit and a low level on the Card I/O pin represents a’1’. Reset Value = 0000 0000b 77 4202F–SCR–07/2008 Table 45. Smart Card Contacts Register - SCCON (S:ACh, SCRS=0) 7 6 5 4 3 2 1 0 CLK - CARDC8 CARDC4 CARDIO CARDCLK CARDRST CARDVCC Bit Number 7 Bit Mnemonic CLK Description Card Clock Selection Clear this bit to use the Card CLK bit (CARDCLK bit below) to drive Card CLK (P1.4) pin. Set this bit to use CK_XTAL1 or CK_PLL signals for CK_ISO to drive the Card CLK pin (CCLK = P1.4 pin) Note: internal synchronization avoids glitches on the CLK pin when switching this bit. 6 5 - CARDC8 Reserved This bit can be changed by software but the read value is indeterminate. Card C8 Clear this bit to drive a low level on the Card C8 pin (CC8 = P1.1 pin). Set this bit to set a high level on the Card C8 pin (CC8 = P1.1 pin).. The CC8 pin can be used as a pseudo bi-directional I/O when this bit is set. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of CC8 pin 4 CARDC4 Card C4 Clear this bit to drive a low level on the Card C4 pin (CC4 = P1.3 pin). Set this bit to set a high level on the Card C4 pin (CC4 = P1.3 pin). The CC4 pin can be used as a pseudo bi-directional I/O when this bit is set. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of CC4 pin Card I/O If UART bit is cleared in SCICR register, this bit enables the use of the Card IO pin (CIO = P1.0) as a C51 pseudo bi-directional port : 3 CARDIO To read from CIO (P1.0) port pin : set CARDIO (P1.0) bit then read CARDIO (P1.0) bit to have the CIO port value To write in CIO (P1.0) port pin : set CARDIO (P1.0) bit to write a 1 in CIO (P1.0) port pin , clear CARDIO (P1.0) bit to write a 0 in CIO (P1.0) port pin. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of CIO pin 2 CARDCLK Card CLK When the CLK bit is cleared in SCCON Register, the value of this bit is driven to the Card CLK pin. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of Card CLK pin 1 CARDRST Card RST Clear this bit to drive a low level on the Card RST pin. Set this bit to set a high level on the Card RST pin. Warning : VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of Card RST pin 0 CARDVCC Card VCC Control Clear this bit to desactivate the Card interface and set its power-off. The other bits of SCCON register have no effect while this bit is cleared. Set this bit to power-on the Card interface. The activation sequence should be handled by software. Reset Value = 0X00 0000b 78 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 46. Smart Card UART Interface Status Register SCISR (S:ADh, SCRS=0) 7 6 5 4 3 2 1 0 SCTBE CARDIN ICARDOVF VCARDOK SCWTO SCTC SCRC SCPE Bit Number Bit Mnemonic 7 SCTBE 6 CARDIN Description UART Transmit Buffer Empty Status This bit is set by hardware when the Transmit Buffer is copied to the transmit shift register of the Smart Card UART. It is cleared by hardware when SCIBUF register is written. Card Presence Status This bit is set by hardware if there is a card presence (debouncing filter has to be done by software). This bit is cleared by hardware if there is no card presence. Card Current Overflow Status 5 ICARDOVF 4 VCARDOK 3 SCWTO 2 1 0 This bit is set when the current on card is above the limit specified by bit OVFADJ in DCCKPS register (Table 61 on page 92) It is cleared by hardware. Card Voltage Correct Status This bit is set when the output voltage is within the voltage range specified by VCARD[1:0] in SCICR register. It is cleared otherwise. Waiting Time Counter Timeout Status This bit is set by hardware when the Waiting Time Counter has expired. It is cleared by the reload of the counter or by the reset of the SCIB. SCTC UART Transmitted Character Status This bit is set by hardware when the Smart Card UART has transmitted a character. If character repetition mode is selected, this bit will be set only after a successful transmission. If the last allowed repetition in not successful, this bit will not be set. It is cleared by software when this register is read. SCRC UART Received Character Status This bit is set by hardware when the Smart Card UART has received a character It is cleared by hardware when SCIBUF register is read. If character repetition mode is selected, this bit will be set only after a successful reception. If the last allowed repetition is still unsuccessful, this bit will be set to let the user read the erroneous value if necessary. SCPE Character Reception Parity Error Status This bit is set when a parity error is detected on the received character. It is cleared by software when this register is read. If character repetition mode is selected, this bit will be set only if the ICC report an error on the last allowed repetition of a TERMINAL transmission, or if a reception parity error is found on the last allowed ICC character repetition. Reset Value = 1000 0000b 79 4202F–SCR–07/2008 Table 47. Smart Card UART Interrupt Identification Register (Read Only) SCIIR (S:AEh, SCRS=0) 7 6 5 4 3 2 1 0 SCTBI - ICARDERR VCARDERR SCWTI SCTI SCRI SCPI Bit Number Bit Mnemonic 7 SCTBI 6 - Description UART Transmit Buffer Empty Interrupt This bit is set by hardware when the Transmit Buffer is copied into the transmit shift register of the Smart Card UART. It generates an interrupt if ESCTBI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. Reserved The value read from this bit is indeterminate. Do not change this bit. Card Current Overflow Interrupt This bit is set when the current on card is above the limit specified by bit OVFADJ in DCCKPS register (Table 61 on page 92). It generates an interrupt if ICARDER bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. 5 ICARDERR 4 VCARDERR Card Voltage Error Interrupt This bit is set when the output voltage goes out of the voltage range specified by VCARD field. It generates an interrupt if EVCARDER bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. 3 SCWTI Waiting Time Counter Timeout Interrupt This bit is set by hardware when the Waiting Time Counter has expired. It generates an interrupt if ESCWTI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. 2 SCTI UART Transmitted Character Interrupt This bit is set by hardware when the Smart Card UART has completed the character transmission. It generates an interrupt if ESCTI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. 1 SCRI UART Received Character Interrupt This bit is set by hardware when the Smart Card UART has completed the character reception. It generates an interrupt if ESCRI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. 0 SCPI Character Reception Parity Error Interrupt This bit is set at the same time as SCTI or SCRI if a parity error is detected on the received character. It generates an interrupt if ESCPI bit is set in SCIER register otherwise this bit is irrelevant. It is cleared by hardware when this register is read. Reset Value = 0X00 0000b Note: 1) In case of multiple interrupts occuring at the same time (sampled by the same edge of the internal clock), the interrupts will be serviced in the following order from the highest to the lowest priority : - UART Transmit Buffer Empty - Card Current Overflow - Card Voltage Error - Waiting Time Counter Timeout - UART Transmitted Character - UART Received Character - Character Reception Parity Error 2) It is recommended that the application saves the SCIIR register after reading it in order to avoid the loss of pending interruptions as the SCIIR register is cleared when it is read by the MCU. 80 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 48. Smart Card UART Interrupt Enabling Register - SCIER (S:AEh, SCRS=1) 7 6 5 4 3 2 1 0 ESCTBI - ICARDER EVCARDER ESCWTI ESCTI ESCRI ESCPI Bit Number Bit Mnemonic Description 7 ESCTBI 6 - 5 ICARDER 4 EVCARDER 3 ESCWTI 2 ESCTI UART Transmitted Character Interrupt Enabled Clear this bit to disable the Smart Card UART Transmitted Character interrupt. Set this bit to enable the Smart Card UART Transmitted Character interrupt. 1 ESCRI UART Received Character Interrupt Enabled Clear this bit to disable the Smart Card UART Received Character interrupt. Set this bit to enable the Smart Card UART Received Character interrupt. 0 ESCPI Character Reception Parity Error Interrupt Enabled Clear this bit to disable the Smart Card Character Reception Parity Error interrupt. Set this bit to enable the Smart Card Character Reception Parity Error interrupt. UART Transmit Buffer Empty Interrupt Enabled Clear this bit to disable the Smart Card UART Transmit Buffer Empty interrupt. Set this bit to enable the Smart Card UART Transmit Buffer Empty interrupt. Reserved The value read from this bit is indeterminate. Do not change this bit. Card Current Overflow Interrupt Enabled Clear this bit to disable the Card Current Overflow interrupt. Set this bit to enable the Card Current Overflow interrupt. Card Voltage Error Interrupt Enabled Clear this bit to disable the Card Voltage Error interrupt. Set this bit to enable the Card Voltage Error interrupt. WaitingTime Counter Timeout Interrupt Enabled Clear this bit to disable the Waiting Time Counter timeout interrupt. Set this bit to enable the Waiting Time Counter timeout interrupt. Reset Value = 0X00 0000b 81 4202F–SCR–07/2008 Table 49. Smart Card Selection Register - SCSR (S:ABh) 7 6 5 4 3 2 1 0 - BGTEN - CREPSEL ALTKPS1 ALTKPS0 SCCLK1 SCRS Bit Number Bit Mnemonic 7 - Description Reserved The value read from this bit is indeterminate. Do not change this bit. Block Guard Time Enable 6 BGTEN Set this bit to select the minimum interval between the leading edge of the start bits of the last character received from the ICC and the first character sent by the Terminal. The transfer of GT[8-0] value to the BGT counter is done on the rising edge of the BGTEN. Clear this bit to suppress the minimum time between reception and transmission. 5 - Reserved The value read from this bit is indeterminate. Do not change this bit. Character repetition selection 4 CREPSEL Clear this bit to select 5 times transmission (1 original + 4 repetitions) before parity error indication (conform to EMV) Set this bit to select 4 times transmission (1 original + 3 repetitions) before parity error indication Alternate Card Clock prescaler factor 00 ALTKPS = 0: prescaler factor equals 1 3-2 ALTKPS1:0 01 ALTKPS = 1: prescaler factor equals 2 10 ALTKPS = 2: prescaler factor equals 4 (reset value) 11 ALTKPS = 3: prescaler factor equals 8 Alternate card clock selection 1 SCCLK1 Set to select the prescaled PR3 clock for CCLK1 (P1.7) pin Clear to select P1.7 port bit 0 SCRS Smart Card Register Selection The SCRS bit selects which set of the SCIB registers is accessed. Reset Value = X000 1000b Table 50. Smart Card Transmit / Receive Buffer - SCIBUF (S:AA) 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description Smart Card Transmit / Receive Buffer - A new byte can be written in the buffer to be transmitted on the I/O pin when SCTBE bit is set. - - The bits are sorted and copied on the I/O pin versus the active convention. - A new byte received from I/O pin is ready to be read when SCRI bit is set. The bits are sorted versus the active convention. Reset Value = 0000 0000b 82 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 51. Smart Card ETU Register 1 - SCETU1 (S:ADh, SCRS=1) 7 6 5 4 3 2 1 0 COMP - - - - ETU10 ETU9 ETU8 Bit Number Bit Mnemonic 7 COMP 6-3 - Description Compensation Clear this bit when no time compensation is needed (i.e. when the ETU to Card CLK period ratio is close to an integer with an error less than 1/4 of Card CLK period). Set this bit otherwise and reduce the ETU period by 1 Card CLK cycle for even bits. Reserved The value read from these bits is indeterminate. Do not change these bits. ETU MSB Used together with the ETU LSB in SCETU0 (Table 52) 2-0 ETU[10:8] Warning : the ETU counter is reloaded at each register’s write operation. Do not change this register during character reception or transmission or while Guard Time or Waiting Time Counters are running. Reset Value = 0XXX X001b Table 52. Smart Card ETU Register 0 - SCETU0 (S:ACh, SCRS=1) 7 6 5 4 3 2 1 0 ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETU0 Bit Number Bit Mnemonic 7-0 ETU[7:0] Description ETU LSB The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK frequency. According to ISO 7816, ETU[10:0] can be set between 11 and 2048. The default reset value of ETU[10:0] is 372 (F=372, D=1). Reset Value = 0111 0100b 83 4202F–SCR–07/2008 Table 53. Smart Card Transmit Guard Time Register 0 - SCGT0 (S:B4h, SCRS=1) 7 6 5 4 3 2 1 0 GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0 Bit Number Bit Mnemonic 7-0 GT[7:0] Description Transmit Guard Time LSB The minimum time between two consecutive start bits in transmit mode is GT[8:0] * ETU. This is equal to ISO IEC Guard Time +10 (see Guard Time Counter description. According to ISO IEC 7816,the time between 2 consecutive leading edge start bits can be set between 11 and 266 (11 to 254+12 ETUs). Reset Value = 0000 1100b Table 54. Smart Card Transmit Guard Time Register 1 - SCGT1 (S:B5h, SCRS=1) 7 6 5 4 3 2 1 0 - - - - - - - GT8 Bit Number Bit Mnemonic 7-1 - 0 GT8 Description Reserved The value read from these bits is indeterminate. Do not change these bits. Transmit Guard Time MSB Used together with the Transmit Guard Time LSB in SCGT0 register (Table 53). Reset Value = XXXX XXX0b Table 55. Smart Card Character/Block Waiting Time Register 3 SCWT3 (S:C1h, SCRS=0) 7 6 5 4 3 2 1 0 WT31 WT30 WT29 WT28 WT27 WT26 WT25 WT24 Bit Number Bit Mnemonic 7-0 WT[31:24] Description Waiting Time Byte3 Used together with WT[23:0] in registers SCWT2,SCWT1, SCWT0 (see Table 56). Reset Value = 0000 0000b 84 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 56. Smart Card Character/Block Waiting Time Register 2 SCWT2 (S:B6h, SCRS=0) 7 6 5 4 3 2 1 0 WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16 Bit Number Bit Mnemonic 7-0 WT[23:16] Description Waiting Time Byte2 Used together with WT[31:24] and WT[15:0] in registers SCWT3,SCWT1, SCWT0 (see Table 58). Reset Value = 0000 0000b Table 57. Smart Card Character/Block Waiting Time Register 1 SCWT1 (S:B5h, SCRS=0) 7 6 5 4 3 2 1 0 WT15 WT14 WT13 WT12 WT11 WT10 WT9 WT8 Bit Number Bit Mnemonic 7-0 WT[15:8] Description Waiting Time Byte 1 Used together with WT[31:16] and WT[7:0] in registers SCWT3,SCWT2, SCWT0 (see Table 55). Reset Value = 0010 0101b Table 58. Smart Card Character/Block Waiting Time Register 0 SCWT0 (S:B4h, SCRS=0) 7 6 5 4 3 2 1 0 WT7 WT6 WT5 WT4 WT3 WT2 WT1 WT0 Bit Number Bit Mnemonic Description Waiting Time Byte 0 7-0 WT[7:0] WT[31:0] is the reload value of the Waiting Time Counter (WTC). The WTC is a general-purpose timer. It is using the ETU clock and is controlled by the WTEN bit (see Table 44 on page 77 and Section “Waiting Time (WT) Counter”, page 67). When UART bit of Registers is set, the WTC is automatically reloaded at each start bit of the UART. It is used to check the maximum time between to consecutive start bits. Reset Value = 1000 0000b 85 4202F–SCR–07/2008 Table 59. Smart Card Clock Reload Register - SCICLK (S:C1h, SCRS=1) 7 6 5 4 3 2 1 0 XTSCS - SCICLK5 SCICLK4 SCICLK3 SCICLK2 SCICLK1 SCICLK0 Bit Number Bit Mnemonic Description Smart Card Clock Selection Bit 7 XTSCS If XTSCS bit is set OR EXT48 bit is set (in PLLCON register) , CK_PLL is used to generate CK_ISO. Otherwise, CK_XTAL1 is used to generate CK_ISO. See the Clock Tree diagram figure 17. 6 - Reserved The value read from this bit is indeterminate. Do not change these bits. SCIB clock reload register Prescaler 2 reload value is used to defines the card clock frequency. If SCICLK[5:0] is smaller than 48 : 5-0 SCICLK[5:0] Fck_iso = Fck_pll or Fck_XTAL1/ (2 * (48 - SCICLK[5:0])) If SCICLK[5:0] is equal to 48 : Fck_iso = Fck_XTAL1 SCICLK[5:0] must be smaller than 49. Reset Value = 0X10 1111b (default value for a divider by two) DC/DC Converter The Smart Card voltage (CVCC) is supplied by the integrated DC/DC converter which is controlled by several registers: • The SCICR register (Table 44 on page 77) controls the CVCC level by means of bits VCARD[1:0]. • The SCCON register (Table 45 on page 78) enables to switch the DC/DC converter on or off by means of bit CARDVCC. • The DCCKPS register (Table 61 on page 92) controls the DC/DC clock and current. The DC/DC converter cannot be switched on while the CPRES pin remains inactive. If CPRES pin becomes inactive while the DC/DC converter is operating an automatic shut down sequence of the DC/DC converter is initiated by the electronics. It is mandatory to switch off the DC/DC Converter before entering in Power-down mode. Configuration The DC/DC Converter can work in two different modes which are selected by bit MODE in DCCKPS register: • Pump Mode: an external inductance of 10 μH must be connected between pins LI and VCC. VCC can be higher or lower than CVCC. • Regulator mode : no external inductance is required but VCC must be always higher than CVCC+0.3V. The Regulation mode will work even if an external inductance of 10 μH is connected between pins LI and VCC The DC/DC clock prescaler which is controlled by bits DCCKPS[3:0], in DCCKPS register must be configured to set the DC/DC clock to a working frequency of 4 MHz which depends upon the value of the crystal. There is no need to change the default configuration set by the reset sequence if an 8 MHz crystal is used by the application. The DC/DC Converter implements a current overflow controller which avoids permanent damage of the DC/DC converter in case of short circuit between CVCC and CVSS. The maximum limit is around 100 mA. It is possible to increase this limit in normal operating 86 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 mode by 20% by means of bit OVFADJ in DCCKPS register. When the current overflow controller is operating, the ICARDOVF is set by the hardware in SCISR register. The current drawn from power supply by the DC/DC converter is controlled during the startup phase in order to avoid high transient current mainly in Pump Mode which could cause the power supply voltage to drop dramatically. This control is done by means of bits BOOST[1:0], which increases progressively the startup current level. Initialization Procedure The initialization procedure is different depending upon the required Card Vcc. One procedure apply for Card Vcc =< 3 volts and one procedure for Card Vcc = 5 volts. The initialization procedure involves : Procedure for CVcc =< 3 volts • Select the CVCC level by means of bits VCARD[1:0] in SCICR register, • Set bits BOOST[1:0] in DCCKPS register following the current level control wanted. • Switch the DC/DC on by means of bit CARDVCC in SCCON register, • Monitor bit VCARDOK in SCISR register in order to know when the DC/DC Converter is ready (CVCC voltage has reached the expected level) The DC/DC regulation mode must be selected for Card Vcc = 1.8 volts and Card Vcc = 3 volts (MODE = 1 in DCCKPS register) The detailed procedures is described in flow chart of Figure 45. for Card Vcc = 1.8 volts and in the flow chart of Figure 46. for Card Vcc = 3 volts 87 4202F–SCR–07/2008 Figure 45. Card Vcc = 1.8V Initialization Procedure SCICR.7=Reset=1 SCICR.7=Reset=0 VCARD[1:0] = 01 Mode Regulation DCCKPS[7]=1 BOOST[1:0]=01 SCCON CardVcc=1 Set Timeout to 3 ms VCARDOK=1 Timeout Expired DC/DC Initialization successful DC/DC Initialization Failure 88 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 46. Card Vcc = 3V Initialization Procedure SCICR.7=Reset=1 SCICR.7=Reset=0 VCARD[1:0] = 10 Mode Regulation DCCKPS[7]=1 BOOST[1:0]=01 SCCON CardVcc=1 Set Timeout to 3 ms VCARDOK=1 Timeout Expired DC/DC Initialization successful DC/DC Initialization Failure 89 4202F–SCR–07/2008 Procedure for CVcc = 5volts The DC/DC pump mode must be selected (MODE = 0 in DCCKPS register). The detailed procedure is described in flow chart of Figure 47. Figure 47. Card Vcc = 5V Initialization Procedure SCICR.7=Reset=1 SCICR.7=Reset=0 VCARD[1:0] = 11 Mode Pump DCCKPS[7]=0 BOOST[1:0]=[0:0] SCCON CardVcc=1 Set Timeout to 3 ms VCARDOK=1 Timeout Expired BOOST[1:0] = [0:0] BOOST[1:0] = max = 3? Decrement BOOST[1:0] to adjust the current overflow Increment BOOST [1:0] DC/DC Initialization Successful DC/DC Initialization Failure While VCC remains higher than 4.0V and startup current lower than 30 mA (depending on the load type), the DC/DC converter should be ready without having to increment BOOST[1:0] bits beyond [0:0] level. If VCC > 4.0V and startup current > 30 mA, it will be necessary to increment the BOOST[1:0] bits until the DC/DC converter is ready. Incrementation of BOOST[1:0] bits increases at the same time the current overflow level in the same proportion as the startup current. So once the DC/DC converter is ready it is 90 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 advised to decrement the BOOST[1:0] bits to restore the overflow current to its normal or desired value. Once the DC/DC has been successfuly initialized, it is necessary to monitor the DC/DC converter by means of bits VCARDOK and ICARDOVF in the SCISR register. Monitoring Procedure Table 60. DC/DC converter status VCARDOK ICARDOVF DC/DC Status - Not Started or switched off by application. 0 0 The current overflow sensor is disabled during the DC/DC converter startup. Then if a current overflow condition is applied during the DC/DC converter startup, the DC/DC converter is unable to start and both bits VCARDOK and ICARDOVF remains at 0. DC/DC converter correctly started then the output voltage is out of ISO/IEC 7816-3 specifications. In this case the firmware must take appropriate actions like deactivating the DC/DC converter in compliance with ISO/IEC 7816. 0 1 Started and automatically switched off by a current overflow condition 1 0 Operating properly according to ISO/IEC 7816-3 and EMV recommendations 1 1 Not applicable 91 4202F–SCR–07/2008 DC/DC Converter register Table 61. DC/DC Converter Control Register - DCCKPS (S:BFh) 7 6 5 4 3 2 1 0 MODE OVFADJ BOOST1 BOOST0 DCCKPS3 DCCKPS2 DCCKPS1 DCCKPS0 Bit Number Bit Mnemonic 7 MODE Description Regulation mode 0 : Pump mode (External Inductance required) 1 : Regulator mode (No External inductance required if VCC > CVCC+0.3V) Current Overflow Adjustment on Smart Card terminal 6 OVFADJ 0 : normal: 100 mA average 1 : normal + 20% 5-4 BOOST[1:0] VCARDOK=0 VCARDOK=1 Maximum Startup Current drawn from power supply Current Overflow Level on Smart Card terminal 00 : Normal: 30 mA average 00 : Normal = OVFADJ 01 : Normal + 30% 01 : Normal + 30% 10 : Normal + 50% 10 : Normal + 50% 11 : Normal + 80% 11 : Normal + 80% DC/DC Clock Prescaler Value 0000 : Division factor: 2 (reset value) 0001 : Division factor: 3 0010 : Division factor: 4 0011 : Division factor: 5 3-0 DCCKPS[3:0] 0100 : Division factor: 6 0101 : Division factor: 8 0110 : Division factor: 10 0111 : Division factor: 12 1000 : Division factor: 24 Other values are reserved Reset Value = 0000 0000b 92 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 USB Controller The AT8xC5122D implements a USB device controller supporting Full Speed data transfer. In addition to the default control endpoint 0, it provides 6 other endpoints, which can be configured in Control, Bulk, Interrupt or Isochronous modes: • Endpoint 0: 32-byte FIFO, default control endpoint • Endpoint 1,2,3: 8-byte FIFO • Endpoint 4,5: 64-byte FIFO • Endpoint 6: 2 x 64-byte Ping-pong FIFO This allows the firmware to be developed conforming to most USB device classes, for example: • USB Mass Storage Class Control/Bulk/Interrupt (CBI) Transport, Revision 1.0 December 14, 1998. • USB Mass Storage Class Bulk-Only Transport, Revision 1.0 - September 31, 1999. • USB Human Interface Device Class, Version 1.1 - April 7, 1999. • USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999. USB Mass Storage Classes USB Mass Storage Class CBI Transport Within the CBI framework, the Control endpoint is used to transport command blocks as well as to transport standard USB requests. One Bulk-Out endpoint is used to transport data from the host to the device. One Bulk-In endpoint is used to transport data from the device to the host. And one interrupt endpoint may also be used to signal command completion (protocol 0); it is optional and may not be used (protocol 1). The following configuration adheres to these requirements: USB Mass Storage Class BulkOnly Transport • Endpoint 0: 8 bytes, Control In-Out • Endpoint 4: 64 bytes, Bulk-Out • Endpoint 5: 64 bytes, Bulk-In • Endpoint 1: 8 bytes, Interrupt In Within the Bulk-Only framework, the Control endpoint is only used to transport classspecific and standard USB requests for device set-up and configuration. One Bulk-Out endpoint is used to transport commands and data from the host to the device. One BulkIn endpoint is used to transport status and data from the device to the host. No interrupt endpoint is needed. The following configuration adheres to these requirements: USB Device Firmware Upgrade (DFU) • Endpoint 0: 8 bytes, Control In-Out • Endpoint 4: 64 bytes, Bulk-Out • Endpoint 5: 64 bytes, Bulk-In The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip program memory of the AT8xC5122D. This allows the implementation of product enhancements and patches to devices that are already in the field. Two different configurations and description sets are used to support DFU functions. The Run-Time configuration co-exists with the usual functions of the device, which may be USB Mass Storage for the AT8xC5122D. It is used to initiate DFU from the normal operating mode. The DFU configuration is used to perform the firmware update after device re-configuration and USB reset. It excludes any other function. Only the default control pipe (endpoint 0) is used to support DFU services in both configurations. 93 4202F–SCR–07/2008 The only possible value for the wMaxPacketSize in the DFU configuration is 32 bytes, which is the size of the FIFO implemented for endpoint 0. The USB device controller provides the hardware that the AT8xC5122D and the AT83C5123 need to interface a USB link to a data flow stored in a double port memory (DPRAM). Description The USB controller requires a 48 MHz reference clock, which is the output of the AT8xC5122D/23 PLL (see Section "Phase Lock Loop (PLL)", page 40) divided by a clock prescaler. This clock is used to generate a 12 MHz full speed bit clock from the received USB differential data and to transmit data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is compliant with the jitter specification of the USB bus. The Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC generation and checking, and the serial-parallel data conversion. The Universal Function Interface (UFI) performs the interface between the data flow and the Dual Port Ram Figure 48. USB Device Controller Block Diagram 48 MHz +/- 0.25% DPLL D+ 12MHz C51 Microcontroller Interface USB D+/DBuffer D- UFI Up to 48 MHz UC_SYSCLK SIE Serial Interface Engine (SIE) 94 The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and unstuffing. • CRC generation and checking. • Handshakes. • TOKEN type identifying. • Address checking. • Clock generation (via DPLL). AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 49. SIE Block Diagram End of Packet Detection SYNC detection Start of Packet Detection D+ NRZI ‘ NRZ Bit Unstuffing Packet bit counter D- Clock Recovery Clk48 (48 MHz) SysClk (12 MHz) USB Pattern Generator Parallel to Serial Converter Bit Stuffing NRZI Converter CRC16 Generator Function Interface Unit (UFI) PID decoder DataOut Address Decoder Serial t o Parallel 8 Conversion CRC5 & CRC16 Generation/Check 8 DataIn [7:0] The Function Interface Unit provides the interface between the AT8xC5122D (or AT83C5123) and the SIE. It manages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint FIFOs. Figure 50. UFI Block Diagram UFI Asynchronous Information Transfer DPLL Transfer Control FSM Endpoint 6 Endpoint 5 CSREG 0 to 7 C51 Microcontroller Interface Registers Bank Endpoint 4 Endpoint 3 Endpoint 2 SIE DPR Control USB side Endpoint 1 Endpoint 0 DPR Control mP side Up to 48 MHz UC_SYSCLK User DPRAM 95 4202F–SCR–07/2008 Figure 51. Minimum Intervention from the USB Device Firmware OUT Transactions: HOST UFI C51 OUT DATA0 (n Bytes) OUT ACK DATA1 OUT interrupt C51 NACK DATA1 ACK Endpoint FIFO read (n bytes) IN Transactions: HOST UFI C51 96 IN IN NACK IN DATA1 Endpoint FIFO write ACK DATA1 interrupt C51 Endpoint FIFO write AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Configuration General Configuration • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (Section "Clock Controller", page 39). The USB controller should be then enabled by setting the USBE bit in the USBCON register. • Set address After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the USBADDR register. This action will allow the USB controller to answer to the requests sent at the address 0. When a SET_ADDRESS request has been received, the USB controller must only answer to the address defined by the request. The new address should be stored in the USBADDR register. The FEN bit and the FADDEN bit in the USBCON register should be set to allow the USB controller to answer only to requests sent at the new address. • Set configuration The CONFG bit in the USBCON register should be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit should be cleared. Endpoint Configuration • Selection of an Endpoint The endpoint register access is performed using the UEPNUM register. The following registers correspond to the endpoint whose number is stored in the UEPNUM register. To select an Endpoint, the firmware has to write the endpoint number in the UEPNUM register. – UEPSTAX, – UEPCONX, – UEPDATX, – UBYCTX, Figure 52. Endpoint Selection Endpoint 0 Endpoint 6 UEPSTA0 UEPCON0 UEPDAT0 0 UEPDAT6 1 2 3 4 5 6 SFR Registers UBYCT0 UEPSTA6 UEPCON6 X UEPSTAX UEPCONX UEPDATX UBYCTX UBYCT6 UEPNUM 97 4202F–SCR–07/2008 • Endpoint enable Before using an endpoint, this one should be enabled by setting the EPEN bit in the UEPCONX register. An endpoint which is not enabled won’t answer to any USB request. The Default Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB standard requests. • Endpoint type configuration All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous mode. The configuration of an endpoint is performed by setting the field EPTYPE with the following values: – Control: EPTYPE = 00b – Isochronous: EPTYPE = 01b – Bulk: EPTYPE = 10b – Interrupt: EPTYPE = 11b The Endpoint 0 is the Default Control Endpoint and should always be configured in Control type. • Endpoint direction configuration For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of the UEPCONX register with the following values: – IN:EPDIR = 1b – OUT:EPDIR = 0b For Control endpoints, the EPDIR bit has no effect. • Summary of Endpoint Configuration: Make sure to select the correct endpoint number in the UEPNUM register before accessing to endpoint specific registers. Table 62. Summary of Endpoint Configuration Endpoint configuration 98 EPEN EPDIR EPTYPE UEPCONX Disabled 0b Xb XXb 0XXX XXXb Control 1b Xb 00b 80h Bulk-In 1b 1b 10b 86h Bulk-Out 1b 0b 10b 82h Interrupt-In 1b 1b 11b 87h Interrupt-Out 1b 0b 11b 83h Isochronous-In 1b 1b 01b 85h Isochronous-Out 1b 0b 01b 81h AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 • Endpoint FIFO reset Before using an endpoint, its FIFO should be reset. This action resets the FIFO pointer to its original value, resets the byte counter of the endpoint (UBYCTX register), and resets the data toggle bit (DTGL bit in UEPCONX). The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corresponding bit in the UEPRST register. For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000 0000b in the UEPRST register. 99 4202F–SCR–07/2008 Read/Write Data FIFO Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the data are stored into the FIFO and the byte counter of the endpoint is updated (UBYCTX register). The firmware has to store the endpoint byte counter before any access to the endpoint FIFO. The byte counter is not updated when reading the FIFO. To read data from an endpoint, select the correct endpoint number in UEPNUM and read the UEPDATX register. This action automatically decreases the corresponding address vector, and the next data is then available in the UEPDATX register. Write Data FIFO The write access for each IN endpoint is performed using the UEPDATX register. To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEPNUM and write into the UEPDATX register. The corresponding address vector is automatically increased, and another write can be carried out. Warning 1: The byte counter is not updated. Warning 2: Do not write more bytes than supported by the corresponding endpoint. Figure 53. Endpoint FIFO Configuration 138H Base Addresses Endpoint 6 - bank 1 F8H B8H Endpoint 5 - bank 0 64 Bytes Endpoint 4 - bank 0 64 Bytes Endpoint 3 - bank 0 8 Bytes Endpoint 2 - bank 0 8 Bytes Endpoint 1 - bank 0 8 Bytes Endpoint 0 - bank 0 32 Bytes 78H 38H 30H 28H 20H 00H 100 2 x 64 Bytes Endpoint 6 - bank 0 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Bulk / Interrupt Transactions Bulk and Interrupt transactions are managed in the same way. Bulk/Interrupt OUT Transactions in Standard Mode Figure 54. Bulk/Interrupt OUT transactions in Standard Mode HOST OUT C51 UFI DATA0 (n bytes) ACK RXOUTB0 Endpoint FIFO read byte 1 OUT DATA1 Endpoint FIFO read byte 2 NAK OUT Endpoint FIFO read byte n DATA1 Clear RXOUTB0 NAK OUT DATA1 ACK RXOUTB0 Endpoint FIFO read byte 1 An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this endpoint. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct and the endpoint byte counter contains the number of bytes sent by the Host. 101 4202F–SCR–07/2008 Bulk/Interrupt OUT Transactions in Ping-Pong Mode (Endpoints 6) Figure 55. Bulk / Interrupt OUT Transactions in Ping-Pong Mode HOST OUT UFI C51 DATA0 (n bytes) ACK RXOUTB0 Endpoint FIFO bank 0 - read byte 1 OUT Endpoint FIFO bank 0 - read byte 2 DATA1 (m bytes) ACK Endpoint FIFO bank 0 - read byte n Clear RXOUTB0 OUT RXOUTB1 DATA0 (p bytes) Endpoint FIFO bank 1 - read byte 1 ACK Endpoint FIFO bank 1 - read byte 2 Endpoint FIFO bank 1 - read byte m RXOUTB0 Clear RXOUTB1 Endpoint FIFO bank 0 - read byte 1 Endpoint FIFO bank 0 - read byte 2 Endpoint FIFO bank 0 - read byte p Clear RXOUTB0 An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt packets. When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUB0 bit to allow the USB controller to accept the next OUT packet on the endpoint bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 0 endpoint FIFO. When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the USB controller will answer a NAK handshake for each OUT requests on the bank 1 endpoint FIFO. The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new valid packet receipt. The firmware has to clear one of these two bits after having read all the data FIFO to allow a new valid packet to be stored in the corresponding bank. A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released by the firmware. 102 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Bulk/Interrupt IN Transactions In Standard Mode Figure 56. Bulk/Interrupt IN Transactions in Standard Mode UFI HOST C51 Endpoint FIFO write byte 1 IN Endpoint FIFO write byte 2 NAK Endpoint FIFO write byte n Set TXRDY IN DATA0 (n bytes) ACK TXCMPL Clear TXCMPL Endpoint FIFO write byte 1 An endpoint should be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint. To send a Zero Length Packet, the firmware should set the TXRDY bit without writing any data into the endpoint FIFO. Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK handshake for each IN requests. To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The packet stored in the endpoint FIFO is then cleared and a new packet can be written and sent. When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more bytes than supported by the endpoint FIFO. All USB retry mechanisms are automatically managed by the USB controller. 103 4202F–SCR–07/2008 Bulk/Interrupt IN Transactions in Ping-Pong Mode Figure 57. Bulk / Interrupt IN transactions in Ping-Pong mode UFI HOST C51 Endpoint FIFO Bank 0 - Write Byte 1 IN Endpoint FIFO Bank 0 - Write Byte 2 NACK Endpoint FIFO Bank 0 - Write Byte n Set TXRDY IN Endpoint FIFO Bank 1 - Write Byte 1 DATA0 (n Bytes) Endpoint FIFO Bank 1 - Write Byte 2 ACK Endpoint FIFO Bank 1 - Write Byte m TXCMPL Clear TXCMPL Set TXRDY IN DATA1 (m Bytes) Endpoint FIFO Bank 0 - Write Byte 1 Endpoint FIFO Bank 0 - Write Byte 2 ACK Endpoint FIFO Bank 0 - Write Byte p TXCMPL Clear TXCMPL Set TXRDY IN DATA0 (p Bytes) Endpoint FIFO Bank 1 - Write Byte 1 ACK An endpoint will be first enabled and configured before being able to send Bulk or Interrupt packets. The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint. The FIFO banks are automatically switched, and the firmware can immediately write into the endpoint FIFO bank 1. When the IN packet concerning the bank 0 has been sent and acknowledged by the Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically switched. When the IN packet concerning the bank 1 has been sent and acknowledged by the Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data. The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller will answer a NAK handshake for each IN requests concerning this bank. Note that in the example above, the firmware clears the Transmit Complete bit (TXCMPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1. The firmware will never write more bytes than supported by the endpoint FIFO. 104 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Control Transactions Setup Stage The DIR bit in the UEPSTAX register should be at 0. Receiving Setup packets is the same as receiving Bulk Out packets, except that the Rxsetup bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an interrupt is triggered if enabled. The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing the RXSETUP bit to free the endpoint FIFO for the next transaction. Data Stage: Control Endpoint Direction The data stage management is similar to Bulk management. A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX register. • If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX register before writing into the FIFO and sending the data by setting to 1 the TXRDY bit in the UEPSTAX register. The IN transaction is complete when the TXCMPL has been set by the hardware. The firmware should clear the TXCMPL bit before any other transaction. • If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware when a new valid packet has been received on the endpoint. The firmware must read the data stored into the FIFO and then clear the RXOUTB0 bit to reset the FIFO and to allow the next transaction. The bit DIR is used to send the correct data toggle in the data stage. To send a STALL handshake, see “STALL Handshake” on page 108. Status Stage The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage. The status stage management is similar to Bulk management. • For a Control Write transaction or a No-Data Control transaction, the status stage consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions In Standard Mode” on page 103). To send a STALL handshake, see “STALL Handshake” on page 108. • For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 101). 105 4202F–SCR–07/2008 Isochronous Transactions Isochronous OUT Transactions in Standard Mode An endpoint should be first enabled and configured before being able to receive Isochronous packets. When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transaction will be lost. If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only the remaining bytes into the FIFO. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous OUT Transactions in Ping-pong Mode An endpoint should be first enabled and configured before being able to receive Isochronous packets. When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTX register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal to 0 and no data has to be read. The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt. When all the endpoint FIFO bytes have been read, the firmware should clear the RXOUB0 bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint FIFO will be lost. If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB controller will store only the remaining bytes into the FIFO. When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be lost. The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new packet receipt. The firmware has to clear one of these two bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank. 106 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. Isochronous IN Transactions in Standard Mode An endpoint should be first enabled and configured before being able to send Isochronous packets. The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning this endpoint. If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should never write more bytes than supported by the endpoint FIFO. Isochronous IN Transactions in Ping-Pong Mode An endpoint should be first enabled and configured before being able to send Isochronous packets. The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN request concerning the endpoint. The FIFO banks are automatically switched, and the firmware can immediately write into the endpoint FIFO bank 1. If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB controller. When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically switched. When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO bank 1 with new data. The bank switch is performed by the USB controller each time the TXRDY bit is set by the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller won’t send anything at each IN requests concerning this bank. The firmware should never write more bytes than supported by the endpoint FIFO. 107 4202F–SCR–07/2008 Miscellaneous USB Reset The EORINT bit in the USBINT register is set by hardware when a End of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still enabled, but all the USB registers are reset by hardware. The firmware should clear the EORINT bit to allow the next USB reset detection. STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the endpoint selected with the UEPNUM register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an interrupt if enabled. The firmware should clear the STALLRQ and STLCRC bits after each STALL sent. The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on a CONTROL type endpoint. Start of Frame Detection The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the next Start of Frame detection. Frame Number When receiving a Start of Frame, the frame number is automatically stored in the UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start Of Frame is valid (CRCOK set at 1) or corrupt (CRCERR set at 1). The UFNUML and UFNUMH registers are automatically updated when receiving a new Start of Frame. Data Toggle Bit The Data Toggle bit is set by hardware when a DATA 0 packet is received and accepted by the USB controller and cleared by hardware when a DATA 1 packet is received and accepted by the USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST register. For Control endpoints, each SETUP transaction starts with a DATA 0 and data toggling is then used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Status stage completes the data transfer with a DATA 1 (for a control read transfer). For Isochronous endpoints, the device firmware should ignore the data-toggle. NAK Handshakes 108 When a NAK handshake is sent by the USB controller to a IN or OUT request from the Host, the NAKIN or NAKOUT bit is set by hardware. This information can be used to determine the direction of the communication during a Control transfer. These bits are cleared by software. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Suspend/Resume Management Suspend The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for more than 3 ms. This triggers a USB interrupt if enabled. In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active. The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-up event is detected. The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit in the USBCON register. 2. Disable the PLL by clearing the PLLEN bit in the PLLCON register. Resume When the USB controller is in Suspend state, the Resume detection is active even if all the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the SUSPCLK bit in the USBCON register if needed. The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated. 109 4202F–SCR–07/2008 Figure 58. Example of a Suspend/Resume Management USB Controller Init SPINT Detection of a SUSPEND State Clear SPINT Put the USB pads in power down mode Set SUSPCLK Disable PLL microcontroller in power-down Detection of a RESUME State Note : WUPCPU bit must be Cleared before enabling the PLL WUPCPU Clear SUSPCLK Clear WUPCPU bit Enable PLL Warning: The core must be switched in external clock mode before disabling the PLL. Upstream Resume A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up purpose. When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware should set to 1 the RMWUPE bit in the USBCON register to enable this function. RMWUPE value should be 0 in the other cases. If the device is in SUSPEND mode, the USB controller can send an upstream resume by clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRMWUP bit in the USBCON register. The USB controller sets to 1 the UPRSM bit in the USBCON register. All clocks must be enabled first. The Remote Wake is sent only if the USB bus was in Suspend state for at least 5 ms. When the upstream resume is completed, the UPRSM bit is reset to 0 by hardware. The firmware should then clear the SDRMWUP bit. 110 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 59. Example of REMOTE WAKEUP Management USB Controller Init SET_FEATURE: DEVICE_REMOTE_WAKEUP Set RMWUPE SPINT Detection of a SUSPEND state Suspend management Need USB Resume Enable Clocks Clear SPINT UPRSM = 1 upstream RESUME sent Set SDMWUP UPRSM Clear SDRMWUP 111 4202F–SCR–07/2008 Detach Simulation In order to be re-enumerated by the Host, the AT83R5122, AT8xC5122/23 has the possibility to simulate a DETACH-ATTACH of the USB bus. The VREF output voltage is between 3.0V and 3.6V. This output can be connected to the D+ pull-up as shown in Figure 60. This output can be put in high-impedance when the DETACH bit is set to 1 in the USBCON register. Maintaining this output in high impedance for more than 3 μs will simulate the disconnection of the device. When resetting the DETACH bit, an ATTACH is then simulated. The USB controller should be enabled to use this feature. Figure 60. Example of VREF Connection VREF R1 DD+ R2 1 2 3 R3 4 VCC DD+ GND USB-B Connector Figure 61. Disconnect Timing D+ VIHZ(min) VIL VSS D>= 2,5 μs Device Disconnected 112 Disconnect Detected AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 USB Interrupt System Interrupt System Priorities Figure 62. USB Interrupt Control System D+ D- 00 01 10 11 USB Controller EUSB EA IEN1.6 IEN0.7 IPH/L Priority Enable Interrupt Enable Lowest Priority Interrupts Table 63. Priority Levels Interrupt Control System IPHUSB IPLUSB USB Priority Level 0 0 0 Lowest 0 1 1 1 0 2 1 1 3 Highest As shown in Figure 63, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data (Table 70 on page 119). This bit is set by hardware when the Host accept a In packet. • RXOUTB0: Received Out Data Bank 0 (Table 70 on page 119). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 0. • RXOUTB1: Received Out Data Bank 1 (only for Ping-Pong endpoints) (Table 70 on page 119). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 1. • RXSETUP: Received Setup (Table 70 on page 119). This bit is set by hardware when an SETUP packet is accepted by the endpoint. • NAKIN and NAKOUT: These bits are set by hardware when a Nak Handshake has been received on the corresponding endpoint. These bits are cleared by software. • STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table on page 120). This bit is set by hardware when a STALL handshake has been sent as requested by STALLRQ, and is reset by hardware when a SETUP packet is received. • SOFINT: Start Of Frame Interrupt (Table 65 on page 116). This bit is set by hardware when a USB start of frame packet has been received. • WUPCPU: Wake-Up CPU Interrupt (Table 65 on page 116). This bit is set by hardware when a USB resume is detected on the USB bus, after a SUSPEND state. • SPINT: Suspend Interrupt (Table 65 on page 116). This bit is set by hardware when a USB suspend is detected on the USB bus. 113 4202F–SCR–07/2008 Figure 63. USB Interrupt Control Block Diagram Endpoint X (X = 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 EPXINT UEPSTAX.6 UEPINT.X RXSETUP EPXIE UEPSTAX.2 UEPIEN.X STLCRC UEPSTAX.3 NAKOUT UEPCONX.5 NAKIN UEPCONX.4 NAKIEN UEPCONX.6 WUPCPU EUSB USBINT.5 EWUPCPU IE1.6 USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.0 114 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Registers Table 64. USB Global Control Register - USBCON (S:BCh) 7 6 5 4 3 2 1 0 USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN Bit Number Bit Mnemonic 7 USBE 6 SUSPCLK 5 4 3 2 Description USB Enable Set this bit to enable the USB controller. Clear this bit to disable and reset the USB controller, to disable the USB transceiver and to disable the USB controller clock inputs. Suspend USB Clock Set this bit to disable the 48MHz clock input (Resume Detection is still active). Clear this bit to enable the 48MHz clock input. Send Remote Wake-up Set this bit to force an external interrupt on the USB controller for Remote Wake UP purpose. SDRMWUP An upstream resume is send only if the bit RMWUPE is set, all USB clocks are enabled AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM below. This bit is cleared by software. DETACH Detach Command Set this bit to simulate a Detach on the USB line. The VREF pin is then in a floating state. Clear this bit to maintain VREF at 3.3V. UPRSM Upstream Resume (read only) This bit is set by hardware when SDRMWUP has been set and if RMWUPE is enabled. This bit is cleared by hardware after the upstream resume has been sent. RMWUPE Remote Wake-Up Enable Set this bit to enabled request an upstream resume signaling to the host. Clear this bit otherwise. Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP feature for the device. 1 0 CONFG Configured This bit should be set by the device firmware after a SET_CONFIGURATION request with a non-zero value has been correctly processed. It should be cleared by the device firmware when a SET_CONFIGURATION request with a zero value is received. It is cleared by hardware on hardware reset or when an USB reset is detected on the bus (SE0 state for at least 32 Full Speed bit times: typically 2.7 μs). FADDEN Function Address Enable This bit should be set by the device firmware after a successful status phase of a SET_ADDRESS transaction. It should not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset or when an USB reset is received (see above). When this bit is cleared, the default function address is used (0). Reset Value = 0000 0000b 115 4202F–SCR–07/2008 Table 65. USB Global Interrupt Register - USBINT (S:BDh) 7 6 5 4 3 2 1 0 - - WUPCPU EORINT SOFINT - - SPINT Bit Bit Number Mnemonic Description 7-6 5 - Reserved The value read from these bits is always 0. Do not change these bits. Wake-up CPU Interrupt This bit is set by hardware when the USB controller is in SUSPEND state and is re-activated by a non-idle signal FROM USB line (not by an upstream resume). WUPCPU This triggers a USB interrupt when EWUPCPU is set in the Table on page 117. When receiving this interrupt, user has to enable all USB clock inputs. This bit should be cleared by software (USB clocks must be enabled before). EORINT End of Reset Interrupt This bit is set by hardware when End of Reset has been detected by the USB controller. This triggers a USB interrupt when EEORINT is set in the Table on page 117. This bit should be cleared by software. 3 SOFINT Start Of Frame Interrupt This bit is set by hardware when an USB Start Of Frame PID (SOF) has been detected. This triggers a USB interrupt when ESOFINT is set in the Table on page 117. This bit should be cleared by software. 2-1 - 4 0 SPINT Reserved The value read from these bits is always 0. Do not change these bits. Suspend Interrupt This bit is set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN register (Table 66 on page 117). This bit must be cleared by software before powering the microcontroller down as it disables the USB pads to reduce the power consumption. Reset Value = 0000 0000b 116 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 66. USB Global Interrupt Enable Register - USBIEN (S:BEh) 7 6 5 4 3 2 1 0 - - EWUPCPU EEORINT ESOFINT - - ESPINT Bit Number Bit Mnemonic Description 7-6 5 - Reserved The value read from these bits is always 0. Do not change these bits. Enable Wake-up CPU Interrupt EWUPCPU Set this bit to enable Wake-up CPU Interrupt. Clear this bit to disable Wake-up CPU Interrupt. 4 EEORINT Enable End of Reset Interrupt Set this bit to enable End of Reset Interrupt. This bit is set after reset. Clear this bit to disable End of Reset Interrupt. 3 ESOFINT Enable SOF Interrupt Set this bit to enable SOF Interrupt. Clear this bit to disable SOF Interrupt. 2-1 - Reserved The value read from these bits is always 0. Do not change these bits. 0 ESPINT Enable Suspend Interrupt Set this bit to enable Suspend Interrupts (See Table 65 on page 116). Clear this bit to disable Suspend Interrupts. Reset Value = 0001 0000b Table 67. USB Address Register - USBADDR (S:C6h) 7 6 5 4 3 2 1 0 FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 Bit Number Bit Mnemonic 7 FEN 6-0 Description Function Enable Set this bit to enable the function. FADD is reset to 1. Cleared this bit to disable the function. USB Address This field contains the default address (0) after power-up or USB bus reset. UADD[6:0] It should be written with the value set by a SET_ADDRESS request received by the device firmware. Reset Value = 1000 0000b 117 4202F–SCR–07/2008 Table 68. USB Endpoint Number - UEPNUM (S:C7h) 7 6 5 4 3 2 1 0 - - - - EPNUM3 EPNUM2 EPNUM1 EPNUM0 Bit Number Bit Mnemonic 7-4 - 3-0 EPNUM[3:0] Description Reserved The value read from these bits is always 0. Do not change these bits. Endpoint Number Set this field with the number of the endpoint which should be accessed when reading or writing to, USB Byte Count Register X (X=EPNUM set in UEPNUM Register) - UBYCTX (S:E2h) or USB Endpoint X Control Register UEPCONX (S:D4h). This value can be 0, 1, 2, 3, 4, 5 or 6. Reset Value = 0000 0000b Table 69. USB Endpoint X Control Register - UEPCONX (S:D4h) 7 6 5 4 3 2 1 0 EPEN NAKIEN NAKOUT NAKIN DTGL EPDIR EPTYPE1 EPTYPE0 Bit Number Bit Mnemonic Description Endpoint Enable Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will always be enabled after a hardware or USB bus reset and participate in the device configuration. Clear this bit to disable the endpoint according to the device configuration. 7 EPEN 6 NAKIEN NAK Interrupt Enable Set this bit to enable NAKIN and NAKOUT Interrupt. Clear this bit to disable NAKIN and NAKOUT Interrupt. 5 NAKOUT NAK OUT Sent This bit is set by hardware when the a NAK handshake is sent by the USB controller to an OUT request from the Host. This generates an interrupt if the NAKIEN bit is set. This bit shall be cleared by software. 4 NAKIN NAK IN Sent This bit is set by hardware when the a NAK handshake is sent by the USB controller to an IN request from the Host. This generates an interrupt if the NAKIEN bit is set. This bit shall be cleared by software. 3 DTGL Data Toggle (Read-only) This bit is set by hardware when a valid DATA0 packet is received and accepted. This bit is cleared by hardware when a valid DATA1 packet is received and accepted. EPDIR Endpoint Direction Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. This bit has no effect for Control endpoints. 2 1-0 EPTYPE[1:0] Endpoint Type Set this field according to the endpoint configuration (Endpoint 0 will always be configured as control): 00Control endpoint 01Isochronous endpoint 10Bulk endpoint 11Interrupt endpoint Reset Value = 1000 0000b when UEPNUM = 0 Reset Value = 0000 0000b otherwise 118 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 70. USB Endpoint Status and Control Register X - UEPSTAX (S:CEh) X=EPNUM set in UEPNUM Register) 7 6 5 4 3 2 1 0 DIR RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP RXOUTB0 TXCMP Bit Bit Number Mnemonic Description 7 DIR Control Endpoint Direction This bit is used only if the endpoint is configured in the control type (see“USB Endpoint X Control Register - UEPCONX (S:D4h)” on page 118). This bit determines the Control data and status direction. The device firmware should set this bit ONLY for the IN data stage, before any other USB operation. Otherwise, the device firmware should clear this bit. 6 Received OUT Data Bank 1 for Endpoint 6 (Ping-pong Mode) This bit is set by hardware after a new packet has been stored in the endpoint FIFO Data bank 1 (only in Ping-pong mode). Then, the endpoint interrupt is triggered if enabled (see “USB Global Interrupt Register - USBINT (S:BDh)” on page 116) and all RXOUTB1 the following OUT packets to the endpoint bank 1 are rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous Endpoints. This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO. 5 Stall Handshake Request Set this bit to request a STALL answer to the host for the next handshake. STALLRQ Clear this bit otherwise. For CONTROL endpoints: cleared by hardware when a valid SETUP PID is received. 4 3 TXRDY TX Packet Ready Set this bit after a packet has been written into the endpoint FIFO for IN data transfers. Data should be written into the endpoint FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet. This bit is cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has acknowledged the packet for Control, Bulk and Interrupt endpoints. When this bit is cleared, the endpoint interrupt is triggered if enabled (see Table 65 on page 116). STLCRC Stall Sent / CRC error flag - For Control, Bulk and Interrupt Endpoints: This bit is set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint interrupt is triggered if enabled (see“” on page 116) It should be cleared by the device firmware. - For Isochronous Endpoints (Read-Only): This bit is set by hardware if the last received data is corrupted (CRC error on data). This bit is updated by hardware when a new data is received. 2 Received SETUP This bit is set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the register RXSETUP are cleared by hardware and the endpoint interrupt is triggered if enabled (see Table 65 on page 116). It should be cleared by the device firmware after reading the SETUP data from the endpoint FIFO. 1 Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints) This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint interrupt is triggered if enabled (see“” on page 116) and all the following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this RXOUTB0 bit has been cleared, excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may overwrite the content of the endpoint FIFO, even if its Data packet is received while this bit is set. This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO. 0 TXCMPL Transmitted IN Data Complete This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled (see Table 65). This bit should be cleared by the device firmware before setting TXRDY. Reset Value = 0000 0000b 119 4202F–SCR–07/2008 Table 71. USB FIFO Data Endpoint X (X=EPNUM set in UEPNUM Register) UEPDATX (S:CFh) 7 6 5 4 3 2 1 0 FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0 Bit Number Bit Mnemonic Description Endpoint X FIFO data 7-0 FDAT[7:0] Data byte to be written to FIFO or data byte to be read from the FIFO, for the Endpoint X (see EPNUM). Reset Value = XXXX XXXXb Table 72. USB Byte Count Register X (X=EPNUM set in UEPNUM Register) - UBYCTX (S:E2h) 7 6 5 4 3 2 1 0 - BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0 Bit Number 7 6-0 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not change this bit. Byte Count LSB BYCT[6:0] Least Significant Byte of the byte count of a received data packet. This byte count is equal to the number of data bytes received after the Data PID. Reset Value = 0000 0000b 120 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h) 7 6 5 4 3 2 1 0 - EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not change this bit. EP6RST Endpoint 6 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. EP5RST Endpoint 5 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. EP4RST Endpoint 4 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. EP3RST Endpoint 3 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. EP2RST Endpoint 2 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. EP1RST Endpoint 1 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. EP0RST Endpoint 0 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. Reset Value = 0000 0000b 121 4202F–SCR–07/2008 Table 74. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only) 7 6 5 4 3 2 1 0 - EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description - Reserved The value read from these bits is always 0. Do not change this bit. EP6INT Endpoint 6 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 6. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP6INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. EP5INT Endpoint 5 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 5. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP5INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. EP4INT Endpoint 4 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 4. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP4INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. EP3INT Endpoint 3 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 3. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP3INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. EP2INT Endpoint 2 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 2. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP2INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. EP1INT Endpoint 1 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 1. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP1INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. EP0INT Endpoint 0 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 0. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP0INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. Reset Value = 0000 0000b 122 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 75. USB Endpoint Interrupt Enable Register - UEPIEN (S:C2h) 7 6 5 4 3 2 1 0 - EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not change this bit. 7 - 6 EP6INTE Endpoint 6 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. 5 EP5INTE Endpoint 5 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. 4 EP4INTE Endpoint 4 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. 3 EP3INTE Endpoint 3 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. 2 EP2INTE Endpoint 2 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. 1 EP1INTE Endpoint 1 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. 0 EP0INTE Endpoint 0 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Reset Value = 0000 0000b 123 4202F–SCR–07/2008 Serial I/O Port The serial I/O port in the AT83R5122, AT8xC5122/23 is compatible with the serial I/O port in the 80C52. The I/O port provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three fullduplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: Framing Error Detection • Framing error detection • Automatic address recognition Framing bit error detection is provided for the three asynchronous modes (Modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 64). Figure 64. Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h) Set FE Bit if Stop Bit is 0 (Framing Error) (SMOD0 = 1) SM0 to UART Mode Control (SMOD0 = 0) SMOD1 SMOD0 - POF GF1 GF0 PD PCON (87h) IDL To UART Framing Error Control When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Figure 69 on page 128) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 65 and Figure 66). Figure 65. UART Timings in Mode 1 RXD D0 Start Bit D1 D2 D3 D4 Data Byte D5 D6 D7 Stop Bit RI SMOD0=X FE SMOD0=1 124 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 66. UART Timings in Modes 2 and 3 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. Note: Given Address The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t care bits (defined by zeros) to form the device’s given address. The don’t care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b 125 4202F–SCR–07/2008 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t care bits, e.g.: SADDR0101 0110b SADEN1111 1100b Broadcast =SADDR OR SADEN1111 111Xb The use of don’t care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Broadcast1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that does not support automatic address recognition. Timer 1 When using the Timer 1, the Baud Rate is derived from the overflow of the timer. As shown in Figure 67 the Timer 1 is used in its 8-bit auto-reload mode). SMOD1 bit in PCON register allows doubling of the generated baud rate. 126 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 67. Timer 1 Baud Rate Generator Block Diagram CK_ T1 /6 0 TL1 (8 bits) 1 T1 Overflow /2 0 1 To serial Port C/T1# TMOD.6 SMOD1 INT1# PCON.7 GATE1 Internal Baud Rate Generator TH1 (8 bits) TR1 TMOD.7 T1 CLOCK TCON.6 When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer. As shown in Figure 68 the Internal Baud Rate Generator is an 8-bit auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in BDRCON register (see Table 82 on page 134). The Internal Baud Rate Generator is enabled by setting BRR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated baud rate. Figure 68. Internal Baud Rate Generator Block Diagram CK_ SI /6 0 BRG (8 bits) 1 Overflow /2 0 1 SPD BRR BDRCON.1 BDRCON.4 SMOD1 PCON.7 To serial Port IBRG CLOCK BRL (8 bits) Synchronous Mode (Mode 0) Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock pulses while the receive data (RXD) pin transmits or receives a byte of data. The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur at a fixed Baud Rate (see Section “Baud Rate Selection (Mode 0)”). Figure 69 shows the serial port block diagram in Mode 0. 127 4202F–SCR–07/2008 Figure 69. Serial I/O Port Block Diagram (Mode 0) SCON.6 SM1 SCON.7 SM0 SBUF Tx SR Mode Decoder RXD M3 M2 M1 M0 SBUF Rx SR Mode Controller CK_ T1 TI SCON.1 Transmission (Mode 0) RI SCON.0 Baud Rate Controller IBRG CLOCK TXD To start a transmission mode 0, write to SCON register clearing bits SM0, SM1. As shown in Figure 70, writing the byte to transmit to SBUF register starts the transmission. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle composed of a high level then low level signal on TXD. During the eighth clock cycle the MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to indicate the end of the transmission. Figure 70. Transmission Waveforms (Mode 0) TXD Write to SBUF RXD D0 D1 D2 D3 D4 D5 D6 D7 TI Reception (Mode 0) To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting the REN bit. As shown in Figure 71, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0 bit is then shifted into the shift register. After eight sampling, the MSB (D7) is shifted into the shift register, and hardware asserts RI bit to indicate a completed reception. Software can then read the received byte from SBUF register. Figure 71. Reception Waveforms (Mode 0) TXD Write to SCON RXD Set REN, Clear RI D0 D1 D2 D3 D4 D5 D6 D7 RI 128 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Baud Rate Selection (Mode 0) In mode 0, baud rate can be either fixed or variable. As shown in Figure 72, the selection is done using M0SRC bit in BDRCON register. Figure 73 gives the baud rate calculation formulas for each baud rate source. Figure 72. Baud Rate Source Selection (Mode 0) CK_ SI /6 0 1 IBRG CLOCK To Serial Port M0SRC BDRCON.0 Figure 73. Baud Rate Formulas (Mode 0) Baud_Rate = Baud_Rate = 6 FCK_SI 6 BRL = 256 - a. Fixed Formula 2SMOD1 ⋅ FCK_SI ⋅ 32 ⋅ (256 -BRL) (1-SPD) 6 2SMOD1 ⋅ FCK_SI ⋅ 32 ⋅ Baud_Rate (1-SPD) b. Variable Formula The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 74 shows the Serial Port block diagram in such asynchronous modes. Asynchronous Modes (Modes 1, 2 and 3) Figure 74. Serial I/O Port Block Diagram (Modes 1, 2 and 3) SCON.6 SCON.7 SCON.3 SM1 SM0 TB8 Mode Decoder SBUF Tx SR TXD Rx SR RXD M3 M2 M1 M0 T1 CLOCK Mode & Clock Controller IBRG CLOCK CK_ SI Mode 1 SBUF Rx SM2 TI RI SCON.4 SCON.1 SCON.0 RB8 SCON.2 Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 75) consists of 10 bits: one start, eight data bits and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. When a data is received, the stop bit is read in the RB8 bit in SCON register. 129 4202F–SCR–07/2008 Figure 75. Data Frame Format (Mode 1) Mode 1 D0 D1 D2 D3 Start bit D4 D5 D6 D7 8-bit data Stop bit Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 76) consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alternatively, you can use the ninth bit as a command/data flag. Modes 2 and 3 Figure 76. Data Frame Format (Modes 2 and 3) Modes 2 and 3 D0 D1 D2 Start bit D3 D4 D5 9-bit data D6 D7 D8 Stop bit Transmission (Modes 1, 2 and 3) To initiate a transmission, write to SCON register, setting SM0 and SM1 bits according to Figure 69 on page 128, and setting the ninth bit by writing to TB8 bit. Then, writing the byte to be transmitted to SBUF register starts the transmission. Reception (Modes 1, 2 and 3) To prepare for a reception, write to SCON register, setting SM0 and SM1 bits according to Figure 69 on page 128, and setting REN bit. The actual reception is then initiated by a detected high-to-low transition on the RXD pin. Framing Error Detection (Modes 1, 2 and 3) Framing error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register as shown in Figure 77. When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two devices. If a valid stop bit is not found, the software sets FE bit in SCON register. Software may examine FE bit after each reception to check for data errors. Once set, only software or a chip reset clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on stop bit instead of the last data bit as detailed in Figure 75 and Figure 76. Figure 77. Framing Error Block Diagram Framing Error Controller FE 1 0 SM0/FE SCON.7 SM0 SMOD0 PCON.6 130 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Baud Rate Selection (Modes 1 and 3) In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud Rate Generator and allows different baud rate in reception and transmission. As shown in Figure 78 the selection is done using RBCK and TBCK bits in BDRCON register. Figure 79 gives the baud rate calculation formulas for each baud rate source while Table 76 details Internal Baud Rate Generator configuration for different peripheral clock frequencies and giving baud rates closer to the standard baud rates. Figure 78. Baud Rate Source Selection (Modes 1 and 3) T1 CLOCK IBRG CLOCK 0 1 To serial reception Port / 16 T1 CLOCK 0 To serial transmission Port / 16 1 IBRG CLOCK RBCK TBCK BDRCON.2 BDRCON.3 Figure 79. Baud Rate Formulas (Modes 1 and 3) Baud_Rate = BRL = 256 - 2SMOD1 ⋅ FCK_SI ⋅ 32 ⋅ (256 -BRL) (1-SPD) 6 6 2SMOD1 ⋅ FCK_SI ⋅ 32 ⋅ Baud_Rate (1-SPD) a. IBRG Formula Baud_Rate = TH1 = 256 - 2SMOD1 ⋅ FCK_T1 192 ⋅ (256 -TH1) 2SMOD1 ⋅ FCK_T1 192 ⋅ Baud_Rate b. T1 Formula 131 4202F–SCR–07/2008 Table 76. Internal Baud Rate Generator Value FCK_IDLE= 4 MHz FCK_IDLE= 8 MHz FCK_IDLE= 9.6 MHz Baud Rate SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% 115200 1 1 254 8.51 1 1 252 8.51 1 1 251 4.17 57600 1 1 252 8.51 1 1 247 3.55 1 1 246 4.17 38400 1 1 249 6.99 1 1 243 0.16 1 1 240 2.34 19200 1 1 243 0.16 1 1 230 0.16 1 1 225 0.81 9600 1 1 230 0.16 1 1 204 0.16 1 1 194 0.81 4800 1 1 204 0.16 1 1 152 0.16 1 1 131 0.00 FCK_IDLE= 12 MHz FCK_IDLE= 16 MHz FCK_IDLE= 24 MHz Baud Rate SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% 115200 1 1 249 6.99 1 1 247 3.55 1 1 243 0.16 57600 1 1 243 0.16 1 1 239 2.12 1 1 230 0.16 38400 1 1 236 2.34 1 1 230 0.16 1 1 217 0.16 19200 1 1 217 0.16 1 1 204 0.16 1 1 178 0.16 9600 1 1 178 0.16 1 1 152 0.16 1 1 100 0.16 4800 1 1 100 0.16 1 1 48 0.16 1 1 N/A N/A Baud Rate Selection (Mode 2) In mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of the peripheral clock frequency. As shown in Figure 80 the selection is done using SMOD1 bit in PCON register. Figure 81 gives the baud rate calculation formula depending on the selection. Figure 80. Baud Rate Generator Selection (Mode 2) CK_ SI x2 1 0 /32 To Serial Port SMOD1 PCON.7 Figure 81. Baud Rate Formula (Mode 2) Baud_Rate = 2SMOD1 ⋅ FCK_SI 32 For mode 0 for UART, thanks to the bit M0SRC located in BDRCON register (Table 82) 132 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Registers Table 77. Serial Control Register - SCON (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Description FE Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 in PCON register must be set to enable access to the FE bit 7 SM0 Serial Port Mode bit 0 (SMOD0=0) Refer to SM1 for serial port mode selection. SMOD0 in PCON register must be cleared to enable access to the SM0 bit 6 5 SM1 SM2 Serial port Mode bit 1 SM1 Mode SM0 DescriptionBaud Rate 0 0 1 0 1 0 0 1 2 Shift Register FCk_IDLE/6 8-bit UARTVariable 9-bit UARTFCK_IDLE /32 or /16 1 1 3 9-bit UARTVariable Serial port Mode 2 bit/Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. 4 REN 3 TB8 Reception Enable bit Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 2 RB8 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8/Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. 1 TI Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. This bit can aslo be set by software. 0 RI Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 65 and Figure 66 in the other modes. This bit can aslo be set by software. Reset Value = 0000 0000b (Bit addressable) 133 4202F–SCR–07/2008 Table 78. Slave Address Mask Register for UART - SADEN (B9h) 7 6 5 4 3 2 1 0 2 1 0 2 1 0 Reset Value = 0000 0000b Table 79. Slave Address Register for UART - SADDR (A9h) 7 6 5 4 3 Reset Value = 0000 0000b Table 80. Serial Buffer Register for UART - SBUF (99h) 7 6 5 4 3 Reset Value = XXXX XXXXb Table 81. Baud Rate Reload Register for the internal baud rate generator, UART - BRL (9Ah) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b Table 82. Baud Rate Control Register - BDRCON - (9Bh) 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD M0SRC Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. 7-5 - 4 BRR Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. 3 TBCK Transmission Baud rate Generator Selection bit for UART Cleared to select Timer 1 for the Baud Rate Generator. Set to select internal Baud Rate Generator. 2 RBCK Reception Baud Rate Generator Selection bit for UART Cleared to select Timer 1 for the Baud Rate Generator. Set to select internal Baud Rate Generator. 1 SPD 0 M0SRC Baud Rate Speed Control bit for UART Cleared to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source select bit in Mode 0 for UART Cleared to select FCK_SI /6 as the Baud Rate Generator. Set to select the internal Baud Rate Generator for UART in mode 0. Reset Value = XXX0 0000b (Not bit addressable) 134 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Serial Port Interface (SPI) Only for AT8xC5122. Features Features of the SPI module include the following: Signal Description The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. • Full-duplex, three-wire synchronous transfers • Master or Slave operation • Eight programmable Master clock rates • Serial clock with programmable polarity and phase • Master Mode fault error flag with MCU interrupt capability • Write collision flag protection Figure 82 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices: Figure 82. Typical SPI Bus Slave 1 MISO MOSI SCK SS MISO MOSI SCK SS VDD Slave 4 Slave 3 MISO MOSI SCK SS MISO MOSI SCK SS 0 1 2 3 MISO MOSI SCK SS PORT Master Slave 2 The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices. Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. Master Input Slave Output (MISO) This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines. 135 4202F–SCR–07/2008 Slave Select (SS) Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. Only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port pins (Figure 82). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Section “Error Conditions”, page 140). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The SS pin could be used as a general-purpose if the following conditions are met: Baud Rate • The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration can be found when only one Master is driving the network and there is no way that the SS pin will be pulled low. Therefore, the MODF flag in the SPSTA will never be set (1). • The Device is configured as a Slave with CPHA and SSDIS control bits set (2). This kind of configuration can happen when the system comprises one Master and one Slave only. Therefore, the device should always be selected and there is no reason that the Master uses the SS pin to select the communicating Slave device. In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of six clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. Table 83 gives the different clock rates selected by SPR2:SPR1:SPR0 Table 83. SPI Master Baud Rate Selection 136 SPR2:SPR1:SPR0 Clock Rate Baud Rate Divisor (BD) 000 Reserved N/A 001 FCK_SPI /4 4 010 FCK_SPI / 8 8 011 FCK_SPI /16 16 100 FCK_SPI /32 32 101 FCK_SPI /64 64 110 FCK_SPI /128 128 111 Reserved N/A 1. Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in this mode, the SS is used to start the transmission. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Functional Description Figure 83 shows a detailed structure of the SPI module. Figure 83. SPI Module Block Diagram Internal Bus SPDAT Shift Register IntClk Clock Divider 7 /4 /8 /16 /32 /64 /128 6 5 4 3 2 1 0 Receive Data Register Pin Control Logic Clock Logic MOSI MISO M S Clock Select SCK SS SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 SPCON SPI Interrupt Request SPI Control 8-bit bus 1-bit signal SPSTA SPIF WCOL Operating Modes - MODF - - - - The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Salve mode. The configuration and initialization of the SPI module is made through one register: • The Serial Peripheral Control register (SPCON) Once the SPI is configured, the data exchange is made using: • SPCON • The Serial Peripheral Status register (SPSTA) • The Serial Peripheral Data register (SPDAT) During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities. When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 84). 137 4202F–SCR–07/2008 Figure 84. Full-duplex Master-Slave Interconnection 8-bit Shift Register SPI Clock Generator MISO MISO MOSI MOSI SCK SS Master MCU Master Mode 8-bit Shift Register SCK VDD SS VSS Slave MCU The SPI operates in Master mode when the Master bit, MSTR (3), in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT. When the pin SS is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the SPDAT is resent. Slave Mode The SPI operates in Slave mode when the Master bit, MSTR (4), in the SPCON register is cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must be set to ’0’. SS must remain low until the transmission is complete. In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module. After a byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another byte enters the shift register (5). A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission. Transmission Formats 138 Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock Polarity (CPOL (6) ) and the Clock Phase (CPHA(4)). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 85 and Figure 86). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device. 3. The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Master SPI should be configured before the Slave SPI. 4. The SPI module should be configured as a Slave before it is enabled (SPEN set). 5. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. 6. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’). AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 85. Data Transmission Format (CPHA = 0) SCK Cycle Number 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 LSB SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) Capture Point Figure 86. Data Transmission Format (CPHA = 1) 1 2 3 4 5 6 7 8 MOSI (from Master) MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB MISO (from Slave) MSB bit6 bit5 bit4 bit3 bit2 bit1 SCK Cycle Number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) LSB SS (to Slave) Capture point As shown in Figure 85, the first SCK edge is the MSB capture strobe. Therefore the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each byte transmitted (Figure 87). Figure 87. CPHA/SS Timing MISO/MOSI Byte 1 Byte 2 Byte 3 Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) Figure 86 shows an SPI transmission in which CPHA is “1”. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmis- 139 4202F–SCR–07/2008 sions (Figure 87). This format may be preferable in systems having only one Master and only one Slave driving the MISO data line. Error Conditions The following flags in the SPSTA signal SPI error conditions. Mode Fault (MODF) MODF error bit in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: • An SPI receiver/error CPU interrupt request is generated. • The SPEN bit in SPCON is cleared. This disable the SPI. • The MSTR bit in SPCON is cleared. When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes ’0’. However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there is no way that another Master is attempting to drive the network. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin. Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT. Overrun Condition An overrun condition occurs when the Master device tries to send several data bytes and the Slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost. This condition is not detected by the SPI peripheral. SS Error Flag ( SSERR ) A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit ( reset of the SPI state machine ). Interrupts Two SPI status flags can generate a CPU interrupt requests: Table 84. SPI Interrupts Flag SPIF (SP data transfer) MODF (Mode Fault) Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = ’0’) Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. 140 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. Figure 88 gives a logical view of the above statements. Figure 88. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SPI CPU Interrupt Request SPI Receiver/error CPU Interrupt Request SSDIS Registers There are three registers in the module that provide control, status and data storage functions. These registers are described in the following paragraphs. Serial Peripheral Control Register (SPCON) The Serial Peripheral Control Register does the following: • Selects one of the Master clock rates • Configures the SPI module as Master or Slave • Selects serial clock polarity and phase • Enables the SPI module • Frees the SS pin for a general-purpose 141 4202F–SCR–07/2008 Table 85. Serial Peripheral Control Register - SPCON (C3h) 7 6 5 4 3 2 1 0 SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 Bit Number Bit Mnemonic R/W Mode 7 SPR2 RW 6 SPEN RW Description Serial Peripheral Rate 2 Bit with SPR1 and SPR0 define the clock rate Serial Peripheral Enable Clear to disable the SPI interface (internal reset of the SPI) Set to enable the SPI interface SS Disable 5 SSDIS RW 4 MSTR RW Clear to enable SS in both Master and Slave modes Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no effect if CPHA = ’0’ Serial Peripheral Master Clear to configure the SPI as a Slave Set to configure the SPI as a Master Clock Polarity 3 CPOL RW Clear to have the SCK set to ’0’ in idle state Set to have the SCK set to ’1’ in idle low Clock Phase 2 CPHA RW Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL) Set to have the data sampled when the SPSCK returns to idle state (see CPOL) Serial Peripheral Rate (SPR2:SPR1:SPR0) 000: Reserved 1 SPR1 RW 001: FCK_SPI /4 010: FCK_SPI/8 011: FCK_SPI/16 100: FCK_SPI/32 0 SPR0 RW 101: FCK_SPI/64 110: FCK_SPI/128 111: Reserved Reset Value = 00010100b 142 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • Inconsistent logic level on SS pin (mode fault error) Table 86. Serial Peripheral Status and Control Register - SPSTA (C4h) 7 6 5 4 3 2 1 0 SPIF WCOL SSERR MODF - - - - Bit Number Bit Mnemonic R/W Mode Description Serial Peripheral data transfer flag 7 SPIF R Clear by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. Write Collision flag 6 WCOL R Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected. Synchronous Serial Slave Error flag 5 SSERR R Set by hardware when SS is modified before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). Mode Fault 4 MODF R Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level 3-0 - RW Reserved The value read from this bit is indeterminate. Do not change these bits. Reset Value = 00X0XXXXb 143 4202F–SCR–07/2008 Serial Peripheral DATa Register (SPDAT) The Serial Peripheral Data Register (Table 87) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model. A read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. Table 87. Serial Peripheral Data Register - SPDAT (C5h) 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 R0 Bit Bit Number Mnemonic Description Receive data bits SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: 7-0 R7:0 Do not change SPR2, SPR1 and SPR0 Do not change CPHA and CPOL Do not change MSTR Clearing SPEN would immediately disable the peripheral Writing to the SPDAT will cause an overflow Reset Value = XXXX XXXXb 144 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Timers/Counters The AT8xC5122D implements two general-purpose, 16-bit Timers/Counters. Although they are identified as Timer 0, Timer 1, you can independently configure each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The Timer registers and associated control registers are implemented as addressable Special Function Registers (SFRs). Two of the SFRs provide programmable control of the Timers as follows: • Timer/Counter mode control register (TMOD) and Timer/Counter control register (TCON) control respectively Timer 0 and Timer 1. The various operating modes of each Timer/Counter are described below. Timer/Counter Operations For example, a basic operation is Timer registers THx and TLx (x= 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in the TCON register (see Table 88 on page 150) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows, it increments THx and when THx overflows it sets the Timer overflow flag (TFx) in the TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but the TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down system clock or the external pin Tx as the source for the counted signal. The TRx bit must be cleared when changing the operating mode, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx#= 0), the Timer register counts the divided-down system clock. The Timer register is incremented once every peripheral cycle. Exceptions are the Timer 2 Baud Rate and Clock-Out modes in which the Timer register is incremented by the system clock divided by two. For Counter operation (C/Tx#= 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled during every S5P2 state. The Programmer’s Guide describes the notation for the states in a peripheral cycle. When the sample is high in one cycle and low in the next one, the Counter is incremented. The new count value appears in the register during the next S3P1 state after the transition has been detected. Since it takes 12 states (24 oscillator periods) to recognize a negative transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. Timer 0 Timer 0 functions as either a Timer or an event Counter in four operating modes. Figure 89 through Figure 95 show the logic configuration of each mode. Timer 0 is controlled by the four lower bits of the TMOD register (see Table 89 on page 151) and bits 0, 1, 4 and 5 of the TCON register (see Table 88 on page 150). The TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and the operating mode (M10 and M00). The TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). 145 4202F–SCR–07/2008 For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets the TF0 flag and generates an interrupt request. It is important to stop the Timer/Counter before changing modes. Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo-32 prescaler implemented with the lower five bits of the TL0 register (see Figure 89). The upper three bits of the TL0 register are indeterminate and should be ignored. Prescaler overflow increments the TH0 register. Mode 0 (13-bit Timer) Figure 90 gives the overflow period calculation formula. Figure 89. Timer/Counter x (x= 0 or 1) in Mode 0 CK_Tx /6 0 THx (8 bits) 1 Tx TLx (5 bits) Overflow Timer x Interrupt Request TFx TCON reg C/Tx# TMOD reg INTx# GATEx TRx TMOD reg TCON reg Figure 90. Mode 0 Overflow Period Formula TFxPER = Mode 1 (16-bit Timer) 6 ⋅ (16384 – (THx, TLx)) FCK_Tx Mode 1 configures Timer 0 as a 16-bit Timer with the TH0 and TL0 registers connected in a cascade (see Figure 91). The selected input increments the TL0 register. Figure 92 gives the overflow period calculation formula when in timer mode. 146 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 91. Timer/Counter x (x = 0 or 1) in Mode 1 CK_Tx /6 0 1 THx (8 bits) TLx (8 bits) Overflow TFx TCON reg Timer x Interrupt Request C/Tx# TMOD reg Tx INTx# GATEx TMOD reg TRx TCON reg Figure 92. Mode 1 Overflow Period Formula TFxPER = Mode 2 (8-bit Timer with AutoReload) 6 ⋅ (65536 – (THx, TLx)) FCK_Tx Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from the TH0 register (see Figure 93). TL0 overflow sets the TF0 flag in the TCON register and reloads TL0 with the contents of TH0, which is preset by the software. When the interrupt request is serviced, the hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to the TH0 register. Figure 94 gives the autoreload period calculation formula when in timer mode. Figure 93. Timer/Counter x (x = 0 or 1) in Mode 2 CK_Tx /6 0 TLx (8 bits) 1 Tx Overflow TFx TCON reg Timer x Interrupt Request C/Tx# TMOD reg INTx# THx (8 bits) GATEx TMOD reg TRx TCON reg Figure 94. Mode 2 Autoreload Period Formula TFxPER= 6 ⋅ (256 – THx) FCK_Tx 147 4202F–SCR–07/2008 Mode 3 configures Timer 0 so that registers TL0 and TH0 operate as 8-bit Timers (see Figure 95). This mode is provided for applications requiring an additional 8-bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in the TMOD register, and TR0 and TF0 in the TCON register in the normal manner. TH0 is locked into a Timer function (counting FUART) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3. Mode 3 (Two 8-bit Timers) Figure 96 gives the autoreload period calculation formulas for both TF0 and TF1 flags. Figure 95. Timer/Counter 0 in Mode 3: Two 8-bit Counters CK_T0 /6 0 1 TL0 (8 bits) Overflow TH0 (8 bits) Overflow T0 TF0 TCON.5 Timer 0 Interrupt Request C/T0# TMOD.2 INT0# GATE0 TMOD.3 CK_T0 TR0 TCON.4 /6 TF1 TCON.7 Timer 1 Interrupt Request TR1 TCON.6 Figure 96. Mode 3 Overflow Period Formula TF0PER = Timer 1 148 6 ⋅ (256 – TL0) FCK_T0 TF1PER = 6 ⋅ (256 – TH0) FCK_T0 Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The following comments help to understand the differences: • Timer 1 functions as either a Timer or an event Counter in three operating modes. Figure 89 through Figure 93 show the logical configuration for modes 0, 1, and 2. Mode 3 of Timer 1 is a hold-count mode. • Timer 1 is controlled by the four high-order bits of the TMOD register (see Table 89 on page 151) and bits 2, 3, 6 and 7 of the TCON register (see Table 88 on page 150). The TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and the operating mode (M11 and M01). The TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and the interrupt type control bit (IT1). • Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. • For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. • Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag and generates an interrupt request. AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 • When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. • It is important to stop the Timer/Counter before changing modes. Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 89). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments the TH1 register. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 91). The selected input increments the TL1 register. Mode 2 (8-bit Timer with AutoReload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from the TH1 register on overflow (see Figure 93). TL1 overflow sets the TF1 flag in the TCON register and reloads TL1 with the contents of TH1, which is preset by the software. The reload leaves TH1 unchanged. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when the TR1 run control bit is not available i.e. when Timer 0 is in mode 3. 149 4202F–SCR–07/2008 Registers Timer/Counter Control Register Table 88. TCON (S:88h) 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow flag Cleared by the hardware when processor vectors interrupt routine. Set by the hardware when Timer 1 register overflows. 6 TR1 Timer 1 Run Control bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. 5 TF0 Timer 0 Overflow flag Cleared by the hardware when processor vectors interrupt routine or by software when the interrupt is disabled Set by the hardware when Timer 0 register overflows. 4 TR0 Timer 0 Run Control bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. 3 IE1 Interrupt 1 Edge flag Cleared by the hardware when interrupt is processed if edge-triggered (see IT1). Set by the hardware when external interrupt is detected on the INT1# pin. 2 IT1 Interrupt 1 Type Control bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. 1 IE0 Interrupt 0 Edge flag Cleared by the hardware when interrupt is processed if edge-triggered (see IT0). Set by the hardware when external interrupt is detected on INT0# pin. 0 IT0 Interrupt 0 Type Control bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0. Reset Value = 0000 0000b 150 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 89. Timer/Counter Mode Control Register - TMOD (S:89h) 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic Description 7 GATE1 Timer 1 Gating Control bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. 5 M11 4 M01 3 GATE0 Timer 0 Gating Control bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. 2 C/T0# Timer 0 Counter/Timer Select bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. 1 M10 0 M00 Timer 1 Mode Select bits M01 Operating mode M11 0 0 Mode 0:8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1:16-bit Timer/Counter. 1 0 Mode 2:8-bit auto-reload Timer/Counter (TL1) reloaded from TH1 at overflow. 1 1 Mode 3:Timer 1 halted. Retains count. Timer 0 Mode Select bit M00 Operating mode M10 0 0 Mode 0:8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1:16-bit Timer/Counter. 1 0 Mode 2:8-bit auto-reload Timer/Counter (TL0). Reloaded from TH0 at overflow. 1 1 Mode 3:TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits. Reset Value = 0000 0000b 151 4202F–SCR–07/2008 Table 90. Timer 0 High Byte Register - TH0 (S:8Ch) 7 6 5 4 3 2 1 0 2 1 0 2 1 0 2 1 0 Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0 Reset Value = 0000 0000b Table 91. Timer 0 Low Byte Register - TL0 (S:8Ah) 7 Bit Number 6 5 4 3 Bit Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 92. Timer 1 High Byte Register - TH1 (S:8Dh) 7 6 5 4 3 Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 1 Reset Value = 0000 0000b Table 93. Timer 1 Low Byte Register - TL1 (S:8Bh) 7 6 5 4 3 Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1 Reset Value = 0000 0000b 152 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Keyboard Interface Only for AT8xC5122. Introduction The AT83R5122, AT8xC5122/23 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P5 and allow to exit from idle and power-down modes. Description The keyboard interfaces with the C51 core through 3 special function registers: KBLS, the Keyboard Level Selection register (Table 96 on page 156), KBE, The Keyboard interrupt Enable register (Table 95 on page 155), and KBF, the Keyboard Flag register (Table ). Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. An interrupt enable bit ( KBD in IE1) allows global enable or disable of the keyboard interrupt (see Figure 97). As detailed in Figure 98 each keyboard input has the capability to detect a programmable level according to KBLS.x bit value. Level detection is then reported in interrupt flags KBF.x that can be masked by software using KBE.x bits. This structure allows keyboard arrangement from 1 by n to 8 by n matrix and allows usage of P5 inputs for other purpose. The KBF.x flags are set by hardware when an active level is on input P5.x. They are automatically reset after any read access on KBF. If the content of KBF must be analyzed, the first read instruction must transfer KBF contend to another location. The KBF register cannot be written by software. Figure 97. Keyboard Interface Block Diagram P5.0 Input Circuitry P5.1 Input Circuitry P5.2 Input Circuitry P5.3 Input Circuitry P5.4 Input Circuitry KBDIT P5.5 Input Circuitry P5.6 Input Circuitry P5.7 Input Circuitry EKB Keyboard Interface Interrupt Request IEN1.0 Figure 98. Keyboard Input Circuitry P5.x 0 1 KBF.x KBE.x KBLS.x 153 4202F–SCR–07/2008 Power Reduction Mode P5 inputs allow exit from idle and power-down modes as detailed in Section "PowerDown Mode". Registers Table 94. Keyboard Flag Register - KBF (9Eh) 7 6 5 4 3 2 1 0 KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description KBF7 Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBE.7 bit in KBE register is set. Cleared by hardware after the read of the KBF register. KBF6 Keyboard line 6 flag Set by hardware when the Port line 6 detects a programmed level. It generates a Keyboard interrupt request if the KBE.6 bit in KBE register is set. Cleared by hardware after the read of the KBF register. KBF5 Keyboard line 5 flag Set by hardware when the Port line 5 detects a programmed level. It generates a Keyboard interrupt request if the KBE.5 bit in KBE register is set. Cleared by hardware after the read of the KBF register. KBF4 Keyboard line 4 flag Set by hardware when the Port line 4 detects a programmed level. It generates a Keyboard interrupt request if the KBE.4 bit in KBE register is set. Cleared by hardware after the read of the KBF register. KBF3 Keyboard line 3 flag Set by hardware when the Port line 3 detects a programmed level. It generates a Keyboard interrupt request if the KBE.3 bit in KBE register is set. Cleared by hardware after the read of the KBF register. KBF2 Keyboard line 2 flag Set by hardware when the Port line 2 detects a programmed level. It generates a Keyboard interrupt request if the KBE.2 bit in KBE register is set. Cleared by hardware after the read of the KBF register. KBF1 Keyboard line 1 flag Set by hardware when the Port line 1 detects a programmed level. It generates a Keyboard interrupt request if the KBE.1 bit in KBE register is set. Cleared by hardware after the read of the KBF register. KBF0 Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a Keyboard interrupt request if the KBE.0 bit in KBE register is set. Cleared by hardware after the read of the KBF register. Reset Value = 0000 0000b 154 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 95. Keyboard Input Enable Register - KBE (9Dh) 7 6 5 4 3 2 1 0 KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Bit Number Bit Mnemonic 7 KBE7 Keyboard line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. 6 KBE6 Keyboard line 6 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.6 bit in KBF register to generate an interrupt request. 5 KBE5 Keyboard line 5 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.5 bit in KBF register to generate an interrupt request. 4 KBE4 Keyboard line 4 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.4 bit in KBF register to generate an interrupt request. 3 KBE3 Keyboard line 3 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.3 bit in KBF register to generate an interrupt request. 2 KBE2 Keyboard line 2 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.2 bit in KBF register to generate an interrupt request. 1 KBE1 Keyboard line 1 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.1 bit in KBF register to generate an interrupt request. 0 KBE0 Keyboard line 0 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.0 bit in KBF register to generate an interrupt request. Description Reset Value = 0000 0000b 155 4202F–SCR–07/2008 Table 96. Keyboard Level Selector Register - KBLS (9Ch) 7 6 5 4 3 2 1 0 KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 Bit Number Bit Mnemonic Description 7 KBLS7 Keyboard line 7 Level Selection bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. 6 KBLS6 Keyboard line 6 Level Selection bit Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6. 5 KBLS5 Keyboard line 5 Level Selection bit Cleared to enable a low level detection on Port line 5. Set to enable a high level detection on Port line 5. 4 KBLS4 Keyboard line 4 Level Selection bit Cleared to enable a low level detection on Port line 4. Set to enable a high level detection on Port line 4. 3 KBLS3 Keyboard line 3 Level Selection bit Cleared to enable a low level detection on Port line 3. Set to enable a high level detection on Port line 3. 2 KBLS2 Keyboard line 2 Level Selection bit Cleared to enable a low level detection on Port line 2. Set to enable a high level detection on Port line 2. 1 KBLS1 Keyboard line 1 Level Selection bit Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. 0 KBLS0 Keyboard line 0 Level Selection bit Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. Reset Value = 0000 0000b 156 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Interrupt System Introduction Interrupt System Description The AT83R5122, AT8xC5122/23 implements an interrupt controller with 15 inputs but only 9 are used for : – two external interrupts (INT0 and INT1) – two timer interrupts (timers 0, 1), – the UART interface – the SPI interface – the keyboard interface – the USB interface – the Smart Card Interface. Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable registers (Table 98 on page 160 and Table 99 on page 161). These registers also contain a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority Low registers (Table 101 on page 162 and Table 103 on page 164) and in the Interrupt Priority High register (Table 102 on page 163 and Table 105 on page 166) shows the bit values and priority levels associated with each combination. A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced first. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 97. Priority Level Bit Values IPH.x IPL.x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) 157 4202F–SCR–07/2008 Figure 99. Interrupt Control System 0 INT0# 1 00 01 10 11 IE0 TCON.1 EX0 IEN0.0 IT0 TCON.0 00 01 10 11 TF0 TCON.5 RXD Highest Priority Interrupts ET0 IEN0.1 RXIT ISEL.4 RXEN ISEL.0 INT1 1 0 0 1 OELEV ISEL.3 CPRES OEEN ISEL.2 00 01 10 11 IE1 TCON.3 EX1 IEN0.2 IT1 TCON.2 0 PRESIT ISEL.5 1 CPLEV PRESEN ISEL.7 ISEL.1 00 01 10 11 TF1 TCON.7 RXD TXD P5.x 0 1 KBLSx ET1 IEN0.3 RI SCON.0 SERIAL INTERFACE CONTROLLER TI SCON.1 00 01 10 11 ES IEN0.4 00 01 10 11 KBFx EKB (1) IEN1.0 KBEx MISO MOSI SCK CIO CCLK 00 01 10 11 SPI CONTROLLER (1) SMART CARD INTERFACE ESPI (1) IEN1.2 00 01 10 11 CONTROLLER ESCI IEN1.3 D+ USB D- CONTROLLER EUSB IEN1.6 note (1) : Not applicable to AT83C5123 158 00 01 10 11 EA IEN0.7 Interrupt Enable IPH/L Priority Enable Lowest Priority Interrupts AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 INT1 Interrupt Vector The INT1 interrupt is multiplexed with the following three inputs: • INT1 : Standard 8051 interrupt input • RXD : Received data on UART • CPRES: Insertion or remove of the main card The setting configurations for each input is detailed below. INT1 Input This interrupt input is active under the following conditions : • It must be enabled by OEEN Bit (ISEL Register) • It can be active on a level or falling edge following IT1 Bit (TCON Register) status • If level triggering selection is set, the active level 0 or 1 can be selected with OELEV Bit (ISEL Register) The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is cleared when interrupt is processed. RXD Input A second vector interrupt input is the reception of a character. UART Rx input can generate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA must also be set. Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on P3.0/RXD input. CPRES Input The third input is the detection of a level change on CPRES input (P1.2). This input can generate an interrupt if enabled with PRESEN (ISEL.1) , EX1 (IE0.2) and EA (IE0.7) Bits. This detection is done according to the level selected with Bit CPLEV (ISEL.7). Then the Bit PRESIT (ISEL.5) is set by hardware when the triggering conditions are met. This Bit must be cleared by software. 159 4202F–SCR–07/2008 Registers Table 98. Interrupt Enable Register 0 - IEN0 (A8h) 7 6 5 4 3 2 1 0 EA - - ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description Enable All interrupt bit 7 EA 6-5 - 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Cleared to disable all interrupts. Set to enable all interrupts. Reserved The value read from this bit is indeterminate. Do not change these bits. Serial port Enable bit Cleared to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Cleared to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 1 Enable bit Cleared to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Cleared to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b (Bit addressable) 160 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 99. Interrupt Enable Register 1 - IEN1 (B1h) for AT8xC5122 7 6 5 4 3 2 1 0 - EUSB - - ESCI ESPI - EKB Bit Bit Number Mnemonic 7 - 6 EUSB 5-4 - 3 ESCI SCI interrupt Enable bit Cleared to disable SCIinterrupt . Set to enable SCI interrupt. 2 ESPI SPI interrupt Enable bit Cleared to disable SPI interrupt . Set to enable SPI interrupt. 1 - 0 EKB Description Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Enable bit Cleared to disable USB interrupt . Set to enable USB interrupt. Reserved The value read from this bit is indeterminate. Do not change these bits. Reserved The value read from this bit is indeterminate. Do not change this bit. Keyboard interrupt Enable bit Cleared to disable keyboard interrupt . Set to enable keyboard interrupt. Reset Value = X0XX 00X0b (Bit addressable) 161 4202F–SCR–07/2008 Table 100. Interrupt Enable Register 1 - IEN1 (B1h) for AT83C5123 7 6 5 4 3 - EUSB - - ESCI Bit Bit Number Mnemonic 7 - 6 EUSB 5-4 - 3 ESCI 2 1 0 - Description Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Enable bit Reserved The value read from this bit is indeterminate. Do not change these bits. SCI interrupt Enable bit Cleared to disable SCIinterrupt . Set to enable SCI interrupt. Reserved The value read from this bit is indeterminate. Do not change this bit. 2 1 Cleared to disable USB interrupt . Set to enable USB interrupt. - Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change this bit. 0 Reset Value = X0XX 0XXXb (Bit addressable) Table 101. Interrupt Priority Low Register 0 - IPL0 (B8h) 7 6 5 4 3 2 1 0 - - - PSL PT1L PX1L PT0L PX0L Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. 7-5 - 4 PSL Serial port Priority bit Refer to PSH for priority level. 3 PT1L Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1L External interrupt 1 Priority bit Refer to PX1H for priority level. 1 PT0L Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. 0 PX0L External interrupt 0 Priority bit Refer to PX0H for priority level. Reset Value = X000 0000b (Bit addressable) 162 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 102. Interrupt Priority High Register 0 - IPH0 (B7h) 7 6 5 4 3 2 1 0 - - - PSH PT1H PX1H PT0H PX0H Bit Number Mnemonic 7-5 - Bit Description Reserved The value read from this bit is indeterminate. Do not change these bits. Serial port Priority High bit 4 PSH PSH 0 0 1 1 PSL 0 1 0 1 Priority Level Lowest Highest Timer 1 overflow interrupt Priority High bit 3 PT1H PT1H 0 0 1 1 PT1L 0 1 0 1 Priority Level Lowest Highest External interrupt 1 Priority High bit 2 PX1H PX1H 0 0 1 1 PX1L 0 1 0 1 Priority Level Lowest Highest Timer 0 overflow interrupt Priority High bit 1 PT0H PT0H 0 0 1 1 PT0L 0 1 0 1 Priority Level Lowest Highest External interrupt 0 Priority High bit 0 PX0H PX0H 0 0 1 1 PX0L 0 1 0 1 Priority Level Lowest Highest Reset Value = X000 0000b (Not bit addressable) 163 4202F–SCR–07/2008 Table 103. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT8xC5122 7 6 5 4 3 2 1 0 - PUSBL - - PSCIL PSPIL - PKBDL Bit Number Bit Mnemonic Description Reserved 7 - 6 PUSBL 5-4 - 3 PSCIL SCI Interrupt Priority bit Refer to PSPIH for priority level. 2 PSPIL SPI Interrupt Priority bit Refer to PSPIH for priority level. 1 - 0 PKBL The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Priority bit Refer to PUSBH for priority level. Reserved The value read from this bit is indeterminate. Do not change these bits. Reserved The value read from this bit is indeterminate. Do not change this bit. Keyboard Interrupt Priority bit Refer to PKBDH for priority level. Reset Value = X00X 00X0b (Bit addressable) 164 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 104. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT83C5123 7 6 5 4 3 - PUSBL - - PSCIL Bit Number 6 PUSBL 5-4 - 3 PSCIL 0 0 Bit - 1 1 Mnemonic Description 7 2 2 Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Priority bit Refer to PUSBH for priority level. Reserved The value read from this bit is indeterminate. Do not change these bits. SCI Interrupt Priority bit Refer to PSPIH for priority level. Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change this bit. Reset Value = X0XX 0XXXb (Bit addressable) 165 4202F–SCR–07/2008 Table 105. Interrupt Priority High Register 1 - IPH1 (B3h) for AT8xC5122 7 6 5 4 3 2 - PUSBH - - PSCIH 1 0 - Bit Bit Number Mnemonic 7 - 6 PUSBH 5-4 - Description Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Priotity High bit Priority Level PUSBH PUSBL 0 0 Lowest 0 1 1 0 1 1 Highest Reserved The value read from this bit is indeterminate. Do not change these bits. SCI Interrupt Priority High bit 3 PSCIH PSCIH 0 0 1 1 PSCIL 0 1 0 1 Priority Level Lowest Highest SPI Interrupt Priority High bit 2 1 PSPIH - PSPIH 0 0 1 1 PSPIL 0 1 0 1 Priority Level Lowest Highest Reserved The value read from this bit is indeterminate. Do not change this bit. Keyboard Interrupt Priority High bit 0 PKBH PKBDH 0 0 1 1 PKBDL 0 1 0 1 Priority Level Lowest Highest Reset Value = XXXX X000b (Not bit addressable) 166 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 106. Interrupt Priority High Register 1 - IPH1 (B3h) for AT83C5123 7 6 5 4 3 2 1 0 - PUSBH - - PSCIH - - - Bit Bit Number Mnemonic 7 - 6 PUSBH 5-4 - Description Reserved The value read from this bit is indeterminate. Do not change this bit. USB Interrupt Priotity High bit Priority Level PUSBH PUSBL 0 0 Lowest 0 1 1 0 1 1 Highest Reserved The value read from this bit is indeterminate. Do not change these bits. SCI Interrupt Priority High bit 3 PSCIH 0 PSCIL 0 1 0 1 Priority Level Lowest Highest Reserved The value read from this bit is indeterminate. Do not change these bits. 2 1 PSCIH 0 0 1 1 - Reserved The value read from this bit is indeterminate. Do not change this bit. Reserved The value read from this bit is indeterminate. Do not change these bits. Reset Value = X0XX 0XXXb (Not bit addressable) 167 4202F–SCR–07/2008 Table 107. Interrupt Enable Register - ISEL (S:A1h) 7 6 5 4 3 2 1 0 CPLEV - PRESIT RXIT OELEV OEEN PRESEN RXEN Bit Bit Number Mnemonic Description Card presence detection level 7 CPLEV This bit indicates which CPRES level will bring about an interrupt Set this bit to indicate that Card Presence IT will appear if CPRES is at high level. Clear this bit to indicate that Card Presence IT will appear if CPRES is at low level. 6 - 5 PRESIT Reserved The value read from this bit is indeterminate. Do not change this bit. Card presence detection interrupt flag Set by hardware Must be cleared by software Received data interrupt flag 4 RXIT Set by hardware Must be cleared by software 3 OELEV INT1 signal active level Set this bit to indicate that high level is active. Clear this bit to indicate that low level is active. INT1 Interrupt Disable bit 2 OEEN Clear to disable INT1 interrupt Set to enable INT1 interrupt Card presence detection Interrupt Enable bit 1 PRESEN Clear to disable the card presence detection interrupt coming from SCIB. Set to enable the card presence detection interrupt coming from SCIB. Received data Interrupt Enable bit 0 RXEN Clear to disable the RxD interrupt. Set to enable the RxD interrupt (a minimal bit width of 100 μs is required to wake up from power-down) . Reset Value = 0000 0000b 168 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Interrupt Sources and Vectors Table 108. Interrupt Vectors Polling Priority at Same Level Interrupt Source 0 Reset (Highest Priority) Vector Address C:0000h INT0 1 C:0003h Timer 0 2 C:000Bh INT1 3 C:0013h Timer 1 4 C:001Bh UART 6 C:0023h Reserved 7 C:002Bh 5 C:0033h 8 C:003Bh 9 C:0043h 10 C:004Bh Smart Card Controller 11 C:0053h Reserved 12 C:005Bh Reserved 13 C:0063h USB Controller 14 C:006Bh Reserved Keyboard Controller (1) Reserved SPI Controller (1) Reserved Note: 15 (Lowest Priority) C:0073h 1. Only fot AT8xC5122 169 4202F–SCR–07/2008 Microcontroller Reset Introduction The internal reset is used to start up (cold reset) or to re-start (warm reset) the microcontroller activity. When the reset is applied (active state), all internal registers are initialized so that the microcontroller starts from a known and clean state for the program always runs as expected. The reset is released (inactive state) when the following conditions are internally met : – The power supply has reatched a minimum level which garantees that the microcontroller works properly – The on-chip oscillator has reached a minimum oscillation level which ensures a good noise to signal ratio and a correct internal duty cycle – the active state duration is at least two machine cycles. If one of the above conditions is not met the microcontroller is not correctly reset and might not work properly. The internal reset comes from four different sources : – Reset pin – Power On Reset (POR) – Power Fail Detector (PFD) – Hardware Watch-Dog Timer (WDT) Figure 100. Reset bock diagram Vcc VCore 3.3V Internal Digital Regulator POR PFD C51 Core Watch Dog Timer Internal Reset RST Microcontroller 170 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Power On Reset (POR) The role of the POR is to monitor the power supply rise of the microcontroller core and release the internal reset only when the internal voltage exceeds the VPFDP threshold from which the microcontroller core is stable (see Figure 101). This feature replaces the external reset function and therefore avoid the use of external components on the reset pin. Power Fail Detector (PFD) The role of the PFD is to monitor the power supply falls during a steady state condition in order to suspend the microcontroller and peripherals activity as soon as the power supply drops below the VPFDM threshold from which the microcontroller’s core might become instable (see Figure 101). The PDF suspends the microcontroller’s activity by holding the microcontroller under a reset state to avoid an unpredictable behaviour. A filter prevents the system from reseting when glitches lower than 50 ns duration are carried on Vcore. See Figure 101 and Figure 102 on page 172. 171 4202F–SCR–07/2008 Figure 101. Static behaviour of POR and PFD VCore VPFDP POR PFD POR VPFDM t Internal Reset 1 0 Figure 102. Dynamic behaviour of POR and PFD VCore VPFDP VPFDM POR t>50ns PFD POR t<50ns t Internal Reset 1 0 172 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Reset pin As explained in the POR section there is no need to use the reset pin as the internal reset function at power up is ensured by the POR. Anyway, if some applications requires a long reset, a reset controlled by the user or a reset controlled by external superviser device, the use of the reset pin is necessary. Long Reset As the pad integrates an internal pull-up of 10K, only an external capacitor of at least 10 μF is required to have an impact on the reset duration. Figure 103. Long Reset Vcc 10 K RST Internal Reset Microcontrolleur 10 μF Reset Controlled by the User The external capacitor is not needed if no long reset is required. Figure 104. Reset Controlled by the User Vcc 10 K RST Internal Reset Microcontrolleur 173 4202F–SCR–07/2008 Reset Controlled by an External Superviser Device As the reset pin can be forced in output by the Watch-Dog timer (WDT) or the POR/PFD features, there can be a conflict between the external superviser device and the microcontroller’s reset pin when in one side the external superviser is pulling the reset pin to VCC and in another side the WDT or POR/PFD features tries to force the reset pin to ground. Therefore, it recommended to insert a series resistor of 1.8K +/-10% or a diode (1N4148 for instance) between the external superviser device and the reset pin as detailed in the following figures. Figure 105. Use of an External Serial Resistor Microcontrolleur Vcc 10 K Superviser device 1.8 K RST Power On Reset Power Fail Detector Watchdog Timer To other on-board circuitry Figure 106. Use of an External Diode Microcontrolleur Vcc 1N4148 Superviser device 10 K RST Power On Reset Power Fail Detector Watchdog Timer To other on-board circuitry 174 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Watchdog Timer The AT83R5122, AT8xC5122/23 microcontrollers contain a powerfull programmable hardware Watchdog Timer (WDT) that automatically resets the chip if its software fails to reset the WDT before the selected time interval has elapsed. It permits large timeout ranking from 4ms to 524ms @ FCK_WD = 24 MHz / X2 This WDT consist of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programmation (WDTPRG) register. When exiting the reset, the WDT is, by default, disabled. To activate the WDT, the user has to write the sequence 1EH and E1H into WDRST register. When the Watchdog Timer is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. The WDT is controlled by two registers (WDTRST and WDTPRG). Figure 107. Watchdog Timer Decoder RESET WR Control WDTRST Enable 14-bit COUNTER FCK_WD 7 - bit COUNTER Outputs - - - - - WDTPRG 2 1 0 RESET 175 4202F–SCR–07/2008 Table 109. Watchdog Timer Out Register - WDTPRG (0A7h) 7 6 5 4 3 2 1 0 - - - - - S2 S1 S0 Bit Bit Number Mnemonic 7-3 - 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Description Reserved The value read from this bit is indeterminate. Do not change these bits. Reset Value = XXXX X000b The three lower bits (S0, S1, S2) located into WDTPRG register enables to program the WDT duration. Table 110. Machine Cycle Count S2 S1 S0 Machine Cycle Count 0 0 0 214 - 1 0 0 1 215 - 1 0 1 0 216 - 1 0 1 1 217 - 1 1 0 0 218 - 1 1 0 1 219 - 1 1 1 0 220 - 1 1 1 1 221 - 1 To compute WD Timeout, the following formula must be applied: Time Out = 6 * (214 * 2 Svalue - 1 ) / FCK_WD Note: 176 Svalue represents the decimal value of (S2 S1 S0) AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table 111. Timeout value for FCK_WD = 24 MHz / X2 S2 S1 S0 Timeout for FCK_WD= 24 MHz / X2 0 0 0 4.10 ms 0 0 1 8.19 ms 0 1 0 16.38 ms 0 1 1 32.77 ms 1 0 0 65.54 ms 1 0 1 131.07 ms 1 1 0 262.14 ms 1 1 1 524.29 ms Table 112. Watchdog Timer Enable register (Write Only) - WDTRST (A6h) 7 6 5 4 3 2 1 0 - - - - - - - - Reset Value = XXXX XXXXb The WDTRST register is used to reset / enable the WDT by writing 1EH then E1H in sequence. 177 4202F–SCR–07/2008 Power Management Before activating the Idle Mode or Power Down Mode, the CPU clock must be switched to on-chip oscillator source if the PLL is used to fed the CPU clock. Idle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high level. There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. Power Down Mode To save maximum power, a power-down mode can be invoked by software (see Table 13, PCON register). WARNING: To minimize power consumption, all peripherals and I/Os with static current consumption must be set in the proper state. I/Os programmed with low speed output configuration (KB_OUT) must be switch to push-pull or Standard C51 configuration before entering power-down. The CVCC generator must also be switch off. In power-down mode, the oscillator is stopped and the instruction that invoked powerdown mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from powerdown. To properly terminate power-down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 , INT1, Keyboard, Card insertion/removal and USB Interrupts are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power-down mode, 1024 clocks are necessary to exit to power-down mode and enter in operating mode. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 108. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power-down exit will be completed when the first input is released. In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put AT83R5122, AT8xC5122/23 into power-down mode. 178 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 108. Power-down Exit Waveform INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. Note: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Table shows the state of ports during idle and power-down modes. Table State of Ports Mode Program Memory ALE PSEN P0 (1) P1 P2 P3 P4 P5 Port Data Port Data Port Data Port Data Port Data Idle Internal 1 1 Port Data Idle External 1 1 Floating Port Data Address Port Data Port Data Port Data Power-down Internal 0 0 Port Dat* Port Data Port Data Port Data Port Data Port Data Power-down External 0 0 Floating Port Data Port Data Port Data Port Data Port Data Note: 1. Port 0 can force a 0 level. A "one" will leave port floating. Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. 179 4202F–SCR–07/2008 USB Interface Suspend The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for more than 3 ms. This triggers a USB interrupt if enabled. In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active. The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-up event is detected. The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit in the USBCON register. 2. If CPU clock is fed from PLL, the on-chip oscillator must be selected to fed the CPU clock. 3. Disable the PLL by clearing the PLLEN bit in the PLLCON register. Resume When the USB controller is in Suspend state, the Resume detection is active even if all the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the SUSPCLK bit in the USBCON register if needed. The firmware has to clear the SPINT bit in the USBINT register before any other USB operation in order to wake up the USB controller from its Suspend mode. The USB controller is then re-activated. 180 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Figure 109. Example of a Suspend/Resume Management USB Controller Init SPINT Detection of a SUSPEND State Clear SPINT Put the USB pads in power down mode Set SUSPCLK Disable PLL microcontroller in power-down Detection of a RESUME State WUPCPU Note : WUPCPU bit must be Cleared before enabling the PLL Clear SUSPCLK Clear WUPCPU bit Enable PLL Warning: The core must be switched in external clock mode before disabling the PLL. Smart Card Interface Entering in Power-down Mode In order to reduce the power consumption, a power-down or idle mode can be invoked by software (see Table 13, PCON register). Before activating these modes the application will need to: Power-off the Smart Card Interface by applying the following sequence: • Set CRST pin at low level by clearing the bit CARDRST in SCCON register. • Set CCLK pin at low level by clearing the bit CLK then the CARDCLK in SCCON register. • Set CIO pin at low level by clearing the bit UART in SCICR register then the bit CARDIO in SCCON register. • Power the Smart Interface off by clearing the CARDVCC bit in SCCON register. This instruction enables to switch DC/DC converter off. CPRES input: • Set the bit PRSEN in ISEL register • Set the bit EX1 in IE0 register • Set the bit EA in the IE0 register • Invert the bit CPLEV in ISEL register (INT1 interrupt vector) • Clear the bit PRESIT in the ISEL register 181 4202F–SCR–07/2008 Exiting from Power-down Mode The microcontroller will exit from Power-down or Idle modes upon a reset or INT1 interrupt which is a multiplexing of the interruptions generated by the CPRES pin (Card detection), RxD flag (UART reception) and INT1 pin. Keyboard Interface The keyboard interface applies only to AT8xC5122 version. Entering in Power-down Mode In order to reduce the power consumption, the microcontroller can be set in power-down or idle mode by software (see Table 13, PCON register). Before activating these modes the application will need to configure the keyboard interface as follows: • Set all keyboard’s ouputs pins KB Rx at low level by writing a 0 on the ports. This operation has a double effect: – any key that is pressed generates an interrupt capable of waking-up the microcontroller, – Set all bits KBE.x in KBE registers to enable interrupts. Exiting from Power-down Mode The microcontroller will exit from Power-down Mode upon a reset or any interrupt generated by a key press. Note that 1024 clocks are necessary to exit from power-down mode when a keyboard interrupt occurs. This means that there will be a delay between the time at which the key is pressed and the time at which the application is able to identify the key. Watchdog Timer during Power-down and Idle Mode In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode the user does not need to service the WDT. There are 2 methods of exiting Power-down mode : by a hardware reset or by a level activated external interrupt which is enabled prior to entering power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever AT8xC5122D is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting while the microcontroller is in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. 182 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Registers Table 113. Power Control Register - PCON (S:87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 6 SMOD0 Serial Port Mode bit 1 for UART Set to select double baud rate in mode 1,2 or 3 Serial Port Mode bit 0 for UART Cleared to select SM0 bit in SCON register Set to select FE bit in SCON register 5 - Reserved The value read from this bit is indeterminate. Do not change this bit. Power-Off Flag (Only for ROM version parts) Cleared to recognize next reset type 4 POF Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software Warning : in CRAM and FLASH versions, this bit is reserved. General purpose Flag 3 GF1 Cleared by user for general-purpose usage Set by user for general-purpose usage General purpose Flag 2 GF0 Cleared by user for general-purpose usage Set by user for general-purpose usage Power-Down mode bit 1 PD Cleared by hardware when reset occurs Set to enter power-down mode Idle mode bit 0 IDL Cleared by hardware when interrupt or reset occurs Set to enter idle mode Reset Value = 00X1 0000b Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. 183 4202F–SCR–07/2008 Electrical Characteristics Absolute Maximum Ratings Note: Ambiant Temperature Under Bias ......................-25°C to 85°C Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power Dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package. Storage Temperature .................................... -65°C to + 150°C Voltage on VCC to VSS ......................................-0.5 V to + 6.0V Voltage on Any Pin to VSS ........................-0.5 V to VCC + 0.5 V Power Dissipation 1 W DC Parameters TA = -40 to +85°C; VSS = 0 V, FCK_CPU= 0 to 24 MHz , VCC = 3.0V to 5.5V Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL Output Low Voltage: P0, ALE, PSEN VOH Output High Voltage: P0, ALE, PSEN VOL1 Output Low Voltage: P2, P3, P4, P5, P1.2, P1.6, P1.7 VOH1 Output High Voltage: P2, P3, P4, P5, P1.2, P1.6, P1.7 IIL Logical 0 Input Current ports 2 to 5 and P1.2, P1.6, P1.7, if Weak pull-up enabled ILI Typ Max Unit -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.45 V IOL = 1.6 mA V IOH = 10 μA V IOL = 0.8 mA V IOH = -10 μA -50 μA Vin = 0.45 V Input Leakage Current ±10 μA 0.45 V < VIN < VCC ITL Logical 1 to O transistion Current, Port 51 configuration −650 μA VIN = 2 V RMEDIUM Medium Pullup Resistor 10 kΩ RWEAK Weak Pullup Resistor 100 kΩ CIO Capacitance of I/O Buffer DVCC Digital Supply Voltage DICC Digital Supply Output Current (DVcc pin) VPFDP Power Fail High Level Threshold VPFDM Power Fail Low Level Threshold 2,5 trise, tfall VDD rise and fall time 1μs 184 AT83R5122, AT8xC5122/23 0.9 VCC 0.45 0.9 VCC 3 3.4 2.8 Test Conditions 10 pF Fc = 1MHz TA = 25°C 3.6 V CL = 470 nF 10 mA 3 V 2.6 CL = 100 nF FCK_CPU = 24 MHz V 600 second 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Symbol Parameter RRST Internal reset pull-up resistor IPD Power down consumption Min Typ Max Unit Test Conditions 5 10 30 kΩ 60μA 200μA Vcc = 5.5V 40μA 200μA Vcc = 3.6V ICCIDLE Power Supply current in IDLE mode 0.4*F+2 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT89C5122) with DC/DC ON 1.6*F+3 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT85C5122) with DC/DC ON 1.6*F+3 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT83C5122) with DC/DC ON 1.6*F+2 mA Vcc = 5.5V (F in MHz) ICCWRITE Power Supply current in Active mode (AT89C5122) Flash or E2PROM write DC/DC ON 1.6*F+4 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT89C5122) with DC/DC OFF 0.8*F+3 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT85C5122) with DC/DC FF 0.8*F+3 mA Vcc = 5.5V (F in MHz) ICCOP Power Supply current in Active mode (AT83C5122) with DC/DC OFF 0.8*F+2 mA Vcc = 5.5V (F in MHz) ICCWRITE Power Supply current in Active mode (AT89C5122) Flash or E2PROM write DC/DC OFF 0.8*F+4 mA Vcc = 5.5V (F in MHz) 185 4202F–SCR–07/2008 ICC Current Test Conditions Figure 110. Power Down Mode VCC All other pins are disconnected. Ipd LI VCC AVCC VCC P0 VCC (NC) XTAL2 XTAL1 EA PLLF GND Vss AVss GND GND GND Figure 111. Active and Idle Mode VCC Icc All other pins are disconnected. LI VCC AVCC VCC P0 VCC (NC) CLOCK SIGNAL XTAL2 XTAL1 Vss EA PLLF AVss GND GND GND LED’s Symbol Parameter IOL Output Low Current, P3.0 and P3.7 LED modes Note: 186 Min Typ Max Unit Test Conditions 1 3 5 mA 2 mA configuration 2 6 8 mA 4 mA configuration 5 10 20 mA 10 mA configuration 1. (TA = -20°C to +50°C, VCC - VOL = 2 V ) AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Smart Card Interface Card VCC 5V (for IEC7816-3 Class A cards) Symbol Parameter Vcc Power Supply CICC_ovf Card Supply Current overflow CVCC Card Supply Voltage Min Typ 3.0 Max Unit 5.5 V 100 4.6 Ripple on Card Voltage Test Conditions mA 5.4 V 200 mV VccMin = 4.0V, CICC = 60 mA VccMin = 3.0V, CICC = 30 mA 0 < CIcc < 60 mA Max. charge 20 nA.s CVCC Card Supply Voltage during spike on Icc 4.5 5.5 Max. duration 400 ns Max. variation CICC 100 mA TOFF CVcc to 0 750 μs TON 0 to CVcc 750 μs Cload=10μF, Lload=10μH Vcard = CVcc to 0.4V Cload=10μF, Lload=10μH Vcard = 0V to CVcc With Boost at 60% Card VCC 3V Power Supply (for IEC7816-3 Class B cards) Symbol Parameter Vcc Power Supply CICC_ovf Card Supply Current overflow CVCC Card Supply Voltage Min Typ 3.0 Max Unit 5.5 V 100 2.76 Ripple on Vcard Test Conditions mA 3.24 V 200 mV 3.3 V VccMin = 3.6V, CICC = 55mA VccMin = 3.0V, CICC = 30 mA 0 < CICC < 55mA Maxi. charge 10nA.s CVCC Card Supply Voltage during spike on Icc 2.7 Max. duration 400 ns Max. variation CICC 50mA TOFF CVcc to 0 750 μs TON 0 to CVcc 750 μs Cload=10μF, Lload=10μH Vcard = CVcc to 0.4V Cload=10μF, Lload=10μH Vcard = 0V to CVcc With Boost at 60% 187 4202F–SCR–07/2008 Card VCC 1.8V Power Supply (for IEC7816-3 Class C cards) Symbol Parameter Vcc Power Supply CICC_ovf Card Supply Current overflow CVCC Card Supply Voltage TOFF TON Min Typ Max Unit 5.5 V 3.0 100 Test Conditions mA 1.68 1.92 V CVcc to 0 750 μs 0 to CVcc 750 μs CICC = 35 mA Cload=10μF, Lload=10μH Vcard = CVcc to 0.4V Cload=10μF, Lload=10μH Vcard = 0V to CVcc With Boost at 60% Notes: 1. Test conditions, Capacitor 10 μF, Inductance 10 μH. 2. Ceramic X7R, SMD type capacitor with minimum ESR or 250 mΩ is mandatory Smart Card CCLK, DC parameters Symbol Parameter VOL Output Low Voltage Min Typ Max Unit IOH = 50 μA (5V until 2009) 0.4 0(1) 0.15 CVCC IOH = 100 μA (5V from 2009) V IOH = 100 μA (3V & 1.8V) 0.15 CVCC IOL Output Low Current VOH Output High Voltage 15 mA CVCC V CVCC-0,5 IOH = 50μA (+5V until 2009) 0.8 CVCC IOH = 100 μA (+5V from 2009) IOH = 100 μA (+3V & 1.8V) 0.8 CVCC IOH Output High Current tR tF Rise and Fall delays 15 mA 14.5 15.5 32 Voltage Stability -0.25 0.4 CVCC CVCC-0.5 CVCC + 0.25 Frequency variation (Jitter) Cycle ratio Notes: Test Conditions CIN=30pF (5V) CIN=30pF (3V) ns CIN=30pF (1.8V) Low level V High level 1% 45% 55% 1. The voltage on CLK should remain between -0.3V and VCC+0.3V during dynamic operation. Smart Card CIO, DC Parameters Symbol Parameter VIL Input Low Voltage IIL Input Low Current VIH Input High Voltage IIH Input High Current Min 0(1) 0.6 CVCC Typ Max Unit 0.2 CVCC V 500 μA CVCC V -20 / +20 μA Test Conditions IOL = 1mA (5V & 3V)) VOL 188 Output Low Voltage 0 (1) 0.15 CVCC V IOL = 0.5 mA (1.8V) External 10K pull-up tied to CVCC AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Smart Card CIO, DC Parameters Symbol Parameter IOL Output Low Current VOH Output High Voltage IOH Output High Current Min Typ Max Unit 15 mA CVCC (1) V 15 mA -0.25 0.4 V 0.8 CVCC CVCC + 0.25 Test Conditions IOH = 20 μA Voltage Stability tR tF 0.8 CVCC Rise and Fall delays Note: External 10K pull-up resistor tied to CVCC Low level High level μs 0.8 CIN=30pF. 1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation. Smart Card RST, I/O, DC Parameters Symbol Parameter Min Typ Max Unit Test Conditions IOL = 50 μΑ (5V until 2009) 0.4 Output Low Voltage VOL 0(1) 0.12 CVCC IOL = 200 μΑ (5V from 2009) V IOL = 200 μΑ (3V & 1.8V) 0.12 CVCC IOL Output Low Current VOH Output High Voltage 15 mA CVCC (1) V IOH = 50 μΑ (+5V until 2009) CVCC-05 0.8 CVCC IOH = 150 μΑ (+5V from 2009) IOH = 150 μΑ (+3V & 1.8V) 0.8 CVCC IOH Output High Current 15 mA tR tF Rise and Fall delays 0.8 μs Voltage Stability Note: CIN=30 pF -0.25 0.4 CVCC Low level CVCC-0.5 CVCC + 0.25 High level 1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation. Card Presence (P1.2) DC Parameters Symbol IOL1 Parameter CPRES weak pull-up output current Min Typ Max Unit 3 10 25 μA Test Conditions P1.2=1, short to VSS Pull-up enabled 189 4202F–SCR–07/2008 USB Interface Figure 112. USB Interface Symbol VREF 190 Parameter Min Typ(5) Max Unit USB Reference Voltage 3.0 3.6 V VIH Input High Voltage for D+ and D- (driven) 2.0 4.0 V VIHZ Input High Voltage for D+ and D- (floating) 2.7 3.6 V VIL Input Low Voltage for D+ and D- 0.8 V VOH Output High Voltage for D+ and D- 2.8 3.6 V VOL Output Low Voltage for D+ and D- 0.0 0.3 V AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -40°C to +85°C; VSS = 0V; VCC = 3.0V to 5.5V ; FCK_CPU = 0 to 24 MHz. (Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs = 60 pF.) Table and Table 118 give the description of each AC symbols. Table 117 and Table 120 give for each range the AC parameter. Table 115, Table 117 and Table 119 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value and use this value in the formula. Example: TLLIV and 20 MHz, Standard clock. x = 30 ns T = 50 ns TCCIV = 4T - x = 170 ns External Program Memory Characteristics Table 114. Symbol Description Symbol T Parameter CPU clock period (FCK_CPU) TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction Float After PSEN TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float 191 4202F–SCR–07/2008 Table 115. AC Parameters for a Variable Clock Symbol Type Standard clock X2 Clock X parameter Units TLHLL Min 2T - x T-x 15 ns TAVLL Min T-x 0.5 T - x 20 ns TLLAX Min T-x 0.5 T - x 20 ns TLLIV Max 4T - x 2T-x 35 ns TLLPL Min T-x 0.5 T - x 15 ns TPLPH Min 3T - x 1.5 T - x 25 ns TPLIV Max 3T - x 1.5 T - x 45 ns TPXIX Min x x 0 ns TPXIZ Max T-x 0.5 T - x 15 ns TAVIV Max 5T - x 2.5 T - x 45 ns TPLAZ Max x x 10 ns External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV TLLPL ALE TPLPH PSEN PORT 0 TLLAX TAVLL INSTR IN TPLIV TPLAZ A0-A7 TPXIX INSTR IN TPXAV TPXIZ A0-A7 INSTR IN TAVIV PORT 2 192 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 External Data Memory Characteristics Table 116. Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high 193 4202F–SCR–07/2008 Table 117. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter Units TRLRH Min 6T - x 3T-x 20 ns TWLWH Min 6T - x 3T-x 20 ns TRLDV Max 5T - x 2.5 T - x 25 ns TRHDX Min x x 0 ns TRHDZ Max 2T - x T-x 20 ns TLLDV Max 8T - x 4T - x 40 ns TAVDV Max 9T - x 4.5 T - x 60 ns TLLWL Min 3T - x 1.5 T - x 25 ns TLLWL Max 3T + x 1.5 T + x 25 ns TAVWL Min 4T - x 2T-x 25 ns TQVWX Min T-x 0.5 T - x 15 ns TQVWH Min 7T-x 3.5 T - x 25 ns TWHQX Min T-x 0.5 T - x 10 ns TRLAZ Max x x 0 ns TWHLH Min T-x 0.5 T - x 15 ns TWHLH Max T-x 0.5 T + x 15 ns (warning x value differ from AT89C51RD2) External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TLLAX PORT 0 PORT 2 194 A0-A7 ADDRESS OR SFR-P2 TQVWX TQVWH TWHQX DATA OUT TAVWL ADDRESS A8-A15 OR SFR P2 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 External Data Memory Read Cycle PSEN TLLWL RD TLLAX PORT 0 PORT 2 Serial Port Timing - Shift Register Mode TWHLH TLLDV ALE TRLRH TRHDZ TAVDV TRHDX A0-A7 DATA IN TRLAZ TAVWL ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 Table 118. Symbol Description (F = 40 MHz) Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Table 119. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock TXLXL Min 12T 6T TQVHX Min 10T - x 5T-x 50 ns TXHQX Min 2T - x T-x 20 ns TXHDX Min x x 0 ns TXHDV Max 10T - x 5 T- x 133 ns X parameter Units ns 195 4202F–SCR–07/2008 Shift Register Timing Waveform INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH 0 OUTPUT DATA 1 2 INPUT DATA 4 5 6 TXHDX TXHDV WRITE to SBUF 3 VALID VALID SET TI VALID VALID VALID VALID VALID Table 120. AC Parameters Symbol Parameter Min TCLCL Oscillator Period 125 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns 60 % TCHCX/TCLCX External Clock Drive Waveforms VALID SET RI CLEAR RI External Clock Drive Characteristics (XTAL1) 7 Cyclic ratio in X2 mode VCC-0.5V 0.45V Max 40 Units 0.7VCC 0.2VCC-0.1 TCHCL TCHCX TCLCH TCLCX TCLCL AC Testing Input/Output Waveforms INPUT/OUTPUT VCC -0.5V 0.45V 0.2 VCC + 0.9 0.2 VCC - 0.1 AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 196 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Float Waveforms FLOAT VOH - 0.1 V VLOAD + 0.1 V VLOAD VLOAD - 0.1 V VOL + 0.1 V For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20 mA. Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. Clock Waveforms INTERNAL CLOCK STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 P1 P1 P1 P1 P1 P1 P1 P1 P2 P2 P2 P2 P2 P2 P2 P2 XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED PCL OUT DATA SAMPLED FLOAT P2 (EXT) PCL OUT FLOAT DATA SAMPLED PCL OUT FLOAT INDICATES ADDRESS TRANSITIONS READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt OUT P2 DATA SAMPLED FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION WRITE CYCLE WR P0 PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) DPL OR Rt OUT PCL OUT (IF PROGRAM MEMORY IS EXTERNAL DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION P2 PORT OPERATION MOV PORT SRC MOV DEST P0 OLD DATA NEW DATA P0 PINS SAMPLED MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK P1, P2, P3 PINS SAMPLED RXD SAMPLED P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED TXD (MODE 0) 197 4202F–SCR–07/2008 This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. USB Interface Rise Time Fall Time 90% VHmin 90% VCRS 10% Differential Data Lines VLmax tF tR Symbol Parameter Min tR Rise Time tF Fall Time Typ(5) Max Unit 4 20 ns 4 20 ns 11.9700 12.0300 Mb/s Crossover Voltage 1.3 2.0 V tDJ1 Source Jitter Total to next transaction -3.5 3.5 ns tDJ2 Source Jitter Total for paired transactions -4 4 ns tJR1 Receiver Jitter to next transaction -18.5 18.5 ns tJR2 Receiver Jitter for paired transactions -9 9 ns tFDRATE VCRS 198 10% Full-speed Data Rate AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Packaging Information Ordering Information Lead free/ RoHS Lead free/ RoHS Part Number Internal Part Number Memory Size (bytes) Voltage (V) Supply Temperature Max Frequency Range (MHz) AT83R5122xxx-RDTUM AT83R5122xxx-ALTUM 32K ROM 3.0 - 5.5 Industrial AT83R5122xxx-RDRUM AT83R5122xxx-ALRUM 32K ROM 3.0 - 5.5 AT83R5122xxx-PSTUM AT83R5122xxxZ1TUM 32K ROM AT83R5122xxx-PSRUM AT83R5122xxx-Z1RUM AT85C5122D-RDTUM Package Packing 48 MHz / X1 VQFP64 Tray Industrial 48 MHz / X1 VQFP64 Tape & Reel 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tray & Dry Pack 32K ROM 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel & Dry Pack AT85C5122D-ALTUM 32K CRAM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray AT85C5122D-RDRUM AT85C5122D-ALRUM 32K CRAM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tape & Reel AT89C5122D-RDTUM AT89C5122D-ALTUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray & Dry pack AT89C5122D-RDRUM AT89C5122D-ALRUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 AT89C5122D-PSTUM AT89C5122D-Z1TUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tray & Dry Pack AT89C5122D-PSRUM AT89C5122D-Z1RUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel & Dry Pack AT89C5122DS-RDTUM AT89C5122DS-ALTUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tray & Dry Pack AT89C5122DS-RDRUM AT89C5122DS-ALRUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 VQFP64 Tape & Reel & Dry Pack AT89C5122D-PSTUM AT89C5122D-Z1TUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tray & Dry Pack AT89C5122D-PSRUM AT89C5122D-Z1RUM 32K FLASH 3.0 - 5.5 Industrial 48 MHz / X1 QFN64 Tape & Reel & Dry Pack AT83C5123xxx-RATUM AT83C5123xxx-ALTUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP32 Tray AT83C5123xxx-RARUM AT83C5123xxx-ALRUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 VQFP32 Tape & Reel AT83C5123xxx-PUTUM AT83C5123xxx-Z1TUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 QFN32 Tray AT83C5123xxx-PURUM AT83C5123xxx-Z1RUM 30K ROM 3.0 - 5.5 Industrial 48 MHz / X1 QFN32 Tape & Reel Note: Tape & Reel & Dry pack 1. Check avaibility with sales office 199 4202F–SCR–07/2008 Mechanical Dimensions VQFP64 Package 200 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 PLCC68 Package 201 4202F–SCR–07/2008 VQFP32 Package 202 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 QFN32 Package 203 4202F–SCR–07/2008 Datasheet Revision History Changes from 4202A to 4202B 1. Product AT8xEC5122 added. 2. Products AT83C5123 and AT83EC5123 added. Changes from 4202B to 4202C 1. All sections updated. 2. QFN64 and QFN32 packages added. 3. SCIB section : VCC must be higher than 4.0V when DC/DC is operated at 5V. Changes from 4202C to 4202D 1. Product AT89C5122DS added (EA pin changed to VCC) 2. Typical applications section: external pull-up shown on CIO pin 3. Ports section : Detailed explanations on CIO, CC4, CC8 quasi-bidirectional ports 4. Ordering information section: AT89C5122DS part-numbers added Changes from 4202D to 4202E 1. Changed input voltage frequency from 3.6V to 3.0V throughout the document. 2. Update of DC parameters of smart card interface to be EMV 4.1 compliant. Changes from 4202E to 4202F 1. Product AT83EC5122 and AT83EC5123 removed. 2. Product AT83R5122 added. 3. Package PLCC28 not supported anymore. 4. Global update. 204 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Table of Contents Features ................................................................................................. 1 Reference Documents .......................................................................................... 2 Product Description .............................................................................................. 3 AT8xC5122/AT83R5122 Block Diagram .............................................................. 4 AT83C5123 Block Diagram .................................................................................. 4 Pinout .................................................................................................... 5 High Pin Count Package Description.................................................................... 5 Low Pin Count Package Description .................................................................. 10 Pin Description.................................................................................................... 11 Typical Applications ........................................................................... 15 Recommended External components ................................................................. 15 USB Keyboard with Smart Card Reader Using AT83R5122, AT8xC5122/AT89C5122DS 16 USB Smart Card Reader Using the AT83C5123 Version................................... 17 Memory Organization ......................................................................... 18 Program Memory Managament .......................................................................... 18 Data Memory Managament ................................................................................ 19 Dual Data Pointer Register (DDPTR) ................................................................. 20 Registers............................................................................................................. 22 AT8xC5122’s CRAM and E2PROM Versions .................................................... 24 AT83R5122, AT8xC5122’s ROM Version .......................................................... 28 AT83C5123 Version ........................................................................................... 30 Special Function Registers (SFR’s) .................................................. 31 Introduction ......................................................................................................... AT8xC5122 Version............................................................................................ AT83C5123 Version ........................................................................................... SFR’s Description ............................................................................................... 31 32 33 34 Clock Controller .................................................................................. 39 On-Chip Oscillator .............................................................................................. Phase Lock Loop (PLL) ...................................................................................... Clock Tree Architecture ...................................................................................... Registers............................................................................................................. 39 40 41 48 I/O Port Definition ............................................................................... 51 Port Configuration............................................................................................... 55 Registers............................................................................................................. 59 Smart Card Interface Block (SCIB) ................................................... 62 Block Diagram .................................................................................................... 63 205 4202F–SCR–07/2008 Definitions ........................................................................................................... 63 Functional Description ........................................................................................ 65 Additional Features............................................................................................. 72 Alternate Card..................................................................................................... 76 Registers ............................................................................................................. 76 DC/DC Converter................................................................................................ 86 USB Controller .................................................................................... 93 Description.......................................................................................................... 94 Configuration ...................................................................................................... 97 Read/Write Data FIFO ...................................................................................... 100 Bulk / Interrupt Transactions............................................................................. 101 Control Transactions......................................................................................... 105 Isochronous Transactions................................................................................. 106 Miscellaneous ................................................................................................... 108 Suspend/Resume Management .......................................................................109 Detach Simulation............................................................................................. 112 USB Interrupt System ....................................................................................... 113 Registers........................................................................................................... 115 Serial I/O Port .................................................................................... 124 Framing Error Detection ................................................................................... Automatic Address Recognition........................................................................ Asynchronous Modes (Modes 1, 2 and 3) ........................................................ Modes 2 and 3 .................................................................................................. Registers........................................................................................................... 124 125 129 130 133 Serial Port Interface (SPI) ................................................................ 135 Features............................................................................................................ 135 Signal Description............................................................................................. 135 Functional Description ...................................................................................... 137 Timers/Counters ............................................................................... 145 Timer/Counter Operations ................................................................................ Timer 0.............................................................................................................. Timer 1.............................................................................................................. Registers........................................................................................................... 145 145 148 150 Keyboard Interface ........................................................................... 153 Introduction ....................................................................................................... 153 Description........................................................................................................ 153 Registers........................................................................................................... 154 Interrupt System ............................................................................... 157 Introduction ....................................................................................................... 157 Interrupt System Description ............................................................................ 157 206 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 AT83R5122, AT8xC5122/23 Registers........................................................................................................... 160 Interrupt Sources and Vectors .......................................................................... 169 Microcontroller Reset ....................................................................... 170 Introduction ....................................................................................................... Power On Reset (POR) .................................................................................... Power Fail Detector (PFD)................................................................................ Reset pin........................................................................................................... Watchdog Timer ............................................................................................... 170 171 171 173 175 Power Management .......................................................................... 178 Idle Mode .......................................................................................................... Power Down Mode ........................................................................................... Reduced EMI Mode .......................................................................................... USB Interface ................................................................................................... Smart Card Interface ........................................................................................ Keyboard Interface ........................................................................................... Watchdog Timer during Power-down and Idle Mode........................................ Registers........................................................................................................... 178 178 179 180 181 182 182 183 Electrical Characteristics ................................................................. 184 Absolute Maximum Ratings ..............................................................................184 DC Parameters .................................................................................................184 LED’s ................................................................................................................186 Smart Card Interface ........................................................................................ 187 USB Interface ................................................................................................... 190 AC Parameters ................................................................................................. 191 Float Waveforms............................................................................................... 197 Packaging Information ..................................................................... 199 Ordering Information......................................................................................... 199 Datasheet Revision History ............................................................. 204 Changes from 4202A to 4202B ........................................................................204 Changes from 4202B to 4202C ........................................................................204 Changes from 4202C to 4202D ........................................................................204 Changes from 4202D to 4202E ........................................................................204 Changes from 4202E to 4202F .........................................................................204 Table of Contents ............................................................................. 205 207 4202F–SCR–07/2008 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. 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