Features • Compatible with MCS®-51 Products • 8K Bytes of In-System Programmable (ISP) Flash Memory • • • • • • • • • • • • • • • – Endurance: 10,000 Write/Erase Cycles 2.7V to 4.0V Operating Range Fully Static Operation: 0 Hz to 16 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off Flag Flexible ISP Programming (Byte and Page Modes) Green (Pb/Halide-free) Packaging Option 1. Description The AT89LS52 is a low-voltage, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89LS52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. 8-bit Low-Voltage Microcontroller with 8K Bytes In-System Programmable Flash AT89LS52 The AT89LS52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LS52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. 2601C–MICRO–06/08 2. Pin Configurations 2 P1.4 P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) 44 43 42 41 40 39 38 37 36 35 34 44-lead TQFP (T2) P1.0 1 40 VCC (T2 EX) P1.1 2 39 P0.0 (AD0) P1.2 3 38 P0.1 (AD1) P1.3 4 37 P0.2 (AD2) P1.4 5 36 P0.3 (AD3) (MOSI) P1.5 1 33 P0.4 (AD4) (MOSI) P1.5 6 35 P0.4 (AD4) (MISO) P1.6 2 32 P0.5 (AD5) (MISO) P1.6 7 34 P0.5 (AD5) (SCK) P1.7 3 31 P0.6 (AD6) RST 4 30 P0.7 (AD7) (RXD) P3.0 5 29 EA/VPP NC 6 28 NC PSEN (INT1) P3.3 9 25 P2.7 (A15) (T0) P3.4 10 24 P2.6 (A14) (INT1) P3.3 13 28 P2.7 (A15) (T1) P3.5 11 23 P2.5 (A13) (T0) P3.4 14 27 P2.6 (A14) (T1) P3.5 15 26 P2.5 (A13) (WR) P3.6 16 25 P2.4 (A12) (RD) P3.7 17 24 P2.3 (A11) XTAL2 18 23 P2.2 (A10) XTAL1 19 22 P2.1 (A9) GND 20 21 P2.0 (A8) 22 29 (A12) P2.4 12 21 PSEN (INT0) P3.2 (A11) P2.3 26 20 8 (A10) P2.2 (INT0) P3.2 19 ALE/PROG (A9) P2.1 30 18 11 (A8) P2.0 ALE/PROG (TXD) P3.1 17 27 GND 7 16 (TXD) P3.1 GND EA/VPP 15 31 XTAL1 10 14 (RXD) P3.0 XTAL2 P0.7 (AD7) 13 P0.6 (AD6) 32 12 33 9 (RD) P3.7 8 RST (WR) P3.6 (SCK) P1.7 P1.4 P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) 6 5 4 3 2 1 44 43 42 41 40 44-lead PLCC 14 32 PSEN (INT1) P3.3 15 31 P2.7 (A15) (T0) P3.4 16 30 P2.6 (A14) (T1) P3.5 17 29 P2.5 (A13) 28 ALE/PROG (INT0) P3.2 (A12) P2.4 33 27 13 (A11) P2.3 NC (TXD) P3.1 26 34 (A10) P2.2 12 25 EA/VPP NC (A9) P2.1 35 24 11 (A8) P2.0 P0.7 (AD7) (RXD) P3.0 23 36 NC 10 22 P0.6 (AD6) RST GND 37 21 9 XTAL1 P0.5 (AD5) (SCK) P1.7 20 P0.4 (AD4) 38 XTAL2 39 8 19 7 (MISO) P1.6 18 (MOSI) P1.5 (RD) P3.7 2.2 2.3 40-lead PDIP (WR) P3.6 2.1 AT89LS52 2601C–MICRO–06/08 AT89LS52 3. Block Diagram P0.0 - P0.7 P2.0 - P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC GND RAM ADDR. REGISTER B REGISTER PORT 0 LATCH RAM PORT 2 LATCH FLASH PROGRAM ADDRESS REGISTER STACK POINTER ACC BUFFER TMP2 TMP1 PC INCREMENTER ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PROGRAM COUNTER PSW PSEN ALE/PROG EA / VPP TIMING AND CONTROL INSTRUCTION REGISTER DUAL DPTR RST WATCH DOG PORT 3 LATCH PORT 1 LATCH ISP PORT PROGRAM LOGIC OSC PORT 3 DRIVERS P3.0 - P3.7 PORT 1 DRIVERS P1.0 - P1.7 3 2601C–MICRO–06/08 4. Pin Description 4.1 VCC Supply voltage. 4.2 GND Ground. 4.3 Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. 4.4 Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification. 4.5 Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) P1.5 MOSI (used for In-System Programming) P1.6 MISO (used for In-System Programming) P1.7 SCK (used for In-System Programming) Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. 4 AT89LS52 2601C–MICRO–06/08 AT89LS52 Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. 4.6 Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89LS52, as shown in the following table. 4.7 Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe) RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. 4.8 ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. 4.9 PSEN Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89LS52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. 5 2601C–MICRO–06/08 4.10 EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. 4.11 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. 4.12 XTAL2 Output from the inverting oscillator amplifier. 5. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 52) and T2MOD (shown in Table 10-2) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. 6 AT89LS52 2601C–MICRO–06/08 AT89LS52 Table 5-1. AT89LS52 SFR Map and Reset Values 0F8H 0F0H 0FFH B 00000000 0F7H 0E8H 0E0H 0EFH ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 00000000 0C8H T2CON 00000000 0D7H T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 0CFH 0C0H 0C7H 0B8H IP XX000000 0BFH 0B0H P3 11111111 0B7H 0A8H IE 0X000000 0AFH 0A0H P2 11111111 98H SCON 00000000 90H P1 11111111 88H TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 80H P0 11111111 SP 00000111 DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 00000000 AUXR1 XXXXXXX0 WDTRST XXXXXXXX 0A7H SBUF XXXXXXXX 9FH 97H AUXR XXX00XX0 8FH PCON 0XXX0000 87H 7 2601C–MICRO–06/08 Table 5-2. T2CON – Timer/Counter 2 Control Register T2CON Address = 0C8H Reset Value = 0000 0000B Bit Addressable TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 7 6 5 4 3 2 1 0 Bit Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered). CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. 8 AT89LS52 2601C–MICRO–06/08 AT89LS52 Table 5-3. AUXR: Auxiliary Register AUXR Address = 8EH Reset Value = XXX00XX0B Not Bit Addressable Bit – – – WDIDLE DISRTO – – DISALE 7 6 5 4 3 2 1 0 – Reserved for future expansion DISALE Disable/Enable ALE DISRTO DISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction Disable/Enable Reset out DISRTO WDIDLE 0 Reset pin is driven High after WDT times out 1 Reset pin is input only Disable/Enable WDT in IDLE mode WDIDLE 0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset. 9 2601C–MICRO–06/08 Table 5-4. AUXR1: Auxiliary Register 1 AUXR1 Address = A2H Reset Value = XXXXXXX0B Not Bit Addressable Bit – – – – – – – DPS 7 6 5 4 3 2 1 0 – Reserved for future expansion DPS Data Pointer Register Select DPS 0 Selects DPTR Registers DP0L, DP0H 1 Selects DPTR Registers DP1L, DP1H 6. Memory Organization MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed. 6.1 Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89LS52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are directed to external memory. 6.2 Data Memory The AT89LS52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. 10 AT89LS52 2601C–MICRO–06/08 AT89LS52 7. Watchdog Timer (One-time Enabled with Reset-out) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin. 7.1 Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. 7.2 WDT During Power-down and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Powerdown mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89LS52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89LS52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE. 11 2601C–MICRO–06/08 8. UART The UART in the AT89LS52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 9. Timer 0 and 1 Timer 0 and Timer 1 in the AT89LS52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 10. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 5-2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 5-2. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. Table 10-1. Timer 2 Operating Modes RCLK +TCLK CP/RL2 TR2 MODE 0 0 1 16-bit Auto-reload 0 1 1 16-bit Capture 1 X 1 Baud Rate Generator X X 0 (Off) In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. 12 AT89LS52 2601C–MICRO–06/08 AT89LS52 10.1 Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 10-1. Figure 10-1. Timer in Capture Mode ÷12 OSC C/T2 = 0 TH2 TL2 TF2 OVERFLOW CONTROL TR2 C/T2 = 1 CAPTURE T2 PIN RCAP2H RCAP2L TRANSITION DETECTOR TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 10.2 Auto-reload (Up or Down Counter) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 10-2). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Figure 10-2 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. 13 2601C–MICRO–06/08 Figure 10-2. Timer 2 Auto Reload Mode (DCEN = 0) ÷12 OSC C/T2 = 0 TH2 TL2 OVERFLOW CONTR OL TR2 C/T2 = 1 RELO AD T2 PIN RCAP2H TIMER 2 INTERRUPT RCAP2L TF2 TRANSITION DETECTOR EXF2 T2EX PIN CONTROL EXEN2 Table 10-2. T2MOD – Timer 2 Mode Control Register T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable Bit – – – – – – T2OE DCEN 7 6 5 4 3 2 1 0 Symbol Function – Not implemented, reserved for future T2OE Timer 2 Output Enable bit DCEN When set, this bit allows Timer 2 to be configured as an up/down counter 14 AT89LS52 2601C–MICRO–06/08 AT89LS52 Figure 10-3. Timer 2 Auto Reload Mode (DCEN = 1) TOGGLE (DOWN COUNTING RELOAD VALUE) 0FFH OSC 0FFH ÷ 12 EXF2 OVERFLOW C/T2 = 0 TH2 TL2 TF2 CONTROL TR2 TIMER 2 INTERRUPT C/T2 = 1 T2 PIN RCAP2H RCAP2L COUNT DIRECTION 1=UP 0=DOWN (UP COUNTING RELOAD VALUE) T2EX PIN Figure 10-4. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW ÷2 "0" "1" NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 SMOD1 OSC ÷2 C/T2 = 0 "1" TH2 "0" TL2 RCLK CONTROL TR2 ÷ 16 Rx CLOCK C/T2 = 1 "1" "0" T2 PIN TCLK RCAP2H RCAP2L TRANSITION DETECTOR ÷ 16 T2EX PIN EXF2 Tx CLOCK TIMER 2 INTERRUPT CONTROL EXEN2 15 2601C–MICRO–06/08 11. Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 5-2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 10-4. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation. Timer 2 Overflow Rate Modes 1 and 3 Baud Rates = -----------------------------------------------------------16 The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below. Modes 1 and 3 Oscillator Frequency --------------------------------------- = -------------------------------------------------------------------------------------Baud Rate 32 x [65536-RCAP2H,RCAP2L)] where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 10-4. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. 16 AT89LS52 2601C–MICRO–06/08 AT89LS52 Figure 11-1. Timer 2 in Clock-Out Mode OSC TL2 (8-BITS) ÷2 TH2 (8-BITS) TR2 RCAP2L RCAP2H C/T2 BIT P1.0 (T2) ÷2 T2OE (T2MOD.1) TRANSITION DETECTOR P1.1 (T2EX) EXF2 TIMER 2 INTERRUPT EXEN2 12. Programmable Clock Out A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 11-1. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16 MHz operating frequency). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation. Oscillator Frequency Clock-Out Frequency = ------------------------------------------------------------------------------------4 x [65536-(RCAP2H,RCAP2L)] In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. 17 2601C–MICRO–06/08 13. Interrupts The AT89LS52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 13-1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 13-1 shows that bit position IE.6 is unimplemented. User software should not write 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows. Table 13-1. Interrupt Enable (IE) Register (MSB) EA (LSB) – ET2 ES ET1 EX1 ET0 EX0 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. Symbol Position Function EA IE.7 Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. – IE.6 Reserved. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. User software should never write 1s to reserved bits, because they may be used in future AT89 products. 18 AT89LS52 2601C–MICRO–06/08 AT89LS52 Figure 13-1. Interrupt Sources 0 INT0 IE0 1 TF0 0 INT1 IE1 1 TF1 TI RI TF2 EXF2 14. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 16-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 16-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. 15. Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. 19 2601C–MICRO–06/08 16. Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Figure 16-1. Oscillator Connections C2 XTAL2 C1 XTAL1 GND Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators Figure 16-2. External Clock Drive Configuration NC XTAL2 EXTERNAL OSCILLATOR SIGNAL XTAL1 GND 20 AT89LS52 2601C–MICRO–06/08 AT89LS52 Table 16-1. Status of External Pins During Idle and Power-down Modes Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data 17. Program Memory Lock Bits The AT89LS52 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 17-1. Table 17-1. Lock Bit Protection Modes Program Lock Bits 1 LB1 LB2 LB3 Protection Type U U U No program lock features 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash memory is disabled 3 P P U Same as mode 2, but verify is also disabled 4 P P P Same as mode 3, but external execution is also disabled When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. 18. Programming the Flash – Parallel Mode The AT89LS52 is shipped with the on-chip Flash memory array ready to be programmed. The programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers. The AT89LS52 code memory array is programmed byte-by-byte. Programming Algorithm: Before programming the AT89LS52, the address, data, and control signals should be set up according to the Flash programming mode table (Table 20-1) and Figure 20-1 and Figure 20-2. To program the AT89LS52, take the following steps: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The bytewrite cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. 21 2601C–MICRO–06/08 Data Polling: The AT89LS52 features Data Polling to indicate the end of a byte write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be verified directly by reading them back. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (100H) = 62H indicates 89LS52 (200H) = 06H Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns 500 ns. In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During chip erase, a serial read from any address location will return 00H at the data output. 19. Programming the Flash – Serial Mode The Code memory array can be programmed using the serial ISP interface while RST is pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before other operations can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is required. The Chip Erase operation turns the content of every memory location in the Code array into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 16 MHz oscillator clock, the maximum SCK frequency is 1 MHz. 22 AT89LS52 2601C–MICRO–06/08 AT89LS52 19.1 Serial Programming Algorithm To program and verify the AT89LS52 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: a. Apply power between VCC and GND pins. b. Set RST pin to “H”. If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 16 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 16. 3. The Code array is programmed one byte at a time in either the Byte or Page mode. The write cycle is self-timed and typically takes less than 1 ms at 2.7V. 4. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/P1.6. 5. At the end of a programming session, RST can be set low to commence normal device operation. Power-off sequence (if needed): 1. Set XTAL1 to “L” (if a crystal is not used). 2. Set RST to “L”. 3. Turn VCC power off. Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during a byte write cycle an attempted read of the last byte written will result in the complement of the MSB of the serial output byte on MISO. 19.2 Serial Programming Instruction Set The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 22-1. 23 2601C–MICRO–06/08 20. Programming Interface – Parallel Mode Every code byte in the Flash array can be programmed by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. Most major worldwide programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Table 20-1. Flash Programming Modes Mode VCC RST PSEN P0.7-0 P2.4-0 P1.7-0 ALE/ EA/ PROG VPP P2.6 P2.7 P3.3 P3.6 P3.7 Data 12V L H H H H DIN A12-8 A7-0 H L L L H H DOUT A12-8 A7-0 12V H H H H H X X X 12V H H H L L X X X 12V H L H H L X X X H H H L H L P0.2, P0.3, P0.4 X X 12V H L H L L X X X Address (2) Write Code Data 5V H L Read Code Data 5V H L Write Lock Bit 1 5V H L Write Lock Bit 2 5V H L Write Lock Bit 3 5V H L 5V H L Chip Erase 5V H L Read Atmel ID 5V H L H H L L L L L 1EH X 0000 00H Read Device ID 5V H L H H L L L L L 62H X 0001 00H Read Device ID 5V H L H H L L L L L 06H X 0010 00H H (3) (3) (3) Read Lock Bits 1, 2, 3 H (1) Notes: 24 1. 2. 3. 4. 5. Each PROG pulse is 200 ns - 500 ns for Chip Erase. Each PROG pulse is 200 ns - 500 ns for Write Code Data. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. RDY/BSY signal is output on P3.0 during programming. X = don’t care. AT89LS52 2601C–MICRO–06/08 AT89LS52 Figure 20-1. Programming the Flash Memory (Parallel Mode) 4.5V - 5.5V AT89LS52 A0 - A7 ADDR. 0000H/1FFFH A8 - A12 VCC P1.0-P1.7 P2.0 - P2.4 P0 P2.6 P2.7 P3.3 P3.6 SEE FLASH PROGRAMMING MODES TABLE PGM DATA ALE PROG EA VIH/VPP P3.7 XTAL2 3-16 MHz P3.0 RDY/ BSY RST VIH XTAL1 GND PSEN Figure 20-2. Verifying the Flash Memory (Parallel Mode) 4.5V - 5.5V AT89LS52 A0 - A7 ADDR. 0000H/1FFFH A8 - A12 SEE FLASH PROGRAMMING MODES TABLE P1.0-P1.7 VCC P2.0 - P2.4 P0 P2.6 P2.7 P3.3 P3.6 P3.7 PGM DATA (USE 10K PULLUPS) ALE VIH XTAL 2 EA XTAL1 RST 3-16 MHz GND VIH PSEN 25 2601C–MICRO–06/08 21. Flash Programming and Verification Characteristics (Parallel Mode) TA = 20°C to 30°C, VCC = 4.5V to 5.5V Symbol Parameter Min Max Units VPP Programming Supply Voltage 11.5 12.5 V IPP Programming Supply Current 10 mA ICC VCC Supply Current 30 mA 1/tCLCL Oscillator Frequency 16 MHz tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48tCLCL tSHGL VPP Setup to PROG Low 10 µs tGHSL VPP Hold After PROG 10 µs tGLGH PROG Width 0.2 tAVQV Address to Data Valid 48tCLCL tELQV ENABLE Low to Data Valid 48tCLCL tEHQZ Data Float After ENABLE tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 50 µs 3 1 0 µs 48tCLCL Figure 21-1. Flash Programming and Verification Waveforms – Parallel Mode PROGRAMMING ADDRESS P1.0 - P1.7 P2.0 - P2.4 VERIFICATION ADDRESS tAVQV PORT 0 DATA IN tAVGL tDVGL tGHDX DATA OUT tGHAX ALE/PROG tSHGL tGLGH VPP tGHSL LOGIC 1 LOGIC 0 EA/VPP tEHSH tEHQZ tELQV P2.7 (ENABLE) tGHBL P3.0 (RDY/BSY) BUSY READY tWC 26 AT89LS52 2601C–MICRO–06/08 AT89LS52 Figure 21-2. Flash Memory Serial Downloading VCC AT89LS52 VCC INSTRUCTION INPUT P1.5/MOSI DATA OUTPUT P1.6/MISO P1.7/SCK CLOCK IN XTAL2 3-16 MHz XTAL1 VIH RST GND 22. Flash Programming and Verification Waveforms – Serial Mode Figure 22-1. Serial Programming Waveforms 7 6 5 4 3 2 1 0 27 2601C–MICRO–06/08 Table 22-1. Serial Programming Instruction Set Byte 3 Byte 4 Operation 1010 1100 0101 0011 xxxx xxxx xxxx xxxx 0110 1001 (Output on MISO) Enable Serial Programming while RST is high 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase Flash memory array Read Program Memory (Byte Mode) 0010 0000 xxx D3 D2 D1 D0 Read data from Program memory in the byte mode Write Program Memory (Byte Mode) 0100 0000 xxx D3 D2 D1 D0 Write data to Program memory in the byte mode Write Lock Bits(1) 1010 1100 1110 00 xxxx xxxx xxxx xxxx 0010 0100 xxxx xxxx xxxx xxxx xxx 0010 1000 xxx 0011 0000 xxx 0101 0000 xxx A3 A2 A1 A0 A3 A2 A1 A0 A7 A6 A5 A4 A7 A6 A5 A4 A11 A10 A9 A8 B1 B2 A11 A10 A9 A8 A12 Chip Erase A12 Programming Enable Note: A11 A10 A9 A8 A7 A12 Read back current status of the lock bits (a programmed lock bit reads back as a “1”) Signature Byte Byte 0 Byte 1... Byte 255 Read data from Program memory in the Page Mode (256 bytes) Byte 0 Byte 1... Byte 255 Write data to Program memory in the Page Mode (256 bytes) 1. B1 = 0, B2 = 0 ---> Mode 1, no lock protection B1 = 0, B2 = 1 ---> Mode 2, lock bit 1 activated B1 = 1, B2 = 0 ---> Mode 3, lock bit 2 activated B1 = 1, B1 = 1 ---> Mode 4, lock bit 3 activated xxx xxx0 xx A11 A10 A9 A8 Write Program Memory (Page Mode) A12 Read Program Memory (Page Mode) A12 Read Signature Bytes Write Lock bits. See Note 1. A11 A10 A9 A8 Read Lock Bits LB2 LB1 Byte 2 LB3 Instruction D7 D6 D5 D4 Byte 1 D7 D6 D5 D4 Instruction Format } Read Signature Byte Each of the lock bit modes needs to be activated sequentially before Mode 4 can be executed. After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1. For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded. 28 AT89LS52 2601C–MICRO–06/08 AT89LS52 23. Serial Programming Characteristics Figure 23-1. Serial Programming Timing MOSI tOVSH SCK tSHOX tSLSH tSHSL MISO tSLIV Table 23-1. Serial Programming Characteristics, TA = -40⋅ C to 85⋅ C, VCC = 2.7V - 4.0V (Unless otherwise noted) Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Oscillator Period tSHSL Min Typ 3 Max Units 16 MHz 62.5 ns SCK Pulse Width High 8 tCLCL ns tSLSH SCK Pulse Width Low 8 tCLCL ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2 tCLCL ns tSLIV SCK Low to MISO Valid tERASE Chip Erase Instruction Cycle Time tSWC Serial Byte Write Cycle Time 10 16 32 ns 500 ms 64 tCLCL + 400 µs 24. Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current...................................................... 15.0 mA 29 2601C–MICRO–06/08 25. DC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 2.7V to 4.0V, unless otherwise noted. Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA) -0.5 0.7 V VIL1 Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V VIH Input High Voltage 0.2 VCC+0.9 VCC+0.5 V VIH1 Input High Voltage 0.7 VCC VCC+0.5 V IOL = 0.8 mA 0.45 V IOL = 1.6 mA 0.45 V VOL (Except XTAL1, RST) (XTAL1, RST) Output Low Voltage (1) (Ports 1,2,3) (1) VOL1 Output Low Voltage (Port 0, ALE, PSEN) VOH Output High Voltage (Ports 1,2,3, ALE, PSEN) IOH = -60 µA, VCC = 5V ± 10% 2.4 V IOH = -25 µA 0.65 VCC V IOH = -10 µA 0.80 VCC V 2.4 V IOH = -300 µA 0.75 VCC V IOH = -80 µA 0.9 VCC V IOH = -800 µA, VCC = 5V ± 10% VOH1 Output High Voltage (Port 0 in External Bus Mode) IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA ITL Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -150 µA ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pulldown Resistor 300 KΩ CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA VCC = 4.0V 30 µA 50 Power Supply Current ICC Power-down Mode Notes: 30 (1) 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power-down is 2V. AT89LS52 2601C–MICRO–06/08 AT89LS52 26. AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. 26.1 External Program and Data Memory Characteristics 16 MHz Oscillator Variable Oscillator Min Min Max Units 0 16 MHz Symbol Parameter Max 1/tCLCL Oscillator Frequency tLHLL ALE Pulse Width 85 2tCLCL-40 ns tAVLL Address Valid to ALE Low 22 tCLCL-40 ns tLLAX Address Hold After ALE Low 32 tCLCL-30 ns tLLIV ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low 32 tCLCL-30 ns tPLPH PSEN Pulse Width 142 3tCLCL-45 ns tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold After PSEN tPXIZ Input Instruction Float After PSEN tPXAV PSEN to Address Valid tAVIV Address to Valid Instruction In 207 5tCLCL-105 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 275 6tCLCL-100 ns tWLWH WR Pulse Width 275 6tCLCL-100 ns tRLDV RD Low to Valid Data In tRHDX Data Hold After RD tRHDZ Data Float After RD 65 2tCLCL-60 ns tLLDV ALE Low to Valid Data In 350 8tCLCL-150 ns tAVDV Address to Valid Data In 397 9tCLCL-165 ns tLLWL ALE Low to RD or WR Low 137 3tCLCL+50 ns tAVWL Address to RD or WR Low 122 4tCLCL-130 ns tQVWX Data Valid to WR Transition 13 tCLCL-50 ns tQVWH Data Valid to WR High 287 7tCLCL-150 ns tWHQX Data Hold After WR 13 tCLCL-50 ns tRLAZ RD Low to Address Float tWHLH RD or WR High to ALE High 150 4tCLCL-100 82 0 3tCLCL-105 0 37 75 tCLCL-8 0 5tCLCL-165 3tCLCL-50 0 23 103 tCLCL-40 ns ns 0 239 ns ns tCLCL-25 147 ns ns ns 0 ns tCLCL+40 ns 31 2601C–MICRO–06/08 27. External Program Memory Read Cycle tLHLL ALE tAVLL tLLIV tLLPL tPLIV PSEN tPXAV tPLAZ tPXIZ tLLAX tPXIX A0 - A7 PORT 0 tPLPH INSTR IN A0 - A7 tAVIV A8 - A15 PORT 2 A8 - A15 28. External Data Memory Read Cycle tLHLL ALE tWHLH PSEN tLLDV tRLRH tLLWL RD tLLAX tAVLL PORT 0 tRLDV tRLAZ A0 - A7 FROM RI OR DPL tRHDZ tRHDX DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 32 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH AT89LS52 2601C–MICRO–06/08 AT89LS52 29. External Data Memory Write Cycle tLHLL ALE tWHLH PSEN tLLWL WR tAVLL tLLAX tQVWX A0 - A7 FROM RI OR DPL PORT 0 tWLWH tQVWH DATA OUT tWHQX A0 - A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH 30. External Clock Drive Waveforms tCHCX VCC - 0.5V tCHCX tCLCH tCHCL 0.7 VCC 0.2 VCC - 0.1V 0.45V tCLCX tCLCL 31. External Clock Drive Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period tCHCX Min Max Units 0 16 MHz 62.5 ns High Time 20 ns tCLCX Low Time 20 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns 33 2601C–MICRO–06/08 32. Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 2.7V to 4.0V and Load Capacitance = 80 pF. 12 MHz Osc Variable Oscillator Symbol Parameter Min Max Min Max tXLXL Serial Port Clock Cycle Time 1.0 12 tCLCL μs tQVXH Output Data Setup to Clock Rising Edge 700 10 tCLCL-133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2 tCLCL-80 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid 700 Units 10 tCLCL-133 ns 33. Shift Register Mode Timing Waveforms INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH tXHQX WRITE TO SBUF 0 1 2 tXHDV OUTPUT DATA CLEAR RI 3 4 5 6 tXHDX VALID VALID VALID 7 SET TI VALID VALID VALID VALID VALID SET RI INPUT DATA 34. AC Testing Input/Output Waveforms(1) VCC - 0.5V 0.2 VCC + 0.9V TEST POINTS 0.2 VCC - 0.1V 0.45V Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0. 35. Float Waveforms(1) V LOAD+ 0.1V V LOAD - 34 0.1V V OL + 0.1V Timing Reference Points V LOAD Note: V OL - 0.1V 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs. AT89LS52 2601C–MICRO–06/08 AT89LS52 36. Ordering Information 36.1 Green Package Option (Pb/Halide-free) Speed (MHz) 16 Power Supply 2.7V to 4.0V Ordering Code Package AT89LS52-16AU AT89LS52-16JU AT89LS52-16PU 44A 44J 40P6 Operation Range Industrial (-40° C to 85° C) Package Type 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 35 2601C–MICRO–06/08 37. Packaging Information 37.1 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 36 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 44A B AT89LS52 2601C–MICRO–06/08 AT89LS52 37.2 44J 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 17.399 – 17.653 D1 16.510 – 16.662 E 17.399 – 17.653 E1 16.510 – 16.662 D2/E2 14.986 – 16.002 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 44J B 37 2601C–MICRO–06/08 37.3 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). e NOTE Note 2 Note 2 2.540 TYP 09/28/01 R 38 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B AT89LS52 2601C–MICRO–06/08 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 2601C–MICRO–06/08