ATMEL ATR0621-EK1 Gps baseband processor Datasheet

Features
• 16-channel GPS Correlator
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– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –140 dBm
– Tracking Sensitivity: –150 dBm
Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Embedded ICE (In-circuit Emulator)
128 Kbyte Internal RAM
384 Kbyte Internal ROM with u-blox GPS Firmware
6-channel Peripheral Data Controller (PDC)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 2 External Interrupts
24 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) V2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
– Ping-pong Mode for Isochronous and Bulk Endpoints
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
2.3V to 3.6V or 1.8V Core Supply Voltage
Includes Power Supervisor
1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
4 Kbytes Battery Backup Memory
8 mm × 8 mm 56 Pin QFN56 Package
Pb-free, RoHS-compliant, Green
GPS Baseband
Processor
ATR0622
Summary
Preliminary
Rev. 4891CS–GPS–01/06
1. Description
The GPS baseband processor ATR0622 includes a 16-channel GPS correlator and is based
on the ARM7TDMI® processor core.
This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast
exception handling, making the device ideal for real-time control applications. The ATR0622
has two USART and an USB device port. This port is compliant with the Universal Serial Bus
(USB) V2.0 full-speed device specification.
The ATR0622 includes full GPS firmware, licensed from u-blox AG, which performs the basic
GPS operation, including tracking, acquisition, navigation and position data output. For normal
PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM.
The firmware supports the possibility to store the configuration settings in an optional external
EEPROM. For customer-specific applications, a Software Development Kit is available.
The ATR0622 is manufactured using Atmel’s high-density CMOS technology. By combining
the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a
wide range of peripheral functions on a monolithic chip, the ATR0622 provides a highly flexible
and cost-effective solution for GPS applications.
2
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
Advanced
Power
Management
Controller
XT_IN
XT_OUT
GPS
Correlators
RTC
NSHDN
NSLEEP
GPS
Accelerator
ATR0622 Block Diagram
SRAM
RF_ON
CLK23
SMD
Generator
P15/ANTON
P0/NANTSHORT
P14/NAADET1
P25/NAADET0
SIGLO0
SIGHI0
Timer
Counter
Figure 1-1.
SPI
APB
PIO2
Special
Function
USART2
P31/RXD1
USB
Transceiver
USB_DP
USB_DM
Power
Supply
Manager
Reset
Controller
JTAG
NTRST
NRESET
ROM
384K
SRAM
128K
DBG_EN
TDI
TDO
TCK
TMS
ARM7TDMI
Embedded
ICE
ASB
Interface to
Off-Chip
Memory
(EBI)
PDC2
B
R
I
D
G
E
USB
Watchdog
P8/STATUSLED
P16/NEEPROM
P22/RXD2
P18/TXD1
USART1
P30/AGCOUT0
Advanced
Interrupt
Controller
P2/BOOT_MODE
P21/TXD2
PIO2
P9/EXTINT0
PIO2
Controller
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
VBAT18
VBAT
LDOBAT_IN
LDO_OUT
LDO_IN
LDO_EN
3
4891CS–GPS–01/06
2. Architectural Overview
2.1
Description
The ATR0622 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories. The APB is designed for accesses to
on-chip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides
an interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip
USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most
importantly, the PDC2 removes the processor interrupt handling overhead and significantly
reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the
microcontroller is increased and the power consumption reduced.
The ATR0622 peripherals are designed to be easily programmable with a minimum number of
instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of
the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address
space.) The peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status, and interrupt registers.
To maximize the efficiency of bit manipulation, frequently written registers are mapped into
three memory locations. The first address is used to set the individual register bits, the second
resets the bits, and the third address reads the value stored in the register. A bit can be set or
reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0”
has no effect. Individual bits can thus be modified without having to use costly read-modifywrite and complex bit-manipulation instructions.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O
(PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin
or generate an interrupt on a signal change. After reset, the user must carefully program the
PIO2 Controller in order to define which peripheral signals are connected with off-chip logic.
The ARM7TDMI® processor operates in little-endian mode on the ATR0622 GPS Baseband.
The processor's internal architecture and the ARM ® and Thumb ® instruction sets are
described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are
described in detail in the ATR0622 full datasheet. The electrical and mechanical characteristics are also documented in the ATR0622 full datasheet.
The ARM standard In-Circuit Emulator (ICE) debug interface is supported via the JTAG/ICE
port of the ATR0622.
For features of the ROM firmware, refer to the software documentation available from u-blox
AG, Switzerland.
4
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
3. Pin Configuration
3.1
Pinout
Figure 3-1.
Pinout QFN56 (Top View)
42
29
43
28
ATR0622
56
15
1
Table 3-1.
14
ATR0622 Pinout
Pin Name
QFN56
Pin
Type
CLK23
37
IN
DBG_EN
8
IN
GND
(2)
IN
LDOBAT_IN
21
IN
LDO_EN
25
IN
LDO_IN
20
IN
LDO_OUT
19
OUT
Pull Resistor
(Reset Value)(1)
PIO Bank A
Firmware Label
I
PIO Bank B
O
41
I/O
NSHDN
26
OUT
NSLEEP
24
OUT
NTRST
13
IN
P0
40
I/O
PD
NANTSHORT
P1
47
I/O
Configurable (PD)
GPSMODE0
P2
46
I/O
Configurable (PD)
BOOT_MODE
“0”
P8
48
I/O
Configurable (PD)
STATUSLED
“0”
P9
29
I/O
PU
EXTINT0
P12
49
I/O
Configurable (PU)
GPSMODE2
32
I/O
PU
GPSMODE3
P13
O
PD
NRESET
Notes:
I
Open Drain PU
PD
AGCOUT1
EXTINT0
NPCS2
EXTINT1
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. Ground plane
3. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 17.
4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 17.
5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP, see section “Power Supply” on page
17. For operation of the USB interface, supply of 3.0V to 3.6V is required.
6. This pin is not connected
5
4891CS–GPS–01/06
Table 3-1.
ATR0622 Pinout (Continued)
PIO Bank A
QFN56
Pin
Type
Pull Resistor
(Reset Value)(1)
Firmware Label
P14
1
I/O
Configurable (PD)
NAADET1
P15
17
I/O
PD
ANTON
Pin Name
I
PIO Bank B
O
I
O
“0”
P16
6
I/O
Configurable (PU)
NEEPROM
SIGHI1
P17
2
I/O
Configurable (PD)
GPSMODE5
SCK1
P18
45
I/O
Configurable (PU)
TXD1
P19
53
I/O
Configurable (PU)
GPSMODE6
SIGLO1
P20
4
I/O
Configurable (PD)
TIMEPULSE
SCK2
P21
52
I/O
Configurable (PU)
TXD2
P22
30
I/O
PU
RXD2
RXD2
P23
3
I/O
Configurable (PU)
GPSMODE7
SCK
NWD_OVF
SCK1
TXD1
“0”
“0”
SCK2
TIMEPULSE
TXD2
“0”
SCK
MCLK_OUT
P24
5
I/O
Configurable (PU)
GPSMODE8
MOSI
MOSI
“0”
P25
55
I/O
Configurable (PD)
NAADET0
MISO
MISO
“0”
P26
44
I/O
Configurable (PU)
GPSMODE10
NSS
NPCS0
“0”
P27
54
I/O
Configurable (PU)
GPSMODE11
NPCS1
P29
50
I/O
Configurable (PU)
GPSMODE12
NPCS3
P30
16
I/O
PD
AGCOUT0
AGCOUT0
RXD1
P31
31
I/O
PU
RF_ON
15
OUT
PD
SIGHI0
38
IN
SIGLO0
39
IN
TCK
9
IN
PU
TDI
10
IN
PU
TDO
11
OUT
TMS
12
IN
USB_DM
34
I/O
USB_DP
35
I/O
VBAT
22
IN
VBAT18(3)
23
OUT
VDD18
7, 14
IN
VDD18
18, 36
IN
VDD18
51
IN
(4)
VDDIO
43, 56
IN
VDD_USB(5)
33
IN
XT_IN
28
IN
XT_OUT
27
OUT
NC(6)
42
Notes:
“0”
RXD1
PU
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset
2. Ground plane
3. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 17.
4. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29, see section “Power Supply” on page 17.
5. VDD_USB is the supply voltage for following the USB-pins: USB_DM and USB_DP, see section “Power Supply” on page
17. For operation of the USB interface, supply of 3.0V to 3.6V is required.
6. This pin is not connected
6
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
3.2
Signal Description
Table 3-2.
ATR0622 Signal Description
Module
Name
EBI
USART
USB
Function
Type
BOOT_MODE
Boot Mode Input
Input
–
PIO-controlled after reset,
internal pull-down resistor
TXD1 to TXD2
Transmit Data Output
Output
–
PIO-controlled after reset
RXD1 to RXD2
Receive Data Input
Input
–
PIO-controlled after reset
SCK1 to SCK2
PIO-controlled after reset
External Synchronous Serial Clock
I/O
–
USB_DP
USB Data (D+)
I/O
–
USB_DM
USB Data (D-)
I/O
–
Output
–
Input
High/
Low/
Edge
PIO-controlled after reset
Automatic Gain Control
Output
–
Interface to ATR0601
PIO-controlled after reset
NSLEEP
Sleep Output
Output
Low
Interface to ATR0601
NSHDN
Shutdown Output
Output
Low
Connect to pin LDO_EN
Input
–
APMC
RF_ON
AIC
EXTINT0-1
AGC
AGCOUT0-1
RTC
XT_IN
XT_OUT
SPI
External Interrupt Request
Oscillator Input
Oscillator Output
Interface to ATR0601
RTC oscillator
Output
–
RTC oscillator
SCK
SPI Clock
I/O
–
PIO-controlled after reset
MOSI
Master Out Slave In
I/O
–
PIO-controlled after reset
MISO
Master In Slave Out
I/O
–
PIO-controlled after reset
NSS/NPCS0
Slave Select
I/O
Low
PIO-controlled after reset
NPCS1 to NPCS3
Slave Select
Output
Low
PIO-controlled after reset
Output
–
PIO-controlled after reset
I/O
–
Input after reset
WD
NWD_OVF
Watchdog Timer Overflow
PIO
P0 to P31
Programmable I/O Port
GPS
SIGHI0
Digital IF
Input
–
Interface to ATR0601
SIGLO0
Digital IF
Input
–
Interface to ATR0601
SIGHI1
Digital IF
Input
–
PIO-controlled after reset
SIGLO1
Digital IF
Input
–
PIO-controlled after reset
TIMEPULSE
Output
–
PIO-controlled after reset
GPSMODE0-12
GPS Mode
Input
–
PIO-controlled after reset
STATUSLED
Status LED
Output
–
PIO-controlled after reset
Input
Low
PIO-controlled after reset
NEEPROM
CONFIG
ANTON
NANTSHORT
NAADET0-1
Note:
Active Level Comment
GPS synchronized time pulse
Enable EEPROM Support
Active antenna power on Output
Output
–
PIO-controlled after reset
Active antenna short circuit
detection Input
Input
Low
PIO-controlled after reset
Active antenna detection Input
Input
Low
PIO-controlled after reset
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND
(internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
7
4891CS–GPS–01/06
Table 3-2.
Module
ATR0622 Signal Description (Continued)
Name
TMS
JTAG/ICE
Test Data In
TCK
8
Internal pull-up resistor
Internal pull-up resistor
–
–
Test Clock
Input
–
Test Reset Input
Input
Low
Internal pull-down resistor
Debug Enable
Input
High
Internal pull-down resistor
Clock Input
Input
–
Interface to ATR0601,
Schmitt trigger input
Output
–
PIO-controlled after reset
I/O
Low
VDD18
Power
–
Core voltage 1.8V
VDDIO
Power
–
Variable IO voltage 1.65V to 3.6V
VDD_USB
Power
–
USB voltage 0 to 2.0V or
3.0V to 3.6V(1)
GND
Power
–
Ground
LDOBAT_IN
Power
–
2.3V to 3.6V
VBAT
Power
–
1.5V to 3.6V
VBAT18
Out
–
1.8V backup voltage
LDO In
Power
–
2.3V to 3.6V
LDO Out
Power
–
1.8V core voltage, max. 80 mA
LDO Enable
Input
–
NRESET
LDO_OUT
LDO_EN
Note:
–
Input
LDO_IN
LDO18
Active Level Comment
Output
MCLK_OUT
LDOBAT
Input
Test Data Out
CLK23
POWER
Test Mode Select
TDI
DBG_EN
RESET
Type
TDO
NTRST
CLOCK
Function
Master Clock Output
Reset Input
Internal pull-up resistor
Open drain with internal pull-up
resistor
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND
(internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
3.3
Setting GPSMODE0 to GPSMODE12
The start-up configuration of a ROM-based system without external non-volatile memory is
defined by the status of the GPSMODE pins after system reset. Alternatively, the system can
be configured through message commands passed through the serial interface after start-up.
This configuration of the ATR0622 can be stored in an external non-volatile memory like
EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is
disabled (GPSMODE0 = 0).
Table 3-3.
GPSMODE Functions
Pin
Function
GPSMODE0 (P1)
Enable configuration with GPSMODE pins
GPSMODE1 (P9)
This pin (EXTINT0) is used for FixNow functionality and not used for GPSMODE
configuration.
GPSMODE2 (P12)
GPSMODE3 (P13)
GPSMODE4 (P14)
GPSMODE5 (P17)
GPSMODE6 (P19)
GPS sensitivity settings
This pin (NAADET1) is used as active antenna supervisor input and not used for
GPSMODE configuration. This is the default selection if GPSMODE configuration
is disabled.
Serial I/O configuration
GPSMODE7 (P23)
USB Power Mode
GPSMODE8 (P24)
General I/O Configuration
GPSMODE9 (P25)
This pin (NAADET0) is used as active antenna supervisor input and not used for
GPSMODE configuration.
GPSMODE10 (P26)
GPSMODE11 (P27)
General I/O Configuration
GPSMODE12 (P29) Serial I/O configuration
3.3.1
Enable GPSMODE Pin Configuration
Table 3-4.
Enable Configuration with GPSMODE Pins
GPSMODE0
(Reset = PD) Description
0
Ignore all GPSMODE pins. The default settings as indicated below are used.
1
Use settings as specified with GPSMODE[2, 3, 5 to 8, 10 to 12]
If the GPSMODE configuration is enabled (GPSMODE0 = 1) and the other GPSMODE pins
are not connected externally, the reset default values of the internal pull-down and pull-up
resistors will be used.
9
4891CS–GPS–01/06
3.3.2
Sensitivity Settings
Table 3-5.
GPSMODE3
(Fixed PU)
3.3.3
GPS Sensitivity Settings
GPSMODE2
(Reset = PU) Description
0
0
Auto mode
0
1
Fast mode
1
0
Normal mode (Default ROM value)
1
1
High sensitivity
Serial I/O Configuration
The ATR0622 features a two-stage I/O message and protocol selection procedure for the two
available serial ports. At the first stage, a certain protocol can be enabled or disabled for a
given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the
second stage, messages can be enabled or disabled for each enabled protocol on each port.
In all configurations discussed below, all protocols are enabled on all ports. But output messages are enabled in a way that ports appear to communicate at only one protocol. However,
each port will accept any input message in any of the three implemented protocols
Table 3-6.
Serial I/O Configuration
USART1/USB
USART2
GPSMODE5 (Output Protocol/
(Output Protocol/
(Reset = PD) Baud Rate (kBaud)) Baud Rate (kBaud)) Messages Information Messages
GPSMODE12
(Reset = PU)
GPSMODE6
(Reset = PU)
0
0
0
UBX/57.6
NMEA/19.2
High
User, Notice, Warning, Error
0
0
1
UBX/38.4
NMEA/9.6
Medium
User, Notice, Warning, Error
0
1
0
UBX/19.2
NMEA/4.8
Low
User, Notice, Warning, Error
0
1
1
–/Auto
–/Auto
Off
None
1
0
0
NMEA/19.2
UBX/57.6
High
User, Notice, Warning, Error
1
0
1
NMEA/4.8
UBX/19.2
Low
User, Notice, Warning, Error
1
1
0
NMEA/9.6
UBX/38.4
Medium
User, Notice, Warning, Error
1
1
1
UBX/115.2
NMEA/19.2
Debug
All
Both USART ports and the USB port accept input messages in all three supported protocols
(NMEA, RTCM and UBX) at the configured baud rate. Input messages of all three protocols
can be arbitrarily mixed. Response to a query input message will always use the same protocol as the query input message. The USB port does only accept NMEA and UBX as input
protocol by default. RTCM can be enabled via protocol messages on demand.
In Auto Mode, no output message is sent out by default, but all input messages are accepted
at any supported baud rate. Again, USB is restricted to only NMEA and UBX protocols.
Response to query input commands will be given the same protocol and baud rate as it was
used for the query command. Using the respective configuration commands, periodic output
messages can be enabled.
10
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
The following message settings are used in the tables below:
Table 3-7.
NMEA Port
UBX Port
Table 3-8.
NMEA Port
UBX Port
Table 3-9.
NMEA Port
UBX Port
Table 3-10.
NMEA Port
UBX Port
Supported Messages at Setting Low
Standard
GGA, RMC
NAV
SOL, SVINFO
MON
EXCEPT
Supported Messages at Setting Medium
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA
NAV
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
MON
EXCEPT
Supported Messages at Setting High
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST
Proprietary
PUBX00, PUBX03, PUBX04
NAV
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
MON
SCHD, IO, IPC, EXCEPT
Supported Messages at Setting Debug (Additional Undocumented Message
May be Part of Output Data)
Standard
GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST
Proprietary
PUBX00, PUBX03, PUBX04
NAV
SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF,
VELNED, TIMEGPS, TIMEUTC, CLOCK
MON
SCHD, IO, IPC, EXCEPT
RXM
RAW (RAW message support requires an additional license)
The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0
(ROM-Defaults):
Table 3-11.
Serial I/O Default Setting if GPSMODE Configuration is Deselected
(GPSMODE0 = 0)
USB
NMEA
Baud Rate (kBaud)
USART1
NMEA
USART2
UBX
57.6
57.6
Input Protocol
UBX, NMEA
UBX, NMEA, RTCM
UBX, NMEA, RTCM
Output Protocol
NMEA
NMEA
UBX
Messages
GGA, RMC, GSA, GSV
GGA, RMC, GSA, GSV
NAV: SOL, SVINFO
MON: EXCEPT
User, Notice, Warning,
Error
User, Notice, Warning,
Error
Information Messages
User, Notice, Warning,
(UBX INF or NMEA
Error
TXT)
11
4891CS–GPS–01/06
3.3.4
USB Power Mode
For correct response to the USB host queries, the device has to know its power mode. This is
configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported
to the USB host; that is, the device classifies itself as a “low-power bus-powered function” with
no more than one USB power unit load.
Table 3-12.
USB Power Modes
GPSMODE7 (Reset = PU) Description
3.3.5
0
USB device is bus-powered (max. current limit 100 mA)
1
USB device is self-powered (Default ROM value)
Active Antenna Supervisor
The two pins P0/NANTSHORT and P15/ANTON plus one pin of P25/NAADET0/MISO or
P14/NAADET1 are always initialized as general purpose I/Os and used as follows:
• P15/ANTON is an output which can be used to switch on and off antenna power supply.
• Input P0/NANTSHORT will indicate an antenna short circuit, i.e. zero DC voltage at the
antenna, to the firmware. If the antenna is switched off by output P15/ANTON, it is
assumed that also input P0/NANTSHORT will signal zero DC voltage, i.e. switch to its
active low state.
• Input P25/NAADET0/MISO or P14/NAADET1 will indicate a DC current into the antenna. In
case of short circuit, both P0 and P25/P14 will be active, i.e. at low level. If the antenna is
switched off by output P15/ANTON, it is assumed that also input P25/NAADET0/MISO will
signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET
(P14 or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see Table 3-14
on page 13).
Table 3-13.
12
Pin Usage of Active Antenna Supervisor
Pin
Usage
Meaning
P0/NANTSHORT
NANTSHORT
Active antenna short circuit detection
High = No antenna DC short circuit present
Low = Antenna DC short circuit present
P25/NAADET0/
MISO or
P14/NAADET1
NAADET
Active antenna detection input
High = No active antenna present
Low = Active antenna is present
P15/ANTON
ANTON
Active antenna power on output
High = Power supply to active antenna is switched on
Low = Power supply to active antenna is switched off
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
Table 3-14.
Antenna Detection I/O Settings
GPSMODE11 GPSMODE10 GPSMODE8
(Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET
Comment
0
0
0
P25/NAADET0/MISO
0
0
1
P25/NAADET0/MISO
0
1
0
P14/NAADET1
0
1
1
P14/NAADET1
(Default ROM value)
1
0
0
P14/NAADET1
Reserved for further use.
Do not use this setting.
1
0
1
P14/NAADET1
Reserved for further use.
Do not use this setting.
1
1
0
P25/NAADET0/MISO
1
1
1
P25/NAADET0/MISO
Reserved for further use.
Do not use this setting.
The Antenna Supervisor Software will be configured as follows:
1. Enable Control Signal
2. Enable Short Circuit Detection (power down antenna via ANTON if short is detected
via NANTSHORT)
3. Enable Open Circuit Detection via NAADET
The antenna supervisor function may not be disabled by GPSMODE pin selection.
13
4891CS–GPS–01/06
3.4
External Connections for a Working GPS System
Figure 3-2.
Example of an External Connection
ATR0601
SIGH
SIGL
SC
PURF
PUXTO
SIGHI
SIGLO
CLK23
RF_ON
NSLEEP
NC
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
see Table 3-15
NRESET
P0 - 2
P9
P12 - 17
P19
P23 - 27
P29 - 30
NC
NC
NC
NC
NC
TMS
TCK
TDI
NTRST
TDO
NC
DBG_EN
GND
+3V
(see Power Supply)
GND
NSHDN
LDO_EN
LDO_OUT
VDD18
LDO_IN
LDOBAT_IN
ATR0622
P8
P20
STATUS LED
TIMEPULSE
USB_DM
USB_DP
Optional
USB
P31
P18
Optional
USART 1
P22
P21
Optional
USART 2
XT_IN
XT_OUT
32.368 kHz
(see RTC)
+3V
(see Power Supply)
VDDIO
+3V
(see Power Supply)
VBAT18
VBAT
VDD_USB
+3V
(see Power Supply)
GND
NC: Not connected
14
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
Table 3-15.
Recommended Pin Connection
Pin Name
Recommended External Circuit
P0/NANTSHORT
Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if
configured as output by user application.
P1/GPSMODE0
Internal pull-down resistor, leave open, in order to disable the GPSMODE pin configuration feature. Connect
to VDDIO to enable the GPSMODE pin configuration feature. Refer to GPSMODE definitions in section
“Setting GPSMODE0 to GPSMODE12” on page 9. Can be left open if configured as output by user
application.
P2/BOOT_MODE
Internal pull-down resistor, leave open.
P8/STATUSLED
Output in default ROM firmware: leave open, only needs pull-up resistor to VDDIO or pull-down resistor to
GND if used as GPIO input by user application and is not always driven from external sources.
P9/EXTINT0
Internal pull-up resistor, leave open if unused.
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
P12/GPSMODE2/NPCS2
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P13/GPSMODE3/
EXTINT1
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P14/NAADET1
Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if
configured as output by user application.
P15/ANTON
Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if
configured as output by user application.
P16/NEEPROM
Internal pull-up resistor, leave open if no serial EEPROM is connected. Otherwise connect to GND.
P17/GPSMODE5/SCK1
Internal pull-down resistor, can be left open if the GPSMODE feature is not used or configured as output by
user application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page
9.
P18/TXD1
Output in default ROM firmware: leave open if serial interface is not used.
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
P19/GPSMODE6/SIGLO1
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P20/TIMEPULSE/SCK2
Output in default ROM firmware: leave open if timepulse feature is not used.
P21/TXD2
Output in default ROM firmware: leave open if serial interface not used.
P22/RXD2
Internal pull-up resistor, leave open if serial interface is not used.
P23/GPSMODE7/SCK
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P24/GPSMODE8/MOSI
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P25/NAADET0/MISO
Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if
configured as output by user application.
P26/GPSMODE10/NSS/
NPCS0
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P27/GPSMODE11/NPCS1
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P29/GPSMODE12/NPCS3
Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user
application. Refer to GPSMODE definitions in section “Setting GPSMODE0 to GPSMODE12” on page 9.
P30/AGCOUT0
Internal pull-down resistor, leave open.
P31/RXD1
Internal pull-up resistor, leave open if serial interface is not used.
15
4891CS–GPS–01/06
3.4.1
Connecting an Optional Serial EEPROM
The ATR0622 offers the possibility to connect an external serial EEPROM. The internal ROM
firmware supports to store the configuration of the ATR0622 in serial EEPROM. The pin
P16/NEEPROM signals the firmware that a serial EEPROM is connected with the ATR0622.
The 32-bit RISC processor of the ATR0622 accesses the external memory with SPI (Serial
Peripheral Interface). Atmel recommend to use 32 Kbit 1.8V serial EEPROM, e.g. the Atmel
AT25320AY1-1.8. Figure 3-3 shows an example of the serial EEPROM connection.
Figure 3-3.
Example of a Serial EEPROM Connection
AT25320AY1-1.8
ATR0622
P23/SCK
P24/MOSI
P25/MISO/NAADET0
P29/NPCS3
SCK
SI
SO
CS_N
HOLD_N
WP_N
GND
NC
P16/NEEPROM
P1/GPSMODE0
GND
GND
NSHDN
LDO_EN
LDO_OUT
VDD18
VDDIO
+3V
(see Power Supply)
LDO_IN
LDOBAT_IN
NC: Not connected
Note:
16
The GPSMODE pin configuration feature can be disabled, because the configuration can be
stored in the serial EEPROM. VDDIO is the supply voltage for the pins: P23, P24, P25 and P29.
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
4. Power Supply
The baseband IC is supplied with four distinct supply voltages:
• VDD18, the nominal 1.8V supply voltage for the core, the RF-I/O pins, the memory
interface and the test pins and all GPIO-pins not mentioned in next item.
• VDDIO, the variable supply voltage within 1.8V to 3.6V for following GPIO-pins: P1, P2, P8,
P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 In input mode,
these pins are 5V input tolerant.
• VDD_USB, the power supply of the USB pins: USB_DM and USB_DP.
• VBAT18 to supply the backup domain: RTC, backup SRAM and the pins NSLEEP, NSHDN,
LDO_EN, VBAT18, P9/EXTIN0, P13/EXTINT1, P22/RXD2 and P31/RXD1 and the 32kHz
oscillator. In input mode, the four GPIO-pins are 5V input tolerant.
Figure 4-1, Figure 4-2, and Figure 4-3 show examples of the wiring of ATR0622 power supply.
Figure 4-1.
External Wiring Example Using Internal LDOs and Backup Power Supply
ATR0622 internal
2.3V to 3.6V
LDO_IN
NSHDN
LDO_EN
LDO_OUT
LDO18
ldoin
ldoen
ldoout
VDD18
Core
VDDIO
1.8V to 3.3V
variable IO Domain
1 µF
(X7R)
ldobat_in
LDOBAT
LDOBAT_IN
1.5V to 3.6V
VBAT
VBAT18
vbat
vbat18
vdd
1 µF
(X7R)
RTC
Backup Memory
0 to 2V or 3V to 3.6V
VDDUSB
USB SM and
Transceiver
17
4891CS–GPS–01/06
The baseband IC contains a built in low dropout voltage regulator LDO18. This regulator can
be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such
case, LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and
3.6V. The LDO_EN input can be used to shut down VDD18 if the system is in standby mode.
If the host system does however supply a 1.8V core voltage directly, this voltage has to be
connected to the VDD18 supply pins of the baseband IC. LDO_EN must be connected to
GND. LDO_IN can be connected to GND. LDO_OUT must not be connected.
A second built in low dropout voltage regulator LDOBAT provides the supply voltage for the
RTC and backup SRAM from any input voltage LDOBAT_IN between 2.3V and 3.6V or from
VBAT between 1.5V and 3.6V. The backup battery connected to VBAT is only discharged if
the supply connected to LDOBAT_IN is shut-down.
Only after VDD18 has been supplied to ATR0622 the RTC section will be initialized properly. If
only VBAT is applied first, the current consumption of the RTC and backup SRAM is
undetermined.
Figure 4-2.
External Wiring Example Using 1.8V from Host System and Backup Power
Supply
ATR0622 internal
LDO_IN
LDO_EN
LDO_OUT
LDO18
ldoin
ldoen
ldoout
1.65V to 1.95V
1 µF
(X7R)
VDD18
Core
VDDIO
1.8V to 3.3V
variable IO Domain
2.3V to 3.6V
ldobat_in
LDOBAT
LDOBAT_IN
1.5V to 3.6V
VBAT
VBAT18
vbat
vbat18
vdd
1 µF
(X7R)
RTC
Backup Memory
0 to 2V or 3V to 3.6V
18
VDDUSB
USB SM and
Transceiver
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and
USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is
enabled if VDD_USB within 3.0V and 3.6V.
Figure 4-3.
External Wiring Example Using Internal LDOs, USB Supply Voltage and Backup Power Supply
ATR0622 internal
LDO_IN
NSHDN
LDO_EN
LDO_OUT
LDO18
ldoin
ldoen
ldoout
VDD18
Core
VDDIO
1.8V to 3.3V
variable IO Domain
1 µF
(X7R)
ldobat_in
LDOBAT
LDOBAT_IN
1.5V to 3.6V
VBAT
VBAT18
vbat
vbat18
vdd
1 µF
(X7R)
RTC
Backup Memory
USB-VSB 5V
External
LDO 3.3V
VDDUSB
USB SM and
Transceiver
19
4891CS–GPS–01/06
5. Oscillator
Figure 5-1.
Crystal Connection
ATR0622 internal
XT_IN
32 kHz
Crystal
Oscillator
32.768 kHz
50 ppm
32.768 kHz clock
RTC
XT_OUT
max.
25 pF
max.
25 pF
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Pin
Symbol
Min.
Max.
Unit
Operating Free Air Temperature Range
–40
+85
°C
Storage Temperature
–60
+150
°C
DC Supply Voltage
VDD18
–0.3
+1.95
V
DC Supply Voltage
VDDIO
–0.3
+3.6
V
DC Supply Voltage
VDD_USB
–0.3
+3.6
V
DC Supply Voltage
LDO_IN
–0.3
+3.6
V
DC Supply Voltage
LDOBAT_IN
–0.3
+3.6
V
DC Supply Voltage
VBAT
–0.3
+3.6
V
DC Input Voltage
P0, P15, P30, SIGHI, SIGLO,
CLK23, XT_IN, TMS, TCK,
TDI, NTRST, DBG_EN,
LDO_EN, NRESET
–0.3
+1.95
V
DC Input Voltage
USB_DM, USB_DP
–0.3
+3.6
V
+5.0
V
P1, P2, P8, P9, P12 to P14,
DC Input Voltage
–0.3
P16 to P27, P29, P31
Note:
Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified
20
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
7. Electrical Characteristics
If no additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C.
No.
Parameters
1.1
Pin
Symbol
Min.
Typ.
Max.
Unit
DC Supply Voltage Core
VDD18
VDD18
1.65
1.8
1.95
V
1.2
DC Supply Voltage VDDIO
Domain(1)
VDDIO
VDDIO
1.65
1.8/3.3
3.6
V
1.3
DC Supply Voltage USB(2)
VDD_USB
VDDUSB
3.0
3.3
3.6
V
1.4
DC Supply Voltage Backup
Domain(3)
VBAT18
VBAT18
1.65
1.8
3.6
V
1.5
DC Output Voltage VDD18
VO,18
0
VDD18
V
1.6
DC Output Voltage VDDIO
VO,IO
0
VDDIO
V
1.7
Low-level Input Voltage
VDD18 Domain
VDD18 = 1.65V to 1.95V
VIL,18
–0.3
0.3 ×
VDD18
V
1.8
High-level Input Voltage
VDD18 Domain
VDD18 = 1.65V to 1.95V
VIH,18
0.7 ×
VDD18
VDD18 +
0.3
V
1.9
Low-level Input Voltage
VDDIO Domain
VDDIO = 1.65V to 3.6V
VIL,IO
–0.3
+0.41
V
1.10
High-level Input Voltage
VDDIO Domain
VDDIO = 1.65V to 3.6V
VIH,IO
1.46
5.0
V
1.11
Low-level Input Voltage
VBAT18 Domain
VBAT18 = 1.65V to 1.95V
P9, P13, P22,
P31
VIL,BAT
–0.3
+0.41
V
1.12
High-level Input Voltage
VBAT18 Domain
VBAT18 = 1.65V to 1.95V
P9, P13, P22,
P31
VIH,BAT
1.46
5.0
V
1.13 Low-level Input Voltage USB VDD_USB = 3.0V to 3.6V
DP, DM
VIL,USB
–0.3
+0.8
V
1.14 High-level Input Voltage USB VDD_USB = 3.0V to 3.6V
DP, DM
VIH,USB
2.0
4.6
V
0.4
V
Low-level Output Voltage
1.15
VDD18 Domain
Test Conditions
IOL = 1.5 mA, VDD18 = 1.65V
VOL,18
1.16
High-level Output Voltage
VDD18 Domain
IOH = –1.5 mA,
VDD18 = 1.65V
VOH,18
1.17
Low-level Output Voltage
VDDIO Domain
IOL = 1.5 mA, VDDIO = 3.0V
VOL,IO
1.18
High-level Output Voltage
VDDIO Domain
IOH = –1.5 mA, VDDIO = 3.0V
VOH,IO
1.19
Low-level Output Voltage
VBAT18 Domain
IOL = 1 mA
P9, P13, P22,
P31
VOL,BAT
1.20
High-level Output Voltage
VBAT18 Domain
IOH = –1 mA
P9, P13, P22,
P31
VOH,BAT
1.21
Low-level Output Voltage
USB
IOL = 1.5 mA,
VDD_USB = 3.0V to 3.6V,
27Ω external series resistor
DP, DM
VOL,USB
1.22
High-level Output Voltage
USB
IOH = –1.5 mA,
VDD_USB = 3.0V to 3.6V,
27Ω external series resistor
DP, DM
VOH,USB
Notes:
VDD18 –
0.45
V
0.4
VDDIO –
0.5
V
0.4
1.2
V
V
0.4
2.7
V
V
V
1. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT
21
4891CS–GPS–01/06
7. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to a temperature range from –40°C to +85°C.
No.
Parameters
Test Conditions
1.23
Input-leakage Current
(standard Inputs and I/Os)
VDD18 = 1.95V
VIL = 0V
Pin
1.24 Input Capacitance
Symbol
Min.
ILEAK
–1
Typ.
ICAP
Max.
Unit
+1
µA
10
pF
1.25 Input Pull-up Resistor
NRESET
RPU
0.7
1.6
kΩ
1.26 Input Pull-up Resistor
TCK, TDI,
TMS
RPU
10
30
kΩ
1.27 Input Pull-up Resistor
P9, P13, P22,
P31
RPU
100
220
kΩ
1.28 Input Pull-down Resistor
DBG_EN,
NTRST,
RPD
10
30
kΩ
1.29 Input Pull-down Resistor
RF_ON, P0,
P15, P30
RPD
100
220
kΩ
Configurable Input Pull-up
1.30
Resistor
P1, P2, P8,
P12, P14,
P[16-21],
P[23-27], P29
RCPU
62
330
kΩ
Configurable Input Pull-down
1.31
Resistor
P1, P2, P8,
P12, P14,
P[16-21],
P[23-27], P29
RCPD
45
160
kΩ
1.32
Configurable Input Pull-up
Resistor (Idle state)
USB_DP
RCPU
0.9
1.575
kΩ
1.33
Configurable Input Pull-up
Resistor (Operation state)
USB_DP
RCPU
1.425
3.09
kΩ
USB_DP
USB_DM
RPD
10
500
kΩ
1.34 Input Pull-down Resistor
Notes:
1. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29
2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground
3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT
22
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
8. Power Consumption
Mode
Conditions
Typ.
Unit
(1)
Sleep
At 1.8V, no CLK23
0.065
Shutdown
RTC, backup SRAM and LDOBAT
0.007(1)
Normal
Note:
Satellite acquisition
25
Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA
14
All channels disabled
11
mA
1. Specified value only
9. ESD Sensitivity
The ATR0622 is an ESD sensitive device. The current ESD values are to be defined.
Observe precautions for handling
10. LDO18
The LDO18 is a built in low dropout voltage regulator which can be used if the host system
does not provide the core voltage VDD18.
Table 10-1.
Electrical Characteristics of LDO18
Parameter
Conditions
Min.
Supply voltage LDO_IN
2.3
Output Voltage
(LDO_OUT)
1.65
Typ.
1.8
Output Current
(LDO_OUT)
Current consumption
After startup, no load, at room
temperature
Current consumption
Standby Mode (LDO_EN = 0), at room
temperature
1
Max.
Unit
3.6
V
1.95
V
80
mA
80
µA
5
µA
23
4891CS–GPS–01/06
11. LDOBAT and Backup Domain
The LDOBAT is a built in low dropout voltage regulator which provides the supply voltage
VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT
voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V.
Table 11-1.
Electrical Characteristics of LDOBAT
Parameter
Conditions
Supply voltage
LDOBAT_IN
Typ.
2.3
Supply voltage VBAT
1.5
Output Voltage (VBAT18) If switch connects to LDOBAT_IN.
1.65
Output Current (VBAT18)
1.8
Max.
Unit
3.6
V
3.6
V
1.95
V
1.5
mA
Current consumption
LDOBAT_IN(1)
After startup (sleep/backup mode), at
room temperature
15
µA
Current consumption
VBAT(1)
After startup (backup mode and
LDOBAT_IN = 0V), at room
temperature
10
µA
Current consumption
After startup (normal mode), at room
temperature
1.5
mA
Note:
24
Min.
1. If no current is caused by outputs (pad output current as well as current across internal
pull-up resistors)
ATR0622 [Preliminary]
4891CS–GPS–01/06
ATR0622 [Preliminary]
12. Ordering Information
Extended Type Number
Package
MPQ
Remarks
ATR0622-PYQW
QFN56
2000
8 mm × 8 mm, 0.50 mm pitch, Pb-free,
RoHS-compliant, green
ATR0621-EK1
-
1
Evaluation kit/Road test kit
13. Package QFN56
Package: QFN56 8 x 8
Exposed pad 6.5 x 6.5
Dimensions in mm
Not indicated tolerances ±0.05
0.9 max.
8
+0
0.05-0.05
6.5
43
56
1
56
1
42
Pin 1 ID
technical drawings
according to DIN
specifications
29
14
28
0.4±0.1
0.25
14
15
0.5 nom.
Drawing-No.: 6.543-5121.01-4
Issue: 1; 02.09.05
25
4891CS–GPS–01/06
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
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