Rohm BD9876EFJ Flexible step-down switching regulator with built-in power mosfet Datasheet

Single-chip Type with Built-in FET Switching Regulators
Flexible Step-down
Switching Regulator
with Built-in Power MOSFET
BD9876EFJ
No.11027EBT58
●Description
Output 3.0A and below High Efficiency Rate Step-down Switching Regulator Power MOSFET Internal Type BD9876EFJ
mainly used as secondary side Power supply, for example from fixed Power supply of 12V, 24V etc, Step-down Output of
1.2V/1.8V/3.3V/5V, etc, can be produced. This IC has external Coil/Capacitor down-sizing through 300kHz Frequency
operation, inside Nch-FET SW for 45V “withstand-pressure” commutation and also, high speed load response through
Current Mode Control is a simple external setting phase compensation system, through a wide range external constant, a
compact Power supply can be produced easily.
●Features
1) Internal 200 mΩ Nch MOSFET
2) Output Current 3A
3) Oscillation Frequency 300kHz
4) Synchronizes to External Clock ( 200kHz～500kHz )
5) Feedback Voltage 1.0V±1.0%
6) Internal Soft Start Function
7) Internal Over Current Protect Circuit, Low Input Error Prevention Circuit, Heat Protect Circuit
8) ON/OFF Control through EN Pin (Standby Current 0 A Typ.)
9) Package: HTSOP-J8 Package
●Applications
For Household machines in general that have 12V/24V Lines, etc.
●Absolute Maximum Rating
Parameter
VCC-GND Supply Voltage
BST-GND Voltage
Symbol
Ratings
Unit
VCC
45
V
VBST
50
V
⊿VBST
7
V
EN-GND Voltage
VEN
45
V
Lx-GND Voltage
VLX
45
V
FB-GND Voltage
VFB
7
V
BST-Lx Voltage
VC-GND Voltage
SYNC-GND Voltage
VC
7
V
SYNC
7
V
High-side FET Drain Current
IDH
3.5
A
Power Dissipation
Pd
3.76(*1)
W
Topr
-40～+105
℃
Storage Temperature
Tstg
-55～+150
℃
Junction Temperature
Tjmax
+150
℃
Operating Temperature
(*1)During mounting of 70×70×1.6t mm 4layer board (Copper area: 70mm×70mm).Reduce by 30.08mW for every 1℃ increase. (Above 25℃)
●Operating Conditions (Ta=25℃)
Parameter
Power Supply Voltage
Output Voltage
Symbol
VCC
VOUT
Ratings
Unit
Min.
Typ.
Max.
7
－
42
V
－
VCC×0.7
V
(*2)
1.0
(*2)Restricted by minimum on pulse typ. 200ns
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1/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=24V, Vo=5V,EN=3V)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
【Circuit Current】
Stand-by current of VCC
Ist
－
0
10
µA
VEN=0V
Circuit current of VCC
Icc
－
1
2
mA
FB=1.2V
Vuv
6.1
6.4
6.7
V
Vuvhy
－
200
300
mV
fosc
270
300
330
kHz
Dmax
85
91
97
%
FB threshold voltage
VFB
0.990
1.000
1.010
V
Input bias current
IFB
-1.0
0
1.0
µA
Error amplifier DC gain
AVEA
700
7000
70000
V/V
Trans Conductance
GEA
110
220
440
µA/V
Soft Start Time
Tsoft
7
10
13
ms
GCS
5
10
20
A/V
Lx NMOS ON resistance
RonH
－
200
340
mΩ
Lx pre-charge NMOS ON resistance
RonL
－
10
17
Ω
Over Current Detect Current
Iocp
3.5
6
－
A
【Under Voltage Lock Out (UVLO)】
Detect Voltage
Hysteresis width
【Oscillator】
Oscillating frequency
Max Duty Cycle
【Error Amp】
VFB=0V
IVC=±10µA,
VC=1.5V
【Current Sense Amp】
VC to switch current transconductance
【Output】
【CTL】
ON
VENON
2
－
VCC
V
OFF
VENOFF
-0.3
－
0.8
V
REN
2.7
5.5
11
µA
High
VSYNCH
2.0
－
5.5
V
Low
VSYNCL
-0.3
－
0.8
V
SYNC Pin input current
REN
6
12
24
µA
SYNC falling edge to LX rising edge delay
tdelay
200
400
600
ns
EN Pin Control voltage
EN Pin input current
VEN=3V
【SYNC】
SYNC Pin Control voltage
VSYNC=3V
◎ Not designed to withstand radiation.
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2/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Pin Description
8
7
6
5
Thermal Pad
1
2
3
4
Fig.1 Pin Layout Diagram
Pin
No.
Pin
Name
1
Lx
2
GND
3
VC
Error amplifier output
4
FB
Inverting node of the trans conductance error amplifier
5
SYNC
6
EN
Stand-by ON/OFF pin
7
BST
Voltage Supply pin for High Side FET Driver
8
VCC
Voltage input pin
Function
Terminal for inductor
Ground pin
Input pin of an external signal for the device
synchronized by external signal
●Block Diagram
ON/OFF
EN
VCC
TSD
UVLO
Reference
REG
Current
Sense
AMP
VREF
Shutdown
FB
1.0V
+
+
Error AMP
Σ
BST
Current
Comparator
R Q
+
S
200mΩ
LX
Soft
Start
10Ω
Oscillator
300kHz
VC
VOUT
GND
SYNC
Fig.2 Block Diagram
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3/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Block Description
1. Reference
This Block generates Error Amp Standard Voltage.
Standard Voltage is 1.0V.
2.
REG
This is a Gate Drive Voltage Generator and 5V Low Saturation regulator for internal Circuit Power supply.
3.
OSC
This is a precise wave Oscillation Circuit with Operation Frequency fixed to 300 kHz fixed (self-running mode).
To implement the synchronization feature connect a square wave (Hi Level: higher than 2V Low Level: lower than
0.8V ) to the SYNC pin. The synchronization frequency range is 200 kHz to 500 kHz.
After connecting the rising edge of LX will be synchronized to the falling edge of SYNC pin signal after 3 count.
At the synchronization remove the external clock, the device transitions self-running mode after 7 microseconds.
4.
Soft Start
A Circuit that does Soft Start to the Output Voltage of DC/DC Comparator, and prevents Rush Current during Start-up.
Soft Start Time is set at IC internal, after 10ms from starting-up EN Pin, Standard Voltage comes to 1.0V, and Output
Voltage becomes set Voltage.
5.
ERROR AMP
This is an Error amplifier what detects Output Signal, and outputs PWM Control Signal.
Internal Standard Voltage is set to 1.0V. Also, C and R are connected between the Output (VC) Pin GND of Error Amp
as Phase compensation elements. (See P.11)
6.
ICOMP
This is a Voltage-Pulse Width Converter that controls Output Voltage in response to Input Voltage.
This compares the Voltage added to the internal SLOPE waveform in response to the FET WS Current with Error
amplifier Output Voltage, controls the width of Output Pulse and outputs to Driver.
7.
Nch FET SW
This is an internal commutation SW that converts Coil Current of DC/DC Comparator.
It contains 45V” with stand pressure” 200mΩ SW.
Because the Current Rating of this FET is 3.5A included ripple current, please use at within 3.5A.
The device has the circuit of over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 13 msec restart.
8.
UVLO
This is a Low Voltage Error Prevention Circuit.
This prevents internal circuit error during increase of Power supply Voltage and during decline of Power supply Voltage.
It monitors VCC Pin Voltage and internal REG Voltage, And when VCC Voltage becomes 6.4V and below, it turns OFF
all Output FET and turns OFF DC/DC Comparator Output, and Soft Start Circuit resets.
Now this Threshold has Hysteresis of 200mV.
9.
TSD
This is a Heat Protect (Temperature Protect) Circuit.
When it detects an abnormal temperature exceeding Maximum Junction Temperature (Tj=150℃), it turns OFF all
Output FET, and turns OFF DC/DC Comparator Output. When Temperature falls, it has/with Hysteresis and
automatically returns.
10. EN
With the Voltage applied to EN Pin(6pin), IC ON/OFF can be controlled.
When a Voltage of 2.0V or more is applied, it turns ON, at Open or 0V application, it turns OFF.
About 550kΩ Pull-down Resistance is contained within the Pin.
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4/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Detailed Description
◇Synchronizes to External Clock
The SYNC pin can be used to synchronize the regulator to an external system clock. To implement the synchronization
feature connect a square wave to SYNC pin. The square wave amplitude must transition lower than 0.8V and higher than
2.0V on the SYNC pin and have an on time greater than 100ns and an off time greater than 100ns. The synchronization
frequency range is 200 kHz to 500 kHz. The rising edge of the LX will be synchronized to the falling edge of SYNC pin
signal after SYNC input pulse 3 count. At the synchronization, the external clock is removed, the device transitions
self-running mode after 7 microseconds.
SYNC
Set the latch for
synchronization
SYNC_LATCH
400nsec
Lx
about
7µsec
Fig.3 Timing chart at Synchronization
◇SOFT START
The soft start time of BD9876EFJ is determined by the DCDC operating frequency (self-run mode 300 kHz ⇒10ms).
If synchronization is used at the time of EN=ON, The soft start time is restricted by SYNC pin input pulse frequency.
SYNC pin input pulse frequency is fosc_ex kHz, the soft start time is expressed by below equation.
Tss
=
300
fosc_ex
× 10 [ms]
◇OCP operation
The device has the circuit of over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 13 msec restart.
VC
OCP threshold
VC voltage discharged
by OCP latch
VC voltage rising by
output connect to GND
force the High side FET OFF
by detecting OCP current
(pulse by pulse protection)
Lx
output connect to GND
VOUT
OCP
set the OCP latch by detecting
the OCP current 2 times sequencially
OCP latch reset after 13 msec
(300ｋHz 4000 counts)
OCP_LATCH
Fig.4 Timing chart at OCP operation
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5/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Reference Data (Unless otherwise specified, Ta=25℃, VCC=24V, Vo=5V, EN=3V)
2
2
1.5
1.5
1
0.9
0.8
VCC=36V
0.5
VCC=24V
0.4
VCC=12V
0.3
ICC[mA]
VCC=42V
0.6
ICC[mA]
1
Temp=105℃
Temp=25℃
0.5
0.2
0.1
VCC=24V
VCC=36V
VCC=42V
0
-60 -40 -20
0
20
40
60
0
0
80 100 120
5
10
15
20
25
30
35
40
45
-60 -40 -20
Fig.5. Standby Current
Temperature Characteristics
90
330
80
4
reset voltage
3
2
1
0
MAXDUTY[%]
100
340
FREQUENCY[kHz]
350
detect voltage
320
310
300
290
0
20
40
60
80 100 120
20
10
0
1.008
40
60
1.002
1.000
0.998
VCC=24V
1.000
0.998
Temp=‐40℃
Temp=25℃
Temp=105℃
0.992
0.990
0.990
0
20
40
60
80 100 120
Temp[℃ ]
Fig.11. FB Threshold Voltage
Temperature Characteristics
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0
5
10
15
20
25
30
35
40
VCC[V]
Fig.12. FB Threshold
Power supply Characteristics
6/16
20
40
60
80 100 120
Fig.10. Max Duty
Temperature Characteristics
1.002
0.996
0
Temp[℃ ]
1.004
0.994
0.992
-60 -40 -20
-60 -40 -20
80 100 120
1.006
VCC=42V
VFB threshold[V]
VCC=36V
VCC=12V
20
Fig.9. Oscillation Frequency
Temperature Characteristics
1.010
0.994
0
Temp[℃ ]
1.008
0.996
40
260
1.010
1.004
50
30
Temp[℃ ]
1.006
80 100 120
60
270
-60 -40 -20
Fig.8. UVLO Threshold
Temperature Characteristics
60
70
280
250
-60 -40 -20
40
Fig.7. Circuit Current
Temperature Characteristics
Fig.6. Circuit Current
Power supply Voltage Characteristics
7
6
20
Temp[℃ ]
8
5
0
VCC[V]
Temp[℃ ]
UVLO threshold[V]
VCC=12V
Temp=‐40℃
0
VFB threshold[V]
1
0.5
VC terminal current[uA]
ICC[uA]
0.7
45
60
50
40
30
20
10
0
‐10
‐20
‐30
‐40
‐50
‐60
Temp=105℃
Temp=25℃
Temp=‐40℃
0
0.5
1
1.5
2
VFB[V]
Fig.13. FB Voltage - IVC
Current Characteristics
2011.07 - Rev.B
Technical Note
BD9876EFJ
16
12
10
8
VCC=12V
6
VCC=24V
4
VCC=36V
2
PRECHARGE FET RON [Ω]
HIGHSIDE FET RON [mΩ]
Soft Start Time[ms]
20
300
14
250
200
150
100
50
0
20
40
60
80 100 120
0
-60 -40 -20
Temp[℃ ]
7
6
5
VCC=12V
2
1
0
-60 -40 -20
0
20
40
60
40
60
-60 -40 -20
80 100 120
80 100 120
Temp[℃ ]
Fig.17 OCP Detect Current
Temperature Characteristics
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0
20
40
60
80 100 120
Temp[℃ ]
Fig.16. Pre-charge FET ON Resistance
Temperature Characteristics
2
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1.5
EN Threshold[V]
VC to SW Current
transconductance[A/V]
VCC=42V
VCC=36V
VCC=24V
8
20
Fig.15. Nch FET ON Resistance
Temperature Characteristics
10
9
0
Temp[℃ ]
Fig.14. Soft Start Time
Temperature Characteristics
OCP_detect_current[A]
5
0
-60 -40 -20
3
10
VCC=42V
0
4
15
1
0.5
0
-60 -40 -20
0
20
40
60
80 100 120
Temp[℃ ]
Fig.18. VC to SW current transconductance
Temperature characteristics
7/16
-60 -40 -20
0
20
40
60
80 100 120
Temp[℃ ]
Fig.19. EN Threshold
Temperature Characteristics
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Example of Reference Application Circuit (Input 24V, Output 5.0V/ 2.5A)
0.01µF
15µH CDRH105R
(SUMIDA)
Lx
5V/2.5A VOUT
VCC
VCC 24V
10µF/35V
GRM31EB3YA106KA12L
(murata)
RB056L-40 (ROHM)
47µF/15V
GRM32EB31C476KE15 (murata)
BST
GND
R1
120kΩ
R2
30kΩ
C1
6800pF
R3
10kΩ
VC
EN
FB
SYNC
EN
ON/OFF
control
SYNC
Fig.20 Reference Application Circuit
●Reference Application Data (Example of Reference Application Circuit)
Transformation Efficiency η[%]
100
90
80
70
Phase
Phase
Gain
Gain
60
VCC=12V
50
VCC=24V
VCC=36V
40
30
VCC=42V
20
10
0
0
500
1000
1500
2000
2500
3000
LOAD CURRENT[mA]
Fig.22 Frequency Response
Characteristics (Io=0.5A)
Fig.21 Electric Power
Conversion Rate
Fig.23 Frequency Response
Characteristics (Io=3.0A)
VOUT：200mV/div (AC)
VOUT：200mV/div (AC)
IL：1A/div (DC)
IL：1A/div (DC)
Fig.25 Load Response Characteristics
(Io=3.0A→0A)
Fig.24 Load Response Characteristics
(Io=0A→3.0A)
EN：5V/div (DC)
LX：10V/div (DC
EN：5V/div (DC)
LX：10V/div (DC
IL：0.5A/div (DC)
VOUT：2V./div (DC)
IL：0.5A/div (DC)
VOUT：2V./div (DC)
Fig.27 Stop Waveform
Fig.26 startup Waveform
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8/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Evaluation Board Pattern (Reference)
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents
or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies
performance. To help eliminate these problems, the VCC pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with B dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the
VCC pin, and the anode of the catch diode. See Fig.28 for a PCB layout example. The GND pin should be tied directly to
the thermal pad under the IC and the thermal pad.
The thermal pad should be connected to any internal PCB ground planes using multiple VIAs directly under the IC. The LX
pin should be routed to the cathode of the catch diode and to the output inductor. Since the LX connection is the switching
node, the catch diode and output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide
adequate heat dissipating area. The additional external components can be placed approximately as shown. It may be
possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce
good results and is meant as a guideline.
VOUT
Output
Inductor
Output
Capacitor
Topside
Ground
Area
Catch
Diode
Input Bypass
Capacitor
LX
VCC
VCC
BST
GND
CBST
Compensation
Network
VC
EN
FB
SYNC
Route BST Capacitor
Trace on another layer to
provide with wide path for
topside ground
Signal VIA
Thermal VIA
Resistor
Divider
Fig.28 Evaluation Board Pattern
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9/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Application Components Selection Method
(1) Inductor
Something of the shield Type that Fulfills the Current Rating (Current value Ipecac below), with low DCR (Direct
Current Resistance element) is recommended.
Value of Inductor influences Inductor Ripple Current and becomes the cause of Output Ripple.
In the same way as the formula below, this Ripple Current can be made small for as big as the L value of Coil or as
high as the Switching Frequency.
Ipeak =Iout + ⊿IL/2 [A]
⊿IL=
Vin-Vout
L
(1)
Vout
×
Vin
Δ IL
1
×
f
[A]
(2)
Fig.29 Inductor Current
(η: Efficiency, ⊿IL: Output Ripple Current, f: Switching Frequency )
For design value of Inductor Ripple Current, please carry out design tentatively with about 20%～50% of Maximum
Input Current.
※When current that exceeds Coil rating flows to the coil, the Coil causes a Magnetic Saturation, and there are cases
wherein a decline in efficiency, oscillation of output happens. Please have sufficient margin and select so that Peak
Current does not exceed Rating Current of Coil.
(2) Output Capacitor
In order for Capacitor to be used in Output to reduce Output Ripple, Low Ceramic Capacitor of ESR is recommended.
Also, for Capacitor Rating, on top of putting into consideration DC Bias Characteristics, please use something whose
Maximum Rating has sufficient margin with respect to the Output Voltage.
Output Ripple Voltage is looked for using the following formula.
Vpp=⊿IL×
1
2π×f×Co
＋
⊿IL×RESR
[V]
・・・ (3)
Please design in a way that it is held within Capacity Ripple Voltage.
(3) Output Voltage Setting
ERROR AMP internal Standard Voltage is 1.0V. Output Voltage is determined as seen in (4) formula.
VOUT
ERROR AMP
R1
FB
Vo=
(R1+R2)
R2
×1.0 [V] ・・・ (4)
R2
VREF
1.0V
Fig.30 Voltage Return Resistance Setting Method
(4) Boost Capacitor
Please connect CBST = 0.01µF (Laminate Ceramic Capacitor) between BST Pin-Lx Pins as Output capacitors of Gate
Drive Voltage Generator REG(5V).
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10/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
(5) About Adjustment of DC/DC Comparator Frequency Characteristics
Role of Phase compensation element CC1, CC2, RC (See P.7. Example of Reference Application Circuit)
Stability and Responsiveness of Loop are controlled through VC Pin which is the output of Error Amp.
The combination of zero and pole that determines Stability and Responsiveness is adjusted by the combination of
resistor and capacitor that are connected in series to the VC Pin.
DC Gain of Voltage Return Loop can be calculated for using the following formula.
Adc = Rl  GCS  A EA 
V FB
VOUT
Here, VFB is Feedback Voltage (1.0V).AEA is Voltage Gain of Error amplifier (typ: 77dB),
Gcs is the Trans-conductance of Current Detect (typ: 10A/V), and Rl is the Output Load Resistance value.
There are 2 important poles in the Control Loop of this DC/DC.
The first occurs with/ through the output resistance of Phase compensation Capacitor (C1) and Error amplifier.
The other one occurs with/through the Output Capacitor and Load Resistor.
These poles appear in the frequency written below.
G EA
2π  C1  A EA
fp 1 =
1
fp2 =
2π  COUT  Rl
Here, GEA is the trans-conductance of Error amplifier (typ: 220 µA/V).
Here, in this Control Loop, one zero becomes important. With the zero which occurs because of Phase compensation
Capacitor C1 and Phase compensation Resistor R3, the Frequency below appears.
fz 1 =
1
2π  C1  R3
Also, if Output Capacitor is big, and that ESR (RESR) is big, in this Control Loop, there are cases when it has an
important, separate zero (ESR zero).
This ESR zero occurs due to ESR of Output Capacitor and Capacitance, and exists in the Frequency below.
fz ESR =
1
2π COUT  RESR
(ESR zero)
rd
nd
In this case, the 3 pole determined with the 2 Phase compensation Capacitor (C2) and Phase Correction Resistor
(R3) is used in order to correct the ESR zero results in Loop Gain.
This pole exists in the frequency shown below.
fp 3 =
1
2π  C2  R3
(Pole that corrects ESR zero)
The target of Phase compensation design is to create a communication function in order to acquire necessary band
and Phase margin.
Cross-over Frequency (band) at which Loop gain of Return Loop becomes “0” is important.
When Cross-over Frequency becomes low, Power supply Fluctuation Response, Load Response, etc worsens.
On the other hand, when Cross-over Frequency is too high, instability of the Loop can occur.
Tentatively, Cross-over Frequency is targeted to be made 1/20 or below of Switching Frequency.
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11/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
Selection method of Phase Compensation constant is shown below.
1.
Phase Compensation Resistor (R3) is selected in order to set to the desired Cross-over Frequency.
Calculation of RC is done using the formula below.
R3 =
2π  COUT
GEA
 fc
 GCS

VOUT
VFB
Here, fc is the desired Cross-over Frequency. It is made about 1/20 and below of the Normal Switching Frequency (fs).
2.
Phase compensation Capacitor (C1) is selected in order to achieve the desired phase margin.
In an application that has a representative Inductance value (about several µH～20µH), by matching zero of
compensation to 1/4 and below of the Cross-over Frequency, sufficient Phase margin can be acquired. C1 can be
calculated using the following formula.
C1 ＞
4
2π  R3  fc
RC is Phase compensation Resistor.
3.
Examination whether the second Phase compensation Capacitor C2 is necessary or not is done.
If the ESR zero of Output Capacitor exists in a place that is smaller than half of the Switching Frequency, a second
Phase compensation Capacitor is necessary. In other words, it is the case wherein the formula below happens.
1
2π  COUT  RESR
＜
fs
2
In this case, add the second Phase compensation Capacitor C2, and match the frequency of the third pole to the
Frequency fp3 of ESR zero.
C2 is looked for using the following formula.
C2

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© 2011 ROHM Co., Ltd. All rights reserved.
COUT  RESR
R3
12/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●I/O Equivalent Schematic
Pin.
Pin.
No
Name
1
Lx
2
GND
7
BST
8
VCC
Pin.
No
Pin Equivalent Schematic
Pin.
Name
BST
Pin Equivalent Schematic
SYNC
VCC
5
Lx
SYNC
GND
GND
VCC
EN
3
VC
6
VC
EN
GND
GND
FB
4
FB
GND
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© 2011 ROHM Co., Ltd. All rights reserved.
13/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Notes for use
(1) About Absolute Maximum Rating
When the absolute maximum ratings of application voltage, operating temperature range, etc. was exceeded, there is
possibility of deterioration and destruction. Also, the short Mode or open mode, etc. destruction condition cannot be
assumed. When the special mode where absolute maximum rating is exceeded is assumed, please give consideration
to the physical safety countermeasure for the fuse, etc.
(2) About GND Electric Potential
In every state, please make the electric potential of GND Pin into the minimum electrical potential. Also, include the
actual excessive effect, and please do it such that the pins, excluding the GND Pin do not become the voltage below
GND.
(3) About Heat Design
Consider the Power Dissipation (Pd) in actual state of use, and please make Heat Design with sufficient margin.
(4) About short circuit between pins and erroneous mounting
When installing to set board, please be mindful of the direction of the IC, phase difference, etc. If it is not installed
correctly, there is a chance that the IC will be destroyed. Also, if a foreign object enters the middle of output, the middle
of output and power supply GND, etc., even for the case where it is shorted, there is a change of destruction.
(5) About the operation inside a strong electro-magnetic field
When using inside a strong electro-magnetic field, there is a possibility of error, so please be careful.
(6) Temperature Protect Circuit (TSD Circuit)
Temperature Protect Circuit (TSD Circuit) is built-in in this IC. As for the Temperature Protect Circuit (TSD Circuit),
because it a circuit that aims to block the IC from insistent careless runs, it is not aimed for protection and guarantee of
IC. Therefore, please do not assume the continuing use after operation of this circuit and the Temperature Protect
Circuit operation.
(7) About checking with Set boards
When doing examination with the set board, during connection of capacitor to the pin that has low impedance, there is
a possibility of stress in the IC, so for every 1 process, please make sure to do electric discharge. As a countermeasure
for static electricity, in the process of assembly, do grounding, and when transporting or storing please be careful. Also,
when doing connection to the jig in the examination process, please make sure to turn off the power supply, then
connect. After that, turn off the power supply then take it off.
(8) About common impedance
For the power supply and the wire of GND, lower the common impedance, then, as much as possible, make the ripple
smaller (as much as possible make the wire thick and short, and lower the ripple from L・C), etc., then and please
consider it sufficiently.
(9) In the application, when the mode where the VCC and each pin electrical potential becomes reversed exists, there is a
possibility that the internal circuit will become damaged. For example, during cases wherein the condition when charge
was given in the external capacitor, and the VCC was shorted to GND, it is recommended to insert the bypass diode
to the diode of the back current prevention in the VCC series or the middle of each Pin-VCC.
(10) About High-side Nch FET
Please use within 3.5A contained ripple current, because the absolute maximum rating of high-side Nch FET is 3.5A.
(11) About over current detection
The detecting current is the current flowing through high-side Nch FET. Output current containing ripple current,
therefore the detecting current is the current of the output current containing ripple current.
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© 2011 ROHM Co., Ltd. All rights reserved.
14/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
(12) About IC Pin Input
+
This IC is a Monolithic IC, and between each element, it has P isolation for element separation and P board. With the
N layer of each element and this, the P-N junction is formed, and the parasitic element of each type is composed.
For example, like the diagram below, when resistor and transistor is connected to Pin,
○When GND＞(PinA) in Resistor, when GND＞(PinA), when GND＞(PinB) in Transistor (NPN),
the P-N junction will operate as a parasitic diode.
○Also, during GND＞(Pin B) in the Transistor (NPN), through the N layer of the other elements connected
to the above-mentioned parasitic diode , the parasitic NPN Transistor will operation.
On the composition of IC, depending on the electrical potential, the parasitic element will become necessary. Through
the operation of the parasitic element interference of circuit operation will arouse, and error, therefore destruction can
be caused. Therefore please be careful about the applying of voltage lower than the GND (P board) in I/O Pin, and the
way of using when parasitic element operating.
Transistor (NPN)
(Pin B)
(Pin A)
C
B
E
～
～
Resistor
GND
N
N
N
N
GND
(Pin A)
P+
N
N
N
Parasitic
Element
P Substrate
P Substrate
Parasitic Element
P
P+
P+
～
～
P
P+
Parasitic Element
GND
GND
Fig.31 Example of simple structure of Bipolar IC
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© 2011 ROHM Co., Ltd. All rights reserved.
15/16
2011.07 - Rev.B
Technical Note
BD9876EFJ
●Ordering part number
B
D
9
Part No.
8
7
6
E
Part No.
F
J
Package
EFJ : HTSOP-J8
-
E
2
Packaging and forming specification
E2: Embossed tape and reel
HTSOP-J8
<Tape and Reel information>
4°
(2.4)
3.9±0.1
6.0±0.2
8 7 6 5
+6°
−4°
1
1.05±0.2
(3.2)
0.65±0.15
4.9±0.1
(MAX 5.25 include BURR)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
2 3 4
1PIN MARK
+0.05
0.17 -0.03
1.0MAX
0.545
S
0.08±0.08
0.85±0.05
1.27
+0.05
0.42 -0.04
0.08
M
0.08 S
1pin
Reel
(Unit : mm)
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© 2011 ROHM Co., Ltd. All rights reserved.
16/16
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2011.07 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
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© 2011 ROHM Co., Ltd. All rights reserved.
R1120A