L4923 5V–1A VERY LOW DROP REGULATOR WITH RESET AND INHIBIT . . . . . .. .. VERY LOW DROP (max. 0.9V at 1A) OVER FULL OPERATING TEMPERATURE RANGE (– 40 / + 125 °C) LOW QUIESCENT CURRENT (max 70 mA at 1 A) OVER FULL T RANGE PRECISEOUTPUT VOLTAGE(5V ± 4%) OVER FULL T RANGE POWER ON-OFF INFORMATION WITH SETTABLE DELAY INHIBIT FOR REMOTE ON-OFF COMMAND (active high) LOAD STANDBY CURRENT LOAD DUMP AND REVERSE BATTERY PROTECTION SHORT CIRCUIT PROTECTION THERMAL SHUTDOWN Heptawatt ORDERING NUMBER : L4923 The device is internally protected against load dumps transient of + 60 V, input overvoltage, reverse polarity, overheating and output short circuit : thanks to these featuresthe L4923is very suited for the automotive and industrial applications. DESCRIPTION The reset function is very useful for power off and power on information when supplying a microprocessor. The L4923is a high currentmonolithic voltage regulator with very low voltage drop (0.70 V max at 1 A, TJ = 25 °C). The inhibit function reduces drastically the consumptionwhen no load current is required: typically the standby current value is 300 µA. BLOCK DIAGRAM June 2000 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/6 L4923 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vi DC Input Voltage Vr DC Reverse Voltage VD Positive Load Dump Protection (t = 300ms) Value Unit 35 V – 18 V 60 V TJ Junction Temperature range – 40 to 150 °C Top Operating Temperature Range – 40 to 125 °C Tstg Storage Temperature Range – 55 to 150 °C Value Unit 4 °C/W Note: The circuit is ESD protected according to MIL-STD-883C THERMAL DATA Symbol R th j-case Parameter Thermal Resistance Junction Case PIN CONNECTION Figure 1 : Application Circuit. (*) RECOMMENDED VALUE : C0 = 47 µF, ESR < 10 Ω, (Iout > 10 mA) OVER FULL Trange. 2/6 L4923 ELECTRICAL CHARACTERISTICS (Vi = 14. 4V, – 40°C ≤ TJ ≤ + 125°C unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Vi Operating Input Voltage (*) Note 1 Vo Output Voltage Io = 0mA to 1A TJ = 25°C ∆VLine SVR Line Regulation Vi = 6 to 26V; IO = 10mA 5 Supply Voltage Rejection Io = 700mA f = 120Hz; Co = 47µF Vi = 12Vdc + 5Vpp 55 Load Regulation Io = 10mA to 1A 15 ∆V LOAD Vi – Vo Dropout Voltage ISC Quiescent Current V 4.8 4.9 5.2 5.1 V V 25 mV 0.45 TJ = 25°C, IO = 1A Short Circuit Current Io = 350mA ; f = 120Hz Co = 100µF ; Vi = 12V ± 5Vpp VR Rset Output Saturation Voltage 1.5V < V O < VRT (off), IR = 1.6mA 3V < VO < VRT (off), IR = 8mA VRT peak Power On-Off Reset out Peak Voltage 1KΩ Reset Pull-up to VO IR Reset Output Leakage Current (high level) Vo in Regul. VR = 5V tD Reset Pulse Delay Time CD = 100nF VRthOFF Power OFF Vo Threshold Vo @ Reset out H to L Transition; TJ = 25°C – 40°C ≤ TJ ≤ + 125°C IC6 VRthON V6 7 25 0.30 Io = 10mA Io = 1A Active High Inhibit Supply Volt. Rej. SVR Delay Capacitor Charging Current (current generator) V6 = 3V Power ON Vo Threshold Vo @ Reset out L to H Transition Delay Comparator Threshold V6H Delay Comparator Hysteresis VInhL Low Inhibit Voltage V InhH High Inhibit Voltage IInhL Low Level Inhibit Current 50 4.75 4.7 Reset out = ”1” H to L Transition 3.2 3.7 dB 50 0.70 V 0.90 V 12 70 0.65 mA mA mA A 60 dB 0.40 0.40 V V 1.0 V 50 µA 20 ms Vo – 0.15 V V 20 µA VrthOFF + 0.03V Vo – 0.04V 3.8 V 4 4.4 V 500 2.0 V mV 0.5 – 40 mV 1.8 0.65 Reset out = ”0” L to H Transition VInh L = 0.4V Unit 26 Over Full T, Io = 1A Iq Max. 6 V V – 10 µA (*) Note 1 : The device is not operating within the range : 26 V < Vi < 37 V. EXTERNAL COMPENSATION Since the purpose of a voltageregulatoris tosupply a fixed output voltage in spite of supply and load variations, the open loop gain of the regulator must be very high at low frequencies.This may cause instability as a result of the various poles present in the loop. To avoid this instability dominant pole compensationis used to reduce phase shifts due to other poles at the unity gain frequency. The lower the frequencyof theseother poles, the greatermust be the capacitor used to create the dominant pole for the same DC gain. Where the output transistor is a lateral PNP type there is a pole in the regulation loop at a frequency too low to be compensatedby a capacitor wich can be integrated. An external compensation is therefore necessary so a very high value capacitor must be connectedfrom the output to ground. The parassiticequivalentseries resistance of thecapacitorused adds a zero to the regulationloop. This zero may compromise the stability of the system since its effect tends to cancel the effect of the pole added. In regulators this ESR must be less than 3Ω and the minimum capacitor value is 47µF. 3/6 L4923 FUNCTIONAL DESCRIPTION The operating principle of the voltage regulator is basedon thereference,the error amplifier,the driver and the power PNP. This stage uses an Isolated CollectorVertical PNP transistor which allowsto obtain very low dropout voltage (typ. 450 mV) and low quiescent current (IQ = 20 mA typically at IO = 1 A). Thanks to these features the device is particularly suited when the power dissipation must be limited as, for example, in automotive or industrial applications supplied by battery. The three gain stages (operational amplifier, driver and power PNP) require the external capacitor (COmin = 22 µF) to guarantee the global stability of the system. The antisaturationcircuit allows to reducedrastically the current peak which takes place during the start up. Figure 2 : Typical Reset Output Waveform. 4/6 The reset function is LOW active when the output voltage level is lower than the reset threshold voltage VRth (typ.value : VO - 150 mV). When the output voltageis higher than VRth the reset becomes HIGH aftera delay time settablewith theexternalcapacitor Cd. Typically td = 20 ms, Cd = 0.1 µF. The reset threshold hysteresis improves the noise immunity allowing to avoid false switchings. The typical reset output waveform is shown in fig. 2. The inhibit circuit acceptsstandardTTL inputlevels : thisblockswitchesoffthe voltageregulatorwhen the input signal is HIGH and switches on it when the input signal is LOW. Thanksto inhibit functionthe consumption is drastically reduced (650 µA max) when no load current is required. L4923 DIM. A C D D1 E E1 F F1 G G1 G2 H2 H3 L L1 L2 L3 L4 L5 L6 L7 L9 M M1 V4 Dia MIN. mm TYP. 2.4 1.2 0.35 0.7 0.6 2.34 4.88 7.42 10.05 16.7 21.24 22.27 2.6 15.1 6 2.55 4.83 2.54 5.08 7.62 16.9 14.92 21.54 22.52 2.8 15.5 6.35 0.2 2.8 5.08 3.65 MAX. 4.8 1.37 2.8 1.35 0.55 0.97 0.8 0.9 2.74 5.28 7.82 10.4 10.4 17.1 21.84 22.77 1.29 3 15.8 6.6 inch TYP. MIN. 0.094 0.047 0.014 0.028 0.024 0.095 0.193 0.295 0.396 0.657 0.386 0.877 0.102 0.594 0.236 3.05 0.100 5.33 0.190 40° (typ.) 3.85 0.144 0.100 0.200 0.300 0.668 0.587 0.848 0.891 0.110 0.610 0.250 0.008 0.110 0.200 OUTLINE AND MECHANICAL DATA MAX. 0.189 0.054 0.110 0.053 0.022 0.038 0.031 0.035 0.105 0.205 0.307 0.409 0.409 0.673 0.860 0.896 0.051 0.118 0.622 0.260 0.120 0.210 Heptawatt V 0.152 V L V E L1 M1 A M D C D1 L5 H2 L2 L3 F E E1 V4 L9 H3 H1 G G1 G2 Dia. F L7 L4 L6 H2 F1 HEPTAMEC 5/6 L4923 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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