PD-94593C iP1202 Dual Output Full Function 2 Phase Synchronous Buck Power Block Integrated Power Semiconductors, PWM Control & Passives Features • • • • • • • • • • • • • • • • 5.5V to 13.2V input voltage 0.8V to 5V output voltage 2 Phase Synchronous Buck Power Block 180° out of phase operation Single or Dual output capability Dual 15A maximum load capability Single 2 phase 30A maximum load capability 200-400kHz per channel nominal switching frequency Over Current Hiccup or Over Current Latch External Synchronization Capable Overvoltage protection Individual soft start per outputs Over Temperature protection Internal features minimize layout sensitivity * Ease of layout Very small outline 15.5mm x 9.25mm x 2.6mm iP1202 Power Block Description The iP1202 is a fully optimized solution for medium current synchronous buck applications requiring up to 15A or 30A. The iP1202 is optimized for 2 phase single output applications up to 30A or dual output, each up to 15A with interleaved input. It includes full function PWM control, with optimized power semiconductor chip-sets and associated passives, achieving high power density. Very few external components are required to create a complete synchronous buck power supply. iPOWIR technology offers designers an innovative space-saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. iP1202 Configurations Channel 1 V IN V OUT V OUT V IN Channel 2 V OUT Single Output Dual Output * Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be applied for the design of the power supply board. The iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long term operation. See layout guidelines in datasheet for more detailed information. www.irf.com 10/28/04 1 iP1202 All specifications @ 25°C (unless otherwise specified) Absolute Maximum Ratings Parameter VIN Feedback Output Overvoltage Sense PGOOD ENABLE Soft Start Vp-ref HICCUP SYNC Output RMS Current Per Channel Block Temperature Symbol VIN VFB1/VFB2 VFB1S/VFB2S Conditions Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Typ - Max 15 6 6 15 15 6 6 15 6 Units IoutVSW - - 15 A 2 Independent outputs. See Fig. 3 TBLK -40 - 125 °C Capable of start up over full temperature range. See Note 1. Min 5.5 Typ - Max 13.2 Units - - 15 A - - 11 A 0.8 0.8 - 5.0 3.3 V Min Typ Max Units SS1/SS2 HICCUP V Recommended Operating Conditions Parameter Input Voltage Range Output RMS Current Per Channel Output Voltage Range Symbol VIN IoutVSW VOUT Conditions 2 Independent outputs TPCB = TCASE = 90°C. See Fig. 3 2 Independent outputs TPCB = 90°C, TCASE = no airflow, no heatsink. See Fig. 3 For VIN = 12V For VIN = 5.5V Electrical Specifications @ VIN = 12V Parameter Power Loss Over Current Shutdown HICCUP duty cycle Soft Start Time Reference Voltage VOUT Accuracy Error Amplifier 2 input offset voltage FB1/FB2 Input bias current Error Amplifier source/sink Current Error Amplifier Transconductance Output Overvoltage Shutdown Threshold OVP Fault Propagation Delay PGOOD Trip Threshold PGOOD Output Low Voltage 2 Symbol PLOSS - 7.0 8.75 W IOC - 25 - A DHICCUP - 5 - % tSS 5 ms VREF - 0.8 - VOUT_ACC1 -3 - 3 VOUT_ACC2 -2.5 - 2.5 VOS2 -4 - 4 mV IBFB - -0.1 - µA IERR - 60 - µA gm1, gm2 - 2000 - µmho OVP - 1.15 x VOUT - V tOVP VTh_PGOOD VLO_PGOOD - 25 0.85 x VOUT - 0.25 - µs V V Conditions fSW = 300kHz, VIN = 12V, TBLK= 25°C VOUT1 = VOUT2 = 1.5V, IOUT1 = IOUT2= 15A VIN = 12V, VOUT = 1.5V fSW = 300KHz, ROCSET = 51.1kΩ HICCUP pin pulled Low HICCUP pin pulled high, output short circuited. VIN = 12V, VOUT = 1.5V, CSS1= CSS2=0.1µF V % TBLK = -40°C to 125°C, See Note 1. VIN= 12V, VOUT = 1.5V TBLK = 0°C to 125°C, See Note 1. VIN= 12V, VOUT = 1.5V VIN = 12V, VOUT = 1.5V, specified for current share accuracy in parallel configuration. Rshunt1 = Rshunt2 =5mΩ , Iout= 30A. See Fig. 15 See OVP note in Design Guidelines Output forced to 1.125Vref FB1 or FB2 ramping down ISINK=2mA www.irf.com iP1202 Electrical Specifications (continued) Parameter Oscillator Ramp Voltage Vramp Min 170 255 340 - SYNC Frequency Range fSYNC 480 - 800 kHz SYNC Pulse Duration tSYNC - 200 - ns 2 - - V - - 0.8 V - 15 - mA Frequency Symbol fSW SYNC, HICCUP High Level Threshold Voltage SYNC, HICCUP Low Level Threshold Voltage VIN Quiescent Current IIN-LEAKAGE Thermal Shutdown Typ 1.25 Max 230 345 460 - Units kHz kHz kHz V Conditions RT = 48.7kΩ ( See Fig.9 for RT = 30.9kΩ RT selection ) RT = 21.5kΩ Free running frequency set 20% below sync frequency VIN = 12V, ENABLE high Tempshdn - 140 - °C Max Duty Cycle DMAX 85 - - % fSW= 200kHz, TBLK = 25°C ENABLE Threshold Voltage VEN-LO 5 - - V Measured between VIN and ENABLE VIN Turn On Threshold Voltage VON_th - 4.8 - V Measured at start of soft start, ENABLE pulled low, VIN ramping up VIN Turn Off Threshold Voltage VOFF_th - 4.3 - V Measured at fall of soft start, ENABLE pulled low, VIN ramping down Output Disable Voltage Soft Start Low Threshold Voltage VSS-DIS - - 0.25 V SS1 / SS2 Pins Pulled Low Note 1: Guaranteed to meet specifications from TBLK = 0°C to 90°C. Specifications outside of this temperature range are guaranteed by design, and not production tested. www.irf.com 3 4 Oscillator Two phase PWM Comp2 SW1 / SW3 OFF SW2 / SW4 ON Ramp2 Ramp1 R S S R Q Q PWM2 PWM1 Driver 2 Driver 1 SW4 SW3 SW2 20k 20k VSW2 PGND OCSET1 VSW1 FB2S OVP (+15%) PGOOD PGood (-10%) Error Amp2 Error Amp1 PWM Comp1 OC Latch / Hiccup Control SW1 FB1S 64uA 3uA 25uA UVLO OCSET2 25k 25k 0.8V 25k 25k 64uA 3uA Bias Generator HICCUP ENABLE VIN CC2 FB2 VP-REF VREF RT SYNC CC1 FB1 0.8V SS2 SS1 25uA VCC iP1202 Fig. 1: iP1202 Internal Block Diagram www.irf.com iP1202 12 V IN = 12V V OUT 1 = V OUT 2 = 1.5V f SW = 300kHz L = 1.0µH TBLK = 125°C Total Power Loss, Both Outputs (W) 11 10 9 8 M aximum 7 6 T ypical 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output Current per Channel (A) Fig. 2: Power Loss vs. Current Case Temperature (& 16 0 10 20 30 40 50 60 70 80 90 100 110 120 15 14 Output Current Per Channel (A) 13 Safe Operating Area 12 11 10 9 8 7 TX 6 5 V IN = 12V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f SW = 300kHz L = 1.0 µH 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (ºC) www.irf.com Fig. 3: Safe Operating Area (SOA) vs. TPCB & TCASE 5 iP1202 2.0 Norm alized Power Loss 1.030 1.0 f S W =300kHz L =1.0µ H 1.015 0.5 T B L K =125°C 1.000 0.0 0.985 - 0.5 0.970 - 1.0 0.955 - 1.5 0.940 - 2.0 0.925 6 7 8 9 10 11 12 13 1.105 I OU T 1 =I OU T 2 =15A 3.5 1.090 f S W =300k Hz 3.0 L =1.0µ H 1.075 2.0 1.045 1.5 1.030 1.0 1.015 0.5 1.000 0.0 0.985 - 0.5 0.970 - 1.0 - 1.5 0.5 14 1 1.5 Fig. 4: Normalized Power Loss vs. VIN Normalized Power Loss L =1.0µ H 0.5 1.000 0.0 0.985 - 0.5 0.970 - 1.0 0.955 - 1.5 0.940 - 2.0 0.925 - 2.5 0.910 250 300 350 I OU T 1 =I OU T 2 =15A 1.18 1.15 1.12 4.0 1.09 3.0 1.06 2.0 1.03 1.0 1.00 0.0 - 1.0 = 300kHz sw L = 1.0µH T BLK = 125°C 165 145 125 25 in 105 = 12V 85 20 V 15 in 65 = 5.5V 45 10 25 5 5 6 8 10 12 14 16 18 20 22 24 Overload Current (A) 6 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 Fig. 8: Nominal Overcurrent Threshold Setting External Resistor Selection 400 Switching Frequency in kHz ROC-SET (kOhms) for 12Vin f V 5.0 T B L K =125°C Fig. 7: Normalized Power Loss vs. Inductance ROC-SET (kOhms) for 5.5Vin 185 30 6.0 f S W =300kHz 0.2 205 V OUT = 1.5V 35 7.0 VOU T 1 =VOU T 2 =1.5V Output Inductance ( P H) 55 40 5 0.97 400 Fig. 6: Normalized Power Loss vs. Frequency 45 4.5 8.0 Sw itching Fre que ncy (k Hz) 50 4 VI N =12V 1.21 - 3.0 200 3.5 SOA Temp Adjustment ( °C) T B L K =125°C 1.0 SOA Temp Adjustment (°C) 1.5 VOU T 1 =VOU T 2 =1.5V 1.015 3 1.24 2.0 VI N =12V I OU T 1 =I OU T 2 =15A 2.5 Fig. 5: Normalized Power Loss vs. VOUT Normalized Power Loss 1.060 1.030 2 Output V oltage (V ) Input Voltage (V) 1.045 2.5 T B L K =125°C 1.060 0.955 - 2.5 5 4.0 VI N =12V SOA Temp Adjustment (°C) 1.5 I OU T 1 =I OU T 2 =15A SO A Temp Adjustment ( 0 C) VOU T 1 =VOU T 2 =1.5V 1.045 1.120 Normalized Power Loss 1.060 380 360 340 320 300 280 260 240 220 200 20 25 30 35 40 45 R T in kOhms Fig. 9: Per Channel Switching Frequency vs RT www.irf.com 50 iP1202 Applying the Safe Operating Area (SOA) Curve The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn Cas e Te m pe ratur e ( & out through the printed circuit board and the top of the case. 16 Procedure 0 10 20 30 40 50 60 70 80 90 100 110 120 15 14 3 13 12 Output Current (A) 1) Draw a line from Case Temp axis at TCASE to the PCB Temp axis at TPCB. 2) Draw a vertical line from the TX axis intercept to the SOA curve. (see AN-1047 for further explanation of TX ) 3) Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y axis. The point at which the horizontal line meets the y-axis is the SOA current. 4) If no top sided heatsinking is available, assume TCASE temperature of 125°C for worst case performance. 1 11 Safe Operating Area 10 9 8 2 7 TX 6 5 V IN = 12V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f S W = 300kHz L = 1.8uH 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (ºC) Adjusting the Power Loss and SOA curves for different operating conditions To make adjustments to the power loss curves in Fig. 2, multiply the normalized value obtained from the curves in Figs. 4, 5, 6 or 7 by the value indicated on the power loss curve in Fig. 2. Remember that the power loss in Fig 2. is the power loss for 2 outputs operating with the same output voltage. If differing output voltages are used the initial power loss for each channel needs to be divided by 2. Then if multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 2. The resulting product is the final power loss based on all factors. See example no. 1. To make adjustments to the SOA curve in Fig. 3, determine your maximum PCB Temp & Case Temp at the maximum operating current of each iP1202. Then, add the correction temperature from the normalized curves in Figs. 4, 5, 6 or 7 to the TX axis intercept (see procedure no. 2 above) in Fig. 3. When multiple adjustments are required, add all of the temperatures together, then add the sum to the TX axis intercept in Fig. 3. See example no. 2. Operating Conditions for the following examples: Output1 Output2 Output Current = 12A Output Voltage = 1.2V Input Voltage = 8V Sw Freq= 300kHz Inductor = 1.75µH Output Current = 10A Output Voltage = 3.3V Input Voltage =8V Sw Freq= 300kHz Inductor = 1.75µH Example 1) Adjusting for Maximum Power Loss: Output1 (Fig. 2) Maximum power loss = W 8.25/2 = 4.125W (Fig. 4) Normalized power loss for input voltage ≈ 0.93 (Fig. 5) Normalized power loss for output voltage ≈ 0.98 (Fig. 6) Normalized power loss for frequency ≈ 1.0 (Fig. 7) Normalized power loss for inductor value ≈ 0.98 Adjusted Power Loss = 4.125 x 0.93 x 0.98 x 1.0 x 0.98 ≈ 3.7W www.irf.com 7 iP1202 Output2 (Fig. (Fig. (Fig. (Fig. (Fig. 2) 4) 5) 6) 7) Maximum power loss =6.4W /2 = 3.2W Normalized power loss for input voltage ≈ 0.93 Normalized power loss for output voltage ≈ 1.075 Normalized power loss for frequency ≈ 1.0 Normalized power loss for inductor value ≈ 0.98 Adjusted Power Loss = 3.2W x 0.93 x 1.075 x 1.0 x 0.98 ≈ 3.13W Total device power loss = 3.7W + 3.13W ≈ 6.8W Example 2) Adjusting for SOA Temperature: Assuming TCASE = 110°C & TPCB = 90°C for both outputs Output1 (Fig. 4) Normalized SOA Temperature for input voltage ≈ -2.3°C (Fig. 5) Normalized SOA Temperature for output voltage ≈ -0.6°C (Fig. 6) Normalized SOA Temperature for frequency ≈ 0°C (Fig. 7) Normalized SOA Temperature for inductor value ≈−0.7°C TX axis intercept temp adjustment = -2.3°C - 0.6°C + 1.9°C - 0.7°C ≈ -3.6°C The following example shows how the SOA current is adjusted for a TX change of -3.6°C and output 1 is in SOA Cas e Te m pe rature ( & 16 0 10 20 30 40 50 60 70 80 90 100 110 120 15 A djusted SOA Current 14 13 Unadjusted SOA Current Output Current (A) 12 11 Safe Operating Area 10 9 8 7 TX 6 5 V IN = 12V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f SW = 300kHz L = 1.8uH 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (ºC) Output2 (Fig. 4) (Fig. 5) (Fig. 6) (Fig. 7) Normalized SOA Temperature for input voltage ≈ -2.3°C Normalized SOA Temperature for output voltage ≈ 3.9°C Normalized SOA Temperature for frequency ≈ 0°C Normalized SOA Temperature for inductor value ≈ −0.7°C TX axis intercept temp adjustment = -2.3°C + 3.9°C - 0°C - 0.7°C ≈ 0.9°C The following example shows how the SOA current is adjusted for a TX change of 0.9°C and output 2 is in SOA. Cas e Te m pe ratur e ( & 16 0 10 20 30 40 50 60 70 80 90 100 110 120 15 14 13 Unadjusted SOA Current Output Current (A) 12 A djusted SOA Current 11 Safe Operating Area 10 9 8 7 TX 6 5 V IN = 12V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f SW = 300kHz L = 1.8uH 4 3 2 1 0 0 8 10 20 30 40 50 60 70 80 PCB Temperature (ºC) 90 100 110 120 www.irf.com iP1202 Pin Name CC1 CC2 Ball Designator A1 A2 A3 A4 A15 A16 A17 A18 B1 B2 B3 B4 B15 B16 B17 B18 C1 C2 C3 C4 C15 C16 C17 C18 H6 H13 ENABLE A8 B8 SS1 H8 SS2 H11 FB1 FB1s FB2 FB2s J6 J8 J13 J11 Output of the first error amplifier Output of the second error amplifier Single pin for both outputs. Commands ouputs ON or OFF. Normally Pulled High. Pulled low, turns both outputs ON. Soft start pin for output 1. External capacitor provides soft start. Pulling soft start pin low will disable this output. Soft start pin for output 2. External capacitor provides soft start. Pulling soft start pin low will disable this output. Inverting input of error amplifier 1 Output 1 overvoltage sense pin. Inverting input of error amplifier 2 Output 2 overvoltage sense pin. VSW1 D1 D2 D3 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 K2 L1 L2 Output 1 inductor connection pins VSW2 D16 D17 D18 E17 E18 F17 F18 G17 G18 H17 H18 J17 J18 K17 K18 L17 L18 Output 2 inductor connection pins PGND A5 A6 A7 A9 A10 A12 A13 A14 B5 B6 B7 B10 B11 B12 B13 B14 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E3 E4 E5 E6 E13 E14 E15 E16 F3 F4 F5 F6 F8 F9 F10 F11 F13 F14 F15 F16 G3 G4 G6 G9 G10 G13 G15 G16 H4 H9 H10 H15 J4 J5 J9 J10 J14 J15 K4 K5 K14 K15 L3 L4 L5 L13 L14 L15 L16 Power Ground pins Vref L9 Amplifier 1 reference Voltage. Connect a 100pF cap from this pin to PGND. VP-ref L8 Amplifier 2 reference voltage. Connect to Vref for independent output configuration. Refer to application notes on how to connect to parallel configuration or output voltage tracking configurations. SYNC K6 External Clock synchronization pin. Set free running frequency to 80% of the SYNC frequency. When not in use, leave pin floating RT L11 PGOOD L10 HICCUP L6 OCSET1 OCSET2 G8 G11 VIN Pin Description Input voltage connection pins Switching frequency setting pin. For RT selection, refer to Fig.9 of the datasheet. Power Good pin. Open collector, requires external pulll-up. If function not needed, pin can be left floating Logic level pin. Pulled high enables hiccup mode of operation. Pulled low enables latched overcurrent shutdown mode. Overcurrent trip threshold pin for output 1 Overcurrent trip threshold pin for output 2 Table 1: Pin Description www.irf.com 9 iP1202 Iin Average A V Vin Average Cin PIN = VIN Average x IIN Average POUT = (VOUT1 Average x IOUT1 Average) + + (VOUT2 Average x IOUT2 Average) PLOSS = PIN - POUT Vin DC VIN Iout1 Average VSW1 Lo1 Vout1 A Co1 Iout1 FB1 Averaging Circuit 1 iP1202 V Vout1 Average FB2 Iout2 Average PGND Lo2 VSW2 A Co2 Averaging Circuit 2 Vout2 Iout2 V Vout2 Average Fig. 10: Power Loss Test Circuit 10 www.irf.com iP1202 ENABLE VIN VIN PGND PGND OCSET1 VSW1 OCSET2 CC1 SS1 FB1 CC2 SS2 FB2 FB1s SYNC FB2s VSW2 Vref HICCUP VP-ref PGOOD RT All Dimensions in inches (millimeters) Fig. 11: Recommended PCB Footprint (Top View) www.irf.com 11 iP1202 iP1202 Users Design Guidelines The iP1202 can be configured as a dual channel 15A or parallel single 30A power block consisting of optimized power semiconductors, PWM control and its associated passive components. It is based on a synchronous buck topology and offers an optimized solution where space, efficiency and noise caused by parasitics are of concern. The phase shifted, two output power block operates with fixed frequency voltage mode control and can be configured to operate as a dual output or paralleled single output with current sharing. The iP1202 components are integrated in a ball grid array (BGA) package. This threshold voltage should be taken into consideration when designing sequencing profiles using the iP1202 as it will effect start-up delays and ramptimes. For proper implementation of sequencing of outputs using the iP1202, refer to IR Application Note AN1053 - Power sequencing techniques using iP1201 and iP1202. Iss VIN SS1/SS2 The input operating voltage range of the iP1202 is 5.5V to 13.2V. Both channels of the power block have a common input. iP1202 Css Enabling the Outputs The ENABLE pin turns on and turns off both outputs of the iP1202 simultaneously. The iP1202 outputs will be turned off by floating the ENABLE pin. ENABLE low will start the outputs. The converter can also be shutdown by pulling the soft-start pins to PGND through a logic level MOSFET the drain of which connects to the soft start pin (see Fig.12). This feature can be useful if sequencing or different start-up timing of the outputs are required. In situations where the output has undergone a latched shutdown due to overvoltage or overcurrent, cycling ENABLE will reset the outputs. Cycling soft start pins will not unlatch the outputs. Fig. 12: Soft Start/Enable Circuit 3V 0.8Vtyp VCss VOUT Fig. 13: Power Up Threshold Dual Soft Start Mode of Operation The Soft Start function provides a controlled rise of the output voltage, thus limiting the inrush current during start-up. The iP1202 provides two independent soft start functions. The soft start pins can be connected to the soft start capacitors to provide different start-up and sequencing profiles. Each soft start function has an internal 25uA +/-20% current source that charges the external soft start capacitor Css up to 3V. During power-up, the output voltage starts ramping up only after the charging voltage across the C ss capacitor has reached a 0.8Vtyp threshold, as shown in Fig. 13. The iP1202 can be configured to provide either two independent dual outputs or single paralleled output with current share. In dual output mode, the two error amplifiers of the PWM controller operate independently. Each output voltage of the iP1202 block is controlled by its own error amplifier. The output of the error amplifier and the internally generated ramp signal are compared to produce PWM pulses of fixed frequency that drive the internal power switches. In this mode, the VP-ref pin must be connected to Vref pin. Vref pin is the internally generated 0.8V reference input of first error amplifier . Refer to the internal block diagram of the iP1202 in Fig.1. 12 www.irf.com iP1202 In single output mode, one error amplifier controls the output voltage and the other amplifier monitors the inductor current information for current sharing. In this mode, VP-ref pin must be disconnected from Vref pin and connected to the output of channel1 inductor, see Fig. 15. The inductor current information is provided through external shunts placed in series with the output inductors. A lossless inductor current sensing scheme can also be implemented as shown in Fig.16, where the current is sensed through the DC resistance of the inductor. In this case RL and CL are selected such that RLx CL = L / Rdc. Set RL = 1K and solve for CL. Rdc is the internal DC resistance of inductor L. In single output two phase mode, leave SS2 pin open. The iP1202 can also be configured in dual output tracking mode where the second output tracks the first output. For a specific output configuration, follow the connection diagram shown in Fig.14, Fig.15, Fig.16 at the end of this section. Out of Phase Operation The dual output PWM controller inside the iP1202 provides a 180° out of phase operation of the PWM outputs. This method of control offers the advantage of reducing the amount of input bypass capacitors due to increase in input ripple frequency and hence reduction of ripple amplitude. Moreover, for paralleled output configurations 180° phase shifting contributes to smaller output capacitors due to output inductor ripple current cancellation and ripple reduction. Frequency and Synchronization The operating switching frequency (fSW) range of iP1202 is 200 kHz to 400 kHz. The desired frequency is set by placing an external resistor to the RT pin of the iP1202. See Fig. 9 for the proper resistor value. The iP1202 is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge clock. The free running oscillator frequency is twice the per-channel frequency. During synchronization, RT is selected such that the free running frequency is 20% below the synchronization frequency. The maximum synchronization frequency that iP1202 can accept is 800kHz. Note that the actual free running frequency of individual output is half the synchronization frequency. www.irf.com Synchronization capability is provided both in independent and parallel configurations. When unused, the SYNC pin must be left floating. Overcurrent Protection/Autorestart The Overcurrent Protection function of the iP1202 offers two distinct modes: HICCUP of the output and Overcurrent Shutdown. If the Hiccup pin is pulled high (Hiccup enabled), hiccup mode will be selected. If Hiccup pin is pulled low (Hiccup dis- abled), overcurrent shutdown will be selected. During overloads, in HICCUP disabled mode, the controller shuts down as soon as the trip threshold is reached. In HICCUP enabled mode, when overcurrent trip threshold is reached, the power supply output shuts down and attempts to restart. The time duration between the shutdown of the output and the restart is determined by the time it takes to discharge the soft start capacitor. Typically, the discharge time of the soft start capacitor is 10 times the charge time. The duty cycle of the hiccup process is typically 5%. The output will stay in hiccup indefinitely until the overload is removed. The typical overcurrent trip threshold of the device is internally set at 30A. The overcurrent shutdown / HICCUP threshold is ±30% accurate. The iP1202 overcurrent shutdown and HICCUP threshold can be set externally by adding ROCSET1 and ROCSET2 resistors from OCSET1 and OCSET2 pins to VSW1 and VSW2 pins respectively. Refer to Fig.8 for ROCSET1 and ROCSET2 selection. Overvoltage Protection (OVP) Overvoltage is sensed through separate output voltage sense pins FB1s and FB2s. A separate OVP circuit is provided for each output and the OVP threshold is set to 115% of the output voltage. Upon overvoltage condition of either one of the outputs, the OVP forces a latched shutdown on both outputs. In this mode, the upper FETs turn off and the lower FETs turn on, thus crowbaring the outputs. Reset is performed by recycling the ENABLE pin. Overvoltage can be sensed by either connecting FB1s and FB2s to their corresponding outputs through separate output voltage divider resistor networks, or they can be connected directly to their corrsponding feedback pins FB1 and FB2. For Type III control loop compensation, FB1s and FB2s should be connected through voltage dividers only. 13 iP1202 Refer to iP1202 Design Procedure section on how to set the OVP Trip threshold. PGOOD This is an output voltage status signal that is open collector and is pulled low when the output voltage falls below 85% of the output voltage. High state indicates that outputs are in regulation. There is only one PGOOD for both outputs. The PGOOD pin can be left floating if not used. VIN 12V Cin 22uF x6 R1 100k Thermal Shutdown The iP1202 provides thermal shutdown. The threshold typically is set to 140°C. When the trip threshold is exceeded, thermal shutdown turns the outputs off. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to the normal range. OC1 VIN VSW1 ROC1 51.1k VOUT1 1.5V L1 1.0uH R9 FB1 887 HICCUP FB1S Cout1 470uF x2 R7 1k C9 CC1 0.018uF R2 100k C8 0.1uF PGOOD R5 2.49k SS1 iP1202 VP-REF VREF 0.8V C10 100pF SS2 C7 0.1uF OC2 ROC2 51.1k VSW2 ENABLE 1.0uH FB2 SYNC PGND RT CC2 0.012uF Cout2 470uF x2 R8 1k C11 30.9k R10 2.15k FB2S R3 VOUT2 2.5V L2 R6 3.32k PGND Fig. 14: iP1202 Dual Output Simplified Schematic 14 www.irf.com iP1202 VIN 12V R1 51.1k VSW1 Cin 22uF x6 FB1 HICCUP 100k ROC1 OC1 VIN L1 Rshunt1 1.0uH R9 5mOhm 887 FB1S Cout 470uF x4 R7 1k C9 CC1 VOUT 1.5V 0.018uF R5 2.49k R2 100k PGOOD SS1 C8 0.1uF iP1202 VP-REF 0.8V VREF C10 100pF SS2 ROC2 OC2 51.1k VSW2 ENABLE L2 Rshunt2 1.0uH 5mOHM R17 FB2 8.87k FB2S R3 PGND RT 30.9k SYNC C11 CC2 2.2nF R6 2.61k PGND Fig. 15: iP1202 Single Output Simplified Schematic Rdc1 (inductor dc resistance) L1 OC1 1.0uH VIN 12V VIN VSW1 RL1 Cin 22uF x6 R1 100k CL1 1.0uF 1.0k HICCUP 100k PGOOD R9 887 R7 1k C9 CC1 0.018uF R5 2.49k iP1202 SS1 VP-REF VREF C8 0.1uF 0.8V C10 100pF L2 OC2 VSW2 RL2 1.0k 30.9k SYNC PGND FB2 PGND ENABLE RT Rdc2 (inductor dc resistance) 1.0uH SS2 R3 Cout 470uF x4 FB1 FB1S R2 VOUT 1.5V CL2 1.0uF R17 8.87k FB2S CC2 C11 2.2nF R6 2.61k Fig. 16: iP1202 Single Output Lossless Inductor Current Sensing Simplified Schematic www.irf.com 15 iP1202 iP1202 Design Procedure Only a few external components are required to complete a dual output synchronous buck power supply using iP1202. The following procedure will guide the designer through the design and selection process of these external components. A typical application for iP1202 will be: VIN = 12V, VOUT1 = 1.5V, IOUT1 = 15A, VOUT2 = 2.5V, IOUT2 = 10A, fsw = 300kHz, Vp-p1 = Vp-p2 = 50mV Setting the Output Voltage The output voltage of the iP1202 is set by the 0.8V reference Vref and external voltage dividers. Vout1 R9 FB1 R7 ence source to VP-ref. In this case, to ensure proper start-up, power to VP-ref and iP1202 must be applied simultaneuosly. Setting the Overvoltage Trip Both outputs of the iP1202 will shut down if either one of the outputs experiences a voltage in the range of 115% of VOUT. The overvoltage sense pins FB1s and FB2s are connected to the output through voltage dividers, R13 and R14 (Fig. 17), and the trip setpoints are programmed according to equation (1). Separate overvoltage sense pins FB1s and FB2s are provided to protect the power supply output if for some reason the main feedback loop is lost (for instance, loss of feedback resistors). An optional 100pF capacitor (C26) is used for delay and filtering purposes. If this redundancy is not required and if Type II control loop compensation scheme is utilized, FB1s and FB2s pins can be connected to FB1 and FB2 pins respectively. In parallel configuration, FB2s should be connected to FB1s iP1202 Setting the Soft-Start Capacitor R13 The soft start capacitor Css is selected according to equation (2): FB1S C26 (Optional) R14 tss = 40 x Css Fig. 17: Typical scheme for output voltage setting For Type II compensation, where, tss is the output voltage ramp time in milliseconds, and Css is the soft start capacitor in µF. A 0.1µF capacitor will provide an output voltage rampup time of about 4ms. VOUT1 is set according to equation (1): VOUT1 = Vref x (1 + R9 /R7 ) (see Fig. 17) (2) (1) Setting R7 to 1K, VOUT1 to 1.5V and Vref to 0.8V, will result in R9= 875 ohms (select 887 ohms). Final values can be selected according to the desired accuracy of the output. To set the output voltage for Type III compensation, refer to equation (25) in Type III compensation section. If the 0.8V reference is used to set the voltage for the second output VOUT2, VP-ref pin must be shorted to Vref pin and in a similar way, voltage divider resistors are selected for the second output VOUT2. The second output can also be set by applying an external refer16 Input Capacitor Selection The switching currents impose RMS current requirements on the input capacitors. The expression in equation (3) allows the selection of the input capacitors for duty cycles less than 0.5: 2 2 (3) I = I D (1 − D ) + I D (1 − D ) − 2 I I D D RMS ( 1 1 1 2 2 2 1 2 1 2 ) where, I1 and I2 are the load currents for outputs 1 and 2 respectively and D1 and D2 are the duty cycles for channel 1 and channel 2 respectively. For output1 of the above example D= 0.13 and, For output2 of the above example D = 0.21 and, For the above example, using equation (3) the capacitor rms current yields 5.8A. www.irf.com iP1202 For better efficiency and low input ripple, select low ESR ceramic capacitors. The amount of the capacitors is determined based on the r.m.s. rating. In the above example, a total of 4 x 22µF, 2A capacitors will be required to support the input r.m.s. current, including derating (see the parts list in the reference design section of this datasheet). The 180° out of phase operation of the iP1202 provides reduced voltage ripple at the input of the device. This reduction in ripple requires less input bypass capacitance. For single output configuration and a duty cycle greater than 0.5, select the input capacitors according to equation (4) : I RMS = I LOAD ((2 − 2 D )(2 D − 1) (4) D is the duty cycle and is expressed as: D = VOUT / VIN. Output Capacitor CO Selection Selection of the output capacitors depends on two factors: a. Low effective ESR for ripple and load transient requirements To support the load transients and to stay within a specified voltage dip ∆V due to the transients, e.s.r. selection should satisfy equation (5): Resr ≤ ∆V / ILoadmax (5) Where, ILoadmax is the maximum load current. (6) Where, Vp-p is the single phase peak to peak output voltage ripple. Iripple is the inductor current peak-to peak ripple. In addition, the voltage ripple caused by the output capacitor needs to be significantly smaller than the ripple caused by the ESR of the capacitor. Use equation (7) to satisfy this requirement. Co > 10 2⋅π ⋅ f s Resr www.irf.com When selecting output capacitors, it is important to consider the overshoot performance of the power supply. If the amount of capacitance is not adequate, then, when unloading the output, the magnitude of the overshoot due to stored inductor energy, and depending on the speed of the response of the control loop, can exceed the overvoltage trip threshold of the iP1202 and can cause undesirable shutdown of the output. The magnitude of the overshoot should be kept below 1.125VOUT . To prevent the overshoot from tripping the output a delay can be added by installing capacitor C26 as shown in Fig.17. In paralleled single output configuration, due to 180° phase shift, the peak to peak output voltage ripple will be reduced because of doubling of the ripple frequency. Also, the resulting ripple current in the output capacitors will be smaller than the ripple current of each channel. There is some cancellation effect of these current, the magnitude of which depends on the duty cycle. b. Stability If output voltage ripple is required to be maintained at specified levels then, the expression in equation (6) should be used to select the output capacitors. Resr ≤ Vp-p / Iripple If the inductor current ripple Iripple is 30% of IOUT1, the 50mV peak to peak output voltage ripple requirement will be met if the total e.s.r. of the output capacitors is less than 11mΩ. This will require 2 x 470µF POSCAP capacitors (See the parts list in the reference design section of this datasheet). Additional ceramic capacitors can be added in parallel to further reduce the e.s.r. Care should be given to properly compensate the control loop for low output capacitor e.s.r. values. (7) The value of the output capacitor e.s.r. zero frequency fesr plays a major role in determining stability. fesr is calculated by the expression in equation (8). fesr = 1 / (2 π x Resr x CO) (8) Details on how to consider this parameter to design for stability will be outlined in the control loop compensation section of this datasheet. Inductor LO Selection Inductor selection is based on trade-offs between size and efficiency. Low inductor values result in smaller sizes, but can cause large ripple currents and lower efficiency. Low inductor values also benefit the transient performance. 17 iP1202 The inductor Lois selected according to equation (9): LO = Vout x (1 - D) / (fsw x Iripple) Type II Vout1 (9) R9 For output 1 of the above example, and for Iripple of 30% of IOUT1, LO1 is calculated to be 1.0µH. The core must be selected according to the peak of maximum output current. A similar calculation can be applied to find an inductor value for the second output. iP1202 FB1 R7 E/A1 VREF C10 CC1 Control Loop Compensation C9 The iP1202 feedback control is based on single loop voltage mode control principle if both outputs are configured in dual output independent mode. In this case, both outputs can have identical compensation. If iP1202 outputs are configured for parallel operation, then compensation of the outputs will differ slightly. The goal in the design of the compensator is to achieve the highest unity gain (0 db) crossover frequency with sufficient phase margin for the closed loop transfer function. The LC filter of the power supply introduces a double pole with 40db/dec slope and 1800 phase lag. The 180° phase contribution from the LC filter is the source of instabilty. The resonant frequency of the LC filter is expressed by equation (10): f LC = 1 / (2π L0 × C 0 ) (10) The error amplifiers of the iP1202 PWM controller are transconductance amplifiers, and their outputs are available for external compensation. Two type of compensators are studied in this section. The first one is called Type II and it is used to compensate systems the e.s.r. frequency fesr (equation 8) of which is in the midfrequency range and Type III that can be used for any type of output capacitors and have a wide range of fesr. (Optional) R5 Magnitude(dB) H(s) dB FZ Frequency Fig. 18: Typical Type II compensation and its gain plot From Fig.18 the transfer function H(s) of the error amplifier is given by (11): R7 1 + sR5 C9 (11) × R7 + R9 sC 9 R5 The term s represents the frequency dependence of the transfer function. H ( s) = g m × The Type II controller introduces a gain and a zero expressed by equations (12) and (13): H (s) = g m × R7 × R5 R7 + R9 (12) where, gm is the transconductance of the error amplifier. fz = 1 2π × R5 × C 9 (13) Follow the steps below to determine the feedback loop compensation component values: 18 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. www.irf.com iP1202 2. Calculate R5 using equation (14): R5 =V 1ramp .25 × f ×f R + R9 1 1 × 0 2esr × 7 × VIN R7 gm f LC (14) Where, VIN = Maximum Input voltage f0 = Error amplifier zero crossover frequency fesr= Output capacitor Co zero frequency fLC = Output frequency resonant filter gm= Error amplifier transconductance. Use 2mS for gm. Vramp = Oscillator ramp Voltage. Use 1.25V for Vramp Type III Type III compensation scheme allows the use of any type of capacitors with esr frequency of any range. This scheme suggests a double pole double zero compensation and requires more components around the error amplifier to achieve the desired gain and phase margins. Fig. 19 represents the type III compensation network for iP1202. The transfer function of the type III compensator is given by eqaution (18) H (s) = (1 + sR 23C 9 ) × (1 + sR9 C19 ) 1 × sR9 C 9 (1 + sR 23C18 ) × (1 + sR24 C19 ) 3. Place a zero at 75% of fLC to cancel one of the LC filter poles. f z = 0 . 75 × 1 2π Lo × C o (15) 4. Calculate C9 using equations (13) and (15) Calculation of compensation components for output1, based on the example above yields: fLC = 5.0kHz fz = 3.8kHz f0 = 30kHz fesr = 14kHz, per equation (6) using Resr = 12mΩ. R5 = 2.49K C9 = 18nF (18) C18 Vout1 C9 R23 C19 R24 CC1 R9 iP1202 FB1 R7 E/A1 VREF C10 The same steps can be used to determine the values of the compensation components for output2. Sometimes, a pole fp2 is added at half the switching frequency to filter the switching noise. This is done by adding a capacitor Copt in Fig.18 from the output of the error amplifier (CC pin of iP1202) to ground. This pole is given by equation (16): f p2 ≈ 1 2π × R5 × Copt (16) Copt is found from equation (17) by rearranging the terms in equation (16) and by setting fp2 = fsw / 2: C opt = 1 2π × f p 2 × R5 www.irf.com Magnitude(dB) H(s) dB FZ1 FZ2 FP2 FP3 Frequency Fig. 19: Typical Type III compensation and its gain plot (17) 19 iP1202 The frequencies of the three poles and the two zeros of the type III compensation scheme are represented by the following equations: fp1= 0 f p2 (19) 1 = 2π × R24 × C19 f p3 ≅ f z1 = (20) 1 2π × R23 × C18 (21) 1 2π × R23 × C 9 (22) 7. Place the second pole fp2 at or near fesr of the output capacitor Co and determine the value of R24 from R equation (20). Make sure R24 < 9 10 8. Use equation (25) to calculate R7. V R7 = R9 x V ref (25) -V o ref More than one iteration may be required to calculate the values of the compensation components if crossover frequencies higher than the range specified in step 1 are required (for higher bandwidths and faster transient response performance). To ensure stability a phase margin greater than 45° should be achieved. Refer to AN-1043 for more detailed compensation techniques using Transconductance Amplifiers. Compensation in Current Share Mode f z2 = 1 2π × R9 × C19 (23) The crossover frequency f0 for type III compensation is represented by equation (24): 1 f 0 = V0.8 × VIN × R23 × C19 × ramp 1 2π × L0 × C 0 (24) The iP1202 can be configured in single output paralleled configuration. The feedback loop of the first output is closed around the output voltage, and the second amplifier, which is also a transconductance one, forces equal sharing of the inductor currents in both outputs. Voltage Loop 2. Select R23~ 10kΩ Type II and Type III methods of voltage loop compensation discussed above, can be used to compensate the voltage loop of a single output iP1202. In this case, the total amount of capacitance seen by both channels and the inductance of the voltage controlling channel should be considered for compensation. 3. Place the first zero fz1 at 75% of the resonant frequency fLC of the output filter. Determine C9 from equation (22). Current Loop Use the following procedure for current loop compensation: 4. Place a third pole fP3 at or near the switching frequency fSW. In Fig. 20, L1 and L2 are the inductors for outputs 1 and 2 respectively. Rsh1 and Rsh2 are the current sensing shunts for the same outputs. Follow the steps below to determine the feedback loop compensation component values: 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. Select C18 such that C18 < C9 10 5. Calculate C19 from equation (24). 6. Place the second zero at 125% of the resonant frequency fLC of the output filter. Calculate R9 using equation (23). 20 www.irf.com iP1202 Vsw1 L1 Rsh1 iP1202 Vp-Ref VOUT E/A2 FB2 RLoad CC2 Rsh2 C11 L2 R6 Vsw2 Fig. 20: Output 2 error amplifier compensation network for parallel configuration. Resistor R6 of the compensation network is calculated according to equation (26) 2π × L2 × f 02 1 (26) × g m × Rsh1 Vin It is recommended to set the channel 2 crossover frequency 30% higher than the voltage loop crossover frequency. R6 = Vramp × The power stage of the current loop has a dominant pole at frequency expressed by equation (27): fp = Req 2⋅π ⋅ L2 (27) where, Req represents the total resistance of the power stage that includes the Rdson of the FET switches, the DC resistance of the inductor and the shunt resistance, and is expressed by equation (28): (28) Req = Rdson + RL + Rsh use 10mohm for FET Rdson. To calculate for C11, place the zero frequency fz at 10 times the dominant pole frequency fp using equation (29): f z = 10 × f p 1 C11 = 2 ⋅ π × R6 × f z Select C 11 ≤ 6 .8 nf www.irf.com (29) 21 iP1202 Typical Waveforms Ch1 Ch3 Ch2 Ch4 Ch1: Output 1 switching node, 400kHz Ch2: Output 2 switching node, 400kHz Ch4: 800kHz external synchronization Fig. 21: iP1202 Outputs synchronized to 800kHz Ch1: Output voltage, 100mV/div ac Ch3: Load current, 5A/div Fig. 23: iP1202 Transient response load step 1A to 12A 22 Ch1: Ch2: Ch3: Ch4: Output Output Output Output 1 2 1 2 voltage, 1V/div voltage, 1V/div load current, 10A/div load current, 10A/div Fig. 22: iP1202 hiccup response (Output 1 hiccups due to overload, whereas Output 2 continues uniterrupted) Ch1: Output voltage, 100mV/div ac Ch3: Load current, 5A/div Fig. 24: iP1202 Transient response load step 12A to 0A www.irf.com iP1202 Ch1 Ch3 Ch2 Ch4 Ch1: Ch2: Ch3: Ch4: Output Output Output Output 1 2 1 2 voltage, 1V/div voltage, 1V/div load current, 10A/div load current, 10A/div Fig. 25: iP1202 latched overcurrent response (output1 shutsdown due to overload, whereas output2 continues uninterrupted) Ch1: Output1 voltage, 1V/div Ch2: Output2 voltage, 1V/div Fig. 27: iP1202 overvoltage trip. (Overvoltage on output2 causes both outputs to shutdown) www.irf.com Vin=3.3V Ch1: Output Ch2: Output Ch3: Output Ch4: Output 1 switch node voltage 10V/div 2 switch node voltage 10V/div 1 inductor current, 10A/div 2 inductor current , 10A/div Fig. 26: iP1202 inductor current sharing Vin=12V Ch1: Output 1 switch node voltage 10V/div Ch2: Output 2 switch node voltage 10V/div Ch3: Output voltage ripple, 50mV/div Fig. 28: iP1202 Output voltage ripple in parallel configuration 23 iP1202 Ch1: Output 1, 0.5V/div Ch2: Output 2, 0.5V/div Fig. 29: iP1202 output sequencing with separate soft-start capacitors 24 Ch1: Output 1, 0.5V/div Ch2: Output 2, 0.5V/div Fig. 30: iP1202 output sequencing with separate soft-start capacitor and delayed turn-on www.irf.com iP1202 Layout Guidelines For stable and noise free operation of the whole power system, it is recommended that the designer uses the following guidelines: 1. Follow the layout scheme presented in Fig. 32. Make sure that the output inductors L1 and L2 are placed as close to iP1202 as possible to prevent noise propagation that can be caused by switching of power at the switching node Vsw, to sensitive circuits. 2. Provide a mid-layer solid ground plane with connections to the top layer through vias. The PGND pads of iP1202 also need to be connected to the same ground plane through vias. 3. To increase power supply noise immunity, place input and output capacitors close to one another, as shown in the layout diagram. This will provide short high current paths that are essential at the ground terminals. 4. Although there is a certain degree of VIN bypassing inside the iP1202, the external input decoupling www.irf.com capacitors should be as close to the device as possible. 5. The Feedback tracks from the outputs VOUT1 and VOUT2 to FB1 and FB2 respectively, should be routed as far away from noise generating traces as possible. 6. The compensation components and the Vref bypass capacitor should be placed as close as possible to their corresponding iP1202 pins. 7. For single output configuration, the parasitic paths leading to the common output connector from each parallel branch should be symmetrically routed to ensure equal current sharing. 8. Refer to IR application note AN-1029 to determine what size vias and copper weight and thickness to use when designing the PCB. 9. Place the overcurrent threshold setting resistors ROCSET1 and ROCSET2 close to the iP1202 block at the corresponding connection nodes. Fig. 31: iP1202 suggested layout 25 † 16 15 INPUT/OUTPUT 14 12 10 8 6 4 2 13 11 9 7 5 3 1 CON4 TP29 PGND 25V C1 22uF ENABLE 25V C2 22uF 25V C3 22uF Installed Removed Removed Installed Installed C20, C21 C9, C11 R5, R6 Installed Removed Removed Removed Installed Installed Installed Installed Removed R17 R8 R10 R4 R11 R12 R22 R27 Installed Removed Removed Installed Removed R16 2 phase mode(single output) 5mOHM Independent mode(dual output) Short R15, R19 Designator Output Configuration Installed Removed Installed Removed Installed Type III Configuration C18, C19 Type II Configuration 25V C4 22uF R23, R24, R25, R26 Designator Compensation Configuration †† VOUT2 VOUT1 VSW2S VSW1S PGNDS VINS PGND TP4 PGND TP2 SHUNT SHUNT TP28 VIN VIN VIN=5.5V-13.2V TP1 VIN JP3-1 JP1-1 VIN VIN ENABLE SYNC C7 0.1uF C8 0.1uF 100K R2 JP1 HICCUP 100K R1 25V C23 22uF 30.9K R3 JP3 ENABLE TP6 25V C22 22uF 1 2 1 2 26 SYNC RT SS2 SS1 PGOOD HICCUP VIN SYNC RT ENABLE SS2 SS1 PGOOD HICCUP VIN iP1202 FB1S CC1 FB1 VSW1 OC1 FB2S CC2 FB2 VSW2 OC2 VREF VP-REF PGND TP3 FB2S CC2 FB2 VSW2 OC2 VREF VP-REF FB1S CC1 FB1 C27 100pF C20*** NI 51.1K 1% ROC2 0.8V C26 100pF C18*** NI 51.1K 1% VSW1 OC1 ROC1 887 1% R13 † 1uH L2 R16 0 NI C19 *** † R8 1k 1% † R17 8.87k NI *** R26 † R19 5mOHM (short for independent output configuration) 5mOHM (short for independent output configuration) NI C21*** 2.15k 1% † R10 †† Type III Compensation NI R24*** R9** 887 1% † R15 R27 † 0 6.3V C15 470uF 6.3V C12 470uF 6.3V (2.5V) C16 470uF VOUT2 6.3V (1.5V) C13 470uF VOUT1 For VOUT2: R10 = R8[(VOUT2/VREF) - 1]. C25 NI C24 NI TP18 PGND C17 0.1uF TP17 VOUT2 TP16 PGND C14 0.1uF TP15 VOUT1 ***NI: Not Installed For parallel (single output) mode, check table on the left. Set R7 (or R8) to 1K, VREF to 0.8V, and VOUT to desired output, then solve for R9 (or R10 respectively). For VOUT1: R9 = R7[(VOUT1/VREF) - 1]. 2.15K 1% **For independent mode, output voltages are set by using the following equations: R11 R12 1K 1% R22 0 FB1S C11 0.012uF R6 3.32K *** R25 TP10 VSW2 VSW2S C10 100pF NI 0 † R4 R14 1K 1% ** R5 R7 2.49K 1K 1% 1uH L1 TP8 VSW1 C9 0.018uF *** R23 NI VSW1S PGN TP1 VOU TP1 PGN TP22 PGND TP14 VOUT TP20 VOUT TP11 iP1202 Fig. 32: Reference Design Schematic www.irf.com iP1202 IRDCiP1202-A (Single, paralleled output configuration(for 1.5V output) QTY REF DESIGNATOR DESCRIPTION Capacitor, ceramic, 22µF, 25V, X5R, 20% Capacitor, ceramic, 0.1µF, 50V, X7R, 10% Capacitor, ceramic, 0.012uF, 25V, X7R, 10% Capacitor, poscap, 470µF, 6.3V, electrolytic 20% Capacitor, ceramic, 100pF, 50V, NPO, 5% Capacitor, ceramic, 0.018uF, 25V, X7R, 10% Inductor, 1µH, 19A, 20% Resistor, thick film, 887Ω, 1/10W , 1% Resistor, thick film, 1.0kΩ, 1/10W , 1% Resistor, thick film, 51.1kΩ, 1/10W , 1% Resistor, alloy metal, 5mΩ, 1W , 1% Resistor, manganin-foil, 0Ω, 2W Resistor, thick film, 0Ω, 1/16W Resistor, thick film, 8.87kΩ, 1/10W , 1% 6 C1, C2, C3, C4, C22, C23 4 C7, C8, C14, C17 1 C11 4 C12, C13, C15, C16 3 C10, C26, C27 1 C9 2 L1, L2 2 R13, R9 2 R7, R14 2 ROC1,ROC2 2 R15, R19 1 2 R27 R16, R22 1 R17 15 C18, C19, C20, C21, C24, C25, R10, R11, R12, R4, R8, R23, R24, R25, R26 2 R1, R2 1 R5 1 R6 1 R3 1 U1 Not installed Resistor, thick film, 1/10W , 1% Resistor, thick film, 1/10W , 1% Resistor, thick film, 1/10W , 1% Resistor, thick film, 1/10W , 1% BGA Power Block 100kΩ, 2.49kΩ, 3.32kΩ, 30.9kΩ, SIZE MFR PART NUMBER 1812 TDK C4532X5R1E226M 0603 TDK C1608X7R1H104K 0603 Phycomp 06032R123K8B20 7343 Sanyo 6TPB470M 0603 Phycomp 0603CG101J9B20 0603 Phycomp 06032R183K8B20 13.0mm X 12.9mm Panasonic ETQP1H1R0BFA 0603 KOA RK73H1J8870F 0603 KOA RK73H1J1001F 0603 KOA RK73H1J5112F 2512 Panasonic ERJM1W SF5M0U 2716 0603 Isotek Corp ROHM SMT-R000 MCR03EZHJ000 0603 KOA RK73H1J8871F - - - 0603 KOA RK73H1J1003F 0603 KOA RK73H1J2491F 0603 KOA RK73H1JLTD3321F 0603 KOA RK73H1J3092F 9.25mm X 15.5mm IR iP1202 IRDCiP1202-A (Dual, Independent output configurations(Channel1 1.5V output, Channel2 2.5V output) QTY REF DESIGNATOR DESCRIPTION SIZE MFR PART NUMBER 6 C1, C2, C3, C4, C22, C23 Capacitor, ceramic, 22µF, 25V, X5R, 20% 1812 TDK C4532X5R1E226M 4 1 C7, C8, C14, C17 C11 Capacitor, ceramic, 0.1µF, 50V, X7R, 10% Capacitor, ceramic, 0.012uF, 25V, X7R, 10% 0603 0603 TDK Phycomp C1608X7R1H104K 06032R123K8B20 4 C12, C13, C15, C16 Capacitor, poscap, 470µF, 6.3V, electrolytic 20% 7343 Sanyo 6TPB470M 3 1 2 2 2 4 2 2 1 C10, C26, C27 C9 L1, L2 R13, R9 R10, R11 R7, R8, R12, R14 ROC1,ROC2 R15, R19 R4 C18, C19, C20, C21, C24, C25, R16, R17, R22, R23, R24, R25, R26, R27 R1, R2 R5 R6 R3 U1 Capacitor, ceramic, 100pF, 50V, NPO, 5% Capacitor, ceramic, 0.018uF, 25V, X7R, 10% Inductor, 1µH, 19A, 20% Resistor, thick film, 887Ω, 1/10W, 1% Resistor, thick film, 2.15kΩ, 1/10W, 1% Resistor, thick film, 1.0kΩ, 1/10W, 1% Resistor, thick film, 51.1kΩ, 1/10W, 1% Resistor, manganin-foil, 0Ω, 2W Resistor, thick film, 0Ω, 1/10W, 5% 0603 0603 13.0mm X 12.9mm 0603 0603 0603 0603 2716 0603 Phycomp Phycomp Panasonic KOA KOA KOA KOA Isotek Corp ROHM 0603CG101J9B20 06032R183K8B20 ETQP1H1R0BFA RK73H1J8870F RK73H1J2151F RK73H1J1001F RK73H1J5112F SMT-R000 MCR03EZHJ000 Not installed - - - Resistor, thick film, 100kΩ, 1/10W, 1% Resistor, thick film, 2.49kΩ, 1/10W, 1% Resistor, thick film, 3.32kΩ, 1/10W, 1% Resistor, thick film, 30.9kΩ, 1/10W, 1% BGA Power Block 0603 0603 0603 0603 9.25mm X 15.5mm KOA KOA KOA KOA IR RK73H1J1003F RK73H1J2491F RK73H1JLTD3321F RK73H1J3092F iP1202 14 2 1 1 1 1 www.irf.com Table 2. Reference Design Bill of Materials 27 iP1202 0.15 [.006] C 2X 6 15.50 [.610] B A 5 C 0.45 [.0177] 0.35 [.0138] 0.12 [.005] C 1. 2. 3. 4. 5 DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. CONT ROLLING DIMENS ION: MILLIMET ER S OLDER BALL POS IT ION DES IGNAT ION PER JES D 95-1, S PP-010. PRIMARY DAT UM C (S EAT ING PLANE) IS DEFINED BY T HE S PHERICAL CROWNS OF T HE S OLDER BALLS . 6 BILAT ERAL T OLERANCE ZONE IS APPLIED T O EACH S IDE OF T HE PACKAGE BODY. 7 S OLDER BALL DIAMET ER IS MEAS URED AT T HE MAXIMUM S OLDER BALL DIAMET ER, IN A PLANE PARALLEL T O DAT UM C. 8. NOT T O S CALE. BALL A1 CORNER ID 9.25 [.364] 0.15 [.006] C 2X NOT ES : 6 T OP VIEW 27X 0.80 [.032] 0.40 [.016] BOT T OM VIEW 2X 0.55 [.0216] 154X Ø 0.45 [.0178] 0.15 [.006] 0.08 [.003] 2.33 [.0917] 2.11 [.0831] (2X 0.625 [.025]) 7 C A B C 2.78 [.1094] 2.46 [.0968] S IDE VIEW Fig.33: Mechanical Drawing Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifiers iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGAs on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1043: Stabilize the Buck Converter with Transconductance Amplifier. AN-1047: Graphical solution to two branch heatsinking Safe Operating Area This paper is a suppliment to AN-1030 and explains how to use the double side Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1053: Power Sequencing Techniques using iP1201 and iP1202. 28 www.irf.com iP1202 BALL A1 IDENTIFIER INTERNATONAL RECTIFIER LOGO 0305 XXXX iP1202 ASSEMBLY CODE DATE CODE (YYWW) YY=YEAR WW=WEEK PART NUMBER FACTORY CODE Fig.34: Part Marking 0325 XXXX iP1202 24.00 (.945) 0325 XXXX iP1202 20.00 (.787) FEED DIRECTION NOT ES : 1. OUTLINE CONFORMS TO EIA-481 & EIA-541. iP1202, BGA Fig.35: Tape & Reel Information Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.10/04 www.irf.com 29