A-POWER APU3146

Technology Licensed from International Rectifier
APU3146
DUAL SYNCHRONOUS PWM CONTROLLER WITH
CURRENT SHARING CIRCUITRY AND AUTO-RESTART
DESCRIPTION
FEATURES
Dual Synchronous Controller with 180 out-of-phase
Configurable to 2-Independent Outputs or 2-Phase
Single Output
Current Sharing Using Inductor's DCR
Current Limit using MOSFET's RDS(ON)
Hiccup/Latched Current Limit
Latched Over-Voltage Protection
Vcc from 4.5V to 16V Input
Programmable Switching Frequency up to 500KHz
Two Independent Soft-Starts/ Shutdowns
0.8V Precision Reference Voltage Available
Power Good Output
External Frequency Synchronization
APPLICATIONS
The APU3146 IC combines a Dual synchronous Buck
controller, providing a cost-effective, high performance
and flexible solution. The APU3146 can configured as 2independent or as 2-phase controller. The 2-phase configuration is ideal for high current applications. The
APU3146 features 180 out of phase operation which reduces the required input/output capacitance and results
to few number of capacitor quantity. Other key features
offered by this device include two independent programmable soft starts, programmable switching frequency up
to 500KHz per phase, under voltage lockout function.
The current limit is provided by sensing the lower
MOSFET's on-resistance for optimum cost and performance.
2-Phase Power Supply
Graphic Card
DDR Memory Applications
Embedded Computer Systems
Telecom Systems
Point of Load Power Architectures
D1
C12
12V
C11
C3
C4
VCL VcH1 VOUT3 VcH2
HDrv1
Vcc
C5
OCSet1
Hiccup
VREF
Rt
C8
R3
LDrv1
C14
Q2
L3
Q3
R5
1.8V @ 30A
C15
D2
BAT54A
U1
APU3146 VSEN1
Comp1
C9
R1
PGnd1
VP2
Sync
R2
C13
R10
C16
R11
R7
VSEN2
Fb1
Fb2
R8
R9
C17
R4
Comp2
HDrv2
C18
R6
Q4
L4
OCSet2
PGood
PGood
SS1 / SD
C10
SS2 / SD
LDrv2
Q5
PGnd2
Gnd
Figure 1 - Typical application of APU3146 in 2-phase configuration with inductor current sensing
PACKAGE ORDER INFORMATION
DEVICE
APU3146O(/M)
Data and specifications subject to change without notice.
PACKAGE
28-Pin TSSOP(/SOIC WB)
200407061-1/28
APU3146
ABSOLUTE MAXIMUM RATINGS
Vcc, VCL Supply Voltage .............................................. -0.5V To 16V
VcH1 and VcH2 Supply Voltage ................................ -0.5V To 25V
PGOOD................. ................................................... -0.5V To 16V
Storage Temperature Range ...................................... -40°C To 125°C
Operating Junction Temperature Range ..................... -40°C To 125°C
Caution: Stresses above those listed in Absolute Maximum Ratings" may cause permanent damage to the device.
PACKAGE INFORMATION
28-PIN TSSOP (O)
PGood 1
VCC 2
VOUT3 3
Rt 4
VSEN2 5
Fb2 6
Comp2 7
SS2 / SD 8
OCSet2 9
VcH2 10
28-PIN SOIC WIDE BODY(M)
PGood 1
28 Gnd
27 VREF
28 Gnd
27 VREF
VCC 2
26 VP2
26 VP2
VOUT3 3
Rt 4
25 Hiccup
24 Sync
25 Hiccup
24 Sync
VSEN2 5
Fb2 6
23 VSEN1
22 Fb1
23 VSEN1
22 Fb1
Comp2 7
21 Comp1
SS2 / SD 8
20 SS1 / SD
21 Comp1
20 SS1 / SD
OCSet2 9
19 OCSet1
19 OCSet1
VcH2 10
HDrv2 11
18 VcH1
HDrv2 11
18 VcH1
PGnd2 12
17 HDrv1
PGnd2 12
17 HDrv1
LDrv2 13
16 PGnd1
LDrv2 13
16 PGnd1
VCL 14
15 LDrv1
VCL 14
15 LDrv1
RthJA=80oC/W
RthJA = 84°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=12V, VcH1=VcH2=VCL=12V and TA=0 to 70°C.
Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures
equal to the ambient temperature.
PARAMETER
Reference Voltage Section
Reference Voltage
Voltage Line Regulation
UVLO Section
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - VcH1
UVLO Hysteresis - VcH1
UVLO Threshold - VcH2
UVLO Hysteresis - VcH2
Supply Current Section
Vcc Dynamic Supply Current
VcH1 & VcH2 Dynamic Current
VCL Dynamic Supply Current
Vcc Static Supply Current
VcH1/VcH2 Static Current
VCL Static Supply Current
SYM
VREF
LREG
TEST CONDITION
TYP
MAX
UNITS
0.789
0.805
0.02
0.821
0.04
V
%/V
3.9
4.2
0.25
3.5
0.1
3.5
0.1
4.5
V
V
V
V
V
V
10
15
15
10
6
6
15
25
25
15
10
10
5<Vcc<12
UVLOVCC Supply Ramping Up
Ramp Up and Ramp Down
UVLOVCH1 Supply Ramping Up
Ramp Up and Ramp Down
UVLOVCH2 Supply Ramping Up
Ramp Up and Ramp Down
Dyn ICC
Dyn ICH
Dyn ICL
ICCQ
ICHQ
ICLQ
MIN
Freq=300KHz, CL=1500pF
Freq=300KHz, CL=1500pF
Freq=300KHz, CL=1500pF
SS=0V
SS=0V
SS=0V
3.2
3.2
3.8
3.8
mA
mA
mA
mA
mA
mA
2/28
APU3146
PARAMETER
Soft-Start Section
Charge Current
Power Good Section
VSENS1 Lower Trip Point
VSENS2 Lower Trip Point
PGood Output Low Voltage
Error Amp Section
Fb Voltage Input Bias Current
Transconductance 1
Transconductance 2
Error Amp Source/Sink Current
Input Offset Voltage for PWM1/2
VP2 Voltage Range
Oscillator Section
Frequency
Ramp Amplitude
Synch Frequency Range
Synch Pulse Duration
Synch High Level Threshold
Synch Low Level Threshold
VOUT3 Internal Regulator
Output Voltage
Output Current
Protection Section
OVP Trip Threshold
OVP Fault Prop Delay
Current Limit Threshold
Current Source
Hiccup Duty Cycle
Hiccup High Level Threshold
Hiccup Low Level Threshold
Output Drivers Section
Rise Time
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
Min Pulse Width
Thermal Shutdown Trip Point
Thermal Shutdown Hysteresis
SYM
SSIB
PGFB1L
PGFB2H
IFB1
gm1
gm2
VOS(ERR)2
VP2
TEST CONDITION
SS=0V
VSENS1 Ramping Down
VSENS2 Ramping Down
ISINK=2mA
MIN
TYP
MAX
UNITS
20
25
32
µA
0.8VREF 0.9VREF 0.95VREF
0.8VREF 0.9VREF 0.95VREF
0.1
0.5
V
V
V
-0.1
µA
µmho
µmho
µA
mV
V
SS=3V
Fb to VREF
Note1
1400
1400
60
-5
0.8
100
0
-0.5
2300
2300
140
+5
1.5
KHz
Freq
VRAMP
Rt(SET) to 30K
Note1
20% above free running freq
Note1
Note1
255
345
1.25
800
200
2
300
0.8
5.9
50
OVP
Output forced to 1.125VREF,Note1
OCSet
6.2
6.7
V
KHz
ns
V
V
V
mA
1.1VREF 1.15VREF 1.2VREF
5
16
20
24
V
µs
µA
5
%
V
V
Hiccup pin pulled high, Note1
Note1
2
0.8
Tr
Tf
TDB
DMAX
DMIN
Puls(min)
CL=1500pF, Figure 2
CL=1500pF, Figure 2
Figure 2
Fb=0.6V, FSW=300KHz
Fb=1V
FSW=300KHz, Note1
Note 1
18
25
50
85
0
150
140
20
50
50
100
ns
ns
ns
%
%
ns
C
C
Note 1: Guaranteed by design but not tested for production.
3/28
APU3146
DEADBAND TIME
Tf
Tr
90%
High Side
Driver HD 2V
10%
Tr
Tf
90%
Low Side
Driver LD 2V
10%
Deadband
H_to_L
Deadband
L_to_H
Figure 2 - Deadband time definition.
TDB(TYP)=(Deadband H_toL+Deadband L_to -H)/2
PIN DESCRIPTIONS
PIN#
1
2
3
4
5,23
6,22
7,21
8
20
9,19
10,18
11,17
12,16
13,15
14
24
25
PIN SYMBOL
PGood
Vcc
VOUT3
Rt
VSEN2, VSEN1
Fb2,Fb1
PIN DESCRIPTION
Power Good pin. Low when any of the outputs fall 10% below the set voltages.
Supply voltage for the internal blocks of the IC.
Output of the internal LDO.
Switching frequency setting resistor. (see Figure 10 for selecting resistor values).
Sense pins for OVP and PGood. For 2-Phase operation tie these pins together.
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a
resistor divider to set the output voltage and Fb2 is connected to programming resistor to
achieve current sharing. In independent 2-channel mode, these pins work as feedback
inputs for each channel.
Comp2, Comp1 Compensation pins for the error amplifiers.
These pins provide soft-start for the switching regulator. An internal current source charges
external capacitors that are connected from these pins to ground which ramp up the
SS2 / SD
output of the switching regulators, preventing them from overshooting as well as limiting
SS1 / SD
the input current. The converter can be shutdown by pulling these pins below 0.3V.
OCSet2,OCSet1 Current limit resistor (RLIM) connection pins for output 1 and 2. The other ends of RLIMs are
connected to the corresponding switching nodes.
VcH2, VcH1 Supply voltage for the high side output drivers. These are connected to voltages that must
be typically 6V higher than their bus voltages. A 1µF high frequency capacitor must be
connected from these pins to GND to provide peak drive current capability.
HDrv2, HDrv1 Output drivers for the high side power MOSFETs. 1)
PGnd2, PGnd1 These pins serve as the separate grounds for MOSFET drivers and should be connected
to the system’s ground plane.
LDrv2, LDrv1 Output drivers for the synchronous power MOSFETs.
VCL
Supply voltage for the low side output drivers. This pin should be high for normal operation
The internal oscillator may be synchronized to an external clock via this pin.
Sync
When pulled High, it puts the device current limit into a hiccup mode. When pulled Low,
Hiccup
the output latches off, after an overcurrent event.
4/28
APU3146
PIN DESCRIPTIONS
PIN#
26
PIN SYMBOL
VP2
27
28
VREF
Gnd
PIN DESCRIPTION
Non-inverting input to the second error amplifier. In the current sharing mode, it is connected to the programming resistor. In independent 2-channel mode it is connected to
VREF pin when Fb2 is connected to the resistor divider to set the output voltage.
Reference Voltage. The drive capability of this pin is about 2uA.
Analog ground for internal reference and control circuitry. Connect to PGnd plane with a
short trace.
1) These pins should not go negative (-0.5V), this may cause instability for the gate drive circuits. To prevent this,
a low forward voltage drop diode is required between these pins and ground as shown in Figure 1.
BLOCK DIAGRAM
Vcc
2
25uA 25uA
SS2 / SD
8
SS1 / SD
20
Mode
64uA
Max
3V
Bias
Generator
64uA
0.8V
4.2V / 4.0V
VcH1
VcH2
3.5V / 3.3V
UVLO
POR
Mode
POR
18
VcH1
17
HDrv1
14
VCL
15
LDrv1
16
PGnd1
19
OCSet1
10
VcH2
11
HDrv2
25
Hiccup
13
LDrv2
12
PGnd2
9
OCSet2
1
PGood
3
VOUT3
0.3V
PWM Comp1
Thermal
Shutdown
SS1
Error Amp1
R
0.8V
Comp1
21
Rt
4
Sync
24
VREF
27
SS1
3uA
Q
22
Set1
Ramp1
Two Phase
Oscillator
S
20uA
Reset Dom
Set2
Ramp2
Reset Dom
S
PWM Comp2
0.8V
Q
R
Error Amp2
VP2
Mode
Control
3.5V / 3.3V
POR
Fb1
VP2
0.8V
SS1
SS2
Hiccup
Control
Mode
26
0.3V
Fb2
6
Comp2
7
VSEN1
23
VSEN2
5
Gnd
28
SS2
PGood / OVP
OVP
HDrv OFF / LDrv ON
Regulator
SS2
3uA
20uA
Figure 3 - Block diagram of APU3146.
5/28
APU3146
FUNCTIONAL DESCRIPTION
Introduction
The APU3146 is versatile device for high performance Buck
converters. It is included of two synchronous Buck controllers which can be operated both in two independent
mode or in 2-phase mode.
The timing of the IC is provided through an internal oscillator circuit. These are two out-of-phase oscillators that
can be programmed up to 400KHz per phase.
information for current sharing. The voltage drops across
the current sense resistors (or DCR of inductors) are
measured and their difference is amplified by the slave
error amplifier and compared with the ramp signal to
generate the PWM pulses to match the output current.
In this mode the SS2 pin should be floating.
APU3146
Supply Voltage
Vcc is the supply voltage for internal controller. The operating range is from 4.5V to 16V. It also is fed to the
internal LDO. When Vcc is below under-voltage threshold, all MOSFET drivers will be turned off.
Internal Regulator
The regulator powers directly from VCC and generates a
regulated voltage (Typ. [email protected]). The output is protected for short circuit. This voltage can be used for charge
pump circuitry as describe in Figure12.
PWM Comp1
Comp
Master E/A
PWM Comp2
0.8V
L1
Fb1
R1
RL1
VOUT
C1
VP2
FB2
L2
RL2
Slave E/A
R2
C2
Input Supplies UnderVoltage LockOut
Figure 4 - Loss-less inductive current sensing
The APU3146 UVLO block monitors three input voltages
and current sharing.
(VCC, VCH1 and VCH2) to ensure reliable start up. The
MOSFET driver output turn off when any of the supply
voltages drops below set thresholds. Normal operation In the diagram, L1 and L2 are the output inductors. RL1
resumes once the supply voltages rise above the set and RL2 are inherent inductor resistances. The resistor
R1 and capacitor C1 are used to sense the average invalues.
ductor current. The voltage across the capacitors C1
and C2 represent the average current flowing into resisIndependent Mode
In this mode the APU3146 provides control to two inde- tance RL1 and RL2. The time constant of the RC network
pendent output power supplies with either common or should be equal or at most three times larger than the
different input voltages. The output voltage of each indi- time constant L1/R .
L1
vidual channel is set and controlled by the output of the
R1×C1=(1~3)×
---(1)
L1
R
error amplifier, which is the amplified error signal from
the sensed output voltage and the reference voltage. The
error amplifier output voltage is compared to the ramp
signal thus generating fixed frequency pulses of variable
duty-cycle, which are applied to the FET drivers, Figure18 shows a typical schematic for such application.
L1
2-Phase Mode
This feature allows to connect both outputs together to
increase current handling capability of the converter to
support a common load. The current sharing can be done
either using external resistors or sensing the DCR of
inductors (see Figure 4). In this mode, one control loop
acts as a master and sets the output voltage as a regular Voltage Mode Buck controller and the other control
loop acts as a slave and monitors the current
Figure 5 - 30A Current Sharing using Inductor sensing
(5A/Div)
6/28
APU3146
Dual Soft-Start
The APU3146 has programmable soft-start to control the
output voltage rise and limit the inrush current during
start-up. It provides a separate Soft-Start function for each
outputs. This will enable to sequence the outputs by
controlling the rise time of each output through selection
of different value soft-start capacitors. The soft-start pins
will be connected together for applications where, both
outputs are required to ramp-up at the same time.
To ensure correct start-up, the soft-start sequence initiates when the VCC, VCH1 and VCH2 rise above their
threshold (4.2V and 3.5V respectively) and generate the
Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function
clamps the E/A’s output of the PWM converter. During
power up, the converter output starts at zero and thus
the voltage at Fb is about 0V. A current (64µA) injects
into the Fb pin and generates a voltage about 1.6V
(64µA×25K) across the negative input of E/A and (see
Figure6).
The magnitude of this current is inversely proportional to
the voltage at soft-start pin. The 25µA current source
starts to charge up the external capacitor. In the mean
time, the soft-start voltage ramps up, the current flowing
into Fb pin starts to decrease linearly and so does the
voltage at negative input of E/A.
When the soft-start capacitor is around 1V, the current
flowing into the Fb pin is approximately 32µA. The voltage at the positive input of the E/A is approximately:
32µA×25K = 0.8V
The E/A will start to operate and the output voltage starts
to increase. As the soft-start capacitor voltage continues to go up, the current flowing into the Fb pin will keep
decreasing. Because the voltage at pin of E/A is regulated to reference voltage 0.8V, the voltage at the Fb is:
25uA 25uA
SS2 / SD
8
SS1 / SD
20
64uA
POR
Error Amp1
0.8V
Fb1
22
Comp1
21
Error Amp2
VP2
26
Fb2
6
Comp2
7
Figure 6 -Soft-start circuit for APU3146
Output of POR
3V
≅2V
Soft-Start
Voltage
Current flowing
into Fb pin
≅1V
0V
64uA
0uA
Voltage at negative input ≅1.6V
of Error Amp
0.8V
0.8V
VFB = 0.8-(25K×Injected Current)
The feedback voltage increases linearly as the injecting
current goes down. The injecting current drops to zero
when soft-start voltage is around 2V and the output voltage goes into steady state. Figure 7 shows the theoretical operational waveforms during soft-start.
64uA
Max
Voltage at Fb pin
0V
Figure 7 - Theoretical operational waveforms
during soft-start.
The output start-up time is the time period when softstart capacitor voltage increases from 1V to 2V. The
start-up time will be dependent on the size of the external soft-start capacitor. The start-up time can be estimated by:
25µA×TSTART/CSS = 2V-1V
7/28
APU3146
For a given start up time, the soft-start capacitor can be
calculated by:
CSS ≅ 25µA×TSTART/1V
The soft-start is part of Over Current Protection scheme,
during the overload or short circuit condition the external
soft start capacitors will be charged and discharged in
certain slope rate to achieve the hiccup mode function.
The internal current source develops a voltage across
RSET. When the low side switch is turned on, the inductor current flows through the Q2 and results a voltage
which is given by:
VOCSET = IOCSET×RSET-RDS(ON)×iL
---(2)
IOCSET
25uA
APU3146
Hiccup
Q1
L1
OCSet RSET
SS1 / SD
20
3uA
Figure 8 - 3uA current source for discharging soft
start-capacitor during Hiccup mode
Hiccup
Control
VOUT
Q2
Figure 9 - Diagram of the over current sensing.
The critical inductor current can be calculated by setting:
Out-of-Phase Operation
VOCSET = IOCSET×RSET - RDS(ON)×IL = 0
The APU3146 drives its two output stages 180 out-ofRSET×IOCSET
phase. In 2-phase configuration, the two inductor ripple
ISET = IL(CRITICAL)=
---(3)
currents cancel each other and result in a reduction of
RDS(ON)
the output current ripple and yield a smaller output capacitor for the same ripple voltage requirement.
In single input voltage applications, the input ripple current reduces. This result in much smaller input capacitor's
RMS current and reduces the input capacitor quantity.
The value of RSET should be checked in an actual
circuit to ensure that the Over Current Protection
circuit activates as expected. The APU3146 current
limit is designed primarily as disaster preventing, "no
Over-Current Protection
blow up" circuit, and is not useful as a precision
The APU3146 can provide two different schemes for Overcurrent regulator.
Current Protection (OCP). When the pin Hiccup is pulled
high, the OCP will operate in hiccup mode. In this mode,
In two independent mode, the output of each channel
during overload or short circuit, the outputs enter hiccup
is protected independently which means if one output
mode and stay in that mode until the overload or short
is under overload or short circuit condition, the other
circuit is removed. The converter will automatically reoutput will remain functional. The OCP set limit can be
cover.
programmed to different levels by using the external
When the Hiccup pin is pulled low, the OCP scheme
resistors. This is valid for both hiccup mode and latch
will be changed to the latch up type, in this mode the
up mode.
converter will be turned off during Overcurrent or short
In 2-phase configuration, the OCP's output depends on
circuit. The power needs to be recycled for normal
any one channel, which means as soon as one
operation.
channel goes to overload or short circuit condition the
Each phase has its own independent OCP circuitry.
output will enter either hiccup or latch-up, dependes on
The OCP is performed by sensing current through the
status of Hiccup pin.
RDS(ON) of low side MOSFET. As shown in Figure 9, an
external resistor (RSET) is connected between OCSet pin
and the drain of low side MOSFET (Q2) which sets the
current limit set point.
If using one soft start capacitor in dual configuration for a
precise power up the OCP needs to be set to latch mode.
8/28
APU3146
Operation Frequency Selection
The optimum operating frequency range for APU3146 is
300KHz per phase, theoretically the APU3146 can be
operated at higher switching frequency (e.g. 500KHz).
However the power dissipation for IC, which is function
of applied voltage, gate drivers load and switching frequency, will result in higher junction temperature of device. It may exceed absolute maximum rating of junction temperature, figure 18 (page 16) shows case temperature versus switching frequency with different capacitive loads.
This should be considered when using APU3146 for such
application. The below equation shows the relationship
Thermal Shutdown
Temperature sensing is provided inside APU3146. The trip between IC's maximum power dissipation and Junction
threshold is typically set to 140 C. When trip threshold is temperature:
ΤJ-ΤA
exceeded, thermal shutdown turns off both FETs. TherPd =
θJA
mal shutdown is not latched and automatic restart is ini- Where:
tiated when the sensed temperature drops to normal Tj: Maximum Operating Junction Temperature (125°C)
range. There is a 20 C hysteresis in the shutdown thresh- TA: Ambient Temperature (70°C)
θJA = Thermal Impedance of package (84°C/W)
old.
For Tj=125°C TA=70°C and θJA=84°C/W
Power Good
This will result to power dissipation of 650mW, this inThe APU3146 provides a power good signal. The power
cludes biasing current for all four external MOSFETs
good signal should be available after both outputs have
and IC's biasing current.
reached regulation. This pin needs to be externally pulled
The switching frequency is determined by an external
high. High state indicates that outputs are in regulation.
resistor (Rt). The switching frequency is approximately
Power good will be low if either one of the output voltages
inversely proportioned to resistance (see Fig 10).
is 10% below the set value. There is only one power good
for both outputs.
Per channel Switching Frequency vs. RT
Frequency Synchronization
The APU3146 is capable of accepting an external digital
synchronization signal. Synchronization will be enabled
by the rising edge at an external clock. Per-channel switching frequency is set by external resistor (Rt). The free
running oscillator frequency is twice the per-channel frequency. During synchronization, Rt is selected such that
the free running frequency is 20% below the sync frequency. Synchronization capability is provided for both 2output and 2-phase configurations. When unused, the
Sync pin will remain floating and is noise immune.
700
650
Switching Frequency in KHz
Over-Voltage Protection OVP
Over-voltage is sensed through separate VOUT sense pins
Vsen1 and Vsen2. A separate OVP circuit is provided for
each output. Upon over-voltage condition of either one of
the outputs, the OVP forces a latched shutdown on both
outputs. In this mode, the upper FET drivers turn-off and
the lower FET drivers turn-on, thus crowbaring the outputs. Reset is performed by recycling either Vcc.
600
550
500
450
400
350
300
Error Amplifier
250
The APU3146 is a voltage mode controller. The error am200
plifiers are of transconductance type. In independent mode,
10
20
30
40
50
each amplifier closes the loop around its own output voltRT(Kohm)
age. In current sharing mode, amplifier 1 becomes the
Figure 10- Switching Frequency versus External Resistor.
master which regulates the common output voltage. AmShutdown
plifier 2 performs the current sharing function. Both amplifiers are capable of operating with Type III compensa- The outputs can be shutdown independently by pulling
the respective soft-start pins below 0.3V. This can be
tion control scheme.
easily done by using an external small signal transisLow Temperature Start-Up
tor. During shutdown both MOSFETs will be turned off.
The controller is capable of starting at -40 C ambient
During this mode the LDO will stay on. Cycling softtemperature.
start pins will clear all fault latches and normal operation will resume.
9/28
APU3146
APPLICATION INFORMATION
Soft-Start Programming
The soft-start timing can be programmed by selecting
Design Example:
The following example is a typical application for APU3146, the soft-start capacitance value. The start-up time of
the converter can be calculated by using:
the schematic is Figure18 on page17.
VIN = 12V
VOUT(2.5V) = 2.5V @ 10A
VOUT(1.8V) = 1.8V @ 10A
∆VOUT = Output voltage ripple ≅ 3% of VOUT
FS = 300KHz
Output Voltage Programming
Output voltage is programmed by reference voltage and
external voltage divider. The Fb1 pin is the inverting input
of the error amplifier, which is referenced to the voltage
on non-inverting pin of error amplifier. For this application, this pin (VP) is connected to reference voltage (VREF).
The output voltage is defined by using the following equation:
R6
VOUT = VP × 1 +
---(4)
R5
(
)
VP2 = VREF = 0.8V
When an external resistor divider is connected to the
output as shown in Figure 11.
VOUT
APU3146
VREF
R6
Fb
R5
VP
Figure 11 - Typical application of the APU3146 for
programming the output voltage.
Equation (4) can be rewritten as:
VOUT
R6 = R5 ×
-1
VP
(
Will result to:
VOUT(2.5V) = 2.5V
VREF = 0.8V
R9= 2.14K, R5= 1K
)
VOUT(1.8V) = 1.8V
VREF = 0.8
R7= 1.24K, R8 = 1K
If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage can be set more
accurately by using low value, precision resistors.
Css ≅ 25×tSTART (µF)
---(5)
Where tSTART is the desired start-up time (ms)
For a start-up time of 4ms for both output, the soft-start
capacitor will be 0.1µF. Connect ceramic capacitors at
0.1µF from SS1 pin and SS2 pin to GND.
Supply VCH1 and VCH2
To drive the high side switch, it is necessary to supply
a gate voltage at least 4V grater than the bus voltage.
This is achieved by using a charge pump configuration
as shown in Figure 12. This method is simple and inexpensive. The operation of the circuit is as follows: when
the lower MOSFET is turned on, the capacitor (C1)
charges up to VOUT3, through the diode (D1). The bus
voltage will be added to this voltage when upper
MOSFET turns on in next cycle, and providing supply
voltage (VCH1) through diode (D2). Vc is approximately:
VCH1 ≅ VOUT3 + VBUS - (VD1 + VD2)
Capacitors in the range of 0.1µF and 1µF are generally
adequate for most applications. The diode must be a
fast recovery device to minimize the amount of charge
fed back from the charge pump capacitor into VOUT3.
The diodes need to be able to block the full power rail
voltage, which is seen when the high side MOSFET is
switched on. For low voltage application, schottky diodes can be used to minimize forward drop across the
diodes at start up.
D1
C3
VOUT3
Regulator
D2
VCH1
VBUS
C2
C1
Q1
L2
APU3146
HDrv
Q2
Figure 12 - Charge pump circuit.
10/28
APU3146
Input Capacitor Selection
The 1800 out of phase will reduce the RMS value of the
ripple current seen by input capacitors. This reduces
numbers of input capacitors. The input capacitors must
be selected that can handle both the maximum ripple
RMS at highest ambient temperature as well as the
maximum input voltage. The RMS value of current ripple
for duty cycles under 50% is expressed by:
IRMS= (I D1(1-D1)+I D2(1-D2)-2I1I2D1D2) --- (6)
2
1
2
2
Where:
IRMS is the RMS value of the input capacitor current
D1 and D2 are the duty cycle for each output
I1 and I2 are the current for each output
For this application the IRMS =4.8A
For higher efficiency, low ESR capacitors is recommended.
Choose two Poscap from Sanyo 16TPB47M (16V, 47µF,
70mΩ ) with a maximum allowable ripple current of 1.4A
for inputs of each channel.
Inductor Selection
The inductor is selected based on operating frequency,
transient performance and allowable output voltage ripple.
Low inductor value results to faster response to step
load (high ∆i/∆t) and smaller size but will cause larger
output ripple due to increase of inductor ripple current.
As a rule of thumb, select an inductor that produces a
ripple current of 10-40% of full load DC.
For the buck converter, the inductor value for desired
operating ripple current can be determined using the following relation:
∆i
VOUT
1
; ∆t = D×
;D=
∆t
VIN
fS
VOUT
L = (VIN - VOUT)×
---(7)
VIN×∆i×fS
Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage
∆i = Inductor Ripple Current
fS = Switching Frequency
∆t = Turn On Time
D = Duty Cycle
VIN - VOUT = L×
For ∆i(2.5V) = 38%(IO(2.5V) ), then the output inductor will
be:
For ∆i(1.8V) = 30%(IO(1.8V) ), then the output inductor will
be:
L3 = 1.7µH
Panasonic provides a range of inductors in different values and low profile for large currents.
Choose ETQP6F1R8BFA (1.71µH, 14A, 3.3mΩ) both
for L3 and L4.
For 2-phase application, equation (7) can be used for
calculating the inductors value. In such case the inductor ripple current is usually chosen to be between 1040% of maximum phase current.
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy stability requirements. The ESR of the output capacitor is
calculated by the following relationship:
(ESL, Equivalent Series Inductance is neglected)
∆VO
ESR ≤
---(8)
∆IO
Where:
∆VO = Output Voltage Ripple
∆i = Inductor Ripple Current
∆VO = 3% of VO will result to ESR(2.5V) =19.7mΩ and
ESR(1.8V) =16mΩ
The Sanyo TPC series, Poscap capacitor is a good choice.
The 6TPC330M, 330µF, 6.3V has an ESR 40mΩ. Selecting two of these capacitors in parallel for 2.5V output, results to an ESR of ≅ 20mΩ which achieves our
low ESR goal. And selecting four of these capacitors in
parallel for 1.8V output, results to an ESR of ≅ 10mΩ
which achieves our low ESR goal.
The capacitors value must be high enough to absorb the
inductor's ripple current.
Power MOSFET Selection
The APU3146 uses four N-Channel MOSFETs. The selections criteria to meet power transfer requirements is
based on maximum drain-source voltage (VDSS), gatesource drive voltage (VGS), maximum output current, Onresistance RDS(ON) and thermal management.
The both control and synchronous MOSFETs must have
a maximum operating voltage (VDSS) that exceeds the
maximum input voltage (VIN).
L4 = 1.71µH
11/28
APU3146
The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET,
which results a in shoot-through.
The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter,
the average inductor current is equal to the DC
load current. The conduction loss is defined as:
2
VDS(OFF) tr + tf
---(9)
×
× ILOAD
T
2
Where:
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
T = Switching Period
ILOAD = Load Current
PSW =
VDS
90%
PCOND(Upper Switch) = ILOAD×RDS(ON)×D×ϑ
2
PCOND(Lower Switch) = ILOAD×RDS(ON)×(1 - D)×ϑ
ϑ = RDS(ON) Temperature Dependency
The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
Choose IRF7457 both for control and synchronous
MOSFET. This device provide low on-resistance in a compact SOIC 8-Pin package.
The MOSFET have the following data:
IRF7457
VDSS = 20V
ID = 15A
RDS(ON) = 7mΩ
The total conduction losses for each output will be:
PCON(TOTAL, 2.5V) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL, 2.5V) = 1.0W
PCON(TOTAL, 1.8V) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL, 1.8V) = 1.0W
The switching loss is more difficult to calculate, even
though the switching transition is well understood. The
reason is the effect of the parasitic components and
switching times during the switching procedures such
as turn-on / turnoff delays and rise and fall times. The
control MOSFET contributes to the majority of the switching losses in a synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the switching losses for synchronous
MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as:
10%
VGS
td(ON)
tr
td(OFF)
tf
Figure 13 - Switching time waveforms.
From IRF7457 data sheet we obtain:
IRF7457
tr = 16ns
tf = 7ns
These values are taken under a certain condition test.
For more details please refer to the IRF7457 data sheet.
By using equation (9), we can calculate the total switching losses.
PSW(TOTAL,2.5V) = 0.414W
PSW(TOTAL,1.8V) = 0.414W
Programming the Over-Current Limit
The over-current threshold can be set by connecting a
resistor (RSET) from drain of low side MOSFET to the
OCSet pin. The resistor can be calculated by using equation (3).
The RDS(ON) has a positive temperature coefficient and it
should be considered for the worse case operation.
RDS(ON) = 7mΩ×1.5 = 10.5mΩ
ISET ≅ IO(LIM) = 10A×1.5 = 15A
(50% over nominal output current)
This results to:
RSET = R1=R6=7.8KΩ
12/28
APU3146
Feedback Compensation
The APU3146 is a voltage mode controller; the control The ESR zero of the output capacitor is expressed as
loop is a single voltage feedback path including error follows:
amplifier and error comparator. To achieve fast transient
1
response and accurate output regulation, a compensaFESR =
---(10A)
2π×ESR×Co
tion circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
VOUT
the highest 0dB crossing frequency and adequate phase
margin (greater than 45 ).
R6 Fb
Comp
The output LC filter introduces a double pole, –40dB/
Ve
E/A
decade gain slope above its corner resonant frequency,
R5
C9
and a total phase lag of 180 (see Figure 14). The ResoVp=VREF
nant frequency of the LC filter is expressed as follows:
R4
1
Gain(dB)
FLC =
---(10)
2π× LO×CO
H(s) dB
Where: Lo is the output inductor
For 2-phase application, the effective output
inductance should be used
FZ Frequency
Co is the total output capacitor
Figure 15 - Compensation network without local
feedback and its asymptotic gain plot.
Figure 14 shows gain and phase of the LC filter. Since
we already have 180 phase shift just from the output
The transfer function (Ve / VOUT) is given by:
Gain
Phase
(
0
0dB
H(s) = gm×
-40dB/decade
FLC Frequency
-180
FLC
Figure14 - gain and phase of LC filter
Frequency
)
R5
1 + sR4C9
×
R6 + R5
sC9
---(11)
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:
R5
|H(s=j×2π×FO)| = gm×
×R4
---(12)
The APU3146’s error amplifier is a differential-input
R6+R5
transconductance amplifier. The output is available for
1
DC gain control or AC phase compensation.
FZ =
---(13)
2π×R
4×C9
The E/A can be compensated with or without the use of
local feedback. When operated without local feedback,
the transconductance properties of the E/A become evi- |H(s)| is the gain at zero cross frequency.
dent and can be used to cancel one of the output filter First select the desired zero-crossover frequency (F ):
O1
poles. This will be accomplished with a series RC circuit
from Comp pin to ground as shown in Figure 15.
FO1 > FESR and FO1 ≤ (1/5 ~ 1/10)×fS
Note that this method requires the output capacitor to
have enough ESR to satisfy stability requirements. In
general, the output capacitor’s ESR generates a zero
typically at 5KHz to 50KHz which is essential for an
acceptable phase margin.
13/28
APU3146
R4 = VOSC ×
VIN
1
FO1×FESR R5 + R6
×
×
gm
FLC2
R5
---(14)
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
FO1 = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R6 = Resistor Dividers for Output Voltage
Programming
gm = Error Amplifier Transconductance
For V2.5V:
VIN = 12V
VOSC = 1.25V
FO1 = 30KHz
FESR = 12KHz
For a general solution for unconditional stability for ceramic output capacitor with very low ESR or any type of
output capacitors, in a wide range of ESR values we
should implement local feedback with a compensation
network. The typically used compensation network for a
voltage-mode controller is shown in Figure 16.
To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole:
FZ ≅ 75%FLC
1
FZ ≅ 0.75×
---(15)
2π LO × CO
For:
Lo = 1.71µH
FZ = 3.56KHz
Co = 660µF
R4 = 2.61K
Using equations (13) and (15) to calculate C9, we get:
C9 ≅ 17.18nF; Choose C9 =18nF
C12
C10
R7
R8
C11
R6
Zf
Fb
FLC = 4.75KHz
R5 = 1K
R6 = 2.14K
gm = 2000µmho
This results to R4=2.61K
Choose R4=2.61K
VOUT
ZIN
E/A
R5
Comp
Ve
Vp=VREF
Gain(dB)
H(s) dB
FZ1
FZ2
FP2
FP3
Frequency
Figure 16- Compensation network with local
feedback and its asymptotic gain plot.
In such configuration, the transfer function is given by:
Ve
1 - gmZf
=
VOUT 1 + gmZIN
The error amplifier gain is independent of the transconductance under the following condition:
gmZf >> 1
and
gmZIN >>1
---(16)
Same calcuation For V1.8V will result to: R3 = 2.8K and
C8 = 22nF
By replacing ZIN and Zf according to Figure 16, the transformer function can be expressed as:
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to suppress the switching noise. The additional
pole is given by:
1
FP =
C9×CPOLE
2π×R4×
C9 + CPOLE
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
1
1
CPOLE =
≅
π×R4×fS
1
π×R4×fS C9
fS
for FP <<
2
H(s) =
(1+sR7C11)×[1+sC10(R6+R8)]
1
×
sR6(C12+C11)
C12C11
1+sR7 C12+C11 ×(1+sR8C10)
[
(
)]
As known, transconductance amplifier has high impedance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the
necessary range.
The compensation network has three poles and two zeros and they are expressed as follows:
14/28
APU3146
FP1 = 0
FP2 =
FP3 =
FZ1 =
1
2π×R8×C10
1
(
)
C12×C11
2π×R7×
C12+C11
≅
1
2π×R7×C12
1
2π×R7×C11
1
1
FZ2 = 2π×C10×(R6 + R8) ≅
2π×C10×R6
Cross Over Frequency:
VIN
1
FO = R7×C10×
×
VOSC 2π×Lo×Co
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors
---(17)
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (16) regarding transconductance error amplifier.
These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load transient response. The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greater than 45 for overall
stability.
Based on the frequency of the zero generated by ESR
versus crossover frequency, the compensation type can
be different. The table below shows the compensation
type and location of crossover frequency.
Compensator
Location of Zero
Typical
Type
Crossover Frequency
Output
(FO)
Capacitor
Type II (PI)
FPO < FZO < FO < fS/2
Electrolytic,
Tantalum
Type III (PID)
FPO < FO < FZO < fS/2
Tantalum,
Method A
Ceramic
Type III (PID)
FPO < FO < fS/2 < FZO
Ceramic
Method B
Table - The compensation type and location of zero
crossover frequency.
Details are dicussed in application Note AN-1043 which
can be downloaded from the IR Web-Site.
Compensation for Slave Error Amplfier for 2-Phase
Configuration
The slave error amplifier is a differential-input transconductance amplifier, in 2-phase configuration the main goal
for the slave feed back loop is to control the inductor
current to match the masters inductor current as well
provides highest bandwidth and adequate phase margin
for overall stability. The following analysis is valid for both
using external current sense resistor and using DCR of
inductors.
The transfer function of power stage is expressed by:
IL2(s)
VIN - VOUT
=
Ve(s)
sL2 × VOSC
Where:
VIN = Input Voltage
VOUT = Output Voltage
L2 = Output Inductor
VOSC = Oscillator Peak Voltage
G(s) =
---(18)
As shown the transfer function is a function of inductor
current.
The transfer function for the compensation network is
given by equation (19), when using a series RC circuit
as shown in Figure 17:
D(s) =
Ve(s)
=
RS2 × IL2(s)
(g × RR )×(1 +sCsC R ) ---(19)
m
S1
2
S2
2
2
IL2
L2
Fb2
RS2
Vp2
Comp2
E/A2
Ve
R2
RS1
C2
L1
IL1
Figure 17 - The PI compensation network
for slave channel.
The loop gain function is:
H(s)=[G(s) × D(s) × RS2]
C × V -V
(g × RR )×(1+sR
sC ) (sL ×V )
H(s)=RS2×
m
S1
2
S2
2
2
IN
2
OUT
OSC
15/28
APU3146
Select a zero crossover frequency for control loop (FO2)
1.25 times larger than zero crossover frequency for voltage loop (FO1):
Fo2 ≅ 1.25%xF01
H(Fo) =
gm×RS1×R2×
VIN - VOUT
=1
2π×Fo×L2×VOSC
---(20)
From (20), R2 can be express as:
R2 =
1
gm × RS1
× 2π × FO2 × L2 × VOSC
VIN - VOUT
---(21)
Set the zero of compensator to be half of FLC(SLAVE), the
compensator capacitor, C2, can be calculated as:
FLC(SLAVE) =
2π
1
L2×COUT
Fz =
FLC(SLAVE)
2
C2 =
1
2π × R2 × Fz
---(22)
When using the DCR of inductors as current sense element, replace RS1 in equation (21) with DCR value of inductor.
Layout Consideration
The layout is very important when designing high frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start by placing the power components. Make all the
connections in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET
should be as close to each other as possible. This helps
to reduce the EMI radiated by the power traces due to
the high switching. Place input capacitor near to the
drain of the high-side MOSFET.
The layout of driver section should be designed for a low
resistance (a wide, short trace) and low inductance (a
wide trace with ground return path directly beneath it),
this directly affects the driver's performance.
To reduce the ESR, replace the one input capacitor with
two parallel ones. The feedback part of the system should
be kept away from the inductor and other noise sources
and must be placed close to the IC. In multilayer PCB's,
use one layer as power ground plane and have a separate control circuit ground (analog ground), to which all
signals are referenced. The goal is to localize the high
current paths to a separate loops that does not interfere
with the more sensitive analog control function. These
two grounds must be connected together on the PC board
layout at a single point.
Switching Frequency vs. Case Temp
Case temp (oC)
90
80
100pF
70
1000pF
60
1800pF
50
3300pF
40
30
200
300
400
500
600
700
Freq (KHz)
Figure18- Case Temperature versus Switching Frequency at Room Temperature
Test Condition: Vin=Vcl=Vch1=Vch2=12V, Capacitors used as loads for output
drivers.
16/28
APU3146
C12
1uF
L1
12V
C1
47uF
1uH
C2
47uF
D1
BAT54S
C3
1uF
C4
1uF
C5
1uF
VCL
VcH1 VOUT3 VcH2
Vcc
HDrv1
OCSet1
Hiccup
VREF
Rt
33K
R3
C8
20nF 2.8K
R4
C9
18nF 2.61K
U1
APU3146 VSEN1
Comp1
Comp2
PGood
C10
0.1uF
SS1 / SD
C15
0.1uF
7.8K
HDrv2
SS2 / SD
LDrv2
C14
2x 47uF
16TPB47M
Q2
IRF7457
L3
VSEN1
R6
7.8K
1.8V @ 10A
1.7uH
Q3
IRF7457
VSEN1
D2
BAT54A
VSEN2 VSEN2
Fb1
Fb2
OCSet2
PGood
R1
PGnd1
Sync
VP2
R2
LDrv1
C13
1uF
C11
0.1uF
C16
4x 330uF, 40mΩ
6TPB330M
R20
1.24K
R21
1K
R7
1.24K
R8
C17
2x 47uF
16TPB47M
Q4
L4
IRF7457
Q5
IRF7457
PGnd2
Gnd
VSEN2
1.7uH
R22
2.24K
R5
1K
1K
R9
2.14K
2.5V @ 10A
C18
2x 330uF, 40mΩ
6TPB330M
R23
1K
Figure 19 - Typical application of APU3146.
12V input and two independent outputs.
17/28
APU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 20 - Input Supply Ramps up.
Ch1: 1.8V, Ch2: 2.5V, Ch3: Input Supply
Figure 21 - Input Supply Ramps up/down.
Ch1: 1.8V, Ch2: 2.5V, Ch3: Input Supply
Figure 22 - Normal condition at No Load.
Ch1: HDrv2, Ch2: HDrv1, Ch3 and Ch4: Inductor
Currents
Figure 23 - Normal condition at 10A Load.
Ch1: HDrv2, Ch2: HDrv1, Ch3 and Ch4: Inductor
Currents
Ch3:ch4: 5A/div
Ch3:ch4: 5A/div
18/28
APU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 24 - Soft_Start.
Ch1: SS2, Ch2: 1.8V, Ch3: SS1, Ch4: 2.5V
Figure 26 - Deadband Time (1.8V Output).
Ch1: LDrv2, Ch2: HDrv2, Ch3: Switching Node
Figure 25 - Soft_Start.
Ch1: Vin, Ch2: Vout3(LDO), Ch3: SS2, Ch4: SS2
Figure 27 - Deadband Time (2.5V Output).
Ch1: LDrv1, Ch2: HDrv1, Ch3: Switching Node
19/28
APU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 28 - Shut Down (Pulling down the SS1 pin).
Ch1: HDrv1, Ch2: LDrv1, Ch3: SS1
Figure 30 - High side and Low side Drivers peak
Current for 1.8V Output
Ch1: HDrv2, Ch2: LDrv2, Ch3: High Side Peak
Current, Ch4: Low Side Peak Current
Ch3:ch4: 1A/div
Figure 29 - Shut Down (pulling down the SS2 pin).
Ch1: HDrv2, Ch2: LDrv2, Ch3: SS2
Figure 31 - High side and Low side Drivers peak
Current for 2.5V Output
Ch1: HDrv1, Ch2: LDrv1, Ch3: High Side Peak
Current, Ch4: Low Side Peak Current
Ch3:ch4: 1A/div
20/28
APU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 32 - Load Transient Response.
Ch2: 2.5V, Ch4: Step Load (0-10A)
Figure 33 - Load Transient Response.
Ch1: 1.8V, Ch3: Step Load (0-10A)
Ch3:ch4: 5A/div
Ch3:ch4: 5A/div
Figure 34 - Power Good Signal
Ch1: Input Supply, Ch2: 2.5V Output, Ch3: 1.8V
Output, Ch4 : Power Good Signal
Figure 35 - Short Circuit Condition (Hiccup Mode).
Ch1: SS1 pin, Ch2: SS2 pin, Ch3 and Ch4 : Inductor
Currents
Ch3:ch4: 10A/div
21/28
APU3146
TYPICAL APPLICATION
L1
12V
C1
47uF
1uH
C2
47uF
D1
BAT54S
C12
1uF
C11
0.1uF
C3
1uF
C4
1uF
C5
1uF
VCL
VcH1 VOUT3 VcH2
Vcc
HDrv1
OCSet1
Hiccup
VREF
Rt
33K
R3
C8
22nF 2.2K
C6 120pF
R4
C9
12nF 8K
U1
APU3146 VSEN1
Comp1
Comp2
PGood
C10
0.1uF
VSEN2
Fb1
Fb2
12K
SS1 / SD
SS2 / SD
C14
3x 47uF
Q2
IRFR3706
L3
1uH, 2mΩ DCR
Q3
IRFR3711
R5
HDrv2
LDrv2
1.8V @ 30A
1K
D2
BAT54A
VSEN
R21
1K
VSEN
C17
3x 47uF
OCSet2
C7 82pF
PGood
R1
PGnd1
VP2
Sync
R2
LDrv1
C13
1uF
R6
12K
Q4
IRFR3706
Q5
IRFR3711
C15
1uF
R20
1.24K
R7
1.24K
R8
1K
R9
1K
L4
C16
8x 330uF, 40mΩ
6TPB330M
C18
1uF
1uH, 2mΩ DCR
PGnd2
Gnd
Figure 36 - 2-phase operation with inductor current sensing.
12V to 1.8V @ 30A output
22/28
APU3146
TYPICAL APPLICATION
L1
12V
C1
47uF
1uH
C2
47uF
D1
BAT54S
C12
1uF
C11
0.1uF
C3
1uF
C4
1uF
C5
1uF
VCL
VcH1 VOUT3 VcH2
Vcc
HDrv1
OCSet1
Hiccup
VREF
33K
R3
C8
22nF 2.2K
C6 120pF
R4
C9
12nF 8K
Rt
U1
APU3146 VSEN1
Comp1
Comp2
PGood
C10
0.1uF
VSEN2
Fb1
Fb2
12K
SS1 / SD
SS2 / SD
C14
3x 47uF
Q2
IRFR3706
Q3
IRFR3711
L3
R5
1uH
D2
BAT54A
HDrv2
LDrv2
12K
Q4
IRFR3706
Q5
IRFR3711
C16
8x 330uF, 40mΩ
6TPB330M
R20
1.24K
VSEN
R21
1K
VSEN
R6
1.8V @ 30A
2mΩ
R7
1.24K
R8
1K
C17
3x 47uF
OCSet2
C7 82pF
PGood
R1
PGnd1
VP2
Sync
R2
LDrv1
C13
1uF
L4
1uH
R9
2mΩ
PGnd2
Gnd
Figure 37 - 2-phase operation with resistor current sensing.
12V to 1.8V @ 30A output
23/28
APU3146
TYPICAL APPLICATION
L2
5V
1uH
C18
150uF
C17
3x 150uF
C19
0.1uF
D3
BAT54S
C20
1uF
12V
C1
47uF
C13
1uF
L1
1uH
C2
47uF
C3
1uF
C4
1uF
C5
1uF
HDrv1
Vcc
OCSet1
Hiccup
Rt
R3
C8
22nF 2.2K
C6 120pF
R4
C9
4.7nF 23K
Comp1
Comp2
SS1 / SD
SS2 / SD
Q2
IRFR3706
L3
Q3
IRFR3711 R5
1K
HDrv2
LDrv2
PGnd2
Gnd
1.8V @ 30A
1uH,
2mΩ DCR
D2
BAT54A
C21
1uF
C16
8x 330uF, 40mΩ
6TPB330M
R20
1.24K
R21
1K
VSEN2
Fb1
Fb2
OCSet2
PGood
C10
0.1uF
12K
U1
APU3146 VSEN1
C7 27pF
PGood
R1
PGnd1
VP2
VREF
33K
LDrv1
C11
0.1uF
C14
3x 47uF
VCL VcH1 VOUT3 VcH2
Sync
R2
D1
BAT54S
C12
1uF
Q4
IRFR3706
R6
12K
Q5
IRFR3711
R9
1K
C22
1uF
R7
1.24K
R8
1K
L4
1uH,
2mΩ DCR
Figure 38 - Typical application of APU3146 using 5V and 12V supplies to generate single output voltage.
1.8V @ 30A using inductor sensing.
24/28
APU3146
TYPICAL APPLICATION
L2
1uH
5V
C18
150uF
C17
3x 150uF
D3
BAT54S
C20
1uF
12V
C1
47uF
C19
0.1uF
C13
1uF
L1
1uH
C2
47uF
C3
1uF
C4
1uF
C5
1uF
HDrv1
Vcc
OCSet1
Hiccup
R3
C8
22nF 2.2K
C6 120pF
R4
C9
4.7nF 23K
Rt
Comp1
Comp2
SS1 / SD
SS2 / SD
Q2
IRFR3706
Q3
IRFR3711
C11
0.1uF
L3
1uH
R5
1.8V @ 30A
2mΩ
HDrv2
LDrv2
C16
8x 330uF, 40mΩ
6TPB330M
R20
1.24K
D2
BAT54A
R21
1K
VSEN2
Fb1
Fb2
OCSet2
PGood
C10
0.1uF
15K
U1
APU3146 VSEN1
C7 27pF
PGood
LDrv1
R1
PGnd1
VP2
VREF
33K
C14
3x 47uF
VCL VcH1 VOUT3 VcH2
Sync
R2
D1
BAT54S
C12
1uF
R7
1.24K
R8
1K
R6
10K
Q4
IRFR3706
Q5
IRFR3711
L4
R9
1uH
3mΩ
PGnd2
Gnd
Figure 39 - Typical application of APU3146.
1.8V @ 30A output with 5V and 12V input and different input current setting.
(5V @ 5A and 12V @ 3A)
25/28
APU3146
TYPICAL APPLICATION
L1
5V
C1
47uF
1uH
C2
47uF
D1
BAT54S
C12
1uF
C3
1uF
C4
1uF
C5
1uF
VCL
VcH1 VOUT3
HDrv1
Vcc
OCSet1
Hiccup
VREF
Rt
33K
R3
C8
8.2nF 6K
C6
47pF
R4
C9
4.7nF 15K
C7
Comp1
Comp2
SS1 / SD
C15
0.1uF
10K
HDrv2
SS2 / SD
LDrv2
C14
3x 330uF
6TPB330M
Q2
IRF7457
L3
1.8V @ 10A
1uH
Q3
IRF7460
C16
4x 330uF, 40mΩ
6TPB330M
R20
1.24K
VSEN1
D2
BAT54A
VSEN2
Fb1
Fb2
OCSet2
PGood
C10
0.1uF
R1
U1
APU3146 VSEN1
27pF
PGood
LDrv1
C13
1uF
PGnd1
Sync
VP2
R2
VcH2
C11
0.1uF
R21
1K
R7
1.24K
R8
R6
8.5K
R5
C17
3x 330uF
6TPB330M
Q4
1/2 IRF7910 L4
Q5
1/2 IRF7910
1K
R9
2.14K
3.3uH
PGnd2
Gnd
1K
2.5V @ 5A
C18
2x 330uF, 40mΩ
6TPB330M
R22
2.14K
VSEN2
R23
1K
Figure 40 - Single 5V input and two independent outputs.
26/28
APU3146
TYPICAL APPLICATION
12V
5V
C1
47uF
L1
1uH
C2
47uF
C3
1uF
C4
1uF
VCL
VcH1 VOUT3
C5
1uF
OCSet1
Hiccup
Rt
33K
R3
C8
8.2nF 6K
4.7nF 15K
Comp2
PGood
SS1 / SD
C15
0.1uF
VSEN2
Fb1
Fb2
HDrv2
OCSet2
C7 27pF
C10
0.1uF
Q2
IRF7457
L3
SS2 / SD
LDrv2
1.8V @ 10A
1uH
Q3
IRF7460
D2
BAT54A
U1
APU3146 VSEN1
Comp1
C6 47pF
R4
C9
10K
Sync
VREF
R2
LDrv1
R1
C14
3x 330uF
6TPB330M
C16
4x 330uF, 40mΩ
6TPB330M
R20
1.24K
PGnd1
VP2
PGood
VcH2
HDrv1
Vcc
C13
1uF
VSEN1
R21
1K
R7
1.24K
R8
C17
3x 330uF
6TPB330M
R6
5.1K
Q4
IRF7457
Q5
IRF7460
PGnd2
Gnd
L4
3.3uH
R22
2.14K
R5
1K
1K
R9
2.14K
2.5V @ 5A
C18
2x 330uF, 40mΩ
6TPB330M
VSEN2
R23
1K
Figure 41 - Typical application of APU3146.
5V input, 12V drive and two independent outputs.
27/28
APU3146
TYPICAL APPLICATION
3.3V
L1
5V
C1
47uF
1uH
C2
47uF
C3
1uF
C4
1uF
C5
1uF
VCL
VcH1 VOUT3
VcH2
HDrv1
Vcc
OCSet1
LDrv1
Hiccup
VREF
R2
R3
C8
4.7nF 15K
C6 27pF
R4
C9
5.6nF 8.2K
C7
U1
Rt
33K
APU3146
Comp1
Comp2
PGood
SS1 / SD
C15
0.1uF
R1
8.5K
SS2 / SD
C11
0.1uF
C14
2x 330uF
6TPB330M
Q2
1/2 IRF7910
L3
LDrv2
C16
2x 330uF, 40mΩ
6TPB330M
R20
2.14K
VSEN1
R21
1K
Fb1
Fb2
HDrv2
2.5V @ 5A
3.3uH
Q3
1/2 IRF7910
D2
BAT54A
VSEN1
VSEN2
OCSet2
27pF
PGood
C13
1uF
PGnd1
Sync
VP2
C10
0.1uF
D1
BAT54S
C12
1uF
R7
2.14K
R8
1K
R6
8.5K
C17
2x 330uF
Q4 6TPB330M
L4
1/2 IRF7910
Q5
1/2 IRF7910
PGnd2
Gnd
R5
R9
1.24K
2.2uH
1K
1.8V @ 5A
C18
2x 330uF, 40mΩ
6TPB330M
R22
1.24K
VSEN2
R23
1K
Figure 42 - Typical application of APU3146.
5V to 2.5V and 3.3V to 1.8V inputs and two independent outputs.
28/28