MOTOROLA MC74HC163AD

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC54/74HC161A and HCI63A are identical in pinout to the LS161
and LS163. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC161A and HC163A are programmable 4–bit binary counters with
asynchronous and synchronous reset, respectively.
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
•
•
•
•
•
•
1
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 192 FETs or 48 Equivalent Gates
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
LOGIC DIAGRAM
ORDERING INFORMATION
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK
3
14
4
13
5
12
6
11
2
15
RESET
LOAD
ENABLE P
ENABLE T
Q0
Q1
Q2
BCD OR
BINARY
OUTPUT
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
Q3
RIPPLE
CARRY
OUT
RESET
1
16
CLOCK
2
15
P0
3
14
VCC
RIPPLE
CARRY OUT
Q0
1
P1
4
13
Q1
9
P2
5
12
Q2
7
P3
6
11
Q3
ENABLE P
7
10
ENABLE T
GND
8
9
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COUNT
ENABLES
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
10
Device
Count
Mode
Reset Mode
HC161A
Binary
Asynchronous
HC163A
Binary
Synchronous
PIN 16 = VCC
PIN 8 = GND
LOAD
FUNCTION TABLE
Inputs
Clock
Output
Reset*
Load
Enable P
Enable T
Q
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Reset
Load Preset Data
Count
No Count
No Count
* HC163A only. HC161A is an Asynchronous Reset Device
H = high level
L = low level
X = don’t care
10/95
 Motorola, Inc. 1995
3–1
REV 6
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MC54/74HC161A MC54/74HC163A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.50
1.35
1.80
0.50
1.35
1.80
0.50
1.35
1.80
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
2.0
4.5
6.0
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
V
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
V
6.0
± 0.1
± 1.0
± 1.0
µA
6.0
4
40
160
µA
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
ICC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
4.0 mA
5.2 mA
Vin = VCC or GND
Vin = VCC or GND
Iout = 0 µA
4.0 mA
5.2 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
3–2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC161A MC54/74HC163A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)*
1, 7
2.0
4.5
6.0
6
30
35
5
24
28
4
20
24
MHz
tPLH
Maximum Propagation Delay, Clock to Q
1, 7
2.0
4.5
6.0
120
20
16
160
23
20
200
28
22
ns
1, 7
2.0
4.5
6.0
145
22
18
185
25
20
320
30
23
ns
Symbol
Parameter
Fig.
tPHL
tPHL
Maximum Propagation Delay, Reset to Q (HC161A Only)
2, 7
2.0
4.5
6.0
145
20
17
185
22
19
220
25
21
ns
tPLH
Maximum Propagation Delay, Enable T to Ripple Carry Out
3, 7
2.0
4.5
6.0
110
16
14
150
18
15
190
20
17
ns
3, 7
2.0
4.5
6.0
135
18
15
175
20
16
210
22
20
ns
1, 7
2.0
4.5
6.0
120
22
18
160
27
22
200
30
25
ns
1, 7
2.0
4.5
6.0
145
22
20
185
28
24
220
35
28
ns
tPHL
tPLH
Maximum Propagation Delay, Clock to Ripple Carry Out
tPHL
tPHL
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC161A Only)
2, 7
2.0
4.5
6.0
155
22
18
190
26
22
230
30
25
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
2, 7
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
1, 7
—
10
10
10
pF
Cin
* Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable. See
Applications information in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Gate)*
30
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC161A MC54/74HC163A
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tsu
Minimum Setup Time,
Preset Data Inputs to Clock
5
2.0
4.5
6.0
40
15
12
60
20
18
80
30
20
ns
tsu
Minimum Setup Time,
Load to Clock
5
2.0
4.5
6.0
60
15
12
75
20
18
90
30
20
ns
tsu
Minimum Setup Time,
Reset to Clock (HC163A Only)
4
2.0
4.5
6.0
60
20
17
75
25
23
90
35
25
ns
tsu
Minimum Setup Time,
Enable T or Enable P to Clock
6
2.0
4.5
6.0
80
20
17
95
25
23
110
35
25
ns
th
Minimum Hold Time,
Clock to Load or Preset Data Inputs
5
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time,
Clock to Reset (HC163A Only)
4
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time,
Clock to Enable T or Enable P
6
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time,
Reset Inactive to Clock (HC161A Only)
2
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
trec
Minimum Recovery Time,
Load Inactive to Clock
5
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
tw
Minimum Pulse Width,
Clock
1
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
Minimum Pulse Width,
Reset (HC161A Only)
2
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
tr, tf
Parameter
Fig.
Maximum Input Rise and Fall Times
MOTOROLA
3–4
Unit
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC161A MC54/74HC163A
FUNCTION DESCRIPTION
The HC161A/163A are programmable 4–bit synchronous
counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading and count–
enable controls.
The HC161A and HC163A are binary counters with
asynchronous Reset and synchronous Reset, respectively.
CONTROL FUNCTIONS
INPUTS
Loading
Clock (Pin 2)
With the rising edge of the Clock, a low level on Load (Pin
9) loads the data from the Preset Data input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load is
low.
Resetting
A low level on the Reset pin (Pin 1) resets the internal flip–
flops and sets the outputs (Q0 through Q3) to a low level.
The HC161A resets asynchronously, and the HC163A resets
with the rising edge of the Clock input (synchronous reset).
The internal flip–flops toggle and the output count advances with the rising edge of the Clock input. In addition,
control functions, such as resetting and loading occur with
the rising edge of the Clock input.
Count Enable/Disable
These devices have two count–enable control pins: Enable P (Pin 7) and Enable T (Pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the internal flip–flops and appear at the counter outputs. P0 (Pin 3)
is the least–significant bit and P3 (Pin 6) is the most–significant bit.
Count Enable = Enable P • Enable T • Load
The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count–
enable control: Enable T is both a count–enable and a
Ripple–Carry Output control.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
Table 1. Count Enable/Disable
These are the counter outputs. Q0 (Pin 14) is the least–
significant bit and Q3 (Pin 11) is the most–significant bit.
Control Inputs
Result at Outputs
Load
Enable P
Enable T
Q0 – Q3
Ripple Carry Out
Ripple Carry Out (Pin 15)
H
H
H
Count
When the counter is in its maximum state 1111, this output
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count
state. The logic equation for this output is:
L
H
H
No Count
High when Q0–Q3
are maximum*
X
L
H
No Count
High when Q0–Q3
are maximum*
X
X
L
No Count
L
Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3
* Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.
OUTPUT STATE DIAGRAMS
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
Binary Counters
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
MC54/74HC161A MC54/74HC163A
SWITCHING WAVEFORMS
tr
tf
CLOCK
tw
VCC
90%
50%
10%
VCC
GND
GND
tPHL
tw
1/fmax
tPLH
tPHL
50%
ANY
OUTPUT
90%
50%
10%
ANY
OUTPUT
50%
RESET
trec
VCC
tTLH
50%
CLOCK
tTHL
GND
Figure 1.
tr
Figure 2.
tf
VCC
90%
50%
10%
ENABLE T
GND
tPLH
th
tsu
tPHL
90%
50%
10%
RIPPLE
CARRY
OUT
50%
RESET
VCC
50%
CLOCK
tTLH
GND
tTHL
Figure 3.
Figure 4. HC163A Only
VALID
INPUTS
P0, P1,
P2, P3
VCC
50%
GND
tsu
th
VALID
VCC
LOAD
ENABLE T
OR
ENABLE P
50%
GND
tsu
CLOCK
th
VCC
50%
GND
tsu
trec
th
VCC
VCC
CLOCK
50%
50%
GND
GND
Figure 5.
Figure 6.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 7.
MOTOROLA
3–6
High–Speed CMOS Logic Data
DL129 — Rev 6
High–Speed CMOS Logic Data
DL129 — Rev 6
3
3–7
CLOCK
LOAD
RESET
ENABLE T
ENABLE P
P3
P2
2
9
1
10
7
6
5
P1 4
P0
C
C
LOAD
LOAD
R
Q3
Q2
Q2
Q1
Q1
Q0
Q0
VCC = PIN 16
GND = PIN 8
Q3
Q2
Q1
Q0
15 RIPPLE
CARRY
OUT
11
12
13
14
The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–
Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip–flop low.
T3
R
C
C
LOAD
LOAD
P3
T2
R
C
C
LOAD
LOAD
P2
T1
R
C
C
LOAD
LOAD
P1
T0
R
C
C
LOAD
LOAD
P0
MC54/74HC161A MC54/74HC163A
Figure 8. 4–Bit Binary Counter with Asynchronous Reset
(MC54/74HC161A)
MOTOROLA
MC54/74HC161A MC54/74HC163A
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit.
RESET (HC161A)
(ASYNCHRONOUS)
RESET (HC163A)
(SYNCHRONOUS)
LOAD
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK (HC161A)
CLOCK (HC163A)
COUNT
ENABLES
ENABLE P
ENABLE T
Q0
Q1
OUTPUTS
Q2
Q3
RIPPLE
CARRY
OUT
12
13 14
15
0
1
COUNT
RESET
2
INHIBIT
LOAD
Figure 9. Timing Diagram
MOTOROLA
3–8
High–Speed CMOS Logic Data
DL129 — Rev 6
High–Speed CMOS Logic Data
DL129 — Rev 6
3–9
CLOCK
LOAD
RESET
ENABLE T
ENABLE P
P3
P2
P1
P0
2
9
1
10
7
6
5
4
3
C
C
LOAD
LOAD
R
Q3
Q2
Q2
Q1
Q1
Q0
Q0
VCC = PIN 16
GND = PIN 8
Q3
Q2
Q1
Q0
15 RIPPLE
CARRY
OUT
11
12
13
14
The flip–flops shown in the circuit diagrams are Toggle–Enable flip–flops. A Toggle–
Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip–flop low.
T3
R
C
C
LOAD
LOAD
P3
T2
R
C
C
LOAD
LOAD
P2
T1
R
C
C
LOAD
LOAD
P1
T0
R
C
C
LOAD
LOAD
P0
MC54/74HC161A MC54/74HC163A
Figure 10. 4–Bit Binary Counter with Synchronous Reset
(MC54/74HC163A)
MOTOROLA
MC54/74HC161A MC54/74HC163A
TYPICAL APPLICATIONS CASCADING
LOAD
INPUTS
LOAD
P0 P1 P2 P3
H = COUNT
L = DISABLE
ENABLE P
H = COUNT
L = DISABLE
ENABLE T
CLOCK
Q0 Q1 Q2 Q3
R
LOAD
P0 P1 P2 P3
ENABLE P
RIPPLE
CARRY
OUT
INPUTS
INPUTS
LOAD
P0 P1 P2 P3
ENABLE P
RIPPLE
CARRY
OUT
ENABLE T
CLOCK
CLOCK
R
R
Q0 Q1 Q2 Q3
RIPPLE
CARRY
OUT
ENABLE T
TO
MORE
SIGNIFICANT
STAGES
Q0 Q1 Q2 Q3
RESET
OUTPUTS
OUTPUTS
OUTPUTS
CLOCK
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on
number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Figure 11. N–Bit Synchronous Counters
INPUTS
INPUTS
INPUTS
LOAD
ENABLE P
ENABLE T
LOAD
P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
LOAD
P0 P1 P2 P3
ENABLE P
RIPPLE
CARRY
OUT
LOAD
P0 P1 P2 P3
ENABLE P
RIPPLE
CARRY
OUT
ENABLE T
ENABLE T
CLOCK
CLOCK
CLOCK
R
R
R
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
RIPPLE
CARRY
OUT
TO
MORE
SIGNIFICANT
STAGES
Q0 Q1 Q2 Q3
RESET
OUTPUTS
OUTPUTS
OUTPUTS
Figure 12. Nibble Ripple Counter
MOTOROLA
3–10
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC161A MC54/74HC163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HC163A
OTHER
INPUTS
HC163A
Q0
Q1
OTHER
INPUTS
OPTIONAL BUFFER
FOR NOISE REJECTION
Q2
Q0
Q1
OUTPUT
OPTIONAL BUFFER
FOR NOISE REJECTION
Q2
Q3
OUTPUT
Q3
RESET
RESET
Figure 13. Modulo–5 Counter
Figure 14. Modulo–11 Counter
The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch–free due to the
synchronous Reset.
High–Speed CMOS Logic Data
DL129 — Rev 6
3–11
MOTOROLA
MC54/74HC161A MC54/74HC163A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
K
N
SEATING
–
PLANE
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
9
1
8
T B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
M
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
1
P 8 PL
0.25 (0.010)
8
B
M
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
MOTOROLA
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
3–12
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC161A MC54/74HC163A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
*MC54/74HC161A/D*
3–13
MC54/74HC161A/D
MOTOROLA