ispLSI Macro Library Reference Manual

ispLSI Macro Library
Reference Manual
Version 8.2
Technical Support Line: 1-800-LATTICE or (408) 826-6002
IDE-ISPML-RM 8.2.1
Copyright
This document may not, in whole or part, be copied, photocopied, reproduced,
translated, or reduced to any electronic medium or machine-readable form without
prior written consent from Lattice Semiconductor Corporation.
The software described in this manual is copyrighted and all rights are reserved by
Lattice Semiconductor Corporation. Information in this document is subject to change
without notice.
The distribution and sale of this product is intended for the use of the original
purchaser only and for use only on the computer system specified. Lawful users of
this product are hereby licensed only to read the programs on the disks, cassettes, or
tapes from their medium into the memory of a computer solely for the purpose of
executing them. Unauthorized copying, duplicating, selling, or otherwise distributing
this product is a violation of the law.
Trademarks
The following trademarks are recognized by Lattice Semiconductor Corporation:
Generic Array Logic, ISP, ispANALYZER, ispATE, ispCODE, ispDCD,
ispDesignEXPERT, ispDOWNLOAD, ispDS, ispDS+, ispEXPERT, ispGDS, ispGDX,
ispHDL, ispJTAG, ispSmartFlow, ispStarter, ispSTREAM, ispSVF, ispTA, ispTEST,
ispTURBO, ispVECTOR, ispVerilog, ispVHDL, ispVM, Latch-Lock, LHDL, pDS+, RFT,
and Twin GLB are trademarks of Lattice Semiconductor Corporation. E2CMOS, GAL,
ispGAL, ispLSI, pDS, pLSI, Silicon Forest, and UltraMOS are registered trademarks
of Lattice Semiconductor Corporation.
SPEEDSearch, Performance Analyst, and DesignDirect are trademarks of Vantis
Corporation. Kooldip, MACH, MACHPRO, MACHXL, Monolithic Memories, PAL,
PALASM, and Vantis are registered trademarks of Vantis Corporation.
Project Navigator is a trademark of Data I/O Corporataion. ABEL-HDL is a registered
trademark of Data I/O Corporation.
All other trademarks and registered trademarks are the property of their respective
owners.
Lattice Semiconductor Corporation
5555 NE Moore Ct.
Hillsboro, OR 97124
(503) 268-8000
August 2000
ispLSI Macro Library Reference Manual
2
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Purpose and Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Module Macro Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Labeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Logic Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Using the NOMIN Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Quick Reference Macro Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Arithmetic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADDF1, ADDF2, F3ADD, ADDF4, ADDF8, ADDF8A, and ADDF16A. . . . . . . . . . . . . . . . . . .
ADDH1, ADDH2, ADDH3, ADDH4, ADDH8, ADDH8A, and ADDH16A . . . . . . . . . . . . . . . . .
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMP2, CMP4, and CMP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAG2, MAG4, and MAG8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MULT24 and MULT44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Propagate-Generate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG1, PG2, PG3, and PG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subtractors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SUBF1, SUBF2, F3SUB, SUBF4, SUBF8, SUBF8A, and SUBF16A . . . . . . . . . . . . . . . . . . .
SUBH1, SUBH2, SUBH3, SUBH4, SUBH8, SUBH8A, and SUBH16A . . . . . . . . . . . . . . . . . .
39
39
54
67
67
68
70
70
74
74
80
80
90
Coders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIN27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEC2 and DEC2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEC3 and DEC3E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEC4 and DEC4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PREN8 and PREN8E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PREN10 and PREN10E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PREN16 and PREN16E 111
ispLSI Macro Library Reference Manual
104
104
106
107
108
109
109
110
3
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD11, CBD12, CBD14, and CBD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD21, CBD22, CBD24, and CBD28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD31, CBD32, CBD34, and CBD38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD41, CBD42, CBD44, and CBD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBD516 and CBD616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBU11, CBU12, CBU14, and CBU18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBU21, CBU22, CBU24, and CBU28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBU31, CBU32, CBU34, and CBU38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBU41, CBU42, CBU44, and CBU48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBU516 and CBU616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBU716 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CBUD1, CBUD2, CBUD4, and CBUD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Decade Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDD14 and CDD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDD24 and CDD28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDD34 and CDD38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDD44 and CDD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDU14 and CDU18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDU24 and CDU28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDU34 and CDU38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDU44 and CDU48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDUD4 and CDUD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDUD4c and CDUD8c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gray Code Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGD14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGD24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGU14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGU24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGUD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
113
119
125
132
139
149
155
161
168
175
184
190
200
200
206
212
218
222
228
234
240
246
256
266
266
269
272
276
279
I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Bidirectional Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BI11, BI14, and BI18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BI21, BI24, and BI28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BI31, BI34, and BI38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BI41, BI44, and BI48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIID11, BIID14, and BIID18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIID21, BIID24, and BIID28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIID31, BIID34, and BIID38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIID41, BIID44, and BIID48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIID51, BIID54, and BIID58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIID61, BIID64, and BIID68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIID71, BIID74, and BIID78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIID81, BIID84, and BIID88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIIL11, BIIL14, and BIIL18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIIL21, BIIL24, and BIIL28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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284
284
285
286
287
288
289
290
291
292
293
294
295
296
297
4
BIIL31, BIIL34, and BIIL38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIIL41, BIIL44, and BIIL48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIIL51, BIIL54, and BIIL58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIIL61, BIIL64, and BIIL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIIL71, BIIL74, and BIIL78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIIL81, BIIL84, and BIIL88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IB11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID11, ID14, and ID18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID21, ID24, and ID28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IL11, IL14, and IL18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IL21, IL24, and IL28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OB11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OB21, OB24, and OB28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OT11, OT14, and OT18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OT21, OT24, and OT28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OT31, OT34, and OT38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OT41, OT44, and OT48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
298
299
300
301
302
303
304
304
305
306
307
308
309
309
310
311
312
313
314
Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AND2 through AND18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUF and INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NAND2 through NAND12, and NAND16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOR2 through NOR12, and NOR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OR2 through OR12, and OR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XNOR2, XNOR3, XNOR4, XNOR7, XNOR8, and XNOR9 . . . . . . . . . . . . . . . . . . . . . . . . . .
XOR2, LXOR2, XOR3, XOR4, XOR8, and XOR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
316
316
317
318
319
320
321
322
MUX/DMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX2 and MUX2E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX4 and MUX4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX8 and MUX8E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX16 and MUX16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX22 and MUX22E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX24 and MUX24E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX42 and MUX42E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX44 and MUX44E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX44A and MUX44AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUX82 and MUX82E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMUX2 and DMUX2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMUX4 and DMUX4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMUX22 and DMUX22E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMUX24 and DMUX24E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMUX42 and DMUX42E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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324
325
326
327
331
332
333
334
335
338
339
339
340
341
342
343
5
DMUX44 and DMUX44E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
DMUX82 and DMUX82E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
D Flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD11, FD14, and FD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD21, FD24, and FD28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD31, FD34, and FD38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD41, FD44, and FD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD51, FD54, and FD58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD61, FD64, and FD68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD71, FD74, and FD78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD81, FD84, and FD88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FD91, FD94, and FD98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FDA1, FDA4, and FDA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JK Flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJK11 and FJK21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJK31 and FJK41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FJK51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Toggle Flip-flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FT11 and FT21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD11, LD14, and LD18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD21, LD24, and LD28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD31, LD34, and LD38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD41, LD44, and LD48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD51, LD54, and LD58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD61, LD64, and LD68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD71, LD74, and LD78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD81, LD84, and LD88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LD91, LD94, and LD98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LDA1, LDA4, and LDA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LSR1 and LSR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRR11, SRR14, and SRR18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRR21, SRR24, and SRR28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRR31, SRR34, and SRR38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRR41, SRR44, and SRR48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRRL1, SRRL4, and SRRL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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347
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349
350
351
352
353
354
355
356
357
357
358
359
360
360
361
361
362
363
364
365
366
367
368
369
370
371
371
372
372
376
380
384
388
6
Preface
Overview
This Preface contains information on the following topics:
■
■
■
■
Purpose and Scope
Documentation Conventions
Quick Reference Macro Table
Programmable Macro Reference
ispLSI Macro Library Reference Manual
7
Purpose and Scope
Purpose and Scope
The ispLSI Macro Library Reference Manual documents the features, capabilities,
and use of the library macros provided with the pLSI and ispLSI Development System
from Lattice Semiconductor Corporation (LSC). This reference manual provides the
following information about each macro:
Function
The purpose and use of the macro.
Availability
1000, 2000, 3000, 5000, or 8000 devices.
Symbol
The representation of a macro within a schematic.
Type
Macro types are as follows:
Logic
These are the building blocks of macros.
Primitive
AND, NAND, OR, NOR, and XOR gates, and the FD11 and
FD12 D-type flip-flops are logic primitives.
Soft
A soft macro is a predefined netlist of a particular logic
function.
Hard
A hard macro is a netlist that is pre-mapped to the ispLSI
architecture for optimal resource utilization or performance.
Logic Resources
The number of product terms (PTs), Generic Logic Blocks
(GLBs), GLB outputs, and approximate GLB levels a macro
requires.
Macro Port Definition The format of the equation you enter that represents the
macro and the port order.
Truth Table
The table that shows the relationships between all the
possible inputs and outputs for the macro.
Schematic
A diagram of the logic within the macro is provided for the
more complex macros.
ispLSI Macro Library Reference Manual
8
Documentation Conventions
Documentation Conventions
The following sections describe the conventions used for signal names, truth tables,
pin labeling, and logic resources. A quick reference table is also included which gives
a brief description of each macro and its availability.
Signal Names
A0..An-1,B0..Bn-1 .... inputs
Z0..Zn-1................... outputs
ZN0 ........................ output of inverted gate
XI0.......................... external input pin
XO0 ........................ external output pin
OE .......................... Output Enable
XB0 ........................ external bidirectional pin
CLK ........................ Clock line
D0..Dn-1 .................. input to D flip-flop/latch; input to T flip-flop; load inputs for counters
and shift registers
Q0..Qn-1 ................. output of flip-flop or latch
Q0’..Qn-1’................ previous output of flip-flop or latch
TE........................... Test Enable input for scan flip-flops
TI0..TIn-1................. Test Inputs for scan flip-flops and latches
G ............................ Gate for latch
TG .......................... Test Gate for scan latch
LD........................... parallel Load for shift registers and counters
CD .......................... Clear Direct (asynchronous)
PS .......................... Preset Synchronous
CS .......................... Clear Synchronous
PD .......................... Preset Direct (only on latches)
J0,K0 ...................... inputs to JK flip-flop
S0,S1,R0,R1 .......... inputs to SR latch
S0..Sn-1 .................. select lines – multiplexors/demultiplexors, decoders/priority
encoders
EN .......................... Enable for multiplexors and counters
CI............................ Carry In for adders
CO.......................... Carry Out for adders
BI............................ Borrow In for subtractors
BO .......................... Borrow Out for subtractors
EQ .......................... A equals B output for comparators
GT .......................... A greater than B output for comparators
LT ........................... A Less Than B output for comparators
EQI ......................... Cascade input of EQ from previous stage for mag comparators
GTI ......................... Cascade input of GT from previous stage for mag comparators
LTI .......................... Cascade input of LT from previous stage for mag comparators
ispLSI Macro Library Reference Manual
9
Documentation Conventions
CAI ......................... shift registers: serial input; counters: CAscade In
CAIR....................... shift right serial input
CAIL ....................... shift left serial input
RL........................... shift Right/shift Left control for SRRL shift registers
CAO ....................... CAscade Out for counters
DNUP ..................... count Down/count UP control for up-down counters
ispLSI Macro Library Reference Manual
10
Documentation Conventions
Truth Tables
x ...................don’t care
X...................X (unknown) state
Z ...................high impedance state
d ...................any pattern of 1s and 0s on an input or set of inputs
d ...................the inverse of d
↑ ...................rising clock edge
↓ ...................falling clock edge
- ....................appears in output column if a bidirectional pin acts as an input pin
For macros such as the MUX2 and the MUX2E, which are identical except for the
enable feature on the MUX2E, table cells in gray represent the additional truth table
row and column that apply only to the macro with the enable. For example, the truth
table for the MUX2 and MUX2E appears as follows:
Input
Output
EN
S0
Z0
1
0
A0
1
1
A1
0
x
0
By disregarding the gray cells in the truth table shown above, you can see the truth
table for the MUX2.
Input
Output
S0
0
Z0
A0
1
A1
Some truth tables show input and output information for several macros that perform
the same function but handle a different number of bits. For example, LD11 and LD14
have one-bit and four-bit D latches, respectively. In these truth tables, you see 0~n-1,
which indicates that the column represents bits 0 through n-1, where n is the number
of bits in the macro of interest. The truth table for LD11 and LD14 looks like:
Input
D0~Dn-1
Output
d
G
1
Q0~Qn-1
d
x
0
Q0~Qn-1
ispLSI Macro Library Reference Manual
11
Documentation Conventions
The truth table for LD11 alone would look like this:
Input
Output
D0
d
G
1
Q0
d
x
0
Q0
Module Macro Truth Tables
*.............. These inputs, once set, are fixed and can only be connected to VCC/GND.
‡ ............. Refer to the User Programmable Features table.
† ............. Refer to the section on Control Blocks for functionality.
** ............ ADI and ADO are required to share I/O pins so they must be connected to
bidirectional pins.
§ ............. Data-in can only be external input signals. No logic can be connected.
§§ ........... Data-out can only be external output signals. No logic can be connected.
ispLSI Macro Library Reference Manual
12
Documentation Conventions
Pin Labeling
Two formats for describing groups of pins–logic diagrams and equation entry lines–
are included in this manual. Both of these formats are shown in the following
example:
Logic Symbol
CBUD8
PS
CAI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
DN/UP
LD CAO
EN
CD CS
Macro Port Definition
CBUD8([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,DNUP,CD,CS);
Both of these examples refer to pins Q0 through Q7. The expressions [Q0..Q7] and
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 are equivalent.
Macro Port Definition shows the pin order of the macros.
ispLSI Macro Library Reference Manual
13
Documentation Conventions
Logic Resources
The logic resources of each macro are described as follows:
Product Terms (PTs)
The number of gates in the AND array of the
GLBs used by the macro. Add one product term
if you use the Product Term Clock option with
the macro or if the macro has an asynchronous
clear (CD). If “/out” follows the number of
product terms, it means the “number of product
terms per output.”
Generic Logic Blocks(GLB)
The number of GLBs that the macro uses.
GLB Outputs (Outputs)
The number of GLB outputs the macro uses,
including outputs internal to the macro. A GLB
output is also called an Output Logic Macrocell
(OLMC).
GLB Levels (Levels)
The number of levels of GLBs (not gates) used.
For example, this is the logic resource summary for MUX24 and MUX24E:
Macro
MUX24
PT
4/out
GLBs
.5
MUX24E
4/out
.5
Outputs Levels
2
1
2
1
A dash (-) indicates that the amount of the resource the macro uses depends on how
the macro is used or how the partitioner in ispEXPERT Compiler arranges the macro
in the device.
Logic resources for most of the logic primitive macros are not listed. These macros
are rarely used by themselves, and when used with other macros, they are placed in
space left over by other macros.
Logic resource information is approximate because the partitioner may use different
resources for a given macro depending on the rest of the design.
ispLSI Macro Library Reference Manual
14
Documentation Conventions
Using the NOMIN Attribute
Calling some macros and specifying the NOMIN attribute for a specific pin results in
error 5319 being issued to indicate a problem fitting the logic. The following table lists
the macros and the pin that cannot be assigned the NOMIN attribute.
Macro
Parameter
F3ADD_2
P012
ADDF8A_2
P012
ADDF8A_5
P345
ADDF16A_2
P012
ADDF16A_4
P345
ADDF16A_6
P678
ADDF16A_8
P911
ADDF16A_10
P1214
ADDH8A_4
P345
ADDH16A_4
P345
ADDH16A_6
P678
ADDH16A_8
P911
ADDH16A_10
P1214
CMP8
EQ
MULT44_6
P345
F3SUB_2
P012
SUBF8A_2
P012
SUBF8A_5
P345
SUBF16A_2
P012
SUBF16A_4
P345
SUBF16A_6
P678
SUBF16A_8
P911
SUBF16A_10
P1214
SUBH8A_4
P345
SUBH16A_4
P345
SUBH16A_6
P678
SUBH16A_8
P911
SUBH16A_10
P1214
ispLSI Macro Library Reference Manual
15
Quick Reference Macro Table
Quick Reference Macro Table
The following table lists the macros available from LSC for use with the ispLSI 1000,
2000, 3000, 5000, and 8000 device families.
Macro
Description
1000
2000
3000
5000
8000
ADDF1
1-bit full adder
X
X
X
X
X
ADDF2
2-bit full adder
X
X
X
X
X
F3ADD
3-bit full adder with
propagate-generate
X
X
X
X
X
ADDF4
4-bit full adder
X
X
X
X
X
ADDF8
8-bit full adder
X
X
X
X
X
ADDF8A
8-bit full adder with
propagate-generate
submacros
X
X
X
X
X
ADDF16A
16-bit full adder with
propagate-generate
submacros
X
X
X
X
X
ADDH1
1-bit half adder
X
X
X
X
X
ADDH2
2-bit half adder
X
X
X
X
X
ADDH3
3-bit half adder
X
X
X
X
X
ADDH4
4-bit half adder
X
X
X
X
X
ADDH8
8-bit half adder
X
X
X
X
X
ADDH8A
8-bit half adder built with
propagate-generate
submacros
X
X
X
X
X
ADDH16A
16-bit half adder built with
propagate-generate
submacros
X
X
X
X
X
AND2 through
AND18
2 to 18-input AND gates
X
X
X
X
X
BI11
1-bit bidirect pin
X
X
X
X
X
BI14
Four BI11s with common
Output Enable
X
X
X
X
X
BI18
Eight BI11s with common
Output Enable
X
X
X
X
X
ispLSI Macro Library Reference Manual
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
BI21
1-bit bidirect pin with
inverted output
X
X
X
X
X
BI24
Four BI21s with common
Output Enable
X
X
X
X
X
BI28
Eight BI21s with common
Output Enable
X
X
X
X
X
BI31
1-bit bidirect pin with active
low Output Enable
X
X
X
X
X
BI34
Four BI31s with common
Output Enable
X
X
X
X
X
BI38
Eight BI31s with common
Output Enable
X
X
X
X
X
BI41
1-bit bidirect pin with
inverted output and active
low Output Enable
X
X
X
X
X
BI44
Four BI41s with common
Output Enable
X
X
X
X
X
BI48
Eight BI41s with common
Output Enable
X
X
X
X
X
BIID11
1-bit bidirect pin with
registered input
X
X
X
X
BIID14
Four BIID11s with common
clock and Output Enable
X
X
X
X
BIID18
Eight BIID11s with common
clock and Output Enable
X
X
X
X
BIID21
1-bit bidirect pin with
registered input and inverted
output
X
X
X
X
BIID24
Four BIID21s with common
clock and Output Enable
X
X
X
X
BIID28
Eight BIID21s with common
clock and Output Enable
X
X
X
X
BIID31
1-bit bidirect pin with
registered input and active
low enable
X
X
X
X
ispLSI Macro Library Reference Manual
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
BIID34
Four BIID31s with common
clock and Output Enable
X
X
X
X
BIID38
Eight BIID31s with common
clock and Output Enable
X
X
X
X
BIID41
1-bit bidirect pin with
registered input, inverted
output, and active low enable
X
X
X
X
BIID44
Four BIID41s with common
clock and Output Enable
X
X
X
X
BIID48
Eight BIID41s with common
clock and Output Enable
X
X
X
X
BIID51
1-bit bidirect pin with
registered input and inverted
clock
X
X
X
X
BIID54
Four BIID51s with common
clock and Output Enable
X
X
X
X
BIID58
Eight BIID51s with common
clock and Output Enable
X
X
X
X
BIID61
1-bit bidirect pin with
registered input, inverted
output, and inverted clock
X
X
X
X
BIID64
Four BIID61s with common
clock and Output Enable
X
X
X
X
BIID68
Eight BIID61s with common
clock and Output Enable
X
X
X
X
BIID71
1-bit bidirect pin with
registered input, active low
enable, and inverted clock
X
X
X
X
BIID74
Four BIID71s with common
clock and Output Enable
X
X
X
X
BIID78
Eight BIID71s with common
clock and Output Enable
X
X
X
X
BIID81
1-bit bidirect pin with
registered input, inverted
output, active low enable,
and inverted clock
X
X
X
X
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18
Quick Reference Macro Table
Macro
Description
1000
2000
3000
BIID84
Four BIID81s with common
clock and Output Enable
X
X
X
X
BIID88
Eight BIID81s with common
clock and Output Enable
X
X
X
X
BIIL11
1-bit bidirect pin with latched
input
X
X
X
X
BIIL14
Four BIIL11s with common
G and Output Enable
X
X
X
X
BIIL18
Eight BIIL11s with common
G and Output Enable
X
X
X
X
BIIL21
1-bit bidirect pin with latched
input and inverted output
X
X
X
X
BIIL24
Four BIIL21s with common
G and Output Enable
X
X
X
X
BIIL28
Eight BIIL21s with common
G and Output Enable
X
X
X
X
BIIL31
1-bit bidirect pin with latched
input and active low enable
X
X
X
X
BIIL34
Four BIIL31s with common
G and Output Enable
X
X
X
X
BIIL38
Eight BIIL31s with common
G and Output Enable
X
X
X
X
BIIL41
1-bit bidirect pin with latched
input, inverted output, and
active low enable
X
X
X
X
BIIL44
Four BIIL41s with common
G and Output Enable
X
X
X
X
BIIL48
Eight BIIL41s with common
G and Output Enable
X
X
X
X
BIIL51
1-bit bidirect pin with latched
input, and inverted G
X
X
X
X
BIIL54
Four BIIL51s with common
G and Output Enable
X
X
X
X
BIIL58
Eight BIIL51s with common
G and Output Enable
X
X
X
X
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19
Quick Reference Macro Table
Macro
Description
1000
2000
3000
BIIL61
1-bit bidirect pin with latched
input, inverted output, and
inverted G
X
X
X
X
BIIL64
Four BIIL61s with common
G and Output Enable
X
X
X
X
BIIL68
Eight BIIL61s with common
G and Output Enable
X
X
X
X
BIIL71
1-bit bidirect pin with latched
input, active low enable, and
inverted G
X
X
X
X
BIIL74
Four BIIL71s with common
G and Output Enable
X
X
X
X
BIIL78
Eight BIIL71s with common
G and Output Enable
X
X
X
X
BIIL81
1-bit bidirect pin with latched
input, inverted output, active
low enable, and inverted G
X
X
X
X
BIIL84
Four BIIL81s with common
G and Output Enable
X
X
X
X
BIIL88
Eight BIIL81s with common
G and Output Enable
X
X
X
X
BIN27
Binary-7-segment decoder
with enable
X
X
X
X
X
BUF
Single input buffer
X
X
X
X
X
CBD11
1-bit down counter with
async clear, CAI, and CAO
X
X
X
X
X
CBD12
2-bit down counter with
async clear, CAI, and CAO
X
X
X
X
X
CBD14
4-bit down counter with
async clear, CAI, and CAO
X
X
X
X
X
CBD18
8-bit down counter with
async clear, CAI, and CAO
X
X
X
X
X
CBD21
1-bit down counter with
async clear, enable, CAI,
and CAO
X
X
X
X
X
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20
Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
CBD22
2-bit down counter with
async clear, enable, CAI,
and CAO
X
X
X
X
X
CBD24
4-bit down counter with
async clear, enable, CAI,
and CAO
X
X
X
X
X
CBD28
8-bit down counter with
async clear, enable, CAI,
and CAO
X
X
X
X
X
CBD31
1-bit down counter with
async clear, enable, parallel
data load, sync preset, CAI,
and CAO
X
X
X
X
X
CBD32
2-bit down counter with
async clear, enable, parallel
data load, sync preset, CAI,
and CAO
X
X
X
X
X
CBD34
4-bit down counter with
async clear, enable, parallel
data load, sync preset, CAI,
and CAO
X
X
X
X
X
CBD38
8-bit down counter with
async clear, enable, parallel
data load, sync preset, CAI,
and CAO
X
X
X
X
X
CBD41
1-bit down counter with sync
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBD42
2-bit down counter with sync
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBD44
4-bit down counter with sync
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
ispLSI Macro Library Reference Manual
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
CBD48
8-bit down counter with sync
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBD516
16-bit down counter with
async clear and enable
X
X
X
X
X
CBD616
16-bit down counter with
async clear, CAO, and
enable
X
X
X
X
X
CBU11
1-bit up counter with async
clear, CAI, and CAO
X
X
X
X
X
CBU12
2-bit up counter with async
clear, CAI, and CAO
X
X
X
X
X
CBU14
4-bit up counter with async
clear, CAI, and CAO
X
X
X
X
X
CBU18
8-bit up counter with async
clear, CAI, and CAO
X
X
X
X
X
CBU21
1-bit up counter with async
clear, enable, CAI, and CAO
X
X
X
X
X
CBU22
2-bit up counter with async
clear, enable, CAI, and CAO
X
X
X
X
X
CBU24
4-bit up counter with async
clear, enable, CAI, and CAO
X
X
X
X
X
CBU28
8-bit up counter with async
clear, enable, CAI, and CAO
X
X
X
X
X
CBU31
1-bit up counter with async
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBU32
2-bit up counter with async
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBU34
4-bit up counter with async
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
CBU38
8-bit up counter with async
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBU41
1-bit up counter with sync
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBU42
2-bit up counter with sync
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBU44
4-bit up counter with sync
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBU48
8-bit up counter with sync
clear, enable, parallel data
load, sync preset, CAI, and
CAO
X
X
X
X
X
CBU516
16-bit up counter with async
clear and enable
X
X
X
X
X
CBU616
16-bit up counter with async
clear, enable, and CAO
X
X
X
X
X
CBU716
16-bit up counter with async
clear, enable, parallel data
load and carry out
X
X
X
X
X
CBUD1
1-bit up/down counter with
async clear, sync clear,
enable, parallel data load,
sync preset, CAI, and CAO
X
X
X
X
X
CBUD2
2-bit up/down counter with
async clear, sync clear,
enable, parallel data load,
sync preset, CAI, and CAO
X
X
X
X
X
CBUD4
4-bit up/down counter with
async clear, sync clear,
enable, parallel data load,
sync preset, CAI, and CAO
X
X
X
X
X
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
CBUD8
8-bit up/down counter with
async clear, sync clear,
enable, parallel data load,
sync preset, CAI, and CAO
X
X
X
X
X
CDD14
4-bit decade down counter
with async clear, enable, and
parallel data load
X
X
X
X
X
CDD18
8-bit decade down counter
with async clear, enable, and
parallel data load
X
X
X
X
X
CDD24
4-bit decade down counter
with sync clear, enable, and
parallel data load
X
X
X
X
X
CDD28
8-bit decade down counter
with sync clear, enable, and
parallel data load
X
X
X
X
X
CDD34
4-bit decade down counter
with async clear, enable, and
parallel data load, CAI, and
CAO
X
X
X
X
X
CDD38
8-bit decade down counter
with async clear, enable, and
parallel data load, CAI, and
CAO
X
X
X
X
X
CDD44
4-bit decade down counter
with sync clear, enable,
parallel data load, CAI, and
CAO
X
X
X
X
X
CDD48
8-bit decade down counter
with sync clear, enable,
parallel data load, CAI, and
CAO
X
X
X
X
X
CDU14
4-bit decade up counter with
async clear, enable, and
parallel data load
X
X
X
X
X
CDU18
8-bit decade up counter with
async clear, enable, and
parallel data load
X
X
X
X
X
ispLSI Macro Library Reference Manual
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
CDU24
4-bit decade up counter with
sync clear, enable, and
parallel data load
X
X
X
X
X
CDU28
8-bit decade up counter with
sync clear, enable, and
parallel data load
X
X
X
X
X
CDU34
4-bit decade up counter with
async clear, enable, parallel
data load, CAI, and CAO
X
X
X
X
X
CDU38
8-bit decade up counter with
async clear, enable, parallel
data load, CAI, and CAO
X
X
X
X
X
CDU44
4-bit decade up counter with
sync clear, enable, parallel
data load, CAI, and CAO
X
X
X
X
X
CDU48
4-bit decade up counter with
sync clear, enable, parallel
data load, CAI, and CAO
X
X
X
X
X
CDUD4
4-bit up/down decade
counter with async clear,
sync clear, enable, and
parallel data load
X
X
X
X
X
CDUD8
8-bit up/down decade
counter with async clear,
sync clear, enable, and
parallel data load
X
X
X
X
X
CDUD4c
4-bit up/down decade
counter with async clear,
sync clear, enable, and
parallel data load, CAI, and
CAO
X
X
X
X
X
CDUD8c
8-bit up/down decade
counter with async clear,
sync clear, enable, parallel
data load, CAI, and CAO
X
X
X
X
X
CGD14
4-bit gray code down counter
with async clear, sync
preset, enable, and parallel
data load
X
X
X
X
X
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
CGD24
4-bit gray code down counter
with sync clear, sync preset,
enable, and parallel data
load
X
X
X
X
X
CGU14
4-bit gray code up counter
with async clear, sync
preset, enable, and parallel
data load
X
X
X
X
X
CGU24
4-bit gray code up counter
with sync clear, sync preset,
enable, and parallel data
load
X
X
X
X
X
CGUD4
4-bit gray code up/down
counter with async clear,
sync clear and preset,
enable, and parallel data
load
X
X
X
X
X
CMP2
2-bit equality comparator
X
X
X
X
X
CMP4
4-bit equality comparator
X
X
X
X
X
CMP8
8-bit equality comparator
X
X
X
X
X
DEC2
1-2 decoder
X
X
X
X
X
DEC2E
1-2 decoder with enable
X
X
X
X
X
DEC3
1-3 decoder
X
X
X
X
X
DEC3E
1-3 decoder with enable
X
X
X
X
X
DEC4
1-4 decoder
X
X
X
X
X
DEC4E
1-4 decoder with enable
X
X
X
X
X
DMUX2
1 of 2 output dmux
X
X
X
X
X
DMUX2E
1 of 2 output dmux with
enable
X
X
X
X
X
DMUX4
1 of 4 output dmux
X
X
X
X
X
DMUX4E
1 of 4 output dmux with
enable
X
X
X
X
X
DMUX22
Dual 1 of 2 output dmux with
common select line
X
X
X
X
X
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
DMUX22E
Dual 1 of 2 output dmux with
common select line and
enable
X
X
X
X
X
DMUX24
Dual 1 of 4 output dmux with
common select line
X
X
X
X
X
DMUX24E
Dual 1 of 4 output dmux with
common select line and
enable
X
X
X
X
X
DMUX42
Quad 1 of 2 output dmux
with common select line
X
X
X
X
X
DMUX42E
Quad 1 of 2 output dmux
with common select line and
enable
X
X
X
X
X
DMUX44
Quad 1 of 4 output dmux
with common select line
X
X
X
X
X
DMUX44E
Quad 1 of 4 output dmux
with common select line and
enable
X
X
X
X
X
DMUX82
Octal 1 of 2 output dmux with
common select line
X
X
X
X
X
DMUX82E
Octal 1 of 2 output dmux with
common select line and
enable
X
X
X
X
X
F3SUB
3-bit full subtractor with
propagate-generate
X
X
X
X
X
FD11
1-bit D flip-flop
X
X
X
X
X
FD14
4-bit D flip-flop
X
X
X
X
X
FD18
8-bit D flip-flop
X
X
X
X
X
FD21
1-bit D flip-flop with async
clear
X
X
X
X
X
FD24
4-bit D flip-flop with async
clear
X
X
X
X
X
FD28
8-bit D flip-flop with async
clear
X
X
X
X
X
FD31
1-bit D flip-flop with sync
preset
X
X
X
X
X
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
FD34
4-bit D flip-flop with sync
preset
X
X
X
X
X
FD38
8-bit D flip-flop with sync
preset
X
X
X
X
X
FD41
1-bit D flip-flop with async
clear dominant over sync
preset
X
X
X
X
X
FD44
4-bit D flip-flop with async
clear dominant over sync
preset
X
X
X
X
X
FD48
8-bit D flip-flop with async
clear dominant over sync
preset
X
X
X
X
X
FD51
1-bit D flip-flop with sync
preset dominant over sync
clear
X
X
X
X
X
FD54
4-bit D flip-flop with sync
preset dominant over sync
clear
X
X
X
X
X
FD58
8-bit D flip-flop with sync
preset dominant over sync
clear
X
X
X
X
X
FD61
1-bit flip-flop with scan
X
X
X
X
X
FD64
4-bit flip-flop with scan
X
X
X
X
X
FD68
8-bit flip-flop with scan
X
X
X
X
X
FD71
1-bit D flip-flop with scan and
async clear
X
X
X
X
X
FD74
4-bit D flip-flop with scan and
async clear
X
X
X
X
X
FD78
8-bit D flip-flop with scan and
async clear
X
X
X
X
X
FD81
1-bit D flip-flop with scan and
sync preset
X
X
X
X
X
FD84
4-bit D flip-flop with scan and
sync preset
X
X
X
X
X
ispLSI Macro Library Reference Manual
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Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
FD88
8-bit D flip-flop with scan and
sync preset
X
X
X
X
X
FD91
1-bit D flip-flop with scan and
async clear dominant over
sync preset
X
X
X
X
X
FD94
4-bit D flip-flop with scan and
async clear dominant over
sync preset
X
X
X
X
X
FD98
8-bit D flip-flop with scan and
async clear dominant over
sync preset
X
X
X
X
X
FDA1
1-bit D flip-flop with scan and
sync preset dominant over
async clear
X
X
X
X
X
FDA4
4-bit D flip-flop with scan and
sync preset dominant over
async clear
X
X
X
X
X
FDA8
8-bit D flip-flop with scan and
sync preset dominant over
async clear
X
X
X
X
X
FJK11
JK flip-flop
X
X
X
X
X
FJK21
JK flip-flop with async clear
X
X
X
X
X
FJK31
JK flip-flop with scan
X
X
X
X
X
FJK41
JK flip-flop with scan and
async clear
X
X
X
X
X
FJK51
JK flip-flop with async clear
and sync preset
X
X
X
X
X
FT11
Toggle flip-flop with async
clear
X
X
X
X
X
FT21
Toggle flip-flop with sync
clear and preset, preset
dominant
X
X
X
X
X
IB11
1-bit input pin
X
X
X
X
X
ID11
1-bit registered input pin
X
X
X
X
ID14
Four ID11s with common
clock
X
X
X
X
ispLSI Macro Library Reference Manual
29
Quick Reference Macro Table
Macro
Description
1000
2000
3000
ID18
Eight ID11s with common
clock
X
X
X
X
ID21
1-bit registered input pin with
inverted clock
X
X
X
X
ID24
Four ID21s with common
clock
X
X
X
X
ID28
Eight ID21s with common
clock
X
X
X
X
IL11
1-bit input pin with D latch on
input
X
X
X
X
IL14
Four IL11s with common G
X
X
X
X
IL18
Eight IL11s with common G
X
X
X
X
IL21
1-bit input pin with D latch on
input, inverted enable
X
X
X
X
IL24
Four IL21s with common G
X
X
X
X
IL28
Eight IL21s with common G
X
X
X
X
INV
Single input inverter
X
X
X
X
X
LD11
1-bit D latch
X
X
X
X
X
LD14
4-bit D latch
X
X
X
X
X
LD18
8-bit D latch
X
X
X
X
X
LD21
1-bit D latch with async clear
X
X
X
X
X
LD24
4-bit D latch with async clear
X
X
X
X
X
LD28
8-bit D latch with async clear
X
X
X
X
X
LD31
1-bit D latch with async
preset
X
X
X
X
X
LD34
4-bit D latch with async
preset
X
X
X
X
X
LD38
8-bit D latch with async
preset
X
X
X
X
X
LD41
1-bit D latch with async clear
dominant over async preset
X
X
X
X
X
LD44
4-bit D latch with async clear
dominant over async preset
X
X
X
X
X
ispLSI Macro Library Reference Manual
5000
8000
30
Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
LD48
8-bit D latch with async clear
dominant over async preset
X
X
X
X
X
LD51
1-bit D latch with async
preset dominant over async
clear
X
X
X
X
X
LD54
4-bit D latch with async
preset dominant over async
clear
X
X
X
X
X
LD58
8-bit D latch with async
preset dominant over async
clear
X
X
X
X
X
LD61
1-bit D latch with scan
X
X
X
X
X
LD64
4-bit D latch with scan
X
X
X
X
X
LD68
8-bit D latch with scan
X
X
X
X
X
LD71
1-bit D latch with scan and
async clear
X
X
X
X
X
LD74
4-bit D latch with scan and
async clear
X
X
X
X
X
LD78
8-bit D latch with scan and
async clear
X
X
X
X
X
LD81
1-bit D latch with scan and
async preset
X
X
X
X
X
LD84
4-bit D latch with scan and
async preset
X
X
X
X
X
LD88
8-bit D latch with scan and
async preset
X
X
X
X
X
LD91
1-bit D latch with scan and
async clear dominant over
async preset
X
X
X
X
X
LD94
4-bit D latch with scan and
async clear dominant over
async preset
X
X
X
X
X
LD98
8-bit D latch with scan and
async clear dominant over
async preset
X
X
X
X
X
ispLSI Macro Library Reference Manual
31
Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
LDA1
1-bit D latch with scan and
async preset dominant over
async clear
X
X
X
X
X
LDA4
4-bit D latch with scan and
async preset dominant over
async clear
X
X
X
X
X
LDA8
8-bit D latch with scan and
async preset dominant over
async clear
X
X
X
X
X
LSR1
Simple SR latch
X
X
X
X
X
LSR2
SR latch with OR on S and R
inputs
X
X
X
X
X
LXOR2
XOR gate
X
X
X
X
X
MAG2
2-bit magnitude comparator
X
X
X
X
X
MAG4
4-bit magnitude comparator
X
X
X
X
X
MAG8
8-bit magnitude comparator
X
X
X
X
X
MULT24
2-bit by 4-bit multiplier
X
X
X
X
X
MULT44
4-bit by 4-bit multiplier
X
X
X
X
X
MUX2
1 of 2 input mux
X
X
X
X
X
MUX2E
1 of 2 input mux with enable
X
X
X
X
X
MUX4
1 of 4 input mux
X
X
X
X
X
MUX4E
1 of 4 input mux with enable
X
X
X
X
X
MUX8
1 of 8 input mux
X
X
X
X
X
MUX8E
1 of 8 input mux with enable
X
X
X
X
X
MUX16
1 of 16 input mux
X
X
X
X
X
MUX16E
1 of 16 input mux with
enable
X
X
X
X
X
MUX22
Dual 1 of 2 input mux with
common select line
X
X
X
X
X
MUX22E
Dual 1 of 2 input mux with
common select line and
enable
X
X
X
X
X
ispLSI Macro Library Reference Manual
32
Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
MUX24
Dual 1 of 4 input mux with
common select line
X
X
X
X
X
MUX24E
Dual 1 of 4 input mux with
common select line and
enable
X
X
X
X
X
MUX42
Quad 1 of 2 input mux with
common select line
X
X
X
X
X
MUX42E
Quad 1 of 2 input mux with
common select line and
enable
X
X
X
X
X
MUX44
Quad 1 of 4 input mux with
common select line
X
X
X
X
X
MUX44A
Quad 1 of 4 input mux with
common select line
X
X
X
X
X
MUX44AE
Quad 1 of 4 input mux with
common select line and
enable
X
X
X
X
X
MUX44E
Quad 1 of 4 input mux with
common select line and
enable
X
X
X
X
X
MUX82
Octal 1 of 2 input mux with
common select line
X
X
X
X
X
MUX82E
Octal 1 of 2 input mux with
common select line and
enable
X
X
X
X
X
NAND2 through
NAND12 &
NAND16
2 through 12 and 16-input
NAND gate
X
X
X
X
X
NOR2 through
NOR12 &
NOR16
2 though 12 and 16-input
NOR gate
X
X
X
X
X
OB11
1-bit output pin
X
X
X
X
X
OB21
1-bit inverting output pin
X
X
X
X
X
OB24
Four OB21s
X
X
X
X
X
OB28
Eight OB21s
X
X
X
X
X
ispLSI Macro Library Reference Manual
33
Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
OR2 through
OR12 & OR16
1 through 12 and 16-input
OR gate
X
X
X
X
X
OT11
1-bit 3-state output pin
X
X
X
X
X
OT14
Four OT11s with common
Output Enable
X
X
X
X
X
OT18
Eight OT11s with common
Output Enable
X
X
X
X
X
OT21
1-bit inverting 3-state output
pin
X
X
X
X
X
OT24
Four OT21s with common
Output Enable
X
X
X
X
X
OT28
Eight OT21s with common
Output Enable
X
X
X
X
X
OT31
1-bit 3-state output pin with
active low enable
X
X
X
X
X
OT34
Four OT31s with common
Output Enable
X
X
X
X
X
OT38
Eight OT31s with common
Output Enable
X
X
X
X
X
OT41
1-bit inverting 3-state output
pin with active low enable
X
X
X
X
X
OT44
Four OT41s with common
Output Enable
X
X
X
X
X
OT48
Eight OT41s with common
Output Enable
X
X
X
X
X
PG1
1-bit propagate-generate
X
X
X
X
X
PG2
2-bit propagate-generate
X
X
X
X
X
PG3
3-bit propagate-generate
X
X
X
X
X
PG4
4-bit propagate-generate
X
X
X
X
X
PREN8
7-line to 3-line priority
encoder
X
X
X
X
X
PREN8E
7-line to 3-line priority
encoder with enable
X
X
X
X
X
ispLSI Macro Library Reference Manual
34
Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
PREN10
9-line to 4-line priority
encoder
X
X
X
X
X
PREN10E
9-line to 4-line priority
encoder with enable
X
X
X
X
X
PREN16
15-line to 4-line priority
encoder
X
X
X
X
X
PREN16E
15-line to 4-line priority
encoder with enable
X
X
X
X
X
SRR11
1-bit right shift register with
async reset
X
X
X
X
X
SRR14
4-bit right shift register with
async reset
X
X
X
X
X
SRR18
8-bit right shift register with
async reset
X
X
X
X
X
SRR21
1-bit right shift register with
async reset and enable
X
X
X
X
X
SRR24
4-bit right shift register with
async reset and enable
X
X
X
X
X
SRR28
8-bit right shift register with
async reset and enable
X
X
X
X
X
SRR31
1-bit right shift register with
async reset, enable, parallel
data load, and sync preset
X
X
X
X
X
SRR34
4-bit right shift register with
async reset, enable, parallel
data load, and sync preset
X
X
X
X
X
SRR38
8-bit right shift register with
async reset, enable, parallel
data load, and sync preset
X
X
X
X
X
SRR41
1-bit right shift register with
sync reset, enable, parallel
data load, and sync preset
X
X
X
X
X
SRR44
4-bit right shift register with
sync reset, enable, parallel
data load, and sync preset
X
X
X
X
X
ispLSI Macro Library Reference Manual
35
Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
SRR48
8-bit right shift register with
sync reset, enable, parallel
data load, and sync preset
X
X
X
X
X
SRRL1
1-bit right/left shift register
with async reset, enable,
parallel data load, and sync
preset
X
X
X
X
X
SRRL4
4-bit right/left shift register
with async reset, enable,
parallel data load, and sync
preset
X
X
X
X
X
SRRL8
8-bit right/left shift register
with async reset, enable,
parallel data load, and sync
preset
X
X
X
X
X
SUBF1
1-bit full subtractor
X
X
X
X
X
SUBF2
2-bit full subtractor
X
X
X
X
X
SUBF4
4-bit full subtractor
X
X
X
X
X
SUBF8
8-bit full subtractor
X
X
X
X
X
SUBF8A
8-bit full subtractor with
propagate-generate
X
X
X
X
X
SUBF16A
16-bit full subtractor with
propagate-generate
X
X
X
X
X
SUBH1
1-bit half subtractor
X
X
X
X
X
SUBH2
2-bit half subtractor
X
X
X
X
X
SUBH3
3-bit half subtractor
X
X
X
X
X
SUBH4
4-bit half subtractor
X
X
X
X
X
SUBH8
8-bit half subtractor
X
X
X
X
X
SUBH8A
8-bit half subtractor built with
propagate-generate
submacro
X
X
X
X
X
SUBH16A
16-bit half subtractor built
with propagate-generate
submacro
X
X
X
X
X
XNOR2
Input XNOR gate
X
X
X
X
X
ispLSI Macro Library Reference Manual
36
Quick Reference Macro Table
Macro
Description
1000
2000
3000
5000
8000
XNOR3
Input XNOR gate
X
X
X
X
X
XNOR4
Input XNOR gate
X
X
X
X
X
XNOR7
Input XNOR gate
X
X
X
X
X
XNOR8
Input XNOR gate
X
X
X
X
X
XNOR9
Input XNOR gate
X
X
X
X
X
XOR2
Input XOR gate
X
X
X
X
X
XOR3
Input XOR gate
X
X
X
X
X
XOR4
Input XOR gate
X
X
X
X
X
XOR8
Input XOR gate
X
X
X
X
X
XOR9
Input XOR gate
X
X
X
X
X
*
**
***
CAO is a 2-level output (1 logic level and 1 CO delay).
ADDF8: CO is a 3-level output.
SUBF8: BO is a 3-level output.
ispLSI Macro Library Reference Manual
37
Arithmetic Functions
This chapter contains information on the following macros:
■
■
■
■
■
Adders
Comparators
Multipliers
Propagate-Generate
Subtractors
ispLSI Macro Library Reference Manual
38
Adders
Adders
ADDF1, ADDF2, F3ADD, ADDF4,
ADDF8, ADDF8A, and ADDF16A
ADDF1
ADDF8
CI
CI
A0
Z0
A0
B0
CO
A1
Function:
ADDF1:
ADDF2:
F3ADD:
ADDF4:
ADDF8:
ADDF8A:
ADDF16A:
A2
1-bit full adder.
2-bit full adder.
3-bit full adder with propagate-generate.
4-bit full adder.
8-bit full adder.
8-bit full adder built with propagate-generate
submacros.
16-bit full adder built with propagate-generate
submacros.
CI
A0
A1
Z0
B0
Z1
B1
CO
F3ADD
ADDF1, ADDF2, F3ADD, ADDF4, ADDF8, ADDF8A, and
ADDF16A can be used with 1000, 2000, 3000, 5000, and
8000 devices.
Additional symbols and schematics appear on the
following pages.
Type:
A3
A4
Z0
A5
Z1
A6
Z2
A7
B0
Z3
B1
Z5
B2
Z6
B3
Z7
B4
CI
Availability:
Soft:
Hard:
ADDF2
B5
A0
Z0
B6
A1
Z1
B7
A2
Z2
Z4
CO
B0
B1 G012
B2 P012
ADDF4
ADDF1, ADDF2, F3ADD, ADDF8A, ADDF16A
ADDF4, ADDF8
CI
A0
A1
A2
Z0
A3
Z1
B0
Z2
B1
Z3
B2
B3
ispLSI Macro Library Reference Manual
CO
39
Adders
Logic Resources:
Macro
PT
GLB
Output
Level
ADDF4
ADDF8
****
*****
2
9
6
27
2
3
****
*****
Z0: 4 PT
Z3: 7 PT
Z0: 2 PT
Z3: 5 PT
Z6: 7 PT
CA: 3 PT
G0-G6: 1 PT
Z1: 7 PT
CO: 7 PT
Z1: 3 PT
Z4: 6 PT
Z7: 7 PT
CB: 3 PT
P0-P7: 2 PT
Z2: 4 PT
TCO: 7 PT
Z2: 4 PT
Z5: 7 PT
CO: 6 PT
CC: 7 PT
ADDF8A
ADDF16A
CI
C1
A0
A0
A1
A1
A2
A3
A2
A4
A3
A5
A4
A6
A5
A7
B0
A6
B1
A7
B2
B0
B3
B4
B1
B5
B2
B6
B3
B7
CI
A0
Z0
Z1
Z1
Z2
Z2
Z3
Z4
Z3
Z5
Z4
Z6
Z5
Z7
Z6
C1
Z7
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B4
A12
B5
A13
B6
B7
CO
A14
A15
B0
B1
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
B2
B3
B4
CO
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
ispLSI Macro Library Reference Manual
40
Adders
Macro Port Definition:
ADDF1 (Z0,CAO,A0,B0,CI);
ADDF2 (Z0,Z1,CO,A0,A1,B0,B1,CI);
F3ADD ([Z0..Z2],G012,P012,A0,A1,A2,B0,B1,B2,CI);
F3ADD_1 (Z0,Z1,G012,A0,A1,A2,B0,B1,B2,CI);
F3ADD_2 (Z2,P012,A0,A1,A2,B0,B1,B2,CI);
ADDF4 ([Z0..Z3],CO,[A0..A3],[B0..B3],CI);
ADDF4_1 (Z0,Z1,TCO,A0,A1,B0,B1,CI);
ADDF4_2 (Z2,Z3,CO,A2,A3,B2,B3,TCO);
ADDF8 ([Z0..Z7],CO,[A0..A7],[B0..B7],CI);
ADDF8_1 (CO,[P0..P7],[G0..G3],CC,CI);
ADDF8_2 (Z7,[P0..P7],[G0..G3],A3,B3,CI,CA);
ADDF8_3 (Z6,[P0..P6],G0,G1,A0,A2,B0,B2,CI,CB);
ADDF8_4 (Z5,[P0..P6],G0,G1,G3,A2,A4,A6,B2,B4,B6,CI);
ADDF8_5 (Z2,Z4,[P0..P4],[G0..G2],G4,A1,A3,A4,B1,B3,B4,CI);
ADDF8_6 (Z3,[P0..P3],G1,G2,G5,G6,A0,A1,A5,A6,B0,B1,B5,B6,CI);
ADDF8_7 (Z0,P7,G2,CC,P0,P5,P6,G4,G5,G6,A2,A7,B2,B7,CI);
ADDF8_8 (Z1,CA,CB,P5,P0,P1,P4,P6,[G3..G6],A0,A5,B0,B5,CI);
ADDF8A ([Z0..Z7],CO,[A0..A7],[B0..B7],CI);
ADDF8A_1 (Z0,Z1,G012,A0,A1,A2,B0,B1,B2,CI);
ADDF8A_2 (Z2,P012,A0,A1,A2,B0,B1,B2,CI);
ADDF8A_3 (C2,CCI,CI,P012,P345,G012,G345);
ADDF8A_4 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,C2);
ADDF8A_5 (Z5,P345,A3,A4,A5,B3,B4,B5,C2);
ADDF8A_6 (CO,Z6,Z7,A6,A7,B6,B7,CCI);
ADDF16A ([Z0..Z15],CO,[A0..A15],[B0..B15],CI);
ADDF16A_1 (Z0,Z1,G012,A0,A1,A2,B0,B1,B2,CI);
ADDF16A_2 (Z2,P012,A0,A1,A2,B0,B1,B2,CI);
ADDF16A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,C2);
ADDF16A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,C2);
ADDF16A_5 (Z6,Z7,G678,A6,A7,A8,B6,B7,B8,C5);
ADDF16A_6 (Z8,P678,A6,A7,A8,B6,B7,B8,C5);
ADDF16A_7 (Z9,Z10,G911,A9,A10,A11,B9,B10,B11,C8);
ADDF16A_8 (Z11,P911,A9,A10,A11,B9,B10,B11,C8);
ADDF16A_9 (Z12,Z13,G1214,A12,A13,A14,B12,B13,B14,C11);
ADDF16A_10 (Z14,P1214,A12,A13,A14,B12,B13,B14,C11);
ADDF16A_11 (Z15,CO,C2,CI,P012,G012,A15,B15,C14);
ADDF16A_12 (C5,C8,C11,C14,C2,P345,G345,P678,G678,
P911,G911,P1214,G1214);
ispLSI Macro Library Reference Manual
41
Adders
Truth Table:
The truth table below applies to ADDF1, ADDF2, ADDF4,
ADDF8, ADDF8A, and ADDF16A. The value of CO
depends on the sum of A+B and n.
Input
Output
An-1~A0
Bn-1~B0
CI
Zn-1~Z0
CO
data
data
data
data
0
1
A+B
A+B+1
*
**
*
**
If A+B<2n, CO = 0. If A+B>2n, CO = 1.
If A+B+1<2n, CO = 0. If A+B+1>2n, CO = 1.
The truth table for F3ADD is shown below.
Input
Output
A2~A0
B2~B0
CI
Z2~Z0
G012
P012
data
data
data
data
0
1
A+B
A+B+1
*
**
***
***
*
**
***
If A+B<2n, G012 = 0. If A+B>2n, G012 = 1.
If A+B+1<2n, G012 = 0. If A+B+1>2n, G012 = 1.
P012 = (A0+B0) (A1+B1) (A2+B2).
ispLSI Macro Library Reference Manual
42
Adders
ADDF1
B0
CI
A0
Z0
CO
ispLSI Macro Library Reference Manual
43
Adders
ADDF2
CI
A1
A0
A0
A1
A0
A1
A1
B0
A0
B1
B1
CO
B0
A1
B0
B0
A0
B1
B1
B0
A0
B1
B0
A1
B1
A[0:1]
A0
A0
A0
B[0:1]
CI
B0
B0
B1
B1
B0
Z0
B[0:1]
CI
B0
A1
A0
LX2
Z1
B1
B1
B0
A0
B1
B1
B0
A0
B1
B0
A0
B1
B0
ispLSI Macro Library Reference Manual
44
Adders
F3ADD.1
A0
B0
Z0
LX2
CI
B0
CI
A1
LX2
A0
Z1
B1
A[0:2]
B1
B0
A0
B1
B1
B0
A[0:2]
A0
B1
B0
A0
B1
B0
A0
A0
A1
A1
A0
A1
A2
B0
A2
A2
A1
A2
B1
A0
A0
A1
A1
A2
A2
A0
A2
B0
B1
A2
G012
B2
B0
B0
B1
B1
A0
A1
B2
B2
B0
B2
A1
B[0:2]
B1
B2
B0
B0
B1
B1
B2
B2
A0
B0
B1
B2
A0
B0
A1
B1
B[0:2]
P012
A2
B2
ispLSI Macro Library Reference Manual
45
Adders
F3ADD.2
A2
B0
B[0:2]
LX2
Z2
B1
B2
CI
A0
B1
B2
B[0:2]
A1
B0
B2
A[0:1]
A0
A1
B2
A[0:2]
B0
B1
B2
CI
A0
B1
B2
A1
B0
B2
A0
A1
B2
A0
B0
B1
B2
A1
B1
B2
A0
A1
B0
B2
A0
B0
B1
B2
A1
B1
B2
A0
A1
B0
B2
ispLSI Macro Library Reference Manual
46
Adders
ADDF4
CI
CI
A0
A0
A1
A1
Z0
Z0
B0
B0
Z1
Z1
B1
B1
CO
ADDF2
PRESERVE
CI
A2
A0
A3
A1
Z0
Z2
B2
B0
Z1
Z3
B3
B1
CO
CO
ADDF2
ispLSI Macro Library Reference Manual
47
Adders
ADDF8.1
A0
P0
B0
PRESERVE
A1
P1
B1
PRESERVE
A2
P2
B2
PRESERVE
A3
P3
B3
PRESERVE
A4
P4
B4
PRESERVE
A5
P5
B5
PRESERVE
A6
P6
B6
PRESERVE
A7
P7
B7
PRESERVE
G0
PRESERVE
G1
PRESERVE
G2
PRESERVE
G3
PRESERVE
G4
PRESERVE
G5
PRESERVE
G6
PRESERVE
G7
PRESERVE
ispLSI Macro Library Reference Manual
48
Adders
ADDF8.2
CI
P0
G0
P1
CI
P0
G1
P2
G2
LX2
Z5
LX2
Z2
P3
G0
P1
G3
P4
G4
P5
G1
P2
G2
P3
CO
G3
P4
CI
P0
G4
G0
P5
P1
G1
P2
G5
P6
G6
P7
G7
ispLSI Macro Library Reference Manual
49
Adders
ADDF8.3
Z0
LX2
Z1
CI
P0
G0
P1
G1
P2
G2
P3
LX2
Z7
G3
P4
G4
P5
G5
P6
G6
P7
ispLSI Macro Library Reference Manual
50
Adders
ADDF8.4
CI
P0
G0
P1
LX2
Z3
LX2
Z4
G1
P2
G2
P3
CI
P0
G0
P1
CI
G1
P0
P2
G2
P3
G3
P4
G0
P1
G1
P2
LX2
Z6
G2
P3
G3
P4
G4
P5
G5
P6
ispLSI Macro Library Reference Manual
51
Adders
ADDF8A
CI
CI
A0
A0
Z0
Z0
A1
A1
Z1
Z1
A2
A2
Z2
Z2
B0
B0
B1
B1 G012G012
B2
B2 P012
GI1
P012 PI1
PGO1
F3ADD
PGI1
CI
A3
A0
Z0
Z3
A4
A1
Z1
Z4
A5
A2
Z2
Z5
B3
B0
B4
B1 G012G345 GI2
B2 P012P345 PI2
PG1
B5
PGO2
F3ADD
GI1
PI1
PGI1
CI
A6
A0
A7
A1
Z0
Z6
B6
B0
Z1
Z7
B7
B1
CO
CO
PG2
ADDF2
ispLSI Macro Library Reference Manual
52
Adders
ADDF16 A
CI
CI
A0
A0
Z0
Z0
A1
A1
Z1
Z1
A2
A2
Z2
Z2
B0
B0
B1
B1
G012
B2
B2
P012
G012
GI1
P012
PI1
PGO1
F3ADD
PGI1
PG1
CI
A3
A0
Z0
Z3
A4
A1
Z1
Z4
A5
A2
Z2
Z5
B3
B0
B4
B1
G012
B5
B2
P012
G345
GI1
P345
PI1
PGO1
F3ADD
PGI1
PG1
CI
A6
A0
Z0
Z6
A7
A1
Z1
Z7
A8
A2
Z2
B6
B0
B7
B1
G012
B8
B2
P012
Z8
G678
GI2
P678
PI2
PGO2
F3ADD
GI1
PI1
CI
A9
A0
A10
A11
PGI1
Z0
Z9
A1
Z1
Z10
A2
Z2
Z11
PG2
B9
B0
B10
B1
G012
B11
B2
P012
G911
GI3
P911
PI3
PGO3
F3ADD
GI2
PI2
GI1
CI
PI1
A12
A0
Z0
Z12
A13
A1
Z1
Z13
PGI1
A14
A2
Z2
Z14
B12
B0
B13
B1
G012
G1214
GI4
B14
B2
P012
P1214
PI4
PG3
PGO4
F3ADD
GI3
PI3
GI2
CI
PI2
A15
A0
Z0
Z15
GI1
B15
B0
CO
CO
PI1
PGI1
ADDF1
PG4
ispLSI Macro Library Reference Manual
53
Adders
ADDH1, ADDH2, ADDH3, ADDH4,
ADDH8, ADDH8A, and ADDH16A
Function:
ADDH1:
ADDH2:
ADDH3:
ADDH4:
ADDH8:
ADDH8A:
ADDH16A:
ADDH1
A0
Z0
B0
CO
ADDH8
A0
1-bit half adder.
2-bit half adder.
3-bit half adder.
4-bit half adder.
8-bit half adder.
8-bit half adder built with propagate-generate
submacros.
16-bit half adder built with propagate-generate
submacros.
ADDH2
A2
A0
A3
A1
Z0
A4
Z0
B0
Z1
A5
Z1
B1
CO
A6
Z2
A7
Z3
B0
Z4
B1
Z5
B2
Z6
Z0
B3
Z7
Z1
B4
Z2
B5
ADDH3
Availability:
A0
ADDH1, ADDH2, ADDH3, ADDH4, ADDH8, ADDH8A,
and ADDH16A can be used with 1000, 2000, 3000, 5000,
and 8000 devices.
A1
Additional symbols and schematics appear on the
following pages.
A1
A2
B0
B1
CO
CO
B6
B7
B2
Type:
Soft:
Hard:
ADDH1, ADDH2, ADDH3, ADDH8A, ADDH16A
ADDH4, ADDH8
ADDH4
A0
A1
A2
Z0
A3
Z1
B0
Z2
B1
Z3
B2
B3
ispLSI Macro Library Reference Manual
CO
54
Adders
Logic Resources:
Macro
PT
GLB
Output
Level
ADDH4
ADDH8
****
*****
2
6
6
22
2
3
ADDH8A
A0
A0
A1
A1
****
Z0: 2 PT
Z2: 4 PT
CO: 7 PT
Z0: 2 PT
Z2: 3 PT
Z4: 5 PT
Z6: 11 PT
CO: 7 PT
G1-G5: 1 PT
*****
Z1: 6 PT
Z3: 7 PT
TCO: 3 PT
Z1: 2 PT
Z3: 4 PT
Z5: 9 PT
Z7: 8 PT
CC: 3 PT
P1-P7: 2 PT
A4
Z0
A5
Z1
A6
Z2
A7
Z3
B0
Z4
B1
Z5
B2
Z6
B4
The value of CO depends on the sum of A+B and n.
*
A3
A3
B3
Input
A2
A2
Truth Table:
Output
An-1~A0
Bn-1~B0
Zn-1~Z0
CO
data
data
A+B
*
If A+B<2n, CO = 0. If A+B>2n, CO = 1.
ADDH16A
Z7
CO
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B5
A14
B6
A15
B7
B0
B1
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
B2
B3
B4
CO
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
ispLSI Macro Library Reference Manual
55
Adders
Macro Port Definition:
ADDH1 (Z0,CO,A0,B0);
ADDH2 (Z0,Z1,CO,A0,A1,B0,B1);
ADDH3 ([Z0..Z2],CO,A0,A1,A2,B0,B1,B2);
ADDH3_1 (Z0,A0,B0);
ADDH3_2 (Z1,Z2,CO,A0,A1,A2,B0,B1,B2);
ADDH4 ([Z0..Z3],CO,[A0..A3],[B0..B3]);
ADDH4_1 (Z0,Z1,TCO,A0,A1,B0,B1);
ADDH4_2 (Z2,Z3,CO,A2,A3,B2,B3,TCO);
ADDH8 ([Z0..Z7],CO,[A0..A7],[B0..B7]);
ADDH8_1 (CO,Z1,Z3,[P1..P7],[G1..G5],A0,B0,CC);
ADDH8_2 (Z0,Z2,Z4,Z7,[P1..P7],[G1..G5],A0,A6,B0,B6);
ADDH8_3 (Z6,G5,G4,P4,[P1..P3],P5,P6,[G1..G3],A0,A4,A5,B0,B4,B5);
ADDH8_4 (Z5,G3,P3,G1,P1,P2,P4,P5,G2,G4,A0,A1,A3,B0,B1,B3);
ADDH8_5 (G2,P2,P1,A1,A2,B1,B2);
ADDH8_6 (P7,P6,P5,CC,[A5..A7],[B5..B7]);
ADDH8A ([Z0..Z7],CO,[A0..A7],[B0..B7]);
ADDH8A_1 (Z0,A0,B0,C2,CCI,P345,G345);
ADDH8A_2 (Z1,Z2,C2,A0,A1,A2,B0,B1,B2);
ADDH8A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,C2);
ADDH8A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,C2);
ADDH8A_5 (Z6,Z7,CO,A6,A7,B6,B7,CCI);
ADDH16A ([Z0..Z15],CO,[A0..A15],[B0..B15]);
ADDH16A_1 (Z0,Z15,CO,A0,A15,B0,B15,C14);
ADDH16A_2 (Z1,Z2,C2,A0,A1,A2,B0,B1,B2);
ADDH16A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,C2);
ADDH16A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,C2);
ADDH16A_5 (Z6,Z7,G678,A6,A7,A8,B6,B7,B8,C5);
ADDH16A_6 (Z8,P678,A6,A7,A8,B6,B7,B8,C5);
ADDH16A_7 (Z9,Z10,G911,A9,A10,A11,B9,B10,B11,C8);
ADDH16A_8 (Z11,P911,A9,A10,A11,B9,B10,B11,C8);
ADDH16A_9 (Z12,Z13,G1214,A12,A13,A14,B12,B13,B14,C11);
ADDH16A_10 (Z14,P1214,A12,A13,A14,B12,B13,B14,C11);
ADDH16A_11 (C5,C8,C11,C14,C2,P345,G345,P678,G678,P911,G911,
P1214,G1214);
ispLSI Macro Library Reference Manual
56
Adders
ADDH1
A0
B0
Z0
CO
ispLSI Macro Library Reference Manual
57
Adders
ADDH2
A[0:1]
A1
A0
B0
A0
A0
A0
A1
A1
B1
CO
B0
A1
B1
A0
B0
A0
Z0
B0
A0
A0
A1
B1
A0
A1
B1
B0
A1
B1
A1
A1
A0
A1
Z1
B1
B0
A1
A[0:1]
B1
A0
B0
A1
B1
A0
B0
B0
B0
B1
B1
B0
B0
B1
B1
B[0:1]
B[0:1]
ispLSI Macro Library Reference Manual
58
Adders
ADDH3.1
A0
B0
LX2
Z0
A1
A[0:2]
A0
Z1
LX2
B1
A[0:1]
B1
B0
A0
B[0:2]
B1
B0
A0
A0
A1
A1
A0
A1
A2
B0
A1
B[0:2]
A2
B1
B0
B0
B1
B1
B2
B2
A0
A2
B0
B1
A2
B2
A0
A0
A1
A1
A2
A2
CO
A0
A1
B0
B2
A1
B0
B1
B2
B0
B1
B1
B2
B2
A0
B0
B1
B2
ispLSI Macro Library Reference Manual
59
Adders
ADDH3.2
A2
B0
LX2
Z2
B1
B[0:2]
B2
A0
B1
B2
B[0:2]
A1
B0
A[0:1]
B2
A0
A1
A[0:2]
B2
A0
B0
B1
B2
A1
B1
B2
A0
A1
B0
B2
A1
B1
B2
ispLSI Macro Library Reference Manual
60
Adders
ADDH4
A0
A0
A1
A1
Z0
Z0
B0
B0
Z1
Z1
B1
B1
CO
ADDH2
PRESERVE
CI
A2
A0
A3
A1
Z0
Z2
B2
B0
Z1
Z3
B3
B1
CO
CO
ADDF2
ispLSI Macro Library Reference Manual
61
Adders
ADDH8.1
A0
Z0
B0
A1
B1
P1
PRESERVE
A2
P2
B2
PRESERVE
A3
P3
B3
PRESERVE
A4
P4
B4
PRESERVE
A5
P5
B5
PRESERVE
A6
P6
B6
PRESERVE
A7
P7
B7
PRESERVE
LX2
Z1
G1
PRESERVE
G2
PRESERVE
G3
PRESERVE
G4
PRESERVE
G5
PRESERVE
G6
PRESERVE
G7
PRESERVE
ispLSI Macro Library Reference Manual
62
Adders
ADDH8.2
A0
B0
P1
G1
P2
Z3
LX2
G2
P3
A0
B0
P1
A0
B0
P1
G1
P2
G2
P3
G1
Z5
LX2
P2
G3
P4
G4
P5
G2
P3
G3
P4
CO
G4
P5
A0
B0
P1
G5
G1
P6
P2
LX2
Z2
G6
P7
G7
ispLSI Macro Library Reference Manual
63
Adders
ADDH8.3
A0
B0
P1
G1
P2
G2
P3
Z6
LX2
G3
P4
G4
P5
G5
A0
P6
B0
P1
A0
B0
P1
G1
P2
G1
P2
LX2
Z4
G2
P3
G2
G3
P3
P4
G3
P4
LX2
Z7
G4
P5
G5
P6
G6
P7
ispLSI Macro Library Reference Manual
64
Adders
ADDH8A
A0
A0
A1
A1
Z0
Z0
A2
A2
Z1
Z1
B0
B0
Z2
Z2
B1
B1
G012
CO
B2
B2
CI
A3
A0
Z0
Z3
A4
A1
Z1
Z4
A5
A2
Z2
Z5
B3
B0
B4
B1
B5
B2
ADDH3
G012G345
P345
P012
GI1
PI1
PGO1
F3ADD
CI
PGI1
A6
A0
A7
A1
Z0
Z6
B6
B0
Z1
Z7
B7
B1
CO
CO
PG1
ADDF2
ispLSI Macro Library Reference Manual
65
Adders
ADDH16A
A0
A0
A1
A1
Z0
Z0
A2
A2
Z1
Z1
B0
B0
Z2
B1
B1
CO
B2
Z2
G012
B2
ADDH3
CI
A3
A0
Z0
Z3
A4
A1
Z1
Z4
A5
A2
Z2
B3
B0
B4
B1
G012
B5
B2
P012
Z5
G345
GI1
P345
PI1
PGO1
F3ADD
PGI1
PG1
CI
A6
A0
Z0
Z6
A7
A1
Z1
Z7
A8
A2
Z2
B6
B0
B7
B1
G012
B8
B2
P012
Z8
G678
GI2
P678
PI2
PGO2
F3ADD
GI1
PI1
CI
PGI1
A9
A0
Z0
Z9
A10
A1
Z1
Z10
A11
A2
Z2
B9
B0
PG2
B10
B1
G012
B11
B2
P012
Z11
G911
GI3
P911
PI3
PGO3
F3ADD
GI2
PI2
GI1
CI
PI1
A12
A0
Z0
Z12
A13
A1
Z1
Z13
A14
A2
Z2
Z14
B12
B0
B13
B1
G012
B14
B2
P012
PGI1
PG3
G1214
P1214
GI4
PI4
PGO4
F3ADD
GI3
PI3
GI2
CI
PI2
A15
A0
Z0
Z15
GI1
B15
B0
CO
CO
PI1
PGI1
ADDF1
PG4
ispLSI Macro Library Reference Manual
66
Comparators
Comparators
CMP2, CMP4, and CMP8
CMP2
A0
Function:
CMP2:
CMP4:
CMP8:
CMP8
A0
A1
2-bit equality comparator.
4-bit equality comparator.
8-bit equality comparator.
EQ
A1
A2
B0
A3
B1
A4
A5
Availability:
CMP2, CMP4, and CMP8 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
A6
CMP4
B0
B1
A2
B2
A3
Macro Port Definition:
EQ
CMP2 (EQ,A0,A1,B0,B1);
CMP4 (EQ,[A0..A3],[B0..B3]);
CMP8 (EQ,[A0..A7],[B0..B7]);
EQ
A0
A1
Type: Soft
A7
B0
B1
B2
B3
B3
B4
B5
B6
B7
Truth Table:
Input
Output
A0~An-1, B0~Bn-1
EQ
A0=B0,... An-1=Bn-1
All other values
1
0
ispLSI Macro Library Reference Manual
67
Comparators
MAG2, MAG4, and MAG8
MAG2
Function:
MAG2:
MAG4:
MAG8:
A0
2-bit magnitude comparator.
4-bit magnitude comparator.
8-bit magnitude comparator.
A1
B0
A0
GT
A1
EQ
A2
LT
A3
B1
A4
Availability:
A5
MAG2, MAG4, and MAG8 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
GTI
A6
EQI
A7
LTI
B0
MAG2
MAG4 and MAG8
MAG4
PT
16/out
16/out
B2
B3
A0
B4
A1
B5
A2
MAG4
MAG8
LT
B1
Logic Resources:
Macro
GT
EQ
Type:
Soft:
Hard:
MAG8
GLB
3
6
Output
3
6
Level
1
2
Macro Port Definition:
A3
B6
GT
B7
EQ
B0
LT
GTI
B1
EQI
B2
LTI
B3
MAG2 (GT,EQ,LT,A0,A1,B0,B1,GTI,EQI,LTI);
MAG4 (GT,EQ,LT,[A0..A3],[B0..B3],GTI,EQI,LTI);
MAG4_1 (EQ,[A0..A3],[B0..B3],GTI,EQI,LTI);
MAG4_2 (GT,[A0..A3],[B0..B3],GTI,EQI,LTI);
MAG4_3 (LT,[A0..A3],[B0..B3],GTI,EQI,LTI);
MAG8 (GT,EQ,LT,[A0..A7],[B0..B7],GTI,EQI,LTI);
MAG8_1 (TEQ,[A4..A7],[B4..B7],GTI,EQI,LTI);
MAG8_2 (TGT,[A4..A7],[B4..B7],GTI,EQI,LTI);
MAG8_3 (TLT,[A4..A7],[B4..B7],GTI,EQI,LTI);
MAG8_4 (EQ,[A0..A3],[B0..B3],TGT,TEQ,TLT);
MAG8_5 (GT,[A0..A3],[B0..B3],TGT,TEQ,TLT);
MAG8_6 (LT,[A0..A3],[B0..B3],TGT,TEQ,TLT);
ispLSI Macro Library Reference Manual
GTI
EQI
LTI
68
Comparators
Truth Table:
The truth table is the same for all MAGs.
Input
Output
LTI
ETI
GTI
A
B
LT
EQ
GT
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
1
x
x
x
x
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
A<B
A=B
A>B
x
x
x
x
x
x
x
x
x
x
x = don’t care.
ispLSI Macro Library Reference Manual
69
Multipliers
Multipliers
MULT24 and MULT44
MULT24
Function:
MULT24:
MULT44:
2-bit by 4-bit multiplier.
4-bit by 4-bit multiplier.
Availability:
MULT24 and MULT44 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Schematics appear on the following pages.
MULT44
A0
Z0
A0
Z0
A1
Z1
A1
Z1
B0
Z2
A2
Z2
B1
Z3
A3
Z3
B2
Z4
B0
Z4
B3
Z5
B1
B2
Z5
B3
Z7
Z6
Type: Soft
Macro Port Definition:
MULT24 (Z0,Z1,Z2,Z3,Z4,Z5,A0,A1,B0,B1,B2,B3);
MULT24_1 (Z0,Z1,Z2,Z3,A0,A1,B0,B1,B2,B3);
MULT24_2 (Z4,Z5,A0,A1,B0,B1,B2,B3);
MULT44 ([Z0..Z7],[A0..A3],[B0..B3]);
MULT44_1 (L0,L1,L2,L3,A0,A1,B0,B1,B2,B3);
MULT44_2 (H0,H1,H2,H3,A2,A3,B0,B1,B2,B3);
MULT44_3 (L4,L5,H4,H5,A0,A1,A2,A3,B0,B1,B2,B3);
MULT44_4 (Z0,Z1,Z2,G012,L0,L1,L2,H0);
MULT44_5 (Z3,Z4,G345,L3,L4,L5,H1,H2,H3,G012);
MULT44_6 (Z5,P345,L3,L4,L5,H1,H2,H3,G012);
MULT44_7 (Z6,Z7,G345,P345,G012,H4,H5,C5);
Truth Table:
Input
Output
An-1~A0
Bn-1~B0
Zn-1~Z0
data
data
A*B
* = multiply.
ispLSI Macro Library Reference Manual
70
Multipliers
MULT24.1
A0
B0
A0
A0
A1
A1
Z0
A1
B0
B1
A0
B0
B0
B0
B1
B1
B2
B2
B3
B3
B1
A0
Z1
A1
B1
A0
A0
A0
A1
A1
A1
B0
A[0:1]
A[0:1]
A1
B0
B[0:3]
B1
B2
A0
A1
B1
B[0:3]
A0
B1
Z2
B2
B0
B0
B1
B1
A1
B2
B2
A0
B3
B3
A0
B2
B0
B2
ispLSI Macro Library Reference Manual
71
Multipliers
MULT24.2
A0
B0
A0
A0
A1
A1
Z0
A1
B0
B1
A0
B0
B0
B0
B1
B1
B2
B2
B3
B3
B1
A0
Z1
A1
B1
A0
A0
A0
A1
A1
A1
B0
A[0:1]
A[0:1]
A1
B0
B[0:3]
B1
B2
A0
A1
B1
B[0:3]
A0
B1
Z2
B2
B0
B0
B1
B1
A1
B2
B2
A0
B3
B3
A0
B2
B0
B2
ispLSI Macro Library Reference Manual
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Multipliers
MULT44
G012
A[0:3]
A0
A1
B0
B1
B2
B3
A0
Z0
A1
Z1
B0
Z2
B1
Z3
B2
Z4
B3
Z5
CI
L3
L4
L5
A0
Z0
Z3
A1
Z1
Z4
A2
Z2
Z5
B[0:3]
B0
MULT24
B1
G012
B2
P012
G345
P345
F3ADD
L0
L1
Z0
Z1
L2
A2
A3
B0
B1
B2
B3
A0
Z0
A1
Z1
B0
Z2
B1
Z3
B2
Z4
B3
Z5
Z2
LX2
H0
H1
H2
G012
H3
C5
LX2
Z6
MULT24
Z7
G345
P345
GI1
PI1
PGO1
G012
C5
PGI1
PG1
ispLSI Macro Library Reference Manual
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Propagate-Generate
Propagate-Generate
PG1
PG1, PG2, PG3, and PG4
GI1
PI1
Function:
PG1:
PG2:
PG3:
PG4:
PGO1
PGI1
Propagate-Generate Bit 1.
Propagate-Generate Bit 2.
Propagate-Generate Bit 3.
Propagate-Generate Bit 4.
PG3
GI3
PI3
PGO3
GI2
PI2
GI1
PG2
G12
Availability:
PG1, PG2, PG3, and PG4 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Schematics appear on the following pages.
Type: Soft
PI2
PGO2
GI1
PI1
PGI1
PG4
PI1
GI4
PGI1
PI4
PGO4
GI3
PI3
Macro Port Definition:
GI2
PG1
PG2
PG3
PG4
PI2
(PGO1,PGI1,PI1,GI1);
(PGO2,PGI1,PI1,GI1,PI2,GI2);
(PGO3,PGI1,PI1,GI1,PI2,GI2,PI3,GI3);
(PGO4,PGI1,PI1,GI1,PI2,GI2,PI3,GI3,PI4,GI4);
GI1
PI1
PGI1
Truth Table for PG1:
Input
Output
PGI1
PI1
GI1
PGO1
x
1
x
1
1
x
1
1
x = don’t care.
Truth Table for PG2:
Input
Output
PGI1
PI1
PI2
GI1
G12
PGO2
x
x
1
x
x
1
x
1
1
x
1
x
1
x
x
1
1
1
x = don’t care.
ispLSI Macro Library Reference Manual
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Propagate-Generate
Truth Table for PG3:
Input
Output
PGI1
PI1
PI2
PI3
GI1
GI2
GI3
PGO3
x
x
x
1
x
x
x
1
x
x
1
1
x
1
1
1
x
x
1
x
x
1
x
x
1
x
x
x
1
1
1
1
x = don’t care.
Truth Table for PG4:
Input
Output
PGI1
PI1
PI2
PI3
PI4
GI1
GI2
GI3
GI4
PGO4
x
x
x
x
1
x
x
x
x
1
x
x
x
1
1
x
x
1
1
1
x
1
1
1
1
x
x
x
1
x
x
x
1
x
x
x
1
x
x
x
1
x
x
x
x
1
1
1
1
1
x = don’t care.
ispLSI Macro Library Reference Manual
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Propagate-Generate
PG1
GI1
PI1
PGO1
PGI1
ispLSI Macro Library Reference Manual
76
Propagate-Generate
PG2
GI2
PI2
PGO2
GI1
PI1
PGI1
ispLSI Macro Library Reference Manual
77
Propagate-Generate
PG3
GI3
PI3
PGO3
GI2
PI2
GI1
PI1
PGI1
ispLSI Macro Library Reference Manual
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Propagate-Generate
PG4
GI4
PI4
GI3
PGO4
PI3
GI2
PI2
GI1
PI1
PGI1
ispLSI Macro Library Reference Manual
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Subtractors
Subtractors
SUBF1
SUBF1, SUBF2, F3SUB, SUBF4, SUBF8,
SUBF8A, and SUBF16A
BI
SUBF8
A-B
A-B
BI
A0
Z0
A0
B0
BO
A1
A2
Function:
SUBF1:
SUBF2:
F3SUB:
SUBF4:
SUBF8:
SUBF8A:
SUBF16A:
A3
1-bit full subtractor.
2-bit full subtractor.
3-bit full subtractor with propagate-generate.
4-bit full subtractor.
8-bit full subtractor.
8-bit full subtractor built with propagate-generate
submacros.
16-bit full subtractor built with propagate-generate
submacros.
SUBF2
A-B
BI
A0
A4
Z0
A5
Z1
A6
Z2
A7
Z3
A1
Z0
B0
Z4
B0
Z1
B1
Z5
B1
BO
B2
Z6
B3
Z7
B4
B5
F3SUB
Availability:
SUBF1, SUBF2, F3SUB, SUBF4, SUBF8, SUBF8A, and
SUBF16A can be used with 1000, 2000, 3000, 5000, and
8000 devices.
An additional symbol and schematics appear on the
following pages.
Soft:
Hard:
BI
A0
Z0
A1
Z1
A2
Z2
SUBF8A
A-B
A2
Z0
A3
Z1
B0
Z2
BI
C1
A0
A0
A1
A1
A2
A3
A2
A4
A3
A5
A4
A6
A5
A7
B0
A6
B1
A7
B2
B0
B3
B4
B1
B5
B2
B6
B3
B7
B1
Z3
B4
BO
B5
B1 G012
SUBF1, SUBF2, F3SUB, SUBF8A, SUBF16A
SUBF4, SUBF8
B6
B7
A-B
B0
Type:
BO
B2 P012
SUBF4
A-B
BI
A0
A1
B2
B3
B6
A-B
Z0
Z1
Z1
Z2
Z2
Z3
Z4
Z3
Z5
Z4
Z6
Z5
Z7
Z6
C1
Z7
BO
B7
ispLSI Macro Library Reference Manual
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Subtractors
Logic Resources:
SUBF16A
Macro
PT
GLB
Output
Level
SUBF4
SUBF8
****
*****
2
8
6
27
2
3
****
Z0: 4 PT
Z3: 7 PT
Z0: 2 PT
Z3: 5 PT
Z6: 6 PT
BA: 3 PT
G0-G6: 1 PT
*****
Z1: 7 PT
BO: 7 PT
Z1: 3 PT
Z4: 6 PT
Z7: 7 PT
BB: 7 PT
P0-P7: 2 PT
Z2: 4 PT
TBO: 7 PT
Z2: 4 PT
Z5: 7 PT
BO: 6 PT
BC: 3 PT
A-B
BI
A0
A1
A2
A3
A4
A5
A6
A7
Truth Table:
A8
The truth table below applies to SUBF1, SUBF2, SUBF4,
SUBF8, SUBF8A, and SUBF16A. The value of BO
depends on the difference of A–B.
A9
Input
A10
A11
A12
Output
A13
An-1~A0
Bn-1~B0
BI
Zn-1~Z0
BO
A14
data
data
data
data
0
1
A–B
A–B–1
*
**
A15
*
**
B0
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
B1
If B<A, BO = 0. If B>A, BO = 1.
If B<A, BO = 0. If B>A, BO = 1.
B2
B3
The truth table for F3SUB is shown below.
Input
A2~A0 B2~B0
data
data
*
**
***
data
data
B4
BO
B5
Output
B6
BI
Z2~Z0
G012
P012
0
1
A-B
A-B-1
*
**
***
***
If B<A, G012 = 0. If B>A, G012 = 1.
If B<A, G012 = 0. If B>A, G012 = 1.
P012 = (A0 + B0) (A1 + B1) (A2 + B2) where A0 = inverted A0.
B7
B8
B9
B10
B11
B12
B13
B14
B15
ispLSI Macro Library Reference Manual
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Subtractors
Macro Port Definition:
SUBF1 (Z0,BO,A0,B0,BI);
SUBF2 (Z0,Z1,BO,A0,A1,B0,B1,BI);
F3SUB ([Z0..Z2],G012,P012,[A0..A2],[B0..B2],BI);
F3SUB_1 (Z0,Z1,G012,[A02..A2],[B0..B2],BI);
F3SUB_2 (Z2,P012,[A0..A2][B0..B2],BI);
SUBF4 ([Z0..Z3],BO,[A0..A3],[B0..B3],BI);
SUBF4_1 (Z0,Z1,TBO,A0,A1,B0,B1,BI);
SUBF4_2 (Z2,Z3,BO,A2,A3,B2,B3,TBO);
SUBF8 ([Z0..Z7],BO,[A0..A7],[B0..B7],BI);
SUBF8_1 (BO,[P0..P7],[G0..G3],BB,BI);
SUBF8_2 (Z7,[P0..P7][G0..G3],A3,B3,BI,BA);
SUBF8_3 (Z6,[P0..P6],G0,G1,A0,A2,B0,B2,BI,BC);
SUBF8_4 (Z5,[P0..P6],G0,G1,G3,A2,A4,A6,B2,B4,B6,BI);
SUBF8_5 (Z2,Z4,[P0..P4],[G0..G2],G4,A1,A3,A4,B1,B3,B4,BI);
SUBF8_6 (Z3,[P0..P3],G1,G2,G5,G6,A0,A1,A5,A6,B0,B1,B5,B6,BI);
SUBF8_7 (Z0,P7,G2,BB,P0,P5,P6,G4,G5,G6,A2,A7,B2,B7,BI);
SUBF8_8 (Z1,BA,BC,P5,P0,P1,P4,P6,[G3..G6],A0,A5,B0,B5,BI);
SUBF8A ([Z0..Z7],BO,[A0..A7],[B0..B7],BI);
SUBF8A_1 (Z0,Z1,G012,[A0..A2],[B0..B2],BI);
SUBF8A_2 (Z2,P012,[A0..A2],[B0..B2],BI);
SUBF8A_3 (BB2,BBI,BI,P012,P345,G012,G345);
SUBF8A_4 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,BB2);
SUBF8A_5 (Z5,P345,[A3..A5],[B3..B5],BB2);
SUBF8A_6 (BO,Z6,Z7,A6,A7,B6,B7,BBI);
SUBF16A ([Z0..Z15],BO,[A0..A15],[B0..B15],BI);
SUBF16A_1 (Z0,Z1,G012,A0,A1,A2,B0,B1,B2,BI);
SUBF16A_2 (Z2,P012,A0,A1,A2,B0,B1,B2,BI);
SUBF16A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,BB2);
SUBF16A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,BB2);
SUBF16A_5 (Z6,Z7,G678,A6,A7,A8,B6,B7,B8,BB5);
SUBF16A_6 (Z8,P678,A6,A7,A8,B6,B7,B8,BB5);
SUBF16A_7 (Z9,Z10,G911,A9,A10,A11,B9,B10,B11,BB8);
SUBF16A_8 (Z11,P911,A9,A10,A11,B9,B10,B11,BB8);
SUBF16A_9 (Z12,Z13,G1214,A12,A13,A14,B12,B13,B14,BB11);
SUBF16A_10 (Z14,P1214,A12,A13,A14,B12,B13,B14,BB11);
SUBF16A_11 (Z15,BO,BB2,BI,P012,G012,A15,B15,BB14);
SUBF16A_12 (BB5,BB8,BB11,BB14,BB2,P345,G345,P678,G678,
P911,G911,P1214,G1214);
ispLSI Macro Library Reference Manual
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Subtractors
SUBF1
B0
BI
A0
Z0
BO
ispLSI Macro Library Reference Manual
83
Subtractors
SUBF2
BI
A1
A0
A[0:1]
A1
B0
A0
B1
B1
BO
B0
A1
B0
B0
B1
B1
A0
B0
A0
B1
B0
A1
B1
A0
A0
A0
A0
A1
A1
A1
A1
A[0:1]
B[0:1]
A0
B0
B0
B1
B1
B0
Z0
BI
BI
B[0:1]
B0
A1
A0
LX2
Z1
B1
B1
B0
A0
B1
B1
B0
A0
B1
B0
A0
B1
B0
ispLSI Macro Library Reference Manual
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Subtractors
F3SUB.1
A0
B0
Z0
LX2
BI
B0
BI
A1
LX2
A0
Z1
B1
A[0:2]
B1
B0
A0
B1
B1
B0
A[0:2]
A0
B1
B0
A0
B1
B0
A0
A0
A0
B0
A1
A1
A2
A2
B1
B2
A1
B1
B2
A0
A0
A1
A1
A2
A2
A0
A2
B0
B1
A2
G012
B2
B0
B0
A0
B1
B1
A1
B2
B2
B0
B2
A1
B[0:2]
A2
B1
B0
B0
A0
A1
B1
B1
B2
B2
A2
B0
A0
B0
A1
B1
B[0:2]
P012
A2
B2
ispLSI Macro Library Reference Manual
85
Subtractors
F3SUB. 2
A2
A0
LX2
Z2
A1
B[0:2]
B2
BI
BI
A0
A1
B2
BI
A0
B[0:2]
A1
B0
B2
A[0:1]
A1
B0
B2
BI
A[0:2]
A0
A1
B0
B2
A1
B0
B2
BI
A0
B1
B2
BI
A0
B0
B1
B2
B0
B1
B2
BI
A1
B2
B1
A0
B1
B2
BI
A0
B0
B1
B2
A1
B1
B2
B0
B1
B2
BI
ispLSI Macro Library Reference Manual
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Subtractors
SUBF4
A-B
BI
BI
A0
A0
A1
A1
Z0
Z0
B0
B0
Z1
Z1
B1
B1
BO
SUBF2
PRESERVE
A-B
BI
A2
A0
A3
A1
Z0
Z2
B2
B0
Z1
Z3
B3
B1
BO
BO
SUBF2
ispLSI Macro Library Reference Manual
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Subtractors
SUBF8.1
A0
P0
B0
PRESERVE
A1
P1
B1
PRESERVE
A2
B2
P2
PRESERVE
A3
B3
P3
PRESERVE
A4
B4
P4
PRESERVE
A5
B5
P5
PRESERVE
A6
B6
P6
PRESERVE
A7
B7
P7
PRESERVE
G0
PRESERVE
G1
PRESERVE
G2
PRESERVE
G3
PRESERVE
G4
PRESERVE
G5
PRESERVE
G6
PRESERVE
G7
PRESERVE
ispLSI Macro Library Reference Manual
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Subtractors
SUBF8.2
BI
P0
G0
P1
BI
P0
G1
P2
G2
LX2
Z5
LX2
Z2
P3
G3
G0
P4
P1
G4
P5
G1
P2
G2
P3
BO
BI
G3
P0
P4
G0
P1
G1
G4
P2
P5
G5
P6
G6
P7
G7
ispLSI Macro Library Reference Manual
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Subtractors
SUBH1, SUBH2, SUBH3, SUBH4,
SUBH8, SUBH8A, and SUBH16A
SUBH16A:
SUBH8
A-B
A0 Z0
A-B
B0
Function:
SUBH1:
SUBH2:
SUBH3:
SUBH4:
SUBH8:
SUBH8A:
SUBH1
BO
A0
A1
1-bit half subtractor.
2-bit half subtractor.
3-bit half subtractor.
4-bit half subtractor.
8-bit half subtractor.
8-bit half subtractor built with propagate-generate
submacros.
16-bit half subtractor built with propagate-generate
submacros.
A2
SUBH2
A4
Z0
A1
Z0
A5
Z1
B0
Z1
A6
Z2
B1
BO
A7
Z3
B0
Z4
SUBH3
B1
Z5
A-B
B2
Z6
B3
Z7
Availability:
SUBH1, SUBH2, SUBH3, SUBH4, SUBH8, SUBH8A,
and SUBH16A can be used with 1000, 2000, 3000, 5000,
and 8000 devices.
An additional symbol and schematics appear on the
following pages.
A3
A-B
A0
A0
Z0
A1
Z1
A2
Z2
BO
B5
B0
B1
B4
BO
B6
B2
B7
SUBH4
SUBH8A
Type:
Soft:
Hard:
SUBH1, SUBH2, SUBH3, SUBH8A, SUBH16A
SUBH4, SUBH8
A-B
A0
A1
A2
Z0
A3
Z1
B0
Z2
B1
Z3
B2
B3
BO
C1A-B
A0
A0
A1
A1
A2
Z0
A3
A2
Z1
Z1
A4
Z2
A3
Z2
A5
Z3
A4
A6
Z4
Z3
A5
A7
Z5
Z4
B0
A6
Z6
Z5
B1
Z7
A7
B2
Z6
B0
B3
C1
Z7
B4
B1
B5
B2
B6
B3
B7
B4
B5
BO
B6
B7
ispLSI Macro Library Reference Manual
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Subtractors
Logic Resources:
SUBH16A
Macro
PT
GLB
Output
Level
SUBH4
SUBH8
****
*****
2
6
6
22
2
3
A-B
A0
A1
A2
****
Z0: 2 PT
Z3: 7 PT
Z0: 2 PT
Z3: 4 PT
Z6: 11 PT
BB: 3 PT
*****
Z1: 6 PT
BO: 7 PT
Z1: 2 PT
Z4: 5 PT
Z7: 8 PT
G1-G5: 1 PT
Z2: 4 PT
TBO: 3 PT
Z2: 3 PT
Z5: 9 PT
BO: 7 PT
P1-P7: 2 PT
A3
A4
A5
A6
A7
A8
A9
Truth Table:
A10
The value of BO depends on the difference of A–B.
A11
A12
Input
*
Output
A13
An-1~A0
Bn-1~B0
Zn-1~Z0
BO
data
data
A–B
*
If B<A, BO = 0. If B>A, BO = 1.
A14
A15
B0
B1
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
B2
B3
B4
BO
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
ispLSI Macro Library Reference Manual
91
Subtractors
Macro Port Definition:
SUBH1 (Z0,BO,A0,B0);
SUBH2 (Z0,Z1,BO,A0,A1,B0,B1);
SUBH3 ([Z0..Z2],BO,[A0..A2],[B0..B2]);
SUBH3_1 (Z0,A0,B0);
SUBH3_2 (Z1,Z2,BO,A0,A1,A2,B0,B1,B2);
SUBH4 ([Z0..Z3],BO,[A0..A3],[B0..B3]);
SUBH4_1 (Z0,Z1,TBO,A0,A1,B0,B1);
SUBH4_2 (Z2,Z3,BO,A2,A3,B2,B3,TBO);
SUBH8 ([Z0..Z7],BO,[A0..A7],[B0..B7]);
SUBH8_1 (BO,Z1,Z3,[P1..P7],[G1..G5],A0,B0,BB);
SUBH8_2 (Z0,Z2,Z4,Z7,[P1..P7],[G1..G5],A0,A6,B0,B6);
SUBH8_3 (Z6,[P1..P6],[G1..G5],A0,A4,A5,B0,B4,B5);
SUBH8_4 (Z5,[P1..P5],[G1..G4],A0,A1,A3,B0,B1,B3);
SUBH8_5 (G2,P2,P1,A1,A2,B1,B2);
SUBH8_6 (BB,[P5..P7],[A5..A7],[B5..B7]);
SUBH8A ([Z0..Z7],BO,[A0..A7],[B0..B7]);
SUBH8A_1 (Z0,A0,B0,BB2,BI,P345,G345);
SUBH8A_2 (Z1,Z2,BB2,A0,A1,A2,B0,B1,B2);
SUBH8A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,BB2);
SUBH8A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,BB2);
SUBH8A_5 (Z6,Z7,BO,A6,A7,B6,B7,BI);
SUBH16A ([Z0..Z15],BO,[A0..A15],[B0..B15]);
SUBH16A_1 (Z0,Z15,BO,A0,A15,B0,B15,BB14);
SUBH16A_2 (Z1,Z2,BB2,A0,A1,A2,B0,B1,B2);
SUBH16A_3 (Z3,Z4,G345,A3,A4,A5,B3,B4,B5,BB2);
SUBH16A_4 (Z5,P345,A3,A4,A5,B3,B4,B5,BB2);
SUBH16A_5 (Z6,Z7,G678,A6,A7,A8,B6,B7,B8,BB5);
SUBH16A_6 (Z8,P678,A6,A7,A8,B6,B7,B8,BB5);
SUBH16A_7 (Z9,Z10,G911,A9,A10,A11,B9,B10,B11,BB8);
SUBH16A_8 (Z11,P911,A9,A10,A11,B9,B10,B11,BB8);
SUBH16A_9 (Z12,Z13,G1214,A12,A13,A14,B12,B13,B14,BB11);
SUBH16A_10 (Z14,P1214,A12,A13,A14,B12,B13,B14,BB11);
SUBH16A_11 (BB5,BB8,BB11,BB14,BB2,P345,G345,P678,G678,P911,
G911,P1214,G1214);
ispLSI Macro Library Reference Manual
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Subtractors
SUBH1
A0
B0
Z0
BO
ispLSI Macro Library Reference Manual
93
Subtractors
SUBH2
A[0:1]
A1
A0
B0
A0
B1
BO
B0
A1
B1
A0
B0
A[0:1]
A0
Z0
B0
A0
A0
A1
A1
A1
B1
A0
A1
B1
B0
A1
B1
A0
A1
Z1
B1
A1
A1
A0
A0
B0
A1
B1
A0
B0
A1
B1
A0
B0
B0
B1
B0
B0
B1
B1
B0
B1
B[0:1]
B[0:1]
ispLSI Macro Library Reference Manual
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Subtractors
SUBH3.1
A0
B0
Z0
A1
A[0:2]
A0
Z1
LX2
B1
A[0:2]
B0
B1
A0
B[0:2]
B0
B1
A0
A0
A0
B0
A1
A1
A2
A2
B1
B2
A1
B[0:2]
B1
B2
B0
B0
B1
B1
B2
B2
A0
A2
B0
B1
A2
B2
A0
A1
A2
BO
A0
A0
A1
A1
A2
A2
B0
A1
B0
B1
B2
B0
A2
B1
B1
B2
A0
A1
B0
B2
ispLSI Macro Library Reference Manual
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Subtractors
SUBH3.2
A2
A0
LX2
Z2
A1
B[0:2]
B2
A1
B0
B2
B[0:2]
A1
B1
A[0:1]
B2
A0
B1
A[0:2]
B2
A0
B0
B1
B2
A1
B1
B2
A0
A1
B0
B2
B0
B1
B2
ispLSI Macro Library Reference Manual
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Subtractors
SUBH4
A-B
A0
A0
A1
A1
Z0
Z0
B0
B0
Z1
Z1
B1
B1
BO
SUBH2
PRESERVE
A-B
BI
A2
A0
A3
A1
Z0
Z2
B2
B0
Z1
Z3
B3
B1
BO
BO
SUBF2
ispLSI Macro Library Reference Manual
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Subtractors
SUBH8.1
A0
Z0
B0
A1
B1
P1
PRESERVE
A2
B2
P2
PRESERVE
A3
B3
P3
PRESERVE
A4
B4
P4
PRESERVE
A5
B5
P5
PRESERVE
A6
B6
P6
PRESERVE
A7
P7
B7
PRESERVE
LX2
Z1
G1
PRESERVE
G2
PRESERVE
G3
PRESERVE
G4
PRESERVE
G5
PRESERVE
G6
PRESERVE
G7
PRESERVE
ispLSI Macro Library Reference Manual
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Subtractors
SUBH8.2
A0
B0
P1
G1
P2
LX2
Z3
G2
P3
A0
B0
P1
A0
B0
G1
P1
P2
G2
P3
LX2
Z5
LX2
Z2
G3
G1
P4
P2
G4
P5
G2
P3
BO
G3
P4
A0
B0
G4
P1
P5
G1
P2
G5
P6
G6
P7
G7
ispLSI Macro Library Reference Manual
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Subtractors
SUBH8.3
A0
B0
P1
G1
P2
G2
P3
LX2
Z6
G3
P4
G4
P5
G5
P6
A0
A0
B0
B0
P1
P1
G1
P2
LX2
G1
G2
P2
P3
Z4
G3
P4
G2
P3
G3
P4
LX2
Z7
G4
P5
G5
P6
G6
P7
ispLSI Macro Library Reference Manual
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Subtractors
SUBH8A
A-B
A0
A0
A1
A1
Z0
Z0
A2
A2
Z1
Z1
B0
B0
Z2
Z2
B1
B1
BO
B2
B2
A-B
G012
BI
A3
A0
Z0
Z3
A4
A1
Z1
Z4
A5
A2
Z2
Z5
B3
B0
B4
B1
G012
B5
B2
P012
SUBH3
G345
P345
GI1
PI1
A-B
PGO1
BI
F3SUB
PGI1
A6
A0
A7
A1
Z0
Z6
B6
B0
Z1
Z7
B7
B1
BO
BO
PG1
SUBF2
ispLSI Macro Library Reference Manual
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Subtractors
SUBH16A
A-B
A0
A0
A1
A1
Z0
Z0
A2
A2
Z1
Z1
B0
B0
Z2
B1
B1
B2
B2
Z2
G012
BO
SUBH3
A-B
BI
A3
A0
Z0
Z3
A4
A1
Z1
Z4
A5
A2
Z2
Z5
B3
B0
B4
B1
G012
B5
B2
P012
G345
GI1
P345
PI1
PGO1
F3SUB
PGI1
A-B
PG1
BI
A6
A0
Z0
Z6
A7
A1
Z1
Z7
A8
A2
Z2
Z8
B6
B0
B7
B1
G012
B8
B2
P012
GI2
P678
PI2
PGO2
F3SUB
GI1
PI1
A-B
BI
PGI1
A9
A0
Z0
Z9
A10
A1
Z1
Z10
A11
A2
Z2
Z11
PG2
B9
B0
B10
B1
G012
B11
B2
P012
G911
GI3
P911
PI3
PGO3
F3SUB
GI2
PI2
GI1
A-B
BI
PI1
A12
A0
Z0
Z12
A13
A1
Z1
Z13
A14
A2
Z2
Z14
B12
B0
B13
B1
G012
B14
B2
P012
PGI1
PG3
G1214
P1214
GI4
PI4
PGO4
F3SUB
GI3
PI3
GI2
A-B
BI
A15
A0
B15
B0
PI2
Z0
Z15
GI1
BO
BO
PI1
PGI1
SUBF1
PG4
ispLSI Macro Library Reference Manual
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Coders
This chapter contains information on the following macros:
■
■
Decoders
Encoders
ispLSI Macro Library Reference Manual
103
Decoders
Decoders
BIN27
BIN27
Function:
Z0
Binary to seven segment decoder with enable. A high
level on an output turns on the segment.
EN
Availability:
BIN27 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
Z1
Z2
A0
Z3
A1
Z4
A2
Z5
A3
Z6
Type: Soft
Z0
Z5 Z6 Z1
Z4 Z3 Z2
Macro Port Definition:
BIN27 ([Z0..Z6],[A0..A3],EN);
BIN27_1 ([Z0..Z2],[A0..A3],EN);
BIN27_2 ([Z3..Z6],[A0..A3],EN);
Segment Map:
Each BIN27 output corresponds to one of 7 segments.
Combinations of these segments form hexadecimal digits.
ispLSI Macro Library Reference Manual
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Decoders
Truth Table:
Input
EN
A3
A2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
Output
A1 A0 Z0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
0
Z1
Z2
Z3
Z4
Z5
Z6
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
0
0
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
1
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
Character
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Off
x = don’t care.
ispLSI Macro Library Reference Manual
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Decoders
DEC2 and DEC2E
DEC2
Function:
Z0
DEC2:
DEC2E:
1 to 2 decoder.
1 to 2 decoder with enable.
Z1
S0
Availability:
DEC2 and DEC2E can be used with 1000, 2000, 3000,
5000, and 8000 devices.
DEC2E
Z0
Type: Soft
Z1
EN
Macro Port Definition:
S0
DEC2 (Z0,Z1,S0);
DEC2E (Z0,Z1,EN,S0);
Truth Table:
Gray areas (EN) apply only to DEC2E.
Input
Output
EN
S0
Z0
Z1
1
1
0
0
1
x
1
0
0
0
1
0
x = don’t care.
ispLSI Macro Library Reference Manual
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Decoders
DEC3 and DEC3E
DEC3
Z0
Function:
DEC3:
DEC3E:
1 to 3 decoder.
1 to 3 decoder with enable.
Z1
Z2
S0
S1
Availability:
DEC3 and DEC3E can be used with 1000, 2000, 3000,
5000, and 8000 devices.
DEC3E
Z0
Type: Soft
Z1
EN
Macro Port Definition:
Z2
S0
DEC3 (Z0,Z1,Z2,S0,S1);
DEC3E (Z0,Z1,Z2,EN,S0,S1);
S1
Truth Table:
Gray areas (EN) apply only to DEC3E.
Input
Output
EN
S1
S0
Z0
Z1
Z2
1
1
1
1
1
0
0
1
1
x
0
1
0
1
x
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
x = don’t care.
ispLSI Macro Library Reference Manual
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Decoders
DEC4 and DEC4E
DEC4
Function:
DEC4:
DEC4E:
Z0
1 to 4 decoder.
1 to 4 decoder with enable.
Z1
Z2
S0
Z3
S1
Availability:
DEC4 and DEC4E can be used with 1000, 2000, 3000,
5000, and 8000 devices.
DEC4E
Z0
Type: Soft
Z1
Macro Port Definition:
EN
Z2
S0
Z3
DEC4 ([Z0..Z3],S0,S1);
DEC4E ([Z0..Z3],EN,S0,S1);
S1
Truth Table:
Gray areas (EN) apply only to DEC4E.
Input
Output
EN
S1
S0
Z0
Z1
Z2
Z3
1
1
1
1
0
0
0
1
1
x
0
1
0
1
x
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
x = don’t care.
ispLSI Macro Library Reference Manual
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Encoders
Encoders
PREN8
PREN8 and PREN8E
Function:
PREN8:
PREN8E:
7-line to 3-line priority encoder.
7-line to 3-line priority encoder with enable.
S0
Z0
S1
Z1
S2
Z2
S3
S4
S5
Availability:
S6
PREN8 and PREN8E can be used with 1000, 2000, 3000,
5000, and 8000 devices.
PREN8E
Type: Soft
EN
Macro Port Definition:
PREN8 ([Z0..Z2],[S0..S6]);
PREN8E ([Z0..Z2],[S0..S6],EN);
S0
Z0
S1
Z1
S2
Z2
S3
S4
Truth Table:
S5
Gray areas (EN) apply only to PREN8E.
Input
S6
Output
EN S0 S1 S2 S3 S4 S5 S6 Z2 Z1 Z0
1
1
1
1
1
1
1
1
0
0
1
x
x
x
x
x
x
x
0
0
1
x
x
x
x
x
x
0
0
0
1
x
x
x
x
x
0
0
0
0
1
x
x
x
x
0
0
0
0
0
1
x
x
x
0
0
0
0
0
0
1
x
x
0
0
0
0
0
0
0
1
x
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
x = don’t care
ispLSI Macro Library Reference Manual
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Encoders
PREN10 and PREN10E
PREN10E
PREN10
Function:
PREN10:
PREN10E:
EN
9-line to 4-line priority encoder.
9-line to 4-line priority encoder with enable.
Availability:
S0
Z0
S0
Z0
S1
Z1
S1
Z1
S2
Z2
S2
Z2
S3
Z3
S3
Z3
PREN10 and PREN10E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
S4
S4
S5
S5
S6
S6
Type: Soft
S7
S7
S8
S8
Macro Port Definition:
PREN10 ([Z0..Z3],[S0..S8]);
PREN10E ([Z0..Z3],[S0..S8],EN);
Truth Table:
Gray areas (EN) apply only to PREN10E.
Input
Output
EN
S0
S1
S2
S3
S4
S5
S6
S7
S8
Z3
Z2
Z1
Z0
1
1
1
1
1
1
1
1
1
1
0
0
1
x
x
x
x
x
x
x
x
x
0
0
1
x
x
x
x
x
x
x
x
0
0
0
1
x
x
x
x
x
x
x
0
0
0
0
1
x
x
x
x
x
x
0
0
0
0
0
1
x
x
x
x
x
0
0
0
0
0
0
1
x
x
x
x
0
0
0
0
0
0
0
1
x
x
x
0
0
0
0
0
0
0
0
1
x
x
0
0
0
0
0
0
0
0
0
1
x
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
x = don’t care.
ispLSI Macro Library Reference Manual
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Encoders
PREN16 and PREN16E
PREN16E
PREN16
Function:
PREN16:
PREN16E:
EN
15-line to 4-line priority encoder.
15-line to 4-line priority encoder with enable.
Availability:
PREN16 and PREN16E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
Macro Port Definition:
PREN16 ([Z0..Z3],[S0..S14]);
PREN16_1 (Z0,Z1,[S0..S14]);
PREN16_2 (Z2,Z3,[S3..S14]);
PREN16E ([Z0..Z3],[S0..S14],EN);
PREN16E_1 (Z0,Z1,[S0..S14],EN);
PREN16E_2 (Z2,Z3,[S3..S14],EN);
S0
Z0
S0
Z0
S1
Z1
S1
Z1
S2
Z2
S2
Z2
S3
Z3
S3
Z3
S4
S4
S5
S5
S6
S7
S6
S7
S8
S8
S9
S9
S10
S10
S11
S11
S12
S12
S13
S13
S14
S14
Truth Table:
Gray areas (EN) apply only to PREN16E. Some areas of this table are
not shown. Refer to the PREN10/10E truth table for the logic pattern.
Input
Output
EN
S0
S1
S2
S3
S11
S12
S13
S14
Z3
Z2
Z1
Z0
1
1
1
1
x
1
1
1
0
0
1
x
x
x
x
x
x
x
0
0
1
x
x
x
x
x
x
0
0
0
1
x
x
x
x
x
0
0
0
0
x
x
x
x
x
0
0
0
0
1
x
x
x
x
0
0
0
0
0
1
x
x
x
0
0
0
0
0
0
1
x
x
0
0
0
0
0
0
0
1
x
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
------
------
x = don’t care.
ispLSI Macro Library Reference Manual
111
Counters
This chapter contains information on the following macros:
■
■
■
Binary Counters
Decade Counters
Gray Code Counters
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Binary Counters
Binary Counters
CBD11
CBD11, CBD12, CBD14, and CBD18
CAI Q0
Function:
1-, 2-, 4-, and 8-bit down counters with asynchronous
clear, CAI, and CAO.
CAO
CD
Availability:
CBD12
CBD11, CBD12, CBD14, and CBD18 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
CAI
Q0
Schematics appear on the following pages.
Q1
CAO
Type:
Soft:
Hard:
CD
CBD11 and CBD12.
CBD14 and CBD18.
CBD14
Logic Resources:
*
**
Macro
PT
GLB
Output
Level
CBD14
CBD18
*
*
2
3
5
9
1**
1**
Q0-Qn-1: 2 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
CAI
Q0
Q1
Q2
Q3
CAO
CD
CBD18
Macro Port Definition:
CBD11 (Q0,CAO,CAI,CLK,CD);
CBD12 (Q0,Q1,CAO,CAI,CLK,CD);
CBD14 ([Q0..Q3],CAO,CAI,CLK,CD);
CBD14_1 ([Q0..Q3],CAI,CLK,CD);
CBD14_2 (CAO,[Q0..Q3],CAI);
CBD18 ([Q0..Q7],CAO,CAI,CLK,CD);
CBD18_1 ([Q0..Q3],CAI,CLK,CD);
CBD18_2 ([Q4..Q7],[Q0..Q3],CAI,CLK,CD);
CBD18_3 (CAO,[Q0..Q7],CAI);
CAI Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CAO
CD
ispLSI Macro Library Reference Manual
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Binary Counters
Counting Ranges:
CBD11: 1-0. CBD12: 3-0. CBD14: 15-0. CBD18: 255-0.
Truth Table:
The truth table is the same for all CBD1s.
Input
*
Output
CD
CAI
CLK
Q
CAO
1
0
0
x
0
1
x
x
0
Q
count down
CAI
0
*
↑
CAO = 1 after terminal count, when CAI = 1.
CAI = shift registers: serial input; counters: CAscade In,
Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
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Binary Counters
CBD11
LX2
D
Q
Q0
CAI
CLK
CD
FD21
CD
CAO
ispLSI Macro Library Reference Manual
115
Binary Counters
CBD12
QI[0:1]
QI[0:1]
QI0
QI0
LX2
D
QI0
Q
CAI
QI0
CD
FD21
CLK
QI1
Q0
Q1
CD
QI1
QI1
LX2
D
Q
QI1
QI0
CD
FD21
QI0
QI1
ispLSI Macro Library Reference Manual
CAO
116
Binary Counters
CBD14
QI[0:3]
QI[0:3]
QI0
QI0
LX2
D
QI0
Q
CAI
CD
FD21
CLK
QI1
CD
QI1
QI0
LX2
D
QI1
Q
CD
FD21
QI2
QI2
QI0
LX2
D
QI2
Q
QI0
Q0
QI1
Q1
QI2
Q2
QI1
CD
FD21
QI3
QI3
QI0
QI3
LX2
D
Q
QI1
QI3
Q3
QI0
QI2
QI1
CD
FD21
QI2
CAO
QI3
ispLSI Macro Library Reference Manual
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Binary Counters
CBD18
QI[0:7]
QI[0:7]
QI0
QI0
LX2
D
QI0
Q
CAI
CLK
CD
CD
FD21
QI1
QI1
QI0
LX2
D
QI1
Q
CD
FD21
QI2
QI2
QI0
LX2
D
QI2
Q
QI1
CD
FD21
QI3
QI3
QI0
LX2
D
QI3
Q
QI1
QI2
CD
FD21
QI4
QI4
QI0
LX2
D
QI4
Q
QI1
QI2
CD
FD21
QI3
QI5
QI5
QI0
LX2
D
QI5
Q
QI0
Q0
QI1
Q1
QI2
Q2
QI1
QI2
CD
QI3
FD21
QI4
QI6
QI6
QI0
QI3
LX2
D
QI6
Q
QI4
QI1
Q3
Q4
QI2
CD
FD21
QI3
QI5
Q5
QI4
QI6
QI5
Q6
QI7
QI7
QI0
QI7
LX2
D
Q
QI1
Q7
QI0
QI2
QI3
QI7
QI1
CD
FD21
QI2
QI4
QI3
QI5
QI4
QI6
QI5
CAO
QI6
QI7
ispLSI Macro Library Reference Manual
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Binary Counters
CBD21, CBD22, CBD24, and CBD28
CBD21
Function:
CAI
1-, 2-, 4-, and 8-bit down counters with asynchronous
clear, enable, CAI, and CAO.
Q0
EN
CAO
CD
Availability:
CBD21, CBD22, CBD24, and CBD28 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
CBD22
Schematics appear on the following pages.
CAI Q0
EN
Type:
Soft:
Hard:
CAO
CD
CBD21 and CBD22.
CBD24 and CBD28.
Logic Resources:
*
**
Q1
CBD24
Macro
PT
GLB
Output
Level
CBD24
CBD28
*
*
2
3
5
9
1**
1**
Q0-Qn-1: 2 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
CAI Q0
Q1
Q2
EN
Q3
CAO
CD
CBD28
Macro Port Definition:
CBD21 (Q0,CAO,CAI,CLK,EN,CD);
CBD22 (Q0,Q1,CAO,CAI,CLK,EN,CD);
CBD24 ([Q0..Q3],CAO,CAI,CLK,EN,CD);
CBD24_1 ([Q0..Q3],CAI,CLK,EN,CD);
CBD24_2 (CAO,[Q0..Q3],CAI,EN);
CBD28 ([Q0..Q7],CAO,CAI,CLK,EN,CD);
CBD28_1 ([Q0..Q3],CAI,CLK,EN,CD);
CBD28_2 ([Q4..Q7],[Q0..Q3],CAI,CLK,EN,CD);
CBD28_3 (CAO,[Q0..Q7],CAI,EN);
CAI Q0
Q1
Q2
Q3
Q4
Q5
Q6
EN
Q7
CAO
CD
Counting Ranges:
CBD21: 1-0. CBD22: 3-0. CBD24: 15-0. CBD28: 255-0.
ispLSI Macro Library Reference Manual
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Binary Counters
Truth Table:
The truth table is the same for all CBD2s.
Input
*
Output
CD
EN
CAI
CLK
Q
CAO
1
0
0
0
x
0
x
1
x
x
0
1
x
x
x
0
Q
Q
count down
CAI⋅EN
0
0
*
↑
CAO = 1 after terminal count, when CAI = 1 and EN = 1
CAI⋅EN = shift registers: serial input; counters:
CAscade In, enable for multiplexors and counters, Q = output.
ispLSI Macro Library Reference Manual
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Binary Counters
CBD21
CAI
LX2
D
Q0
Q
EN
CLK
CD
CD
FD21
Q0
CAO
ispLSI Macro Library Reference Manual
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Binary Counters
CBD22
QI[0:1]
QI[0:1]
QI0
QI0
LX2
D
QI0
Q
CAI
QI0
EN
CLK
Q0
CD
CD
QI1
FD21
Q1
QI1
QI1
QI0
LX2
D
Q
CD
FD21
QI1
QI0
QI1
CAO
ispLSI Macro Library Reference Manual
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Binary Counters
CBD24
QI[0:3]
QI[0:3]
QI0
QI0
LX2
D
QI0
Q
CAI
EN
CLK
CD
FD21
CD
QI1
QI1
QI0
LX2
D
QI1
Q
CD
FD21
QI2
QI2
QI0
QI0
LX2
D
Q0
QI2
Q
QI1
QI1
CD
FD21
Q1
QI2
Q2
QI3
QI3
QI0
QI3
LX2
D
Q
QI1
Q3
QI3
QI0
QI2
QI1
CD
FD21
QI2
QI3
ispLSI Macro Library Reference Manual
CAO
123
Binary Counters
CBD28
QI[0:7]
QI[0:7]
QI0
QI0
LX2
D
QI0
Q
CAI
EN
CLK
CD
FD21
CD
QI1
QI1
QI0
LX2
D
QI1
Q
CD
FD21
QI2
QI2
QI0
LX2
D
QI2
Q
QI1
CD
FD21
QI3
QI3
QI0
LX2
D
QI3
Q
QI1
QI2
CD
FD21
QI4
QI4
QI0
LX2
D
QI4
Q
QI1
QI2
CD
QI3
FD21
QI5
QI5
QI0
LX2
D
QI5
Q
QI1
QI2
QI0
CD
FD21
QI3
QI4
QI1
QI2
QI6
Q0
Q1
Q2
QI6
QI0
LX2
D
QI6
Q
QI3
Q3
QI1
QI2
QI4
CD
FD21
QI3
QI4
QI5
Q4
Q5
QI5
QI6
Q6
QI7
QI7
QI7
QI0
LX2
D
Q
QI1
QI2
QI3
QI7
Q7
QI0
QI1
CD
FD21
QI2
QI4
QI3
QI5
QI4
QI6
QI5
CAO
QI6
QI7
ispLSI Macro Library Reference Manual
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Binary Counters
CBD31, CBD32, CBD34, and CBD38
CBD31
CBD32
PS
CAI
PS
CAI
D0
D0
Q0
1
Q1
Function:
1-, 2-, 4-, and 8-bit down counters with asynchronous
clear, enable, parallel data load, synchronous preset, CAI,
and CAO.
Q0
LD CAO
Availability:
CBD31, CBD32, CBD34, and CBD38 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
EN
LD CAO
EN
CD
Schematics appear on the following pages.
CD
Type:
Soft:
Hard:
CBD31 and CBD32.
CBD34 and CBD38.
Logic Resources:
*
**
Macro
PT
GLB
Output
Level
CBD34
CBD38
*
*
2
3
5
9
1**
1**
Q0-Qn-1: 4 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
CBD34
CBD38
PS
CAI
PS
CAI
D0
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
D3
Q3
D3
Q3
D4
Q4
LD CAO
D5
Q5
EN
D6
Q6
D7
Q7
CD
Macro Port Definition:
LD CAO
CBD31 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,CD);
CBD32 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,CD);
CBD34 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,CD);
CBD34_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);
CBD34_2 (CAO,[Q0..Q3],CAI,EN);
CBD38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,CD);
CBD38_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);
CBD38_2 (Q4,Q5,[Q0..Q3],D4,D5,CAI,CLK,PS,LD,EN,CD);
CBD38_3 (Q6,Q7,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,CD);
CBD38_4 (CAO,[Q0..Q7],CAI,EN);
EN
CD
Counting Ranges:
CBD31: 1-0. CBD32: 3-0. CBD34: 15-0. CBD38: 255-0.
ispLSI Macro Library Reference Manual
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Binary Counters
Truth Table:
The truth table is the same for all CBD3s.
Input
*
**
Output
CD
PS
LD
D
EN
1
0
0
0
0
0
x
1
0
0
0
0
x
x
1
0
0
0
x
x
d
x
x
x
x
x
x
0
x
1
CAI CLK
x
x
x
x
0
1
x
↑
↑
x
x
↑
Q
CAO
0
CAI⋅EN
1
0
d
*
Q
0
Q
0
count down
**
CBD31: CAO = CAI⋅EN⋅D0
CBD32: CAO = CAI⋅EN⋅D0⋅D1
CBD34: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3
CBD38: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7
CAO = 1 after terminal count, when CAI = 1 and EN = 1.
CAI⋅EN = shift registers: serial input; counters: CAscade In,
enable for multiplexors and counters, d = any pattern of 1s and
0s on an input or set of inputs, Q = output of flip-flop or latch,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
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Binary Counters
CBD31
LX2
D
Q
Q0
D0
LD
CLK
CAI
CD
FD21
CD
EN
PS
CAO
ispLSI Macro Library Reference Manual
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Binary Counters
CBD32
QI[0:1]
QI0
QI[0:1]
QI0
LX2
D
QI0
Q
D0
LD
QI0
Q0
QI1
Q1
CD
FD21
CLK
CAI
CD
EN
QI1
QI1
LX2
D
Q
QI1
D1
QI0
CD
FD21
QI0
QI1
PS
CAO
ispLSI Macro Library Reference Manual
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Binary Counters
CBD34
QI[0:3]
QI0
QI[0:3]
QI0
LD
LX2
D
QI0
Q
D0
CD
CLK
CAI
FD21
CD
EN
PS
QI1
QI1
LX2
D
QI1
Q
D1
CD
FD21
QI0
QI2
QI2
LX2
D
QI2
Q
D2
CD
FD21
QI0
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI1
QI3
QI3
LX2
D
Q
QI3
D3
QI0
CD
FD21
QI1
QI2
QI0
QI1
QI2
QI3
ispLSI Macro Library Reference Manual
CAO
129
Binary Counters
CBD38.1
QI[0:7]
QI0
QI[0:7]
QI0
LD
LX2
D
QI0
Q
D0
CD
FD21
CLK
CAI
CD
EN
PS
QI1
QI1
LX2
D
QI1
Q
D1
CD
QI0
FD21
QI2
QI0
Q0
QI1
Q1
QI2
LX2
D
QI2
Q
QI2
Q2
D2
QI3
Q3
CD
QI0
FD21
QI4
QI1
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI3
QI3
LX2
D
Q
QI3
D3
QI0
CD
QI0
FD21
QI1
QI1
QI2
QI2
QI3
QI4
QI5
CAO
QI6
QI7
ispLSI Macro Library Reference Manual
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Binary Counters
CBD38.2
QI[0:7]
QI[0:7]
QI4
QI4
LD
LX2
D
QI4
Q
D4
CD
QI0
QI1
CLK
FD21
CD
QI2
QI3
CAI
EN
PS
QI5
QI5
LX2
D
QI5
Q
D5
CD
QI0
FD21
QI1
QI2
QI3
QI4
QI6
QI6
LX2
D
QI6
Q
D6
CD
QI0
FD21
QI1
QI2
QI3
QI4
QI5
QI7
QI7
LX2
D
Q
QI7
D7
QI0
CD
FD21
QI1
QI2
QI3
QI4
QI5
QI6
ispLSI Macro Library Reference Manual
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Binary Counters
CBD41, CBD42, CBD44, and CBD48
Function:
1-, 2-, 4-, and 8-bit down counters with synchronous clear,
enable, parallel data load, synchronous preset, CAI, and
CAO.
CBD41
PS
CAI
PS
CAI
Q0
D0
CS
CBD44
CBD41 and CBD42.
CBD44 and CBD48.
PS
CAI
Logic Resources:
**
Q1
CS
Type:
*
D1
EN
Schematics appear on the following pages.
CBD44
CBD48
Q0
LD CAO
EN
CBD41, CBD42, CBD44, and CBD48 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
Macro
D0
LD CAO
Availability:
Soft:
Hard:
CBD42
PT
*
*
PS
CAI
D0
GLB
2
3
Output
5
9
Level
1**
1**
Q0-Qn-1: 4 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
(CAO is a 2-level output).
D1
Q1
D2
Q2
D3
Q3
LD CAO
EN
CBD48
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
CS
LD CAO
Macro Port Definition:
CBD41 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,CS);
CBD42 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,CS);
CBD44 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,CS);
CBD44_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);
CBD44_2 (CAO,[Q0..Q3],CAI,EN);
CBD48 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,CS);
CBD48_2 (Q4,Q5,[Q0..Q3],D4,D5,CAI,CLK,PS,LD,EN,CS);
CBD48_3 (Q6,Q7,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,CS);
CBD48_4 (CAO,[Q0..Q7],CAI,EN);
EN
CS
Counting Ranges:
CBD41: 1-0. CBD42: 3-0. CBD44: 15-0. CBD48: 255-0.
ispLSI Macro Library Reference Manual
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Binary Counters
Truth Table:
The truth table is the same for all CBD4s.
Input
*
**
Output
PS
CS
LD
D
EN
1
0
0
0
0
0
x
1
0
0
0
0
x
x
1
0
0
0
x
x
d
x
x
x
x
x
x
0
x
1
CAI CLK
x
x
x
x
0
1
↑
↑
↑
x
x
↑
Q
CAO
1
0
0
CAI⋅EN
d
*
Q
0
Q
0
count down
**
CBD41: CAO = CAI⋅EN⋅D0
CBD42: CAO = CAI⋅EN⋅D0⋅D1
CBD44: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3
CBD48: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7
CAO = 1 after terminal count, when CAI = 1 and EN = 1.
CAI⋅EN = shift registers: serial input; counters: CAscade In,
enable for multiplexors and counters, d = any pattern of 1s and
0s on an input or set of inputs, Q = output of flip-flop or latch,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
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Binary Counters
CBD41
LX2
D
Q
Q0
D0
LD
CLK
FD11
CAO
CAI
EN
CS
PS
ispLSI Macro Library Reference Manual
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Binary Counters
CBD42
QI[0:1]
QI[0:1]
QI0
QI0
LD
LX2
D
QI0
Q
D0
FD11
CAI
CLK
EN
QI0
Q0
QI1
Q1
PS
QI1
QI1
LX2
D
Q
QI1
D1
FD11
QI0
QI0
CS
QI1
CAO
ispLSI Macro Library Reference Manual
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Binary Counters
CBD44
QI[0:3]
QI[0:3]
QI0
QI0
LD
LX2
D
QI0
Q
D0
FD11
CAI
EN
CLK
PS
QI1
QI1
LX2
D
QI1
Q
D1
FD11
QI0
QI2
QI2
LX2
D
QI2
Q
D2
FD11
QI0
Q0
QI1
Q1
QI2
Q2
QI0
QI1
QI3
QI3
QI3
LX2
D
Q
Q3
QI3
D3
FD11
QI0
QI0
QI1
QI1
QI2
QI2
QI3
CAO
CS
ispLSI Macro Library Reference Manual
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Binary Counters
CBD48.1
QI[0:7]
QI[0:7]
QI0
QI0
LD
LX2
D
QI0
Q
D0
FD11
CAI
EN
CLK
PS
QI1
QI1
LX2
D
QI1
Q
D1
FD11
QI0
QI2
QI2
QI0
LX2
D
QI2
Q
QI1
Q0
Q1
D2
QI2
FD11
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI0
QI1
QI6
QI3
QI3
QI7
LX2
D
Q
D3
QI3
Q6
Q7
QI0
FD11
QI1
QI2
QI3
QI0
QI4
QI1
QI5
CAO
QI2
QI6
QI7
CS
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Binary Counters
CBD48.2
QI[0:7]
QI[0:7]
QI4
QI4
LD
LX2
D
QI4
Q
D4
FD11
QI0
QI1
QI2
CLK
QI3
CAI
EN
PS
QI5
QI5
LX2
D
QI5
Q
D5
FD11
QI0
QI1
QI2
QI3
QI4
QI6
QI6
LX2
D
QI6
Q
D6
FD11
QI0
QI1
QI2
QI3
QI4
QI5
QI7
QI7
LX2
D
Q
QI7
D7
FD11
QI0
QI1
QI2
QI3
QI4
QI5
QI6
CS
ispLSI Macro Library Reference Manual
138
Binary Counters
CBD516 and CBD616
CBD516
Function:
16-bit down counters with asynchronous clear and
enable. CBD616 also has CAO.
EN
Q0
Q1
Q2
Q3
Availability:
Q4
Q5
CBD516 and CBD616 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Q6
Q7
Schematics appear on the following pages.
Q8
Q9
Type: Hard
Q10
Q11
Logic Resources:
Q12
Macro
PT
GLB
Output
Level
CBD516
CBD616
*
**
4
5
16
18
1
2***
*
**
***
Q0-Qn-1: 2 PT per output.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0-Qn-1: 2 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
Q13
Q14
Q15
CD
CBD616
EN
Q0
Q1
Q2
Q3
Q4
Q5
Macro Port Definition:
Q6
CBD516 ([Q0..Q15],CLK,EN,CD);
CBD516_1 ([Q0..Q3],CLK,EN,CD);
CBD516_2 ([Q4..Q7],[Q0..Q3],CLK,EN,CD);
CBD516_3 ([Q8..Q11],[Q0..Q7],CLK,EN,CD);
CBD516_4 ([Q12..Q15],[Q0..Q11],CLK,EN,CD);
CBD616 ([Q0..Q15],CAO,CLK,EN,CD);
CBD616_1 ([Q0..Q3],CLK,EN,CD);
CBD616_2 ([Q4..Q7],[Q0..Q3],CLK,EN,CD);
CBD616_3 ([Q8..Q11],[Q0..Q7],CLK,EN,CD);
CBD616_4 (Q12,Q13,[Q0..Q11],CLK,EN,CD);
CBD616_5 (Q14,Q15,CAO,[Q0..Q13],CLK,EN,CD);
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
CAO
CD
Counting Ranges:
CBD516: 65,535-0. CBD616: 65,535-0.
ispLSI Macro Library Reference Manual
139
Binary Counters
Truth Table:
Gray areas (CAO) apply only to the CBD616.
Input
*
Output
CD
EN
CLK
1
0
0
x
0
1
x
x
↑
Q
CAO
0
EN
0
Q
count down *
CAO = 1 after terminal count, when EN = 1 and terminal count = 0.
EN = enable for multiplexors and counters,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
140
Binary Counters
CBD516.1
QI[0:15]
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI8
Q8
QI9
Q9
QI10
Q10
QI11
Q11
QI12
Q12
QI[0:14]
QI0
QI0
LX2
D
QI0
Q
EN
CD
FD21
CLK
CD
QI1
QI1
LX2
D
QI1
Q
QI0
CD
FD21
QI2
QI2
LX2
D
QI2
Q
QI0
QI1
CD
FD21
QI3
QI3
QI0
LX2
D
Q
QI3
QI1
QI13
QI2
CD
Q13
FD21
QI14
QI15
ispLSI Macro Library Reference Manual
Q14
Q15
141
Binary Counters
CBD516.2
QI[0:14]
QI[0:15]
QI4
QI4
QI0
LX2
D
Q
QI4
QI1
QI2
QI3
EN
CD
FD21
CLK
CD
QI5
QI5
QI0
LX2
D
Q
QI5
QI1
QI2
CD
QI3
FD21
QI4
QI6
QI6
QI0
LX2
D
Q
QI6
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI7
QI7
QI0
LX2
D
Q
QI7
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
ispLSI Macro Library Reference Manual
142
Binary Counters
CBD516.3
EN
QI[0:15]
QI[0:14]
QI8
QI8
QI0
LX2
D
QI8
Q
QI1
QI2
QI3
QI4
CD
FD21
CLK
CD
QI5
QI6
QI7
QI9
QI9
QI0
LX2
D
QI9
Q
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI10
QI10
QI0
LX2
D
QI10
Q
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI11
QI11
QI0
LX2
D
Q
QI11
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
ispLSI Macro Library Reference Manual
143
Binary Counters
CBD516.4
EN
QI[0:15]
QI[0:14]
QI12
QI12
QI0
LX2
D
QI12
Q
QI1
QI2
QI3
CLK
QI4
CD
CD
FD21
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI13
QI13
QI0
LX2
D
QI13
Q
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI14
QI14
QI0
LX2
D
Q
QI14
QI1
QI2
CD
QI3
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI15
QI0
LX2
D
Q
QI15
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI14
ispLSI Macro Library Reference Manual
144
Binary Counters
CBD616.1
QI[0:15]
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI8
Q8
QI9
Q9
QI10
Q10
QI11
Q11
QI12
Q12
QI13
Q13
QI14
Q14
QI15
Q15
QI[0:15]
QI0
QI0
LX2
D
QI0
Q
EN
CD
FD21
CLK
CD
QI1
QI1
LX2
D
QI1
Q
QI0
CD
FD21
QI2
QI2
LX2
D
QI2
Q
QI0
QI1
CD
FD21
QI3
QI3
QI0
LX2
D
QI3
Q
QI1
QI2
CD
FD21
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI14
QI15
CAO
ispLSI Macro Library Reference Manual
145
Binary Counters
CBD616.2
QI[0:15]
QI[0:15]
QI4
QI4
QI0
LX2
D
Q
QI4
QI1
QI2
QI3
EN
CD
FD21
CLK
CD
QI5
QI5
QI0
LX2
D
Q
QI5
QI1
QI2
CD
QI3
FD21
QI4
QI6
QI6
QI0
LX2
D
Q
QI6
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI7
QI7
QI0
LX2
D
Q
QI7
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
ispLSI Macro Library Reference Manual
146
Binary Counters
CBD616.3
EN
QI[0:15]
QI[0:15]
QI8
QI8
QI0
LX2
D
QI8
Q
QI1
QI2
QI3
QI4
CD
FD21
CLK
CD
QI5
QI6
QI7
QI9
QI9
QI0
LX2
D
QI9
Q
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI10
QI10
QI0
LX2
D
QI10
Q
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI11
QI11
QI0
LX2
D
Q
QI11
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
ispLSI Macro Library Reference Manual
147
Binary Counters
CBD616.4
EN
QI[0:15]
QI[0:15]
QI12
QI12
QI0
LX2
D
QI12
Q
QI1
QI2
QI3
CLK
QI4
CD
CD
FD21
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI13
QI13
QI0
LX2
D
QI13
Q
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI14
QI14
QI0
LX2
D
QI14
Q
QI1
QI2
CD
QI3
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI15
QI15
QI0
LX2
D
Q
QI15
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI14
ispLSI Macro Library Reference Manual
148
Binary Counters
CBU11, CBU12, CBU14, and CBU18
CBU11
Function:
CAI
1-, 2-, 4-, and 8-bit up counters with asynchronous clear,
CAI, and CAO.
Q0
CAO
CD
Availability:
CBU11, CBU12, CBU14, and CBU18 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
CBU12
CAI Q0
Schematics appear on the following pages.
Q1
CAO
Type:
CD
Soft:
Hard:
CBU11 and CBU12.
CBU14 and CBU18.
CBU14
Logic Resources:
*
**
Macro
PT
GLB
Output
Level
CBU14
CBU18
*
*
2
3
5
9
1**
1**
Q0-Qn-1: 2 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
CAI Q0
Q1
Q2
Q3
CAO
CD
CBU18
Macro Port Definition:
CAI Q0
CBU11 (Q0,CAO,CAI,CLK,CD);
CBU12 (Q0,Q1,CAO,CAI,CLK,CD);
CBU14 ([Q0..Q3],CAO,CAI,CLK,CD);
CBU14_1 ([Q0..Q3],CAI,CLK,CD);
CBU14_2 (CAO,[Q0..Q3],CAI);
CBU18 ([Q0..Q7],CAO,CAI,CLK,CD);
CBU18_1 ([Q0..Q3],CAI,CLK,CD);
CBU18_2 ([Q4..Q7],[Q0..Q3],CAI,CLK,CD);
CBU18_3 (CAO,[Q0..Q7],CAI);
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CAO
CD
Counting Ranges:
CBU11: 0-1. CBU12: 0-3. CBU14: 0-15. CBU18: 0-255.
ispLSI Macro Library Reference Manual
149
Binary Counters
Truth Table:
The truth table is the same for all CBU1s.
Input
CD
1
0
0
*
Output
CAI CLK
x
0
1
x
x
↑
Q
CAO
0
Q
count up
0
0
*
CAO = 1 after terminal count, when CAI = 1.
Q = output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
150
Binary Counters
CBU11
CLK
LX2
CD
D
Q
Q0
CAI
CD
FD21
CAO
ispLSI Macro Library Reference Manual
151
Binary Counters
CBU12
CLK
CD
QI[0:1]
QI0
LX2
D
Q
QI0
CAI
CD
FD21
QI0
Q0
QI1
Q1
QI1
QI0
LX2
D
Q
CD
FD21
QI1
QI0
QI1
ispLSI Macro Library Reference Manual
CAO
152
Binary Counters
CBU14
CLK
CD
QI[0:3]
QI0
LX2
D
Q
QI0
CAI
CD
FD21
QI1
QI0
LX2
D
Q
QI1
CD
FD21
QI2
QI0
QI1
LX2
D
Q
QI2
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
CD
FD21
QI3
QI0
QI1
LX2
D
Q
QI3
QI2
QI0
QI1
CD
FD21
QI2
CAO
QI3
ispLSI Macro Library Reference Manual
153
Binary Counters
CBU18
QI[0:7]
QI0
LX2
D
Q
QI0
CAI
CLK
CD
FD21
CD
QI1
QI0
LX2
D
Q
QI1
CD
FD21
QI2
QI0
QI1
LX2
D
Q
QI2
CD
FD21
QI3
QI0
QI1
LX2
D
Q
QI3
QI2
CD
FD21
QI4
QI0
QI0
QI1
QI2
LX2
D
Q
QI1
QI3
QI2
CD
FD21
QI5
Q0
QI4
Q1
Q2
QI0
QI3
QI1
QI2
LX2
D
Q
Q3
QI5
QI4
QI3
Q4
QI4
QI5
CD
FD21
QI6
QI6
QI0
Q5
Q6
QI1
QI7
QI2
QI3
LX2
D
Q
QI0
QI4
QI1
QI5
QI2
CD
FD21
QI3
QI7
QI4
QI0
QI5
QI1
QI6
QI2
QI3
Q7
QI6
CAO
QI7
LX2
D
Q
QI7
QI4
QI5
QI6
CD
FD21
ispLSI Macro Library Reference Manual
154
Binary Counters
CBU21, CBU22, CBU24, and CBU28
CBU21
Function:
1-, 2-, 4-, and 8-bit up counters with asynchronous clear,
enable, CAI, and CAO.
CBU21, CBU22, CBU24, and CBU28 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
Schematics appear on the following pages.
CBU22
CAI Q0
EN
Type:
Soft:
Hard:
Q1
CAO
CD
CBU21 and CBU22.
CBU24 and CBU28.
Logic Resources:
**
EN
CAO
CD
Availability:
*
CAI Q0
CBU24
Macro
PT
GLB
Output
Level
CBU24
CBU28
*
*
2
3
5
9
1**
1**
Q0-Qn-1: 2 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
CAI Q0
Q1
Q2
EN
Q3
CAO
CD
CBU28
Macro Port Definition:
CBU21 (Q0,CAO,CAI,CLK,EN,CD);
CBU22 (Q0,Q1,CAO,CAI,CLK,EN,CD);
CBU24 ([Q0..Q3],CAO,CAI,CLK,EN,CD);
CBU24_1 ([Q0..Q3],CAI,CLK,EN,CD);
CBU24_2 (CAO,[Q0..Q3],CAI,EN);
CBU28 ([Q0..Q7],CAO,CAI,CLK,EN,CD);
CBU28_1 ([Q0..Q3],CAI,CLK,EN,CD);
CBU28_2 ([Q4..Q7],[Q0..Q3],CAI,CLK,EN,CD);
CBU28_3 (CAO,[Q0..Q7],CAI,EN);
CAI Q0
Q1
Q2
Q3
Q4
Q5
Q6
EN
Q7
CAO
CD
Counting Ranges:
CBU21: 0-1. CBU22: 0-3. CBU24: 0-15. CBU28: 0-255.
ispLSI Macro Library Reference Manual
155
Binary Counters
Truth Table:
The truth table is the same for all CBU2s.
Input
*
CD
EN
1
0
0
0
x
0
x
1
Output
CAI CLK
x
x
0
1
x
x
x
↑
Q
CAO
0
Q
Q
count up
0
0
0
*
CAO = 1 after terminal count, when CAI = 1 and EN = 1.
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
156
Binary Counters
CBU21
CAI
LX2
D
Q
Q0
EN
CLK
CD
FD21
CD
CAO
ispLSI Macro Library Reference Manual
157
Binary Counters
CBU22
QI[0:1]
QI0
LX2
D
QQI0
CAI
EN
CD
FD21
CLK
QI0
Q0
QI1
Q1
CD
QI1
QI0
LX2
D
Q
QI1
CD
FD21
QI0
QI1
CAO
ispLSI Macro Library Reference Manual
158
Binary Counters
CBU24
QI[0:3]
QI0
LX2
D
QQI0
CAI
EN
CD
FD21
CLK
CD
QI1
QI0
LX2
D
QQI1
CD
FD21
QI2
QI0
LX2
D
Q
QI2
QI0
Q0
QI1
Q1
QI1
CD
FD21
QI2
QI3
QI0
QI3
LX2
D
Q
QI3
Q2
Q3
QI0
QI1
QI2
QI1
CD
FD21
QI2
QI3
ispLSI Macro Library Reference Manual
CAO
159
Binary Counters
CBU28
QI[0:7]
QI0
CAI
LX2
QI0
Q
D
EN
CLK
CD
FD21
CD
QI1
QI0
LX2
QQI1
D
CD
FD21
QI2
QI0
QI1
LX2
QQI2
D
CD
FD21
QI3
QI0
QI1
QI2
LX2
QQI3
D
CD
FD21
QI4
QI0
QI1
QI2
LX2
QQI4
D
QI0
QI3
CD
QI1
Q0
Q1
FD21
QI5
QI0
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI1
QI2
QI3
LX2
D
QI5
Q
QI4
CD
FD21
QI6
QI6
QI0
Q6
QI1
QI7
QI2
QI3
LX2
D
Q7
QI6
Q
QI4
QI5
CD
FD21
QI7
QI0
QI0
QI1
QI1
QI2
QI2
QI3
QI3
QI4
LX2
D
QI7
Q
QI4
QI5
QI5
QI6
QI6
CD
FD21
CAO
QI7
ispLSI Macro Library Reference Manual
160
Binary Counters
CBU31, CBU32, CBU34, and CBU38
CBU31
CBU32
Function:
1-, 2-, 4-, and 8-bit up counters with asynchronous clear,
enable, parallel data load, synchronous preset, CAI, and
CAO.
PS
CAI
D0
Q0
Availability:
LD CAO
CBU31, CBU32, CBU34, and CBU38 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
EN
PS
CAI
D0
Q0
D1
Q1
LD CAO
EN
CD
Schematics appear on the following pages.
CD
Type:
Soft:
Hard:
CBU31 and CBU32.
CBU34 and CBU38.
CBU34
Logic Resources:
*
**
CBU38
PS
PS
Macro
PT
GLB
Output
Level
CBU34
CBU38
*
*
2
3
5
9
1**
1**
Q0-Qn-1: 4 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
CAI
CAI
D0
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
D3
Q3
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LD CAO
EN
CD
Macro Port Definition:
CBU31 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,CD);
CBU32 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,CD);
CBU34 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,CD);
CBU34_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);
CBU34_2 (CAO,[Q0..Q3],CAI,EN);
CBU38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,CD);
CBU38_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);
CBU38_2 (Q4,Q5,[Q0..Q3],D4,D5,CAI,CLK,PS,LD,EN,CD);
CBU38_3 (Q6,Q7,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,CD);
CBU38_4 (CAO,[Q0..Q7],CAI,EN);
LD CAO
EN
CD
Counting Ranges:
CBU31: 0-1. CBU32: 0-3. CBU34: 0-15. CBU38: 0-255.
ispLSI Macro Library Reference Manual
161
Binary Counters
Truth Table:
The truth table is the same for all CBU3s.
Input
Output
CD
PS
LD
D
EN
1
0
0
0
0
0
x
1
0
0
0
0
x
x
1
0
0
0
x
x
d
x
x
x
x
x
x
0
x
1
CAI CLK
x
x
x
x
0
1
x
↑
↑
x
x
↑
Q
CAO
0
0
1
CAI⋅EN
d
*
Q
0
Q
0
count up
**
*
CBU31: CAO = CAI⋅EN⋅D0
CBU32: CAO = CAI⋅EN⋅D0⋅D1
CBU34: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3
CBU38: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7
**
CAO = 1 after terminal count, when CAI = 1 and EN = 1.
CAI⋅EN = shift registers: serial input, counters:
CAscade In, enable for multiplexors and counters,
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
162
Binary Counters
CBU31
LX2
D
Q
Q0
D0
LD
CLK
CAI
CD
FD21
CD
EN
PS
CAO
ispLSI Macro Library Reference Manual
163
Binary Counters
CBU32
QI[0:1]
QI0
LD
LX2
D
Q
QI0
D0
CD
FD21
CLK
CAI
CD
EN
QI0
QI1
QI1
LX2
D
Q
D1
Q0
Q1
QI1
QI0
QI0
CD
FD21
QI1
CAO
PS
ispLSI Macro Library Reference Manual
164
Binary Counters
CBU34
QI[0:3]
QI0
LD
LX2
QI0
Q
D
D0
CD
CLK
CAI
FD21
CD
EN
PS
QI1
LX2
QQI1
D
D1
CD
FD21
QI0
QI2
LX2
QQI2
D
D2
CD
FD21
QI0
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI1
QI3
LX2
QQI3
D
QI0
D3
QI1
QI0
CD
FD21
QI2
QI3
CAO
QI1
QI2
ispLSI Macro Library Reference Manual
165
Binary Counters
CBU38.1
QI[0:7]
QI0
LD
LX2
D
Q
QI0
D0
CD
FD21
CLK
CAI
CD
EN
PS
QI1
LX2
D
Q
QI1
D1
CD
QI0
FD21
QI2
LX2
D
Q
QI0
Q0
QI1
Q1
QI2
QI2
Q2
D2
QI3
CD
QI0
Q3
FD21
QI1
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI3
LX2
QQI3
D
D3
QI0
CD
QI0
FD21
QI1
QI1
QI2
QI2
QI3
QI4
QI5
CAO
QI6
QI7
ispLSI Macro Library Reference Manual
166
Binary Counters
CBU38.2
QI[0:7]
QI4
LD
LX2
QI4
Q
D
D4
QI0
QI1
CD
FD21
CLK
CD
QI2
QI3
CAI
EN
PS
QI5
LX2
QQI5
D
D5
CD
QI0
FD21
QI1
QI2
QI3
QI4
QI6
LX2
QI6
Q
D
D6
CD
QI0
FD21
QI1
QI2
QI3
QI4
QI5
QI7
LX2
QI7
Q
D
D7
CD
QI0
FD21
QI1
QI2
QI3
QI4
QI5
QI6
ispLSI Macro Library Reference Manual
167
Binary Counters
CBU41, CBU42, CBU44, and CBU48
CBU41
CBU42
Function:
1-, 2-, 4-, and 8-bit up counters with synchronous clear,
enable, parallel data load, synchronous preset, CAI, and
CAO.
Availability:
PS
CAI
CAI
Q0
D0
LD CAO
CBU41, CBU42, CBU44, and CBU48 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
EN
Schematics appear on the following pages.
PS
D0
Q0
D1
Q1
LD CAO
EN
CS
CS
Type:
Soft:
Hard:
CBU41 and CBU42.
CBU44 and CBU48.
CBU44
PS
Logic Resources:
CAI
*
**
Macro
PT
GLB
Output
Level
CBU44
CBU48
*
*
2
3
5
9
1**
1**
Q0-Qn-1: 4 PT per output.
CAO: 1 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
(CAO is a 2-level output).
Macro Port Definition:
CBU41 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,CS);
CBU42 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,CS);
CBU44 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,CS);
CBU44_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);
CBU44_2 (CAO,[Q0..Q3],CAI,EN);
CBU48 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,CS);
CBU48_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);
CBU48_2 (Q4,Q5,[Q0..Q3],D4,D5,CAI,CLK,PS,LD,EN,CS);
CBU48_3 (Q6,Q7,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,CS);
CBU48_4 (CAO,[Q0..Q7],CAI,EN);
CBU48
PS
CAI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
LD CAO
D6
Q6
EN
D7
Q7
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CS
LD CAO
EN
CS
Counting Ranges:
CBU41: 0-1. CBU42: 0-3. CBU44: 0-15. CBU48: 0-255.
ispLSI Macro Library Reference Manual
168
Binary Counters
Truth Table:
The truth table is the same for all CBU4s.
Input
Output
PS
CS
LD
D
EN
CAI
CLK
1
0
0
0
0
0
x
1
0
0
0
0
x
x
1
0
0
0
x
x
d
x
x
x
x
x
x
0
x
1
x
x
x
x
0
1
↑
↑
↑
x
x
↑
Q
CAO
1
CAI⋅EN
0
0
d
*
Q
0
Q
0
count up
**
*
CBU41: CAO = CAI⋅EN⋅D0
CBU42: CAO = CAI⋅EN⋅D0⋅D
CBU44: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3
CBU48: CAO = CAI⋅EN⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7
**
CAO = 1 after terminal count, when CAI = 1 and EN = 1.
CAI⋅EN = shift registers: serial input, counters:
CAscade In, enable for multiplexors and counters,
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
169
Binary Counters
CBU41
LX2
D
Q
Q0
D0
CLK
FD11
LD
CAI
EN
CS
PS
CAO
ispLSI Macro Library Reference Manual
170
Binary Counters
CBU42
QI[0:1]
QI0
LD
LX2
D
Q
QI0
D0
FD11
CAI
CLK
EN
PS
QI1
LX2
D
Q
QI1
D1
FD11
QI0
Q0
QI0
QI1
Q1
QI0
CS
QI1
CAO
ispLSI Macro Library Reference Manual
171
Binary Counters
CBU44
QI[0:3]
QI0
LD
LX2
D
Q
QI0
D0
FD11
CAI
EN
CLK
PS
QI1
LX2
D
Q
QI1
D1
FD11
QI0
QI2
LX2
D
Q
QI2
D2
FD11
QI0
QI1
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI3
LX2
D
QQI3
D3
FD11
QI0
QI1
QI2
QI0
QI1
QI2
CS
QI3
ispLSI Macro Library Reference Manual
CAO
172
Binary Counters
CBU48.1
QI[0:7]
QI0
LD
LX2
QQI0
D
D0
FD11
CAI
EN
CLK
PS
QI1
LX2
QI1
Q
D
D1
FD11
QI0
QI2
QI0
LX2
QI2
Q
D
QI1
Q0
Q1
D2
FD11
QI2
Q2
QI0
QI3
QI1
QI4
QI5
QI6
QI3
QI7
LX2
QI3
Q
D
Q3
Q4
Q5
Q6
Q7
D3
FD11
QI0
QI0
QI1
QI1
QI2
QI2
QI3
QI4
QI5
CAO
QI6
CS
QI7
ispLSI Macro Library Reference Manual
173
Binary Counters
CBU48.2
QI[0:7]
QI4
LD
LX2
QQI4
D
PS
D4
FD11
QI0
CLK
QI1
QI2
QI3
CAI
EN
QI5
LX2
QQI5
D
D5
FD11
QI0
QI1
QI2
QI3
QI4
QI6
LX2
QI6
Q
D
D6
FD11
QI0
QI1
QI2
QI3
QI4
QI5
QI7
LX2
QQI7
D
D7
FD11
QI0
QI1
QI2
QI3
QI4
QI5
QI6
CS
ispLSI Macro Library Reference Manual
174
Binary Counters
CBU516 and CBU616
CBU516
Function:
EN
16-bit up counters with asynchronous clear and enable.
CBU616 also has CAO.
Q0
Q1
Q2
Q3
Q4
Availability:
Q5
CBU516 and CBU616 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Q6
Q7
Q8
Schematics appear on the following pages.
Q9
Q10
Type: Hard
Q11
Q12
Logic Resources:
*
**
Q13
Macro
PT
GLB
Output
Level
Q14
CBU516
CBU616
*
*
4
5
16
18
1
2**
Q15
Q0-Qn-1: 2 PT per output.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
CD
CBU616
EN
Q0
Q1
Macro Port Definition:
Q2
CBU516 ([Q0..Q15],CLK,EN,CD);
CBU516_1 ([Q0..Q3],CLK,EN,CD);
CBU516_2 ([Q4..Q7],[Q0..Q3],CLK,EN,CD);
CBU516_3 ([Q8..Q11],[Q0..Q7],CLK,EN,CD);
CBU516_4 ([Q12..Q15],[Q0..Q11],CLK,EN,CD);
CBU616 ([Q0..Q15],CAO,CLK,EN,CD);
CBU616_1 ([Q0..Q3],CLK,EN,CD);
CBU616_2 ([Q4..Q7],[Q0..Q3],CLK,EN,CD);
CBU616_3 ([Q8..Q11],[Q0..Q7],CLK,EN,CD);
CBU616_4 (Q12,Q13,[Q0..Q11],CLK,EN,CD);
CBU616_5 (Q14,Q15,CAO,[Q0..Q13],CLK,EN,CD);
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Counting Ranges:
CBU516: 0-65,535. CBU616: 0-65,535.
ispLSI Macro Library Reference Manual
CAO
CD
175
Binary Counters
Truth Table:
Gray areas (CAO) apply only to the CBU616.
Input
*
Output
CD
EN
CLK
Q
CAO
1
0
0
x
0
1
CLK
x
0
Q
count up
0
0
*
↑
CAO = 1 after terminal count,
when EN = 1 and each terminal count bit = 1.
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
176
Binary Counters
CBU516.1
QI[0:15]
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI0
LX2
D
Q
QI0
EN
CD
FD21
CLK
CD
QI1
QI0
LX2
D
Q
QI1
CD
FD21
QI2
QI0
LX2
D
Q
QI2
QI8
Q8
QI1
QI9
CD
FD21
QI10
QI3
QI0
QI11
LX2
D
Q
QI1
QI3
QI12
Q9
Q10
Q11
Q12
QI2
CD
FD21
QI13
QI14
QI15
ispLSI Macro Library Reference Manual
Q13
Q14
Q15
177
Binary Counters
CBU516.2
EN
QI[0:15]
CLK CD
QI4
LX2
D
Q
QI4
QI0
QI1
CD
QI2
FD21
QI3
QI5
LX2
D
Q
QI5
QI0
QI1
CD
FD21
QI2
QI3
QI4
QI6
LX2
D
Q
QI6
QI0
QI1
CD
FD21
QI2
QI3
QI4
QI5
QI7
LX2
D
Q
QI7
QI0
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
ispLSI Macro Library Reference Manual
178
Binary Counters
CBU516.3
EN
QI[0:15]
CLK CD
QI8
QI0
LX2
D
Q
QI8
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI9
QI0
LX2
D
Q
QI9
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI10
QI0
LX2
D
Q
QI10
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI11
QI0
LX2
D
Q
QI11
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
ispLSI Macro Library Reference Manual
179
Binary Counters
CBU516.4
CLK CD
EN
QI[0:15]
QI12
QI0
LX2
D
Q
QI12
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI13
QI0
LX2
D
Q
QI13
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI14
QI0
LX2
D
Q
QI14
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI15
QI0
LX2
D
Q
QI15
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI14
ispLSI Macro Library Reference Manual
180
Binary Counters
CBU616.1
QI[0:15]
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI8
Q8
QI9
Q9
QI10
Q10
QI11
Q11
QI12
Q12
QI13
Q13
QI14
Q14
QI0
LX2
D
Q
QI0
EN
CD
FD21
CLK
CD
QI1
QI0
LX2
D
Q
QI1
CD
FD21
QI2
QI0
LX2
D
Q
QI2
QI1
CD
FD21
QI3
QI0
LX2
D
Q
QI1
QI3
QI2
CD
FD21
QI15
Q15
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI14
QI15
CAO
ispLSI Macro Library Reference Manual
181
Binary Counters
CBU616.3
EN
QI[0:15]
CLK CD
QI4
LX2
D
Q
QI4
QI0
QI1
CD
FD21
QI2
QI3
QI5
LX2
D
Q
QI5
QI0
QI1
CD
FD21
QI2
QI3
QI4
QI6
LX2
D
Q
QI6
QI0
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI7
LX2
D
Q
QI7
QI0
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
ispLSI Macro Library Reference Manual
182
Binary Counters
CBU616.4
EN
QI[0:15]
CLK CD
QI8
QI0
LX2
D
Q
QI8
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI9
QI0
LX2
D
Q
QI9
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI10
QI0
LX2
D
Q
QI10
QI1
QI2
CD
FD21
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI11
QI0
LX2
D
Q
QI11
QI1
QI2
QI3
CD
FD21
QI4
QI5
QI6
QI7
QI8
QI9
QI10
ispLSI Macro Library Reference Manual
183
Binary Counters
CBU716
CBU716
Function:
CAI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CBU716 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
D4
Q4
D5
Q5
Schematics appear on the following pages.
D6
Q6
D7
Q7
D8
Q8
Macro Port Definition:
D9
Q9
CBU716 ([Q0..Q15],CAO,CLK,EN,LD,CD,CAI,[D0..D15]);
CBU716_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CD);
CBU716_2 ([Q4..Q7],[Q0..Q3],[D4..D7],CAI,CLK,
LD,EN,CD);
CBU716_3 ([Q8..Q11],[Q0..Q7],[D8..D11],CAI,CLK,
LD,EN,CD);
CBU716_4 ([Q12..Q15],[Q0..Q11],[D12..D15],
CAI,CLK,LD,EN,CD);
CBU716_5 (CAO,[Q0..Q15],CAI,EN);
D10 Q10
16-bit up counter with asynchronous clear, enable,
parallel data load and carry out.
Availability:
Type: Soft
D11 Q11
D12 Q12
D13 Q13
D14 Q14
D15 Q15
CAO
Counting Ranges:
LD
0 - 65,535
EN
CD
Truth Table:
Input
CD LD
1
0
0
0
0
*
**
X
1
0
0
0
D
EN
X
d
X
X
X
X
X
0
X
1
Output
CAI CLK
X
X
X
0
1
X
↑
X
X
↑
Q
CAO
0
d
Q
Q
count up
CAI • EN
*
0
0
**
CBU716: CAO = CAI, EN, D0, D1, D2, D3, D4, D5,
D6, D7, D8, D9, D10, D11, D12,
D13, D14, D15.
CAO = 1 after terminal count, when CAI = 1 and EN = 1.
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
184
Binary Counters
CBU716.1
QI[0:15]
QI0
LD
LX2
D
D0
CD
FD21
CAI
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI8
Q8
QI9
Q9
QI10
Q10
QI11
Q11
QI12
Q12
QI13
Q13
QI14
Q14
QI15
Q15
QQI0
CLK
EN
CD
QI1
LX2
D
QQI1
D1
CD
FD21
QI0
QI2
LX2
D
QQI2
D2
CD
FD21
QI0
QI1
QI3
LX2
D
QQI3
D3
CD
FD21
QI0
QI1
QI2
QI0
QI1
QI4
QI2
LX2
D
QI4
Q
D4
QI3
QI4
QI5
QI0
QI1
CD
FD21
QI6
QI7
QI2
QI8
QI3
QI9
CAO
QI10
QI11
EN
QI12
QI13
QI14
QI15
ispLSI Macro Library Reference Manual
185
Binary Counters
CBU716.2
QI[0:15]
QI5
LD
LX2
QQI5
D
D5
CD
FD21
QI0
QI1
QI2
CLK
CD
QI3
QI4
CAI
EN
QI6
LX2
QQI6
D
D6
CD
QI0
FD21
QI1
QI2
QI3
QI4
QI5
QI7
LX2
QQI7
D
D7
CD
FD21
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI8
LX2
QI8
Q
D
D8
QI0
CD
QI1
FD21
QI2
QI3
QI4
QI5
QI6
QI7
ispLSI Macro Library Reference Manual
186
Binary Counters
CBU716.3
QI[0:15]
QI9
LD
LX2
QQI9
D
D9
CD
FD21
QI0
QI1
QI2
CLK
CD
QI3
QI4
QI5
QI6
QI7
QI8
CAI
EN
QI10
LX2
QQI10
D
D10
CD
FD21
QI0
QI1
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI11
LX2
QQI11
D
D11
QI0
QI1
CD
FD21
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
ispLSI Macro Library Reference Manual
187
Binary Counters
CBU716.4
QI[0:15]
QI12
LD
LX2
QQI12
D
D12
CD
QI0
FD21
QI1
CLK
QI2
CD
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
CAI
EN
QI13
LX2
D
QQI13
D13
QI0
QI1
CD
FD21
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
ispLSI Macro Library Reference Manual
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Binary Counters
CBU716.5
QI[0:15]
QI14
LD
LX2
D
QQI14
D14
CD
FD21
QI0
QI1
QI2
CLK
CD
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
CAI
EN
QI15
LX2
D
QQI15
D15
QI0
QI1
CD
FD21
QI2
QI3
QI4
QI5
QI6
QI7
QI8
QI9
QI10
QI11
QI12
QI13
QI14
ispLSI Macro Library Reference Manual
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Binary Counters
CBUD1, CBUD2, CBUD4, and CBUD8
CBUD1
CBUD2
Function:
1-, 2-, 4-, and 8-bit up/down counters with asynchronous
clear, synchronous clear, enable, parallel data load,
synchronous preset, CAI, and CAO.
Availability:
CBUD1, CBUD2, CBUD4, and CBUD8 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
PS
CAI
PS
CAI
D0
D0
Q0
DN/UP
D1
Q1
LD CAO
DN/UP
EN
LD CAO
Q0
EN
CD CS
CD CS
Schematics appear on the following pages.
CBUD4
Type:
Soft:
Hard:
CBUD1 and CBUD2.
CBUD4 and CBUD8.
PS
CAI
Logic Resources:
*
**
Macro
PT
GLB
Output
Level
CBUD4
CBUD8
*/out
*/out
2
4
5
9
1**
1**
Q0: 4 PT.
Q1-Qn-1: 5 PT.
CAO: 2 PT.
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
(CAO is a 2-level output).
D0
Q0
D1
Q1
D2
Q2
D3
Q3
DN/UP
LD CAO
EN
CD CS
CBUD8
PS
CAI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
DN/UP
LD CAO
EN
CD CS
Macro Port Definition:
CBUD1 (Q0,CAO,D0,CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD2 (Q0,Q1,CAO,D0,D1,CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD4 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD4_1 ([Q0..Q2],[D0..D2],CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD4_2 (Q3,CAO,[Q0..Q2],D3,CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD8 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD8_1 ([Q0..Q2],[D0..D2],CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD8_2 [Q3..Q5],[Q0..Q2],[D3..D5],CAI,CLK,PS,LD,EN,DNUP,CD,CS);
CBUD8_3 (Q6,Q7,CAO,[Q0..Q5],D6,D7,CAI,CLK,PS,LD,EN,DNUP,CD,CS);
Counting Ranges:
CBUD1: 0↔1. CBUD2: 0↔3. CBUD4: 0↔15. CBUD8: 0↔255.
ispLSI Macro Library Reference Manual
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Binary Counters
Truth Table:
The truth table is the same for all CBUDs.
Input
Output
CD
PS
CS
LD
D
EN
CAI
DNUP
CLK
Q
CAO
1
0
0
0
0
0
0
0
x
1
0
0
0
0
0
0
x
x
1
0
0
0
0
0
x
x
x
1
0
0
0
0
x
x
x
d
x
x
x
x
x
x
x
x
0
x
1
1
x
x
x
x
x
0
1
1
x
x
x
x
x
x
0
1
x
0
1
0
d
Q
Q
count up
count down
CAI⋅EN⋅DNUP
CAI⋅EN⋅DNUP
CAI⋅EN⋅DNUP
*
0
0
**
**
↑
↑
↑
x
↑
↑
↑
*
CBUD1: CAO = CAI⋅EN⋅(DNUP⋅D0+DNUP⋅D0)
CBUD2: CAO = CAI⋅EN⋅(DNUP⋅D0⋅D1+DNUP⋅D0⋅D1)
CBUD4: CAO = CAI⋅EN⋅(DNUP⋅D0⋅D1⋅D2⋅D3+DNUP⋅D0⋅D1⋅D2⋅D3)
CBUD8: CAO = CAI⋅EN⋅(DNUP⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7+
DNUP⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7)
**
CAO = 1 after terminal count, when CAI = 1 and EN = 1.
CAI⋅EN = shift registers: serial input; counters: CAcadeIn, enable for multiplexors and counters,
d = any pattern of 1s and 0s on an input or set of inputs, Q = output of flip-flop or latch, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
191
Binary Counters
CBUD1
LX2
D
Q
Q0
D0
LD
CLK
CD
FD21
CD
CAI
EN
CS
PS
UP
CAO
DNUP
ispLSI Macro Library Reference Manual
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Binary Counters
CBUD2
QI[0:1]
QI[0:1]
QI0
QI0
LD
LX2
D
D0
QI0
Q
CD
FD21
CLK
CD
CAI
EN
PS
QI1
QI1
LX2
D
Q
QI1
QI0
D1
CD
FD21
QI1
Q0
Q1
QI0
QI0
QI0
QI1
CS
DNUP
CAO
QI0
UP
ispLSI Macro Library Reference Manual
QI1
193
Binary Counters
CBUD4.1
QI[0:3]
QI0
QI[0:3]
QI0
LD
LX2
D
QI0
Q
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
D0
CD
FD21
CLK
CD
CAI
EN
PS
QI1
QI1
LX2
D
Q
QI1
D1
CD
FD21
QI0
QI0
QI1
QI2
QI3
QI0
CAO
CS
QI0
DNUP
QI1
QI2
UP
QI3
ispLSI Macro Library Reference Manual
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Binary Counters
CBUD4.2
QI[0:3]
QI[0:3]
QI2
QI2
LD
LX2
D
QI2
Q
D2
CD
FD21
CLK
QI0
CD
QI1
CAI
EN
QI0
QI1
PS
QI3
QI3
LX2
D
Q
QI3
D3
CD
FD21
QI0
QI1
QI2
UP
QI0
QI1
QI2
CS
DNUP
ispLSI Macro Library Reference Manual
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Binary Counters
CBUD8.1
QI[0:7]
QI0
QI0
Q0
QI[0:7]
QI1
QI0
LD
LX2
D
Q1
QI0
Q
QI2
Q2
D0
QI3
CD
FD21
CLK
CD
QI4
Q3
Q4
CAI
QI5
EN
QI6
PS
Q5
Q6
QI1
QI7
QI1
LX2
D
Q
Q7
QI1
QI0
QI1
D1
QI2
CD
FD21
QI3
QI4
QI0
QI5
QI6
QI7
QI0
CAO
QI0
QI1
QI2
CS
QI3
DNUP
QI4
QI5
UP
QI6
QI7
ispLSI Macro Library Reference Manual
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Binary Counters
CBUD8.2
QI[0:7]
QI[0:7]
QI2
QI2
LD
LX2
D
QI2
Q
D2
CD
FD21
CLK
QI0
CD
QI1
CAI
EN
QI0
QI1
PS
QI3
QI3
LX2
D
Q
QI3
D3
CD
FD21
QI0
QI1
QI2
UP
QI0
QI1
QI2
CS
DNUP
ispLSI Macro Library Reference Manual
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Binary Counters
CBUD8.3
QI[0:7]
QI[0:7]
QI4
QI4
LD
LX2
D
QI4
Q
D4
CD
FD21
CLK
QI0
CD
QI1
QI2
QI3
CAI
EN
QI0
QI1
QI2
QI3
PS
QI5
QI5
LX2
D
Q
QI5
D5
CD
FD21
QI0
QI1
QI2
QI3
QI4
UP
QI0
QI1
QI2
QI3
QI4
CS
DNUP
ispLSI Macro Library Reference Manual
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Binary Counters
CBUD8.4
QI[0:7]
QI[0:7]
QI6
QI6
LD
LX2
D
D6
QI6
Q
CD
FD21
CLK
CD
QI0
QI1
QI2
QI3
QI4
QI5
CAI
EN
QI0
QI1
QI2
QI3
QI4
QI5
PS
QI7
QI7
LX2
D7
D
Q
QI7
CD
FD21
QI0
QI1
QI2
QI3
QI4
QI5
QI6
UP
QI0
QI1
QI2
QI3
QI4
QI5
QI6
CS
DNUP
ispLSI Macro Library Reference Manual
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Decade Counters
Decade Counters
CDD14 and CDD18
CDD14
D0
Q0
D1
Q1
4- and 8-bit decade down counters with asynchronous
clear, enable, and parallel data load.
D2
Q2
D3
Q3
Availability:
LD
Function:
EN
CDD14 and CDD18 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
CD
Schematics appear on the following pages.
CDD18
Type: Hard
Logic Resources:
*
**
Macro
PT
GLB
Output
Level
CDD14
CDD18
*
**
2
4
4
8
1
1
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0: 5 PT
Q1: 6 PT
Q2: 5 PT
Q3: 5 PT
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0: 5 PT
Q1: 6 PT
Q2: 5 PT
Q3: 5 PT
Q4: 6 PT
Q5: 6 PT
Q6: 5 PT
Q7: 5 PT
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LD
EN
CD
Macro Port Definition:
CDD14 ([Q0..Q3],[D0..D3],CLK,LD,EN,CD);
CDD14_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,CD);
CDD14_2 (Q3,D3,[Q0..Q2],CLK,LD,EN,CD);
CDD18 ([Q0..Q7],[D0..D7],CLK,LD,EN,CD);
CDD18_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,CD);
CDD18_2 ([Q3..Q5],[D3..D5],[Q0..Q2],Q6,Q7,CLK,LD,EN,CD);
CDD18_3 (Q6,Q7,D6,D7,[Q0..Q5],CLK,LD,EN,CD);
Counting Ranges:
CDD14: 9-0. CDD18: 99-0.
ispLSI Macro Library Reference Manual
200
Decade Counters
Truth Table:
The truth table is the same for both CDD1s.
Input
Output
CD
LD
D
EN
CLK
Q
1
0
0
0
x
1
0
0
x
d
x
x
x
x
0
1
x
↑
x
↑
0
d
Q
count down
Valid states for each 4-bit digit are 0-9.
Loading higher hexadecimal input values (A-F)
clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
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Decade Counters
CDD14
QI[0:3]
QI[0:3]
QI0
QI0
HOLD0
LD
LX2
D0
D
QI0
Q
LOAD0
QI3
CD
FD21
CLK
CD
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D1
D
QI1
Q
LOAD1
QI1
CD
FD21
QI0
QI3
QI2
QI0
QI3
QI2
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D2
D
QI2
Q
LOAD2
QI3
CD
FD21
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D3
D
QI3
Q
LOAD3
QI2
QI1
CD
FD21
QI0
Q0
QI0
QI1
QI2
QI3
Q1
Q2
QI2
QI3
Q3
QI3
QI1
ispLSI Macro Library Reference Manual
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Decade Counters
CDD18.1
QI[0:7]
QI[0:7]
QI0
QI0
HOLD0
LD
LX2
D0
D
QI0
Q
LOAD0
QI3
CD
FD21
CLK
CD
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D1
D
QI1
Q
LOAD1
QI1
CD
FD21
QI0
QI3
QI2
QI0
QI3
QI2
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D2
D
QI2
Q
LOAD2
QI3
CD
FD21
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
D3
LX2
D
QI0
LOAD3
QI2
QI3
Q
CD
FD21
QI1
QI1
Q0
Q1
QI0
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI3
QI2
QI3
QI1
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Decade Counters
CDD18.2
QI[0:7]
QI[0:7]
QI4
QI4
HOLD4
LD
LX2
D
Q
QI4
D4
QI7
CD
FD21
CLK
QI3
CD
QI2
QI1
QI0
EN
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI5
HOLD5
LX2
D
Q
QI5
D5
QI5
QI4
CD
FD21
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDD18.3
QI[0:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
D6
CD
FD21
QI7
CLK
QI5
CD
QI4
QI3
QI2
QI1
QI0
EN
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI7
HOLD7
LX2
D
Q
QI7
D7
QI6
QI5
CD
FD21
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDD24 and CDD28
CDD24
Function:
D0
Q0
4- and 8-bit decade down counters with synchronous
clear, enable, and parallel data load.
D1
Q1
D2
Q2
D3
Q3
Availability:
CDD24 and CDD28 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
LD
EN
Schematics appear on the following pages.
CS
Type: Hard
CDD28
Logic Resources:
*
**
Macro
PT
GLB
Output
Level
CDD24
CDD28
*
**
2
3
4
8
1
1
CLK: 1 PT per GLB if Product Term Clock is used.
Q0: 5 PT
Q1: 6 PT
Q2: 5 PT
Q3: 5 PT
CLK: 1 PT per GLB if Product Term Clock is used.
Q0: 5 PT
Q1: 6 PT
Q2: 5 PT
Q3: 5 PT
Q4: 6 PT
Q5: 6 PT
Q6: 5 PT
Q7: 5 PT
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
Macro Port Definition:
LD
CDD24 ([Q0..Q3],[D0..D3],CLK,LD,EN,CS);
CDD24_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,CS);
CDD24_2 (Q3,D3,[Q0..Q2],CLK,LD,EN,CS);
CDD28 ([Q0..Q7],[D0..D7],CLK,LD,EN,CS);
CDD28_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,CS);
CDD28_2 ([Q3..Q5],[D3..D5],[Q0..Q2],Q6,Q7,CLK,LD,EN,CS);
CDD28_3 (Q6,Q7,D6,D7,[Q0..Q5],CLK,LD,EN,CS);
EN
CS
Counting Ranges:
CDD24: 9-0. CDD28: 99-0.
ispLSI Macro Library Reference Manual
206
Decade Counters
Truth Table:
The truth table is the same for both CDD2s.
Input
Output
CS
LD
D
EN
CLK
Q
1
0
0
0
x
1
0
0
x
d
x
x
x
x
0
1
↑
↑
x
0
d
Q
count down
↑
Valid states for each 4-bit digit are 0-9.
Loading higher hexadecimal input values (A-F)
clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
207
Decade Counters
CDD24
QI[0:3]
QI[0:3]
QI0
QI0
HOLD0
LD
LX2
D
Q
QI0
CS
D0
LOAD0
FD11
QI3
EN
CLK
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
Q
QI1
D1
LOAD1
FD11
QI1
QI0
QI3
QI2
QI0
QI3
QI2
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
Q
QI2
D2
LOAD2
FD11
QI3
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
D3
QI0
LOAD3
FD11
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI2
QI1
QI0
QI3
QI2
QI3
QI1
ispLSI Macro Library Reference Manual
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Decade Counters
CDD28.1
QI[0:7]
QI[0:7]
QI0
QI0
HOLD0
LD
LX2
D
Q
QI0
CS
D0
LOAD0
FD11
QI3
EN
CLK
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
Q
QI1
D1
LOAD1
FD11
QI1
QI0
QI3
QI2
QI0
QI3
QI2
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
Q
QI2
D2
LOAD2
FD11
QI3
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
D3
QI3
QI0
LOAD3
FD11
QI1
QI2
Q0
Q1
QI1
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI0
QI3
QI2
QI3
QI1
LATTICE
Semiconductor
CorporationTM
ispLSI Macro Library Reference Manual
209
Decade Counters
CDD28.2
QI[0:7]
QI[0:7]
QI4
QI4
HOLD4
LD
LX2
D
Q
QI4
CS
D4
FD11
QI7
QI3
CLK
QI2
QI1
QI0
EN
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI5
HOLD5
LX2
D
Q
QI5
D5
FD11
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDD28.3
QI[0:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
CS
D6
FD11
QI7
QI5
QI4
CLK
QI3
QI2
QI1
QI0
EN
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI7
HOLD7
LX2
D
Q
QI7
D7
FD11
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDD34 and CDD38
CDD34
Function:
CAI
4- and 8-bit decade down counters with asynchronous
clear, enable, parallel data load, CAI, and CAO.
D0
Q0
D1
Q1
D2
Q2
Availability:
D3
Q3
CDD34 and CDD38 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
LD CAO
EN
Schematics appear on the following pages.
CD
Type: Hard
Logic Resources:
*
**
*
CDD38
Macro
PT
GLB
Output
Level
CDD34
CDD38
*
**
2
4
5
9
1***
1***
CLK: 1 PT per GLB if Product Term Clock is used.
CAO: 1 PT CD: 1 PT per GLB.
Q0: 5 PT
Q1: 6 PT
Q2: 5 PT
Q3: 5 PT
CLK: 1 PT per GLB if Product Term Clock is used.
CAO: 1 PT CD: 1 PT per GLB.
Q0: 5 PT
Q1: 6 PT
Q2: 5 PT
Q3: 5 PT
Q4: 6 PT
Q5: 6 PT
Q6: 5 PT
Q7: 5 PT
(CAO is a 2-level output).
Macro Port Definition:
CAI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LD CAO
EN
CD
CDD34 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,CD);
CDD34_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,CD);
CDD34_2 (Q3,CAO,D3,[Q0..Q2],CAI,CLK,LD,EN,CD);
CDD38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CD);
CDD38_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,CD);
CDD38_2 ([Q3..Q5],[D3..D5],[Q0..Q2],Q6,Q7,CAI,CLK,LD,EN,CD);
CDD38_3 (Q6,Q7,CAO,D6,D7,[Q0..Q5],CAI,CLK,LD,EN,CD);
Counting Ranges:
CDD34: 9-0. 38: 99-0.
ispLSI Macro Library Reference Manual
212
Decade Counters
Truth Table:
The truth table is the same for both CDD3s.
Input
*
**
CD
LD
D
EN
1
0
0
0
0
x
1
0
0
0
x
d
x
x
x
x
x
0
x
1
Output
CAI CLK
x
x
x
0
1
x
↑
x
x
↑
Q
CAO
0
d
Q
Q
count down
CAI⋅EN
*
0
0
**
CAO = CAI⋅EN⋅terminal count.
CAO = 1 after terminal count when CAI = 1 and EN = 1.
Valid states for each 4-bit digit are 0~9. Loading higher hexadecimal
input values (A-F) clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
213
Decade Counters
CDD34
QI[0:3]
QI[0:3]
QI0
QI0
HOLD0
LD
LX2
D0
D
QI0
Q
LOAD0
QI3
CD
FD21
CLK
CD
CAI
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D1
D
QI1
Q
LOAD1
QI1
CD
FD21
QI0
QI3
QI2
QI0
QI3
QI2
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D2
D
QI2
Q
LOAD2
QI3
CD
FD21
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D3
D
QI3
Q
LOAD3
QI2
QI1
CD
FD21
QI0
QI3
QI3
QI2
Q3
Q2
QI2
QI1
QI0
Q1
Q0
QI3
QI1
QI3
QI2
QI1
QI0
ispLSI Macro Library Reference Manual
CAO
214
Decade Counters
CDD38.1
QI[0:7]
QI[0:7]
QI0
QI0
HOLD0
LD
LX2
D0
D
QI0
Q
LOAD0
QI3
CD
FD21
CLK
CD
CAI
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D1
D
QI1
Q
LOAD1
QI1
CD
FD21
QI0
QI3
QI2
QI0
QI3
QI2
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D2
D
QI2
Q
LOAD2
QI3
CD
FD21
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D3
D
QI3
Q
LOAD3
QI2
CD
FD21
QI1
QI0
QI7
QI6
Q7
Q6
QI3
QI2
QI5
Q5
QI7
QI6
QI4
Q4
QI3
Q3
QI2
Q2
QI1
Q1
QI0
Q0
QI5
QI3
QI4
QI1
QI3
QI2
CAO
QI1
QI0
ispLSI Macro Library Reference Manual
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Decade Counters
CDD38.2
QI[0:7]
QI[0:7]
QI4
QI4
HOLD4
LD
LX2
D
Q
QI4
D4
QI7
QI3
CLK
QI2
CD
CD
FD21
QI1
QI0
EN
CAI
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI5
HOLD5
LX2
D
Q
QI5
D5
QI5
QI4
CD
FD21
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDD38.3
QI[0:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
D6
CD
FD21
QI7
CLK
QI5
CD
QI4
QI3
QI2
QI1
QI0
EN
CAI
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI7
HOLD7
LX2
D
Q
QI7
D7
QI6
QI5
CD
FD21
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDD44 and CDD48
CDD44
Function:
CAI
4- and 8-bit decade down counters with synchronous
clear, enable, parallel data load, CAI, and CAO.
D0
Q0
D1
Q1
D2
Q2
Availability:
D3
Q3
CDD44 and CDD48 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
LD CAO
EN
Schematics appear on the following pages.
CS
Type: Hard
Logic Resources:
*
**
***
CDD48
Macro
PT
GLB
Output
Level
CDD44
CDD48
*
**
2
3
5
9
1***
1***
CLK: 1 PT per GLB if Product Term Clock is used.
CAO: 1 PT Q0: 5 PT
Q1: 6 PT
Q2: 5 PT
Q3: 5 PT
CLK: 1 PT per GLB if Product Term Clock is used.
CAO: 1 PT Q0: 5 PT
Q1: 6 PT
Q2: 5 PT
Q3: 5 PT
Q4: 6 PT
Q5: 6 PT
Q6: 5 PT
Q7: 5 PT
(CAO is a 2-level output).
CAI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LD CAO
Macro Port Definition:
EN
CDD44 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,CS);
CDD44_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,CS);
CDD44_2 (Q3,CAO,D3,[Q0..Q2],CAI,CLK,LD,EN,CS);
CDD48 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CS);
CDD48_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,CS);
CDD48_2 ([Q3..Q5],[D3..D5],[Q0..Q2],Q6,Q7,CAI,CLK,LD,
EN,CS);
CDD48_3 (Q6,Q7,CAO,D6,D7,[Q0..Q5],CAI,CLK,LD,EN,CS);
CS
Counting Ranges:
CDD44: 9-0. 48: 99-0.
ispLSI Macro Library Reference Manual
218
Decade Counters
Truth Table:
The truth table is the same for both CDD4s..
Input
*
**
Output
CS
LD
D
EN
CAI
CLK
Q
CAO
1
0
0
0
0
x
1
0
0
0
x
d
x
x
x
x
x
0
x
1
x
x
x
0
1
↑
↑
x
x
0
d
Q
Q
count down
0
*
0
0
**
↑
CAO = CAI⋅EN⋅terminal count.
CAO = 1 after terminal count when CAI = 1 and EN = 1.
Valid states for each 4-bit digit are 0~9. Loading higher hexadecimal
input values (A-F) clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
219
Decade Counters
CDD48.2
QI[0:7]
QI[0:7]
QI4
QI4
HOLD4
LD
LX2
D
Q
QI4
CS
D4
FD11
QI7
QI3
QI2
QI1
CLK
QI0
EN
CAI
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI5
HOLD5
LX2
D
Q
QI5
D5
FD11
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
220
Decade Counters
CDD48.3
QI[0:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
CS
D6
FD11
QI7
QI5
QI4
CLK
QI3
QI2
QI1
QI0
EN
CAI
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI7
HOLD7
LX2
D
Q
QI7
D7
FD11
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
221
Decade Counters
CDU14 and CDU18
CDU14
Function:
4- and 8-bit decade up counters with asynchronous clear,
enable, and parallel data load.
Availability:
CDU14 and CDU18 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
D0
Q0
D1
Q1
D2
Q2
D3
Q3
LD
EN
Schematics appear on the following pages.
CD
Type: Hard
Logic Resources:
*
**
CDU18
Macro
PT
GLB
Output
Level
CDU14
CDU18
*
**
2
3
4
8
1
1
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0: 5 PT
Q1: 4 PT
Q2: 4 PT
Q3: 6 PT
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0: 5 PT
Q1: 4 PT
Q2: 4 PT
Q3: 6 PT
Q4: 6 PT
Q5: 4 PT
Q6: 4 PT
Q7: 6 PT
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LD
EN
Macro Port Definition:
CDU14 ([Q0..Q3],[D0..D3],CLK,LD,EN,CD);
CDU18 ([Q0..Q7],[D0..D7],CLK,LD,EN,CD);
CDU18_1 ([Q0..Q3],[D0..D3],CLK,LD,EN,CD);
CDU18_2 ([Q4..Q6],[D4..D6],[Q0..Q3],Q7,CLK,LD,EN,CD);
CDU18_3 (Q7,D7,[Q0..Q6],CLK,LD,EN,CD);
CD
Counting Ranges:
CDU14: 0-9. 18: 0-99.
ispLSI Macro Library Reference Manual
222
Decade Counters
Truth Table:
The truth table is the same for both CDU1s.
Input
Output
CD
LD
D
EN
CLK
Q
1
0
0
0
x
1
0
0
x
d
x
x
x
x
0
1
x
0
d
Q
count up
↑
x
↑
Valid states for each 4-bit digit are 0-9.
Loading higher hexadecimal input values (A-F)
clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
223
Decade Counters
CDU14
QI[1:3]
QI[0:3]
QI0
HOLD0
LD
LX2
D
QI0
Q
D0
QI3
CD
FD21
CLK
CD
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
QI1
Q
D1
QI3
CD
FD21
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
QI2
Q
D2
QI3
CD
FD21
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
QI3
Q
D3
QI2
QI1
CD
FD21
QI0
QI0
Q0
QI1
Q1
QI3
QI0
QI2
QI3
Q2
Q3
QI3
QI1
QI3
QI2
ispLSI Macro Library Reference Manual
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Decade Counters
CDU18.1
QI[1:3],QI[5:7]
QI[0:7]
QI0
HOLD0
LD
LX2
D
QI0
Q
D0
QI3
CD
FD21
CLK
CD
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
QI1
Q
D1
QI3
CD
FD21
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
QI2
Q
D2
QI3
CD
FD21
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
QI3
Q
D3
QI2
QI1
CD
FD21
QI0
QI0
QI1
Q0
Q1
QI3
QI2
QI0
QI3
Q2
Q3
QI3
QI4
QI1
QI5
Q4
Q5
QI3
QI6
QI2
QI7
ispLSI Macro Library Reference Manual
Q6
Q7
225
Decade Counters
CDU18.2
QI[1:3],QI[5:7]
QI[0:7]
QI4
HOLD4
LD
LX2
D
Q
QI4
D4
QI7
CD
FD21
CLK
QI3
CD
QI2
QI1
QI0
EN
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI5
HOLD5
LX2
D
Q
QI5
D5
QI7
QI4
CD
FD21
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
226
Decade Counters
CDU18.3
QI[1:3],QI[5:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
D6
QI7
CD
CLK
QI5
FD21
CD
QI4
QI3
QI2
QI1
QI0
EN
QI7
QI6
QI7
QI7
HOLD7
LX2
D
Q
QI7
D7
QI6
CD
QI5
FD21
QI4
QI3
QI2
QI1
QI0
QI7
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDU24 and CDU28
CDU24
Function:
4- and 8-bit decade up counters with synchronous clear,
enable, and parallel data load.
Availability:
CDU24 and CDU28 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
D0
Q0
D1
Q1
D2
Q2
D3
Q3
LD
EN
Schematics appear on the following pages.
CS
Type: Hard
Logic Resources:
*
**
CDU28
Macro
PT
GLB
Output
Level
CDU24
CDU28
*
**
1
3
4
8
1
1
CLK: 1 PT per GLB if Product Term Clock is used.
Q0: 5 PT
Q1: 4 PT
Q2: 4 PT
Q3: 6 PT
CLK: 1 PT per GLB if Product Term Clock is used.
Q0: 5 PT
Q1: 4 PT
Q2: 4 PT
Q3: 6 PT
Q4: 6 PT
Q5: 4 PT
Q6: 4 PT
Q7: 6 PT
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LD
Macro Port Definition:
EN
CDU24 ([Q0..Q3],[D0..D3],CLK,LD,EN,CS);
CDU28 ([Q0..Q7],[D0..D7],CLK,LD,EN,CS);
CDU28_1 ([Q0..Q3],[D0..D3],CLK,LD,EN,CS);
CDU28_2 ([Q4..Q6],[D4..D6],[Q0..Q3],Q7,CLK,LD,EN,CS);
CDU28_3 (Q7,D7,[Q0..Q6],CLK,LD,EN,CS);
CS
Counting Ranges:
CDU24: 0-9. CDU28: 0-99.
ispLSI Macro Library Reference Manual
228
Decade Counters
Truth Table:
The truth table is the same for both CDU2s.
Input
Output
CS
LD
D
EN
CLK
Q
1
0
0
0
x
1
0
0
x
d
x
x
x
x
0
1
↑
↑
x
0
d
Q
count up
↑
Valid states for each 4-bit digit are 0~9.
Loading higher hexadecimal input values (A-F)
clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
229
Decade Counters
CDU24
QI[1:3]
QI[0:3]
QI0
HOLD0
LD
LX2
D
Q
QI0
CS
D0
FD11
QI3
CLK
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
Q
QI1
D1
FD11
QI3
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
Q
QI2
D2
FD11
QI3
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
QI0
D3
FD11
QI1
Q0
Q1
QI2
QI1
QI2
Q2
QI0
QI3
Q3
QI3
QI0
QI3
QI1
QI3
QI2
ispLSI Macro Library Reference Manual
230
Decade Counters
CDU28.1
QI[1:3],QI[5:7]
QI[0:7]
QI0
HOLD0
LD
LX2
D
Q
QI0
CS
D0
FD11
QI3
CLK
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
Q
QI1
D1
FD11
QI3
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
Q
QI2
D2
FD11
QI3
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
D3
FD11
QI2
QI0
Q0
QI1
QI0
QI1
QI2
QI3
QI3
Q1
Q2
Q3
QI0
QI4
QI5
Q4
Q5
QI3
QI1
QI6
QI7
Q6
Q7
QI3
QI2
ispLSI Macro Library Reference Manual
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Decade Counters
CDU28.2
QI[1:3],QI[5:7]
QI[0:7]
QI4
HOLD4
LD
LX2
D
Q
QI4
CS
D4
FD11
QI7
CLK
QI3
QI2
QI1
QI0
EN
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI5
HOLD5
LX2
D
Q
QI5
D5
FD11
QI7
QI4
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDU28.3
QI[1:3],QI[5:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
CS
D6
FD11
QI7
QI5
CLK
QI4
QI3
QI2
QI1
QI0
EN
QI7
QI6
QI7
QI7
HOLD7
LX2
D
Q
QI7
D7
FD11
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDU34 and CDU38
CDU34
Function:
CAI
4- and 8-bit decade up counters with asynchronous clear,
enable, parallel data load, CAI, and CAO.
Availability:
CDU34 and CDU38 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
D0
Q0
D1
Q1
D2
Q2
D3
Q3
LD CAO
EN
Schematics appear on the following pages.
CD
Type: Hard
Logic Resources:
Macro
PT
GLB
Output
Level
CDU34
CDU38
*
**
2
3
5
9
1***
1***
*
**
***
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0: 5 PT
Q1: 4 PT
Q2: 4 PT
Q3: 6 PT
CAO: 1 PT
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0: 5 PT
Q1: 4 PT
Q2: 4 PT
Q3: 6 PT
Q4: 6 PT
Q5: 4 PT
Q6: 4 PT
Q7: 6 PT
CAO: 1 PT
(CAO is a 2-level output).
CDU38
CAI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LD CAO
EN
Macro Port Definition:
CD
CDU34 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,CD);
CDU34_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CD);
CDU34_2 (CAO,[Q0..Q3],CAI,EN);
CDU38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CD);
CDU38_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CD);
CDU38_2 ([Q4..Q6],CAO,[D4..D6],[Q0..Q3],Q7,CAI,CLK,
LD,EN,CD);
CDU38_3 (Q7,D7,[Q0..Q6],CAI,CLK,LD,EN,CD);
Counting Ranges:
CDU34: 0-9. CDU38: 0-99.
ispLSI Macro Library Reference Manual
234
Decade Counters
Truth Table:
The truth table is the same for both CDU3s.
Input
*
**
Output
CD
LD
D
EN
CAI
CLK
Q
CAO
1
0
0
0
0
x
1
0
0
0
x
d
x
x
x
x
x
0
x
1
x
x
x
0
1
x
0
d
Q
Q
count up
0
*
0
0
**
↑
x
x
↑
CAO = CAI⋅EN⋅terminal count.
CAO = 1 after terminal count (9 or 99) when CAI = 1 and EN = 1.
Valid states for each 4-bit digit are 0~9.
Loading higher hexadecimal input values (A-F)
clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
235
Decade Counters
CDU34
QI[1:3]
QI[0:3]
QI0
HOLD0
LD
LX2
D
Q
QI0
D0
QI3
CD
CLK
FD21
CD
EN
CAI
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
Q
QI1
D1
QI3
CD
FD21
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
Q
QI2
D2
QI3
CD
FD21
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
D3
QI2
QI1
CD
FD21
QI0
QI3
QI0
QI0
QI1
QI2
QI3
Q0
Q1
Q2
QI1
QI3
Q3
QI3
QI2
QI3
QI2
QI1
QI0
ispLSI Macro Library Reference Manual
CAO
236
Decade Counters
CDU38.1
QI[1:3],QI[5:7]
QI[0:7]
QI0
HOLD0
LD
LX2
D
QI0
Q
D0
QI3
CD
CLK
FD21
CD
EN
CAI
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
QI1
Q
D1
QI3
CD
FD21
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
QI2
Q
D2
QI3
CD
FD21
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
QI3
Q
D3
QI2
CD
FD21
QI1
QI0
Q0
QI0
QI1
QI2
Q1
Q2
QI3
QI3
QI0
QI4
QI5
QI3
Q3
Q4
Q5
QI1
QI7
QI6
Q6
QI6
QI5
QI3
QI4
QI2
QI3
QI2
QI7
Q7
CAO
QI1
QI0
ispLSI Macro Library Reference Manual
237
Decade Counters
CDU38.2
QI[1:3],QI[5:7]
QI[0:7]
QI4
HOLD4
LD
LX2
D
Q
QI4
D4
QI7
CD
CLK
QI3
FD21
CD
QI2
QI1
QI0
EN
CAI
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI5
HOLD5
LX2
D
Q
QI5
D5
QI7
QI4
CD
FD21
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
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Decade Counters
CDU38.3
QI[0:7]
QI[1:3],QI[5:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
D6
QI7
QI5
CLK
QI4
CD
CD
FD21
QI3
QI2
QI1
QI0
EN
CAI
QI7
QI6
QI7
QI7
HOLD7
LX2
D
Q
QI7
D7
QI6
QI5
CD
FD21
QI4
QI3
QI2
QI1
QI0
QI7
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
239
Decade Counters
CDU44 and CDU48
CDU44
Function:
CAI
D0
Q0
D1
Q1
D2
Q2
Availability:
D3
Q3
CDU44 and CDU48 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
LD CAO
4- and 8-bit decade up counters with synchronous clear,
enable, parallel data load, CAI, and CAO.
EN
Schematics appear on the following pages.
CS
Type: Hard
Logic Resources:
*
**
***
CDU48
Macro
PT
GLB
Output
Level
CDU44
CDU48
*
**
2
3
5
9
1***
1***
CLK: 1 PT per GLB if Product Term Clock is used.
CAO: 1 PT
Q0: 5 PT
Q1: 4 PT
Q2: 4 PT
Q3: 6 PT
CLK: 1 PT per GLB if Product Term Clock is used.
CAO: 1 PT
Q0: 5 PT
Q1: 4 PT
Q2: 4 PT
Q3: 6 PT
Q4: 6 PT
Q5: 4 PT
Q6: 4 PT
Q7: 6 PT
(CAO is a 2-level output).
Macro Port Definition:
CAI
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
LD CAO
EN
CDU44 ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,CS);
CDU44_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CS);
CDU44_2 (CAO,[Q0..Q3],CAI,EN);
CDU48 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CS);
CDU48_1 ([Q0..Q3],[D0..D3],CAI,CLK,LD,EN,CS);
CDU48_2 ([Q4..Q6],CAO,[D4..D6],[Q0..Q3],Q7,CAI,CLK,
LD,EN,CS);
CDU48_3 (Q7,D7,[Q0..Q6],CAI,CLK,LD,EN,CS);
CS
Counting Ranges:
CDU44: 0-9. CDU48: 0-99.
ispLSI Macro Library Reference Manual
240
Decade Counters
Truth Table:
The truth table is the same for both CDU4s.
Input
*
**
Output
CS
LD
D
EN
CAI
CLK
Q
CAO
1
0
0
0
0
x
1
0
0
0
x
d
x
x
x
x
x
0
x
1
x
x
x
0
1
↑
↑
x
x
0
d
Q
Q
count up
0
*
0
0
**
↑
CAO = CAI⋅EN⋅terminal count.
CAO = 1 after terminal count (9 or 99) when CAI =1 and EN =1.
Valid states for each 4-bit digit are 0~9.
Loading higher hexadecimal input values (A-F)
clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
241
Decade Counters
CDU44
QI[1:3]
QI[0:3]
CLK
QI0
HOLD0
LD
LX2
D
Q
QI0
CS
D0
FD11
QI3
EN
CAI
QI2
QI1
CLK
QI3
QI0
QI1
QI1
HOLD1
LX2
D
Q
QI1
D1
FD11
QI3
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
Q
QI2
D2
FD11
QI3
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
D3
FD11
QI2
QI1
QI0
QI3
QI0
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI3
QI1
QI3
QI2
QI3
QI2
QI1
QI0
ispLSI Macro Library Reference Manual
CAO
242
Decade Counters
CDU48.1
QI[1:3],QI[5:7]
QI[0:7]
CLK
QI0
HOLD0
LD
LX2
D
QI0
Q
CS
D0
FD11
QI3
EN
CAI
QI2
QI1
CLK
QI3
QI0
QI1
QI1
HOLD1
LX2
D
QI1
Q
D1
FD11
QI3
QI0
QI3
QI1
QI2
QI2
HOLD2
LX2
D
QI2
Q
D2
FD11
QI3
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
QI3
Q
D3
FD11
QI2
QI1
QI0
Q0
QI1
Q1
QI2
Q2
QI3
Q3
QI4
Q4
QI5
Q5
QI6
Q6
QI7
Q7
QI0
QI3
QI0
QI3
QI1
QI7
QI6
QI3
QI5
QI2
QI4
QI3
QI2
CAO
QI1
QI0
ispLSI Macro Library Reference Manual
243
Decade Counters
CDU48.2
QI[1:3],QI[5:7]
QI[0:7]
CLK
QI4
HOLD4
LD
LX2
D
Q
QI4
CS
D4
FD11
QI7
QI3
QI2
QI1
QI0
EN
CAI
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
QI5
QI5
HOLD5
LX2
D
Q
QI5
D5
FD11
QI7
QI4
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
244
Decade Counters
CDU48.3
QI[1:3],QI[5:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
CS
D6
FD11
QI7
CLK
QI5
QI4
QI3
QI2
QI1
QI0
EN
CAI
QI7
QI6
QI7
QI7
HOLD7
LX2
D
Q
QI7
D7
FD11
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
245
Decade Counters
CDUD4 and CDUD8
Function:
4- and 8-bit decade up/down counters with asynchronous
clear, synchronous clear, enable, and parallel data load.
Availability:
CDUD4 and CDUD8 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
CDUD4
CDUD8
D0
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
D3
Q3
D3
Q3
DN/UP
D4
Q4
LD
D5
Q5
EN
D6
Q6
D7
Q7
CD CS
Schematics appear on the following pages.
DN/UP
LD
EN
Type: Hard
CD CS
Logic Resources:
*
**
Macro
PT
GLB
Output
Level
CDUD4
CDUD8
*
**
2
4
4
8
1
1
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0: 5 PT
Q1: 7 PT
Q2: 6 PT
Q3: 7 PT
CLK: 1 PT per GLB if Product Term Clock is used.
CD: 1 PT per GLB.
Q0: 5 PT
Q1: 7 PT
Q2: 6 PT
Q3: 7 PT
Q4: 8 PT
Q5: 7 PT
Q6: 6 PT
Q7: 7 PT
Macro Port Definition:
CDUD4 ([Q0..Q3],[D0..D3],CLK,LD,EN,DNUP,CD,CS);
CDUD4_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,DNUP,CD,CS);
CDUD4_2 (Q3,D3,[Q0..Q2],CLK,LD,EN,DNUP,CD,CS);
CDUD8 ([Q0..Q7],[D0..D7],CLK,LD,EN,DNUP,CD,CS);
CDUD8_1 ([Q0..Q2],[D0..D2],Q3,CLK,LD,EN,DNUP,CD,CS);
CDUD8_2 (Q3,Q4,D3,D4,[Q0..Q2],[Q5..Q7],CLK,LD,EN,DNUP,CD,CS);
CDUD8_3 (Q5,Q6,D5,D6,[Q0..Q4],Q7,CLK,LD,EN,DNUP,CD,CS);
CDUD8_4 (Q7,D7,[Q0..Q6],CLK,LD,EN,DNUP,CD,CS);
Counting Ranges:
CDUD4: 0↔9. 8: 0↔99.
ispLSI Macro Library Reference Manual
246
Decade Counters
Truth Table:
The truth table is the same for both CDUD4 and CDUD8.
Input
Output
CD
CS
LD
D
EN
1
0
0
0
0
0
x
1
0
0
0
0
x
x
1
0
0
0
x
x
d
x
x
x
x
x
x
0
1
1
DNUP CLK
x
x
x
x
0
1
x
↑
↑
x
↑
↑
Q
0
0
d
Q
count up
count down
Valid states for each 4-bit digit are 0~9.
Loading higher hexadecimal input values (A-F)
clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
247
Decade Counters
CDUD4.1
QI[0:3]
QI[0:3]
QI0
QI0
LD
LX2
CS
D
QI0
Q
HOLD0
D0
LOAD0
QI3
CD
FD21
CLK
CD
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
QI1
Q
D1
LOAD1
CD
FD21
QI3
QI0
QI0
Q0
QI1
Q1
DNUP
QI1
QI0
QI2
QI3
Q2
Q3
QI3
QI2
QI0
QI3
QI2
QI0
QI3
QI1
ispLSI Macro Library Reference Manual
248
Decade Counters
CDUD4.2
QI[0:3]
QI[0:3]
CD
QI2
CLK
QI2
LD
HOLD2
CS
LX2
D
Q
QI2
D2
CD
FD21
LOAD2
QI3
QI1
QI0
EN
DNUP
QI3
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
D3
CD
FD21
QI2
QI1
QI0
QI3
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI1
ispLSI Macro Library Reference Manual
249
Decade Counters
CDUD8.1
QI[0:7]
QI[0:7]
QI0
QI0
LD
LX2
CS
D
QI0
Q
HOLD0
D0
LOAD0
QI3
CD
FD21
CLK
CD
EN
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
QI1
Q
D1
LOAD1
CD
FD21
QI3
QI0
DNUP
QI1
QI0
Q0
QI1
Q1
QI0
QI2
QI3
QI3
QI4
Q2
Q3
Q4
QI2
QI0
QI5
QI6
QI7
Q5
Q6
Q7
QI3
QI2
QI0
QI3
QI1
ispLSI Macro Library Reference Manual
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Decade Counters
CDUD8.2
QI[0:7]
QI[0:7]
QI2
QI2
LD
HOLD2
CS
LX2
D
Q
QI2
D2
CD
LOAD2
QI3
CLK
FD21
CD
QI1
QI0
EN
DNUP
QI3
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
D3
CD
FD21
QI2
QI1
QI0
QI3
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI1
ispLSI Macro Library Reference Manual
251
Decade Counters
CDUD8.3
QI[0:7]
QI[0:7]
QI4
QI4
LD
HOLD4
CS
D
LX2
Q
QI4
D4
LOAD4
CLK
QI7
CD
FD21
CD
QI3
QI2
QI1
QI0
EN
DNUP
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI3
QI2
QI1
QI0
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
ispLSI Macro Library Reference Manual
252
Decade Counters
CDUD8.4
QI[0:7]
QI[0:7]
QI5
QI5
HOLD5
LD
LX2
D
Q
QI5
CS
D5
LOAD5
CLK
QI7
CD
FD21
CD
QI4
QI3
QI2
QI1
QI0
EN
DNUP
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI5
ispLSI Macro Library Reference Manual
253
Decade Counters
CDUD8.5
QI[0:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
CS
D6
LOAD6
CLK
QI7
CD
FD21
CD
QI5
QI4
QI3
QI2
QI1
QI0
EN
DNUP
QI7
QI5
QI4
QI3
QI2
QI1
QI0
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
ispLSI Macro Library Reference Manual
254
Decade Counters
CDUD8.6
QI[0:7]
QI[0:7]
QI7
QI7
HOLD7
LD
LX2
D
Q
QI7
CS
D7
LOAD7
CLK
QI6
CD
FD21
CD
QI5
QI4
QI3
QI2
QI1
QI0
EN
DNUP
QI7
QI4
QI3
QI2
QI1
QI0
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
ispLSI Macro Library Reference Manual
255
Decade Counters
CDUD4c and CDUD8c
Function:
4- and 8-bit decade up/down counters with asynchronous
clear, synchronous clear, enable, parallel data load, CAI,
and CAO.
CDUD4c
CDUD8c
CAI
CAI
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
Q3
D3
Q3
DN/UP
D4
Q4
LD CAO
D5
Q5
EN
D6
Q6
D7
Q7
D0
D3
Availability:
CDUD4c and CDUD8c can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Schematics appear on the following pages.
CD CS
CD CS
Logic Resources:
Macro
PT
CDUD4c
CDUD8c
*
**
**
***
LD CAO
EN
Type: Hard
*
DN/UP
GLB Output Level
2
4
5
9
1***
1***
CLK: 1 PT per GLB if Product Term Clock is used.
CAO: 2 PT CD: 1 PT per GLB.
Q0: 5 PT
Q1: 7 PT
Q2: 6 PT
Q3: 7 PT
CLK: 1 PT per GLB if Product Term Clock is used.
CAO: 2 PT CD: 1 PT per GLB.
Q0: 5 PT
Q1: 7 PT
Q2: 6 PT
Q3: 7 PT
Q4: 8 PT
Q5: 7 PT
Q6: 6 PT
Q7: 7 PT
(CAO is a 2-level output).
Macro Port Definition:
CDUD4c ([Q0..Q3],CAO,[D0..D3],CAI,CLK,LD,EN,DNUP,CD,CS);
CDUD4c_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,DNUP,CD,CS);
CDUD4c_2 (Q3,CAO,D3,[Q0..Q2],CAI,CLK,LD,EN,DNUP,CD,CS);
CDUD8c ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,DNUP,CD,CS);
CDUD8c_1 ([Q0..Q2],[D0..D2],Q3,CAI,CLK,LD,EN,DNUP,CD,CS);
CDUD8c_2 (Q3,Q4,CAO,D3,D4,[Q0..Q2],[Q5..Q7],CAI,CLK,LD,
EN,DNUP,CD,CS);
CDUD8c_3 (Q5,Q6,D5,D6,[Q0..Q4],Q7,CAI,CLK,LD,EN,DNUP,CD,CS);
CDUD8c_4 (Q7,D7,[Q0..Q6],CAI,CLK,LD,EN,DNUP,CD,CS);
Counting Ranges:
CDUD4c: 0↔9. CDUD8c: 0↔99.
ispLSI Macro Library Reference Manual
256
Decade Counters
Truth Table:
Input
Output
CD
CS
LD
D
EN
CAI
DNUP
CLK
Q
CAO
1
0
0
0
0
0
0
0
1
0
0
0
0
0
x
x
1
0
0
0
0
x
x
d
x
x
x
x
x
x
x
0
x
1
1
x
x
x
x
0
1
1
x
x
x
x
x
0
1
x
0
0
d
Q
Q
count up
count down
*
*
**
0
0
0
***
*
**
***
↑
↑
x
x
↑
↑
CAO = CAI⋅EN⋅DNUP
CDUD4c: CAO = CAI⋅EN⋅DNUP⋅D0⋅D1⋅D2⋅D3+DNUP⋅9
CDUD8c: CAO = CAI⋅EN⋅DNUP⋅D0⋅D1⋅D2⋅D3⋅D4⋅D5⋅D6⋅D7+DNUP⋅99
CAO = 1 after terminal count (9 or 99) when CAI = 1 and EN = 1.
terminal count = 0 when DNUP = 1 (count down).
terminal count = 9 or 99 when DNUP=0 (count up).
Valid states for each 4-bit digit are 0~9.
Loading higher hexadecimal input values (A-F) clears that decimal output digit on the next clock pulse.
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
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Decade Counters
CDUD4c.1
QI[0:3]
QI[0:3]
QI0
QI0
LD
D
LX2
CS
QI0
Q
HOLD0
D0
CD
LOAD0
QI3
CLK
FD21
CD
EN
CAI
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
D
LX2
QI1
Q
D1
CD
LOAD1
FD21
QI3
QI0
DNUP
QI1
QI0
QI3
Q3
QI2
Q2
QI1
Q1
QI0
Q0
QI3
QI2
QI0
QI3
QI2
QI0
QI3
QI2
QI1
QI0
QI3
QI1
CAO
QI3
QI2
QI1
QI0
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Decade Counters
CDUD4c.2
QI[0:3]
QI[0:3]
QI2
QI2
LD
HOLD2
CS
LX2
D
Q
QI2
D2
CD
LOAD2
QI3
CLK
FD21
CD
QI1
QI0
EN
CAI
DNUP
QI3
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
D3
CD
FD21
QI2
QI1
QI0
QI3
QI0
QI2
QI1
QI0
QI3
QI2
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Decade Counters
CDUD8c.1
QI[0:7]
QI[0:7]
QI0
QI0
LD
LX2
CS
D
QI0
Q
HOLD0
D0
CD
LOAD0
QI3
CLK
FD21
CD
EN
CAI
QI2
QI1
QI3
QI0
QI1
QI1
HOLD1
LX2
D
QI1
Q
D1
CD
LOAD1
FD21
QI3
QI7
QI0
QI6
QI5
Q7
Q6
Q5
DNUP
QI4
QI1
Q4
QI0
QI3
QI2
QI1
Q3
Q2
Q1
QI3
QI0
QI2
Q0
QI0
QI7
QI6
QI5
QI4
QI3
QI3
QI2
QI2
QI1
QI0
QI0
CAO
QI7
QI3
QI6
QI1
QI5
QI4
QI3
QI2
QI1
QI0
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Decade Counters
CDUD8c.2
QI[0:7]
QI[0:7]
QI2
QI2
LD
HOLD2
CS
LX2
D
Q
QI2
D2
CD
LOAD2
QI3
CLK
FD21
CD
QI1
QI0
EN
CAI
DNUP
QI3
QI1
QI0
QI2
QI1
QI0
QI3
QI2
QI3
QI3
HOLD3
LX2
D
Q
QI3
D3
CD
FD21
QI2
QI1
QI0
QI3
QI0
QI2
QI1
QI0
QI3
QI2
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Decade Counters
CDUD8c.3
QI[0:7]
QI[0:7]
QI4
QI4
HOLD4
LD
LX2
D
Q
QI4
CS
D4
LOAD4
CLK
QI7
CD
FD21
CD
QI3
QI2
QI1
QI0
EN
CAI
DNUP
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI3
QI2
QI1
QI0
QI6
QI5
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI7
QI5
QI4
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Decade Counters
CDUD8c.4
QI[0:7]
QI[0:7]
QI5
QI5
LD
LX2
HOLD5
CS
D
Q
QI5
D5
LOAD5
CLK
QI7
CD
FD21
CD
QI4
QI3
QI2
QI1
QI0
EN
CAI
DNUP
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI4
QI3
QI2
QI1
QI0
QI7
QI5
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Decade Counters
CDUD8c.5
QI[0:7]
QI[0:7]
QI6
QI6
HOLD6
LD
LX2
D
Q
QI6
CS
D6
LOAD6
CLK
CD
FD21
CD
QI7
QI5
QI4
QI3
QI2
QI1
QI0
EN
CAI
DNUP
QI7
QI5
QI4
QI3
QI2
QI1
QI0
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
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Decade Counters
CDUD8c.6
QI[0:7]
QI[0:7]
QI7
QI7
HOLD7
LD
LX2
D
Q
QI7
CS
D7
LOAD7
CLK
QI6
CD
FD21
CD
QI5
QI4
QI3
QI2
QI1
QI0
EN
CAI
DNUP
QI7
QI4
QI3
QI2
QI1
QI0
QI6
QI5
QI4
QI3
QI2
QI1
QI0
QI7
QI6
QI7
QI5
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Gray Code Counters
Gray Code Counters
CGD14
CGD14
Function:
PS
D0 Q0
4-bit gray code down counter with asynchronous clear,
synchronous preset, enable, and parallel data load.
D1
Q1
D2
Q2
Availability:
D3
Q3
CGD14 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
LD
EN
Schematics appear on the following pages.
CD
Type: Soft
Macro Port Definition:
CGD14 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,CD);
CGD14_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,CD);
CGD14_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,CD);
Gray Code Pattern: Refer to CGU14.
Counting Range: 15-0.
Truth Table:
Input
Output
CD
PS
LD
D
EN
CLK
Q
1
0
0
0
0
x
1
0
0
0
x
x
1
0
0
x
x
d
x
x
x
x
x
0
1
x
0
1
d
Q
count down
↑
↑
↑
↑
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
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Gray Code Counters
CGD14.1
QI[0:3]
QI0
QI[0:3]
HOLD0
EN
D0
LOAD0
LD
QI3
QI2
QI1
QI3
QI0
QI2
QI1
D
QI0
Q
CD
FD21
QI3
QI2
CD
QI1
CLK
QI3
QI2
QI1
QI1
HOLD1
D1
LOAD1
QI1
QI0
QI1
QI3
D
QI1
Q
QI2
QI0
CD
FD21
QI0
Q0
QI1
Q1
QI2
Q2
QI3
QI2
QI0
QI3
Q3
PS
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Gray Code Counters
CGD14.2
QI[0:3]
QI2
QI[0:3]
HOLD2
EN
D2
LOAD2
LD
QI3
QI1
QI0
QI2
D
QI2
Q
QI2
QI1
CD
FD21
QI2
CD
QI0
CLK
QI3
HOLD3
D3
LOAD3
QI2
QI1
QI0
QI3
QI3
D
Q
QI3
QI0
CD
FD21
QI3
QI1
PS
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Gray Code Counters
CGD24
CGD24
Function:
4-bit gray code down counter with synchronous clear,
synchronous preset, enable, and parallel data load.
D0
PS
Q0
Availability:
D1
Q1
CGD24 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
D2
Q2
D3
Q3
Schematics appear on the following pages.
LD
Type: Soft
EN
Macro Port Definition:
CS
CGD24 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,CS);
CGD24_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,CS);
CGD24_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,CS);
Gray Code Pattern: Refer to CGU14.
Counting Range: 15-0.
Truth Table:
Input
Output
PS
CS
LD
D
EN
CLK
Q
1
0
0
0
0
x
1
0
0
0
x
x
1
0
0
x
x
d
x
x
x
x
x
0
1
↑
↑
↑
↑
↑
1
0
d
Q
count down
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
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Gray Code Counters
CGD24.1
QI[0:3]
QI[0:3]
QI0
HOLD0
EN
D0
LOAD0
LD
QI3
QI2
QI1
QI3
QI2
QI0
QI1
D
QI3
QI0
Q
FD11
QI2
CLK
QI1
QI3
QI2
QI1
QI1
HOLD1
D1
LOAD1
QI1
QI0
QI1
QI3
D
QI1
Q
QI2
QI0
QI0
Q0
QI1
Q1
FD11
QI3
QI2
QI2
Q2
QI0
QI3
Q3
CS
PS
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Gray Code Counters
CGD24.2
QI[0:3]
QI2
QI[0:3]
HOLD2
EN
D2
LOAD2
LD
QI3
QI1
QI0
QI2
D
QI2
Q
QI2
QI1
FD11
CLK
QI2
QI0
QI3
HOLD3
D3
LOAD3
QI2
QI1
QI0
QI3
QI3
D
Q
QI3
QI0
FD11
QI3
QI1
CS
PS
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Gray Code Counters
CGU14
Function:
CGU14
4-bit gray code up counter with asynchronous clear,
synchronous preset, enable, and parallel data load.
D0
PS
Q0
Availability:
D1
Q1
CGU14 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
D2
Q2
D3
Q3
Schematics appear on the following pages.
LD
EN
Type: Soft
Gray Code Pattern:
CD
Note that codes for two successive numbers differ by one bit.
Gray Code Pattern
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
8
9
10
11
12
13
14
15
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
Macro Port Definition:
CGU14 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,CD);
CGU14_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,CD);
CGU14_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,CD);
Counting Range: 0-15.
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Gray Code Counters
Truth Table:
Input
Output
CD
PS
LD
D
EN
CLK
Q
1
0
0
0
0
x
1
0
0
0
x
x
1
0
0
x
x
d
x
x
x
x
x
0
1
x
0
1
d
Q
count up
↑
↑
↑
↑
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
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Gray Code Counters
CGU14.1
QI[0:3]
QI0
QI[0:3]
HOLD0
EN
D0
LOAD0
LD
QI3
QI2
QI1
QI3
QI0
QI2
QI1
D
QI0
Q
CD
FD21
QI3
QI2
CD
QI1
CLK
QI3
QI2
QI1
QI1
HOLD1
D1
LOAD1
QI1
QI0
QI1
QI3
D
QI1
Q
QI2
QI0
CD
FD21
QI0
Q0
QI1
Q1
QI3
QI2
QI0
QI2
QI3
Q2
Q3
PS
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Gray Code Counters
CGU14.2
QI[0:3]
QI2
QI[0:3]
HOLD2
EN
D2
LOAD2
LD
QI3
QI1
QI0
QI2
D
QI2
Q
QI2
QI1
CD
FD21
QI2
CD
QI0
CLK
QI3
HOLD3
D3
LOAD3
QI2
QI1
QI0
QI3
QI3
D
Q
QI3
QI0
CD
FD21
QI3
QI1
PS
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Gray Code Counters
CGU24
CGU24
Function:
4-bit gray code up counter with synchronous clear,
synchronous preset, enable, and parallel data load.
D0
PS
Q0
Availability:
D1
Q1
CGU24 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
D2
Q2
D3
Q3
Schematics appear on the following pages.
LD
Type: Soft
EN
Macro Port Definition:
CGU24 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,CS);
CGU24_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,CS);
CGU24_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,CS);
CS
Gray Code Pattern: Refer to CGU14.
Counting Range: 0-15.
Truth Table:
Input
Output
PS
CS
LD
D
EN
CLK
Q
1
0
0
0
0
x
1
0
0
0
x
x
1
0
0
x
x
d
x
x
x
x
x
0
1
↑
↑
↑
↑
↑
1
0
d
Q
count up
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
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Gray Code Counters
CGU24.1
QI[0:3]
QI[0:3]
QI0
HOLD0
EN
D0
LOAD0
LD
QI3
QI2
QI1
QI3
QI2
QI0
QI1
D
QI3
QI0
Q
FD11
QI2
CLK
QI1
QI3
QI2
QI1
QI1
HOLD1
D1
LOAD1
QI1
QI0
QI1
QI3
D
QI1
Q
QI2
QI0
QI0
Q0
QI1
Q1
FD11
QI3
QI2
QI2
Q2
QI0
QI3
Q3
CS
PS
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Gray Code Counters
CGU24.2
QI[0:3]
QI2
QI[0:3]
HOLD2
EN
D2
LOAD2
LD
QI3
QI1
QI0
QI2
D
QI2
Q
QI2
QI1
FD11
CLK
QI2
QI0
QI3
HOLD3
D3
LOAD3
QI2
QI1
QI0
QI3
QI3
D
Q
QI3
QI0
FD11
QI3
QI1
CS
PS
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Gray Code Counters
CGUD4
CGUD4
Function:
4-bit gray code up/down counter with asynchronous clear,
synchronous clear and preset, enable, and parallel data
load.
Availability:
PS
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CGUD4 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
DN/UP
Schematics appear on the following pages.
EN
LD
Type: Soft
CD CS
Macro Port Definition:
CGUD4 ([Q0..Q3],[D0..D3],CLK,PS,LD,EN,DNUP,CD,CS);
CGUD4_1 (Q0,Q1,D0,D1,Q2,Q3,CLK,PS,LD,EN,DNUP,CD,CS);
CGUD4_2 (Q2,Q3,D2,D3,Q0,Q1,CLK,PS,LD,EN,DNUP,CD,CS);
Gray Code Pattern: Refer to CGU14.
Counting Range: 0↔15.
Truth Table:
Input
CD
PS
CS
LD
D
1
0
0
0
0
0
0
x
1
0
0
0
0
0
x
x
1
0
0
0
0
x
x
x
1
0
0
0
x
x
x
d
x
x
x
Output
DNUP EN CLK
x
x
x
x
x
1
0
x
x
x
x
0
1
1
x
↑
↑
↑
↑
↑
↑
Q
0
1
0
d
Q
count down
count up
d = any pattern of 1s and 0s on an input or set of inputs,
Q = output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
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Gray Code Counters
CGUD4.1
QI[0:3]
QI0
QI[0:3]
HOLD0
EN
D0
LOAD0
LD
QI3
QI2
QI1
QI3
QI2
QI1
QI3
QI2
QI1
QI3
QI2
QI1
DNUP
QI0
PS
D
QI3
QI0
Q
QI2
QI1
CD
CLK
CD
FD21
QI0
QI1
Q0
Q1
QI3
QI2
QI2
Q2
QI1
QI3
Q3
QI3
QI2
QI1
QI3
QI2
QI1
CS
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Gray Code Counters
CGUD4.2
QI[0:3]
QI1
QI[0:3]
HOLD1
EN
D1
LOAD1
LD
PS
QI1
QI0
QI1
D
QI3
Q
QI1
QI2
QI0
CLK
CD
FD21
CD
QI3
QI2
QI0
DNUP
QI3
QI2
QI0
QI3
QI2
QI0
CS
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Gray Code Counters
CGUD4.3
QI[0:3]
QI[0:3]
QI2
HOLD2
EN
D2
LOAD2
LD
QI3
QI1
QI0
QI3
QI1
QI0
QI2
D
QI2
CD
FD21
DNUP
CLK
QI2
Q
CD
QI1
QI2
QI0
QI3
HOLD3
D3
LOAD3
LD
QI2
QI1
QI0
QI2
QI1
QI0
QI3
D
QI3
Q
QI3
CD
FD21
QI0
QI3
QI1
CS
PS
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I/O Pins
This chapter contains information on the following macros:
■
■
■
Bidirectional Pins
Input Pins
Output Pins
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Bidirectional Pins
Bidirectional Pins
BI11, BI14, and BI18
BI11
OE
Function:
BI11:
BI14:
BI18:
A
1-bit bidirectional pin.
Four BI11s with common Output Enable.
Eight BI11s with common Output Enable.
XB
Z
BI14
Availability:
OE
BI11, BI14, and BI18 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
XB0
XB1
XB2
XB3
Type: Hard
Macro Port Definition:
A0
A1
A2
A3
Z0
Z1
Z2
Z3
BI11 (Z0,XB0,A0,OE);
BI14 ([Z0..Z3],[XB0..XB3],[A0..A3],OE);
BI18 ([Z0..Z7],[XB0..XB7],[A0..A7],OE);
Truth Table:
BI18
OE
Do not drive XB0~XBn-1 when OE=1.
Input
Output
OE
A0~An-1
XB0~XBn-1
XB0~XBn-1
Z0~Zn-1
0
0
1
x
x
d
d
Z
Z
d
d
X
d
d = any pattern of 1s and 0s on an input or set of inputs, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
284
Bidirectional Pins
BI21, BI24, and BI28
BI21
OE
Function:
BI21:
BI24:
BI28:
1-bit bidirectional pin with inverted output.
Four BI21s with common Output Enable.
Eight BI21s with common Output Enable.
A
XB
Z
Availability:
BI24
BI21, BI24, and BI28 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
Type: Hard
OE
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Macro Port Definition:
Z0
Z1
Z2
Z3
BI21 (Z0,XB0,A0,OE);
BI24 ([Z0..Z3],[XB0..XB3],[A0..A3],OE);
BI28 ([Z0..Z7],[XB0..XB7],[A0..A7],OE);
Truth Table:
BI28
Do not drive XB0~XBn-1 when OE=1.
OE
Input
Output
OE
A0~An-1
XB0~XBn-1
XB0~XBn-1
Z0~Zn-1
0
0
1
x
x
d
d
Z
Z
d
d
X
d
d = any pattern of 1s and 0s on an input or set of inputs,
d = inverse of d, x = don’t care, X = X (unknown) state,
Z = high impedance state, - = appears in output column if
a bidirectional pin acts as an input pin.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
285
Bidirectional Pins
BI31, BI34, and BI38
BI31
OE
Function:
BI31:
BI34:
BI38:
1-bit bidirectional pin with active low Output Enable.
Four BI31s with common Output Enable.
Eight BI31s with common Output Enable.
A
XB
Z
Availability:
BI34
BI31, BI34, and BI38 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
OE
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Type: Hard
Macro Port Definition:
Z0
Z1
Z2
Z3
BI31 (Z0,XB0,A0,OE);
BI34 ([Z0..Z3],[XB0..XB3],[A0..A3],OE);
BI38 ([Z0..Z7],[XB0..XB7],[A0..A7],OE);
Truth Table:
BI38
Do not drive XB0~XBn-1 when OE=0.
OE
Input
Output
OE
A0~An-1
XB0~XBn-1
0
1
1
d
x
x
Z
d
Z
XB0~XBn-1 Z0~Zn-1
d
-
d
d
X
d = any pattern of 1s and 0s on an input or set of inputs,
x = don’t care, X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
286
Bidirectional Pins
BI41, BI44, and BI48
BI41
OE
Function:
BI41:
BI44:
BI48:
1-bit bidirectional pin with inverted output and active
low Output Enable.
Four BI41s with common Output Enable.
Eight BI41s with common Output Enable.
A
XB
Z
BI44
Availability:
OE
BI41, BI44, and BI48 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Type: Hard
Macro Port Definition:
Z0
Z1
Z2
Z3
BI41 (Z0,XB0,A0,OE);
BI44 ([Z0..Z3],[XB0..XB3],[A0..A3],OE);
BI48 ([Z0..Z7],[XB0..XB7],[A0..A7],OE);
Truth Table:
BI48
Do not drive XB0~XBn-1 when OE=0.
OE
Input
Output
OE
A0~An-1
XB0~XBn-1
XB0~XBn-1
Z0~Zn-1
0
1
1
d
x
x
Z
d
Z
d
-
d
d
X
d = any pattern of 1s and 0s on an input or set of inputs,
d = inverse of d, x = don’t care, X = X (unknown) state,
Z = high impedance state, - = appears in output column if a
bidirectional pin acts as an input pin.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
287
Bidirectional Pins
BIID11, BIID14, and BIID18
BIID11
OE
Function:
BIID11:
BIID14:
1-bit bidirectional pin with registered input.
Four BIID11s with common clock and Output
Enable.
Eight BIID11s with common clock and Output
Enable.
BIID18:
A
XB
D Q
BIID14
Availability:
OE
BIID11, BIID14, and BIID18 can be used with 1000, 2000,
3000, and 8000 devices.
A0
A1
A2
A3
Type: Hard
XB0
XB1
XB2
XB3
Q0
Q1
Q2
Q3
Macro Port Definition:
BIID11 (Q0,XB0,A0,CLK,OE);
BIID14 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);
BIID18 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
BIID18
Truth Table:
OE
Do not drive XB0~XBn-1 when OE=1.
Input
Output
OE A0~An-1 XB0~XBn-1 CLK XB0~XBn-1
0
0
1
0
0
1
1
x
x
d
x
x
d
d
d
Z
Z
x
x
Z
Z
↑
↑
↑
0
1
0
1
d
d
d
Q0~Qn-1
d
X
d
Q’
Q’
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
288
Bidirectional Pins
BIID21, BIID24, and BIID28
BIID21
OE
Function:
BIID21:
1-bit bidirectional pin with registered input and
inverted output.
Four BIID21s with common clock and Output
Enable.
Eight BIID21s with common clock and Output
Enable.
BIID24:
BIID28:
A
XB
D Q
BIID24
OE
Availability:
BIID21, BIID24, and BIID28 can be used with 1000, 2000,
3000, and 8000 devices.
XB0
XB1
XB2
XB3
Type: Hard
A0
A1
A2
A3
Q0
Q1
Q2
Q3
Macro Port Definition:
BIID21 (Q0,XB0,A0,CLK,OE);
BIID24 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);
BIID28 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
BIID28
OE
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
Input
Output
OE
A0~An-1
XB0~XBn-1
CLK
XB0~XBn-1
Q0~Qn-1
0
0
1
0
0
1
1
x
x
d
x
x
d
d
d
Z
Z
x
x
Z
Z
↑
↑
↑
0
1
0
1
d
d
d
d
X
d
Q’
Q’
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
289
Bidirectional Pins
BIID31, BIID34, and BIID38
BIID31
OE
Function:
BIID31:
1-bit bidirectional pin with registered input and
active low enable.
Four BIID31s with common clock and Output
Enable.
Eight BIID31s with common clock and Output
Enable.
BIID34:
BIID38:
A
XB
D Q
BIID34
OE
Availability:
BIID31, BIID34, and BIID38 can be used with 1000, 2000,
3000, and 8000 devices.
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Type: Hard
Q0
Q1
Q2
Q3
Macro Port Definition:
BIID31 (Q0,XB0,A0,CLK,OE);
BIID34 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);
BIID38 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
BIID38
Truth Table:
OE
Do not drive XB0~XBn-1 when OE=1.
Input
Output
OE
A0~An-1
XB0~XBn-1
CLK
XB0~XBn-1
Q0~Qn-1
0
1
1
0
0
1
1
d
x
x
d
d
x
x
Z
d
Z
Z
Z
x
x
↑
↑
↑
0
1
0
1
d
d
d
-
d
d
X
Q’
Q’
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
290
Bidirectional Pins
BIID41, BIID44, and BIID48
BIID41
OE
Function:
BIID41:
1-bit bidirectional pin with registered input, inverted
output, and active low enable.
Four BIID41s with common clock and Output
Enable.
Eight BIID41s with common clock and Output
Enable.
BIID44:
BIID48:
A
XB
D Q
BIID44
OE
Availability:
BIID41, BIID44, and BIID48 can be used with 1000, 2000,
3000, and 8000 devices.
Type: Hard
XB0
XB1
XB2
XB3
A0
A1
A2
A3
Q0
Q1
Q2
Q3
Macro Port Definition:
BIID41 (Q0,XB0,A0,CLK,OE);
BIID44 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);
BIID48 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
BIID48
Truth Table:
OE
Do not drive XB0~XBn-1 when OE=1.
A0
A1
A2
A3
A4
A5
A6
A7
Input
OE
A0~An-1
0
1
1
0
0
1
1
d
x
x
d
d
x
x
Output
XB0~XBn-1 CLK XB0~XBn-1
Q0~Qn-1
↑
↑
↑
0
1
0
1
d
d
X
Q’
Q’
Q’
Q’
Z
d
Z
Z
Z
x
x
d
d
d
-
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,
Q’ = previous output of flip-flop or latch, x = don’t care, X = X (unknown) state,
Z = high impedance state, ↑ = rising clock edge,
- = appears in output column if a bidirectional pin acts as an input pin.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
291
Bidirectional Pins
BIID51, BIID54, and BIID58
BIID51
OE
Function:
BIID51:
1-bit bidirectional pin with registered input and
inverted clock.
Four BIID51s with common clock and Output
Enable.
Eight BIID51s with common clock and Output
Enable.
BIID54:
BIID58:
A
XB
D Q
BIID54
Availability:
OE
BIID51, BIID54, and BIID58 can be used with 1000, 2000,
3000, and 8000 devices.
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Type: Hard
Q0
Q1
Q2
Q3
Macro Port Definition:
BIID51 (Q0,XB0,A0,CLK,OE);
BIID54 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);
BIID58 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
BIID58
Truth Table:
OE
Do not drive XB0~XBn-1 when OE=1.
Input
Output
OE
A0~An-1
XB0~XBn-1
CLK
XB0~XBn-1
Q0~Qn-1
0
0
1
0
0
1
1
x
x
d
x
x
d
d
d
Z
Z
x
x
Z
Z
↓
↓
↓
0
1
0
1
d
d
d
d
X
d
Q’
Q’
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin,
↓ = falling clock edge.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
292
Bidirectional Pins
BIID61, BIID64, and BIID68
BIID61
OE
Function:
BIID61:
1-bit bidirectional pin with registered input, inverted
output, and inverted clock.
Four BIID61s with common clock and Output
Enable.
Eight BIID61s with common clock and Output
Enable.
BIID64:
BIID68:
A
XB
D Q
BIID64
OE
Availability:
BIID61, BIID64, and BIID68 can be used with 1000, 2000,
3000, and 8000 devices.
XB0
XB1
XB2
XB3
Type: Hard
A0
A1
A2
A3
Q0
Q1
Q2
Q3
Macro Port Definition:
BIID61 (Q0,XB0,A0,CLK,OE);
BIID64 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);
BIID68 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
BIID68
Truth Table:
OE
Do not drive XB0~XBn-1 when OE=1.
A0
A1
A2
A3
A4
A5
A6
A7
Input
Output
OE
A0~An-1
XB0~XBn-1
CLK
XB0~XBn-1
Q0~Qn-1
0
0
1
0
0
1
1
x
x
d
x
x
d
d
d
Z
Z
x
x
Z
Z
↓
↓
↓
0
1
0
1
d
d
d
d
X
d
Q’
Q’
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,
Q’ = previous output of flip-flop or latch,
x = don’t care, X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin,
↓ = falling clock edge.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
293
Bidirectional Pins
BIID71, BIID74, and BIID78
BIID71
OE
Function:
BIID71:
1-bit bidirectional pin with registered input, active
low enable, and inverted clock.
Four BIID71s with common clock and Output
Enable.
Eight BIID71s with common clock and Output
Enable.
BIID74:
BIID78:
A
XB
D Q
BIID74
Availability:
OE
BIID71, BIID74, and BIID78 can be used with 1000, 2000,
3000, and 8000 devices.
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Type: Hard
Q0
Q1
Q2
Q3
Macro Port Definition:
BIID71 (Q0,XB0,A0,CLK,OE);
BIID74 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);
BIID78 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
BIID78
Truth Table:
OE
Do not drive XB0~XBn-1 when OE=1.
Input
Output
OE
A0~An-1
XB0~XBn-1
CLK
XB0~XBn-1
Q0~Qn-1
0
1
1
0
0
1
1
d
x
x
d
d
x
x
Z
d
Z
Z
Z
x
x
↓
↓
↓
0
1
0
1
d
d
d
-
d
d
X
Q’
Q’
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs,
Q’ = previous output of flip-flop or latch,
x = don’t care, X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin,
↓ = falling clock edge.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
294
Bidirectional Pins
BIID81, BIID84, and BIID88
BIID81
OE
Function:
BIID81:
1-bit bidirectional pin with registered input, inverted
output, active low enable, and inverted clock.
Four BIID81s with common clock and Output
Enable.
Eight BIID81s with common clock and Output
Enable.
BIID84:
BIID88:
A
XB
D Q
BIID84
OE
Availability:
BIID81, BIID84, and BIID88 can be used with 1000, 2000,
3000, and 8000 devices.
XB0
XB1
XB2
XB3
Type: Hard
A0
A1
A2
A3
Q0
Q1
Q2
Q3
Macro Port Definition:
BIID81 (Q0,XB0,A0,CLK,OE);
BIID84 ([Q0..Q3],[XB0..XB3],[A0..A3],CLK,OE);
BIID88 ([Q0..Q7],[XB0..XB7],[A0..A7],CLK,OE);
BIID88
Truth Table:
OE
Do not drive XB0~XBn-1 when OE=1.
Input
OE
A0~An-1
0
1
1
0
0
1
1
d
x
x
d
d
x
x
Output
XB0~XBn-1 CLK XB0~XBn-1
Q0~Qn-1
↓
↓
↓
0
1
0
1
d
d
X
Q’
Q’
Q’
Q’
Z
d
Z
Z
Z
x
x
d
d
d
-
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state, ↓ = falling clock edge,
- = appears in output column if a bidirectional pin acts as an input pin.
ispLSI Macro Library Reference Manual
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
A0
A1
A2
A3
A4
A5
A6
A7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
295
Bidirectional Pins
BIIL11, BIIL14, and BIIL18
BIIL11
OE
Function:
BIIL11:
BIIL14:
BIIL18:
1-bit bidirectional pin with latched input.
Four BIIL11s with common G and Output Enable.
Eight BIIL11s with common G and Output Enable.
A
XB
D Q
G
Availability:
BIIL14
BIIL11, BIIL14, and BIIL18 can be used with 1000, 2000,
3000, and 8000 devices.
OE
Type: Hard
Macro Port Definition:
BIIL11 (Q0,XB0,A0,G,OE);
BIIL14 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);
BIIL18 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
A0
A1
A2
A3
XB0
XB1
XB2
XB3
G
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
Q0
Q1
Q2
Q3
BIIL18
Input
OE
Output
OE
A0~An-1
XB0~XBn-1
G
XB0~XBn-1
Q0~Qn-1
0
1
0
0
1
x
d
x
x
d
x
Z
d
Z
Z
0
0
1
1
1
d
d
Q’
Q’
d
X
d
d = any pattern of 1s and 0s on an input or set of inputs,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
A0
A1
A2
A3
A4
A5
A6
A7
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
G
ispLSI Macro Library Reference Manual
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
296
Bidirectional Pins
BIIL21, BIIL24, and BIIL28
BIIL21
OE
Function:
BIIL21:
1-bit bidirectional pin with latched input and
inverted output.
Four BIIL21s with common G and Output Enable.
Eight BIIL21s with common G and Output Enable.
BIIL24:
BIIL28:
A
XB
D Q
G
Availability:
BIIL24
BIIL21, BIIL24, and BIIL28 can be used with 1000, 2000,
3000, and 8000 devices.
Type: Hard
Macro Port Definition:
BIIL21 (Q0,XB0,A0,G,OE);
BIIL24 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);
BIIL28 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
OE
A0
A1
A2
A3
XB0
XB1
XB2
XB3
G
Q0
Q1
Q2
Q3
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
BIIL28
Input
OE
Output
OE
A0~An-1
XB0~XBn-1
G
XB0~XBn-1
Q0~Qn-1
0
1
0
0
1
x
d
x
x
d
x
Z
d
Z
Z
0
0
1
1
1
d
d
Q’
Q’
d
X
d
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
A0
A1
A2
A3
A4
A5
A6
A7
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
G
ispLSI Macro Library Reference Manual
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
297
Bidirectional Pins
BIIL31, BIIL34, and BIIL38
BIIL31
OE
Function:
BIIL31:
1-bit bidirectional pin with latched input and active
low enable.
Four BIIL31s with common G and Output Enable.
Eight BIIL31s with common G and Output Enable.
BIIL34:
BIIL38:
A
XB
D Q
G
Availability:
BIIL34
OE
BIIL31, BIIL34, and BIIL38 can be used with 1000, 2000,
3000, and 8000 devices.
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Type: Hard
Macro Port Definition:
BIIL31 (Q0,XB0,A0,G,OE);
BIIL34 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);
BIIL38 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
G
Q0
Q1
Q2
Q3
Truth Table:
Do not drive XB0~XBn-1 when OE=0.
BIIL38
Input
Output
OE
OE
A0~An-1
XB0~XBn-1
G
XB0~XBn-1
Q0~Qn-1
0
1
0
1
1
d
x
d
x
x
Z
x
Z
d
Z
0
0
1
1
1
d
d
-
Q’
Q’
d
d
X
d = any pattern of 1s and 0s on an input or set of inputs,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
A0
A1
A2
A3
A4
A5
A6
A7
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
G
ispLSI Macro Library Reference Manual
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
298
Bidirectional Pins
BIIL41, BIIL44, and BIIL48
BIIL41
OE
Function:
BIIL41:
1-bit bidirectional pin with latched input, inverted
output, and active low enable.
Four BIIL41s with common G and Output Enable.
Eight BIIL41s with common G and Output Enable.
BIIL44:
BIIL48:
A
XB
D Q
G
Availability:
BIIL44
BIIL41, BIIL44, and BIIL48 can be used with 1000, 2000,
3000, and 8000 devices.
OE
Type: Hard
Macro Port Definition:
BIIL41 (Q0,XB0,A0,G,OE);
BIIL44 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);
BIIL48 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
A0
A1
A2
A3
XB0
XB1
XB2
XB3
G
Q0
Q1
Q2
Q3
Truth Table:
Do not drive XB0~XBn-1 when OE=0.
BIIL48
Input
OE
Output
OE
A0~An-1
XB0~XBn-1
G
XB0~XBn-1
Q0~Qn-1
0
1
0
1
1
d
x
d
x
x
Z
x
Z
d
Z
0
0
1
1
1
d
d
-
Q’
Q’
d
d
X
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = X (unknown) state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
A0
A1
A2
A3
A4
A5
A6
A7
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
G
ispLSI Macro Library Reference Manual
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
299
Bidirectional Pins
BIIL51, BIIL54, and BIIL58
BIIL51
OE
Function:
BIIL51:
1-bit bidirectional pin with latched input and
inverted G.
Four BIIL51s with common G and Output Enable.
Eight BIIL51s with common G and Output Enable.
BIIL54:
BIIL58:
A
XB
D Q
G
Availability:
BIIL54
BIIL51, BIIL54, and BIIL58 can be used with 1000, 2000,
3000, and 8000 devices.
OE
A0
A1
A2
A3
Type: Hard
Macro Port Definition:
BIIL51 (Q0,XB0,A0,G,OE);
BIIL54 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);
BIIL58 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
XB0
XB1
XB2
XB3
G
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
Q0
Q1
Q2
Q3
BIIL58
Input
Output
OE
OE
A0~An-1
XB0~XBn-1
G
XB0~XBn-1
Q0~Qn-1
0
0
1
0
1
x
x
d
x
d
d
Z
Z
x
Z
0
0
0
1
1
d
d
d
X
d
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = unknown state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
A0
A1
A2
A3
A4
A5
A6
A7
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
G
ispLSI Macro Library Reference Manual
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
300
Bidirectional Pins
BIIL61, BIIL64, and BIIL68
BIIL61
OE
Function:
BIIL61:
1-bit bidirectional pin with latched input, inverted
output, and inverted G.
Four BIIL61s with common G and Output Enable.
Eight BIIL61s with common G and Output Enable.
BIIL64:
BIIL68:
A
XB
D Q
G
Availability:
BIIL64
BIIL61, BIIL64, and BIIL68 can be used with 1000, 2000,
3000, and 8000 devices.
OE
Type: Hard
Macro Port Definition:
BIIL61 (Q0,XB0,A0,G,OE);
BIIL64 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);
BIIL68 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
A0
A1
A2
A3
XB0
XB1
XB2
XB3
G
Q0
Q1
Q2
Q3
Truth Table:
Do not drive XB0~XBn-1 when OE=1.
BIIL68
Input
OE
Output
OE
A0~An-1
XB0~XBn-1
G
XB0~XBn-1
Q0~Qn-1
0
0
1
0
1
x
x
d
x
d
d
Z
Z
x
Z
0
0
0
1
1
d
d
d
X
d
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = unknown state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
A0
A1
A2
A3
A4
A5
A6
A7
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
G
ispLSI Macro Library Reference Manual
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
301
Bidirectional Pins
BIIL71, BIIL74, and BIIL78
BIIL71
OE
Function:
BIIL71:
1-bit bidirectional pin with latched input, active low
enable, and inverted G.
Four BIIL71s with common G and Output Enable.
Eight BIIL71s with common G and Output Enable.
BIIL74:
BIIL78:
A
XB
D Q
G
Availability:
BIIL74
OE
BIIL71, BIIL74, and BIIL78 can be used with 1000, 2000,
3000, and 8000 devices.
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Type: Hard
Macro Port Definition:
BIIL71 (Q0,XB0,A0,G,OE);
BIIL74 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);
BIIL78 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
G
Truth Table:
Q0
Q1
Q2
Q3
BIIL78
Do not drive XB0~XBn-1 when OE=0.
OE
Input
Output
OE
A0~An-1
XB0~XBn-1
G
XB0~XBn-1
Q0~Qn-1
0
1
1
0
1
d
x
x
d
x
Z
d
Z
Z
x
0
0
0
1
1
d
d
-
d
d
X
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = unknown state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
A0
A1
A2
A3
A4
A5
A6
A7
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
G
ispLSI Macro Library Reference Manual
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
302
Bidirectional Pins
BIIL81, BIIL84, and BIIL88
BIIL81
OE
Function:
BIIL81:
1-bit bidirectional pin with latched input, inverted
output, active low enable, and inverted G.
Four BIIL81s with common G and Output Enable.
Eight BIIL81s with common G and Output Enable.
BIIL84:
BIIL88:
A
XB
D Q
G
Availability:
BIIL84
OE
BIIL81, BIIL84, and BIIL88 can be used with 1000, 2000,
3000, and 8000 devices.
A0
A1
A2
A3
XB0
XB1
XB2
XB3
Type: Hard
Macro Port Definition:
BIIL81 (Q0,XB0,A0,G,OE);
BIIL84 ([Q0..Q3],[XB0..XB3],[A0..A3],G,OE);
BIIL88 ([Q0..Q7],[XB0..XB7],[A0..A7],G,OE);
G
Q0
Q1
Q2
Q3
Truth Table:
BIIL88
Do not drive XB0~XBn-1 when OE=0.
OE
Input
Output
OE
A0~An-1
XB0~XBn-1
G
XB0~XBn-1
Q0~Qn-1
0
1
1
0
1
d
x
x
d
x
Z
d
Z
Z
x
0
0
0
1
1
d
d
-
d
d
X
Q’
Q’
d = any pattern of 1s and 0s on an input or set of inputs, d = inverse of d,
Q’ = previous output of flip-flop or latch, x = don’t care,
X = unknown state, Z = high impedance state,
- = appears in output column if a bidirectional pin acts as an input pin.
A0
A1
A2
A3
A4
A5
A6
A7
XB0
XB1
XB2
XB3
XB4
XB5
XB6
XB7
G
ispLSI Macro Library Reference Manual
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
303
Input Pins
Input Pins
IB11
IB11
XI
Function: 1-bit input pin.
Z
Availability:
IB11 can be used with 1000, 2000, 3000, 5000, and 8000 devices.
Type: Hard
Macro Port Definition:
IB11(Z0,XI0);
Truth Table:
Input
Output
XI0
Z0
d
d
d = any pattern of 1s and 0s on an input or set of inputs,
XI0 = external input pin, Z0 = output.
ispLSI Macro Library Reference Manual
304
Input Pins
ID11, ID14, and ID18
ID11
Function:
ID11:
ID14:
ID18:
XI
D
Q
1-bit registered input pin.
Four ID11s with common clock.
Eight ID11s with common clock.
Availability:
ID14
ID11, ID14, and ID18 can be used with 1000, 2000, 3000,
and 8000 devices.
Type: Hard
XI0
D
Q0
XI1
D
Q1
XI2
D
Q2
XI3
D
Q3
Macro Port Definition:
ID11 (Q0,XI0,CLK);
ID14 ([Q0..Q3],[XI0..XI3],CLK);
ID18 ([Q0..Q7],[XI0..XI7],CLK);
ID18
Truth Table:
Input
Output
XI0~XIn-1
CLK
Q0~Qn-1
d
x
x
↑
0
1
d
Q0’~Qn’
Q0’~Qn’
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
XI0
D
Q0
XI1
D
Q1
XI2
D
Q2
XI3
D
Q3
XI4
D
Q4
XI5
D
Q5
XI6
D
Q6
XI7
D
Q7
305
Input Pins
ID21, ID24, and ID28
ID21
Function:
ID21:
ID24:
ID28:
XI
D
Q
1-bit registered input pin with inverted clock.
Four ID21s with common clock.
Eight ID21s with common clock.
Availability:
ID24
ID21, ID24, and ID28 can be used with1000, 2000, 3000,
and 8000 devices.
XI0
Type: Hard
XI2
XI1
XI3
Macro Port Definition:
D
Q0
D
Q1
D
Q2
D
Q3
ID21 (Q0,XI0,CLK);
ID24 ([Q0..Q3],[XI0..XI3],CLK);
ID28 ([Q0..Q7],[XI0..XI7],CLK);
ID28
Truth Table:
XI0
Input
Output
XI0~XIn-1
CLK
Q0~Qn-1
d
x
x
↓
0
1
d
Q0’~Qn’
Q0’~Qn’
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↓ = falling clock edge.
XI1
XI2
XI3
XI4
XI5
XI6
XI7
ispLSI Macro Library Reference Manual
D
Q0
D
Q1
D
Q2
D
Q3
D
Q4
D
Q5
D
Q6
D
Q7
306
Input Pins
IL11, IL14, and IL18
IL11
Function:
IL11:
IL14:
IL18:
XI
1-bit input pin with D latch on input.
Four IL11s with common G.
Eight IL11s with common G.
D
Q
G
Availability:
IL14
IL11, IL14, and IL18 can be used with 1000, 2000, 3000,
and 8000 devices.
XI0
XI1
XI2
Type: Hard
XI3
D
Q0
D
Q1
D
Q2
D
Q3
Macro Port Definition:
IL11 (Q0,XI0,G);
IL14 ([Q0..Q3],[XI0..XI3],G);
IL18 ([Q0..Q7],[XI0..XI7],G);
G
IL18
XI0
Truth Table:
Input
Output
XI1
XI2
XI0~XIn-1
G
Q0~Qn-1
x
d
0
1
Q0’~Qn’
d
d = any pattern of 1s and 0s on an input or set of inputs,
G = gate for latch, x = don’t care,
Q0’~Qn’ = previous output of flip-flop or latch.
XI3
XI4
XI5
XI6
XI7
D
Q0
D
Q1
D
Q2
D
Q3
D
Q4
D
Q5
D
Q6
D
Q7
G
ispLSI Macro Library Reference Manual
307
Input Pins
IL21, IL24, and IL28
IL21
Function:
IL21:
IL24:
IL28:
XI
1-bit input pin with D latch on input, inverted enable.
Four IL21s with common G.
Eight IL21s with common G.
D
Q
G
Availability:
IL24
IL21, IL24, and IL28 can be used with 1000, 2000, 3000,
and 8000 devices.
Type: Hard
XI0
XI1
XI2
XI3
Macro Port Definition:
IL21 (Q0,XI0,G);
IL24 ([Q0..Q3],[XI0..XI3],G);
IL28 ([Q0..Q7],[XI0..XI7],G);
D
Q0
D
Q1
D
Q2
D
Q3
G
Truth Table:
IL28
Input
Output
XI0
XI0~XIn-1
G
Q0~Qn-1
XI1
d
x
0
1
d
Q0’~Qn’
XI2
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care.
XI3
XI4
XI5
XI6
XI7
D
Q0
D
Q1
D
Q2
D
Q3
D
Q4
D
Q5
D
Q6
D
Q7
G
ispLSI Macro Library Reference Manual
308
Output Pins
Output Pins
OB11
OB11
A
Function: 1-bit output pin.
XO
Availability:
OB11 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
Type: Hard
Macro Port Definition:
OB11 (XO0,A0);
Truth Table:
Input
Output
A0
XO0
d
d
d = any pattern of 1s and 0s on an input or set of inputs
ispLSI Macro Library Reference Manual
309
Output Pins
OB21, OB24, and OB28
OB21
Function:
OB21:
OB24:
OB28:
1-bit inverting output pin.
Four OB21s.
Eight OB21s.
A
XO
Availability:
OB24
OB21, OB24, and OB28 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
A0
Type: Hard
A2
A1
A3
Macro Port Definition:
OB21 (XO0,A0);
OB24 ([XO0..XO3],[A0..A3]);
OB28 ([XO0..XO7],[A0..A7]);
Input
Output
A0~An-1
XO0~XOn-1
d
d
d = any pattern of 1s and 0s on an input or set of inputs,
d = inverse of d.
A0
A2
A3
A4
A5
A6
A7
ispLSI Macro Library Reference Manual
XO1
XO2
XO3
OB28
A1
Truth Table:
XO0
XO0
XO1
XO2
XO3
XO4
XO5
XO6
XO7
310
Output Pins
OT11, OT14, and OT18
OE
Function:
OT11:
OT14:
OT18:
1-bit 3-state output pin.
Four OT11s with common Output Enable.
Eight OT11s with common Output Enable.
OT11
XO
A
OT14
Availability:
OT11, OT14, and OT18 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
OE
A0
Type: Hard
A1
Macro Port Definition:
A2
OT11 (XO0,A0,OE);
OT14 ([XO0..XO3],[A0..A3],OE);
OT18 ([XO0..XO7],[A0..A7],OE);
A3
XO0
XO1
XO2
XO3
OT18
Truth Table:
OE
Input
Output
OE
A0~An-1
XO0~XOn-1
A0
0
1
x
d
Z
d
A1
d = any pattern of 1s and 0s on an input or set of inputs,
x = don’t care, Z = high impedance state.
A2
A3
A4
A5
A6
A7
ispLSI Macro Library Reference Manual
XO0
XO1
XO2
XO3
XO4
XO5
XO6
XO7
311
Output Pins
OT21, OT24, and OT28
OT21
OE
Function:
OT21:
OT24:
OT28:
1-bit inverting 3-state output pin.
Four OT21s with common Output Enable.
Eight OT21s with common Output Enable.
XO
A
OT24
Availability:
OT21, OT24, and OT28 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
OE
A0
Type: Hard
A1
Macro Port Definition:
A2
OT21 (XO0,A0,OE);
OT24 ([XO0..XO3],[A0..A3],OE);
OT28 ([XO0..XO7],[A0..A7],OE);
A3
XO0
XO1
XO2
XO3
OT28
Truth Table:
OE
Input
Output
OE
A0~An-1
XO0~XOn-1
A0
0
1
x
d
Z
d
A1
d = any pattern of 1s and 0s on an input or set of inputs,
d = inverse of d, x = don’t care, Z = high impedance state.
A2
A3
A4
A5
A6
A7
ispLSI Macro Library Reference Manual
XO0
XO1
XO2
XO3
XO4
XO5
XO6
XO7
312
Output Pins
OT31, OT34, and OT38
OT31
OE
Function:
OT31:
OT34:
OT38:
1-bit 3-state output pin with active low enable.
Four OT31s with common Output Enable.
Eight OT31s with common Output Enable.
Availability:
A
XO
OT34
OT31, OT34, and OT38 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
OE
Type: Hard
A0
A1
Macro Port Definition:
OT31 (XO0,A0,OE);
OT34 ([XO0..XO3],[A0..A3],OE);
OT38 ([XO0..XO7],[A0..A7],OE);
Input
0
1
A3
XO1
XO2
XO3
OT38
Truth Table:
OE
A2
XO0
Output
A0~An-1
d
x
OE
XO0~XOn-1
d
Z
d = any pattern of 1s and 0s on an input or set of inputs,
x = don’t care, Z = high impedance state.
A0
A1
A2
A3
A4
A5
A6
A7
ispLSI Macro Library Reference Manual
XO0
XO1
XO2
XO3
XO4
XO5
XO6
XO7
313
Output Pins
OT41, OT44, and OT48
OT41
Function:
OE
OT41:
OT44:
OT48:
A
1-bit inverting 3-state output pin with active low enable.
Four OT41s with common Output Enable.
Eight OT41s with common Output Enable.
Availability:
XO
OT44
OT41, OT44, and OT48 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
OE
A0
Type: Hard
A1
Macro Port Definition:
A2
OT41 (XO0,A0,OE);
OT44 ([XO0..XO3],[A0..A3],OE);
OT48 ([XO0..XO7],[A0..A7],OE);
A3
XO0
XO1
XO2
XO3
OT48
Truth Table:
OE
Input
Output
OE
A0~An-1
XO0~XOn-1
A0
0
1
d
x
d
Z
A1
d = any pattern of 1s and 0s on an input or set of inputs,
d = inverse of d, x = don’t care, Z = high impedance state.
A2
A3
A4
A5
A6
A7
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XO0
XO1
XO2
XO3
XO4
XO5
XO6
XO7
314
Logic Gates
This chapter contains information on logic gate macros.
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Logic Gates
Logic Gates
AND2 through AND18
AND2
Function:
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18
input AND gates.
AND3
Availability:
AND2 through AND18 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
...
Type: Logic Primitive
AND18
Macro Port Definition:
AND2 (Z0,A0,A1);
AND3 (Z0,[A0..A2]);
AND4 (Z0,[A0..A3]);
...
AND18 (Z0,[A0..A17]);
Truth Table:
The truth table is the same for all ANDs.
Input
Output
All inputs high
One or more inputs low
High
Low
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Logic Gates
BUF and INV
Function:
BUF:
INV:
BUF
single input buffer.
single input inverter.
INV
Availability:
BUF and INV can be used with 1000, 2000, 3000, 5000,
and 8000 devices.
Type: Logic Primitive
Macro Port Definition:
BUF (Z0,A0);
INV (ZN0,A0);
Truth Tables:
For BUF:
Input
Output
High
Low
High
Low
For INV:
Input
Output
High
Low
Low
High
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Logic Gates
NAND2 through NAND12, and NAND16
NAND2
Function:
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 16 input NAND gates.
Availability:
NAND3
NAND2 through NAND12, and NAND16 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
Type: Logic Primitive
Macro Port Definition:
NAND2 (ZN0,A0,A1);
NAND3 (ZN0,[A0..A2]);
NAND4 (ZN0,[A0..A3]);
...
NAND12 (ZN0,[A0..A11]);
NAND16 (ZN0,[A0..A15]);
...
NAND16
Truth Table:
The truth table is the same for all NANDs.
Input
Output
All inputs high
One or more inputs low
Low
High
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Logic Gates
NOR2 through NOR12, and NOR16
NOR2
Function:
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 16 input NOR gates.
Availability:
NOR3
NOR2 through NOR12, and NOR16 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
Type: Logic Primitive
Macro Port Definition:
...
NOR2 (ZN0,A0,A1);
NOR3 (ZN0,[A0..A2]);
NOR4 (ZN0,[A0..A3]);
...
NOR12 (ZN0,[A0..A11]);
NOR16 (ZN0,[A0..A15]);
NOR16
Truth Table:
The truth table is the same for all NORs.
Input
Output
All inputs low
One or more inputs high
High
Low
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Logic Gates
OR2 through OR12, and OR16
OR2
Function:
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 16 input OR gates.
OR3
Availability:
OR2 through OR12, and OR16 can be used with 1000,
2000, 3000, 5000, and 8000 devices.
Type: Logic Primitive
...
Macro Port Definition:
OR2 (Z0,A0,A1);
OR3 (Z0,[A0..A2]);
OR4 (Z0,[A0..A3]);
...
OR12 (Z0,[A0..A11]);
OR16 (Z0,[A0..A15]);
OR16
Truth Table:
The truth table is the same for all ORs.
Input
Output
All inputs low
One or more inputs high
Low
High
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Logic Gates
XNOR2, XNOR3, XNOR4, XNOR7, XNOR8,
and XNOR9
XNOR2
Function:
2, 3, 4, 7, 8, and 9 input XNOR gates.
XNOR3
Availability:
XNOR2, XNOR3, XNOR4, XNOR7, XNOR8, and XNOR9 can be
used with 1000, 2000, 3000, 5000, and 8000 devices.
XNOR4
Type:
Logic Primitive: XNOR2, XNOR3, and XNOR4.
Soft:
XNOR9.
Hard:
XNOR7 and XNOR8.
XNOR7
Logic Resources:
*
Macro
PT
GLB
Output
Level
XNOR2
XNOR3
XNOR4
XNOR7
XNOR8
2
4
8
12
16
.25
.25
.5
1
1
1
1
1
1
1
1
1
1
1
1
ZN0: 2 PT
XNOR8
B0: 16 PT
Macro Port Definition:
XNOR2 (ZN0,A0,A1);
XNOR3 (ZN0,[A0..A2]);
XNOR4 (ZN0,[A0..A3]);
XNOR7 (ZN0,[A0..A6]);
XNOR8 (ZN0,[A0..A7]);
XNOR9 (ZN0,[A0..A8]);
XNOR9_1 (B0,[A0..A7]);
XNOR9_2 (ZN0,B0,A8);
XNOR9
Truth Table:
The truth table is the same for all XNORs.
Input
Output
All inputs low
Odd number of inputs high
Even number of inputs high
High
Low
High
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Logic Gates
XOR2, LXOR2, XOR3, XOR4, XOR8, and XOR9
XOR2
Function:
2, 3, 4, 8, and 9 input XOR gates.
Availability:
LXOR2
LXOR2, XOR2, XOR3, XOR4, XOR8, and XOR9 can be used
with 1000, 2000, 3000, 5000, and 8000 devices.
Type:
LX2
XOR3
Logic Primitive:
Soft:
Hard:
Physical (in the silicon):
XOR2, XOR3, and XOR4.
XOR9.
XOR8.
LXOR2.
LXOR2 specifies the use of the physical XOR2 gate in the GLB.
See the Lattice Semiconductor Data Book for more information.
XOR4
Logic Resources:
*
Macro
PT
GLB
Output
Level
XOR2
XOR3
XOR4
XOR8
2
4
8
16
.25
.25
.5
1
1
1
1
1
1
1
1
1
Z0: 2 PT
XOR8
B0: 16 PT
LXOR2: depends on usage.
Macro Port Definition:
XOR2 (Z0,A0,A1);
LXOR2 (Z0,A0,A1);
XOR3 (Z0,[A0..A2]);
XOR4 (Z0,[A0..A3]);
XOR8 (Z0,[A0..A7]);
XOR9 (Z0,[A0..A8]);
XOR9_1 (B0,[A0..A7]);
XOR9_2 ([Z0,B0,A8);
XOR9
Truth Table:
The truth table is the same for all XORs.
Input
Output
All inputs low
Odd number of inputs high
Even number of inputs high
Low
High
Low
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MUX/DMUX
This chapter contains information on the following macros:
■
■
Multiplexers
Demultiplexers
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Multiplexers
Multiplexers
MUX2
MUX2 and MUX2E
A0
A1
Function:
MUX2:
MUX2E:
1 of 2 input mux.
1 of 2 input mux with enable.
Z0
S0
Availability:
Both MUX2 and MUX2E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
MUX2E
A0
A1
Type: Soft
Z0
EN
Macro Port Definition:
S0
MUX2 (Z0,A0,A1,S0);
MUX2E (Z0,A0,A1,EN,S0);
Truth Table:
Gray areas (EN) apply only to MUX2E.
Input
Output
EN
S0
Z0
1
1
0
0
1
x
A0
A1
0
A0..An-1 = inputs, x = don’t care.
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Multiplexers
MUX4 and MUX4E
Function:
MUX4
MUX4:
MUX4E:
1 of 4 input mux.
1 of 4 input mux with enable.
A0
A1
A2
Availability:
A3
Both MUX4 and MUX4E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Z0
S0
Type: Soft
S1
Macro Port Definition:
MUX4 (Z0,[A0..A3],S0,S1);
MUX4E (Z0,[A0..A3],EN,S0,S1);
MUX4E
A0
A1
Truth Table:
A2
Gray areas (EN) apply only to MUX4E.
A3
Input
Output
EN
S0
EN
S1
S0
Z0
1
1
1
1
0
0
0
1
1
x
0
1
0
1
x
A0
A1
A2
A3
0
Z0
S1
A0..An-1 = inputs, x = don’t care.
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Multiplexers
MUX8 and MUX8E
MUX8
Function:
MUX8:
MUX8E:
1 of 8 input mux.
1 of 8 input mux with enable.
Availability:
Both MUX8 and MUX8E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
A0
A1
A2
A3
A4
A5
A6
A7
Z0
Type: Soft
S0
S1
S2
Macro Port Definition:
MUX8 (Z0,[A0..A7],[S0..S2]);
MUX8E (Z0,[A0..A7],EN,[S0..S2]);
Truth Table:
MUX8E
Gray areas (EN) apply only to MUX8E.
A0
A1
A2
A3
A4
A5
A6
A7
Input
Output
EN
S2
S1
S0
Z0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
A0
A1
A2
A3
A4
A5
A6
A7
0
Z0
EN
S0
S1
S2
A0..An-1 = inputs, x = don’t care.
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Multiplexers
MUX16 and MUX16E
Function:
MUX16:
MUX16E:
One of 16 input mux.
One of 16 input mux with enable.
Availability:
Both MUX16 and MUX16E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Schematics appear on the following pages.
MUX16
MUX16E
A0
A0
A1
A1
A2
A2
A3
A3
A4
A4
A5
A6
A5
A6
A7
A7
A8
A8
A9
Z0
A9
A10
A10
A11
A11
Macro Port Definition:
A12
A12
MUX16 (Z0,[A0..A15],[S0..S3]);
MUX16E (Z0,[A0..A15],EN,[S0..S3]);
A13
A14
A13
A14
A15
A15
Type: Soft
Z0
EN
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S0
S0
S1
S2
S1
S3
S3
S2
327
Multiplexers
Truth Table:
Gray areas (EN) apply only to MUX16E.
Input
Output
EN
S3
S2
S1
S0
Z0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
0
A0..An-1 = inputs, x = don’t care.
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Multiplexers
MUX16
A0
A1
A2
A3
A4
A5
A6
A7
Z0
A8
A9
A10
A11
A12
A13
A14
A15
S0
S1
S2
S3
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Multiplexers
MUX16E
A0
A1
A2
A3
A4
A5
A6
A7
Z0
A8
A9
A10
A11
A12
A13
A14
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Multiplexers
MUX22 and MUX22E
Function:
MUX22:
MUX22E:
MUX22
Dual 1 of 2 input mux with common select line.
Dual 1 of 2 input mux with common select line and
enable.
Availability:
A0
A1
B0
Z0
B1
Z1
Both MUX22 and MUX22E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
S0
Type: Soft
Macro Port Definition:
MUX22E
MUX22 (Z0,Z1,A0,A1,B0,B1,S0);
MUX22E (Z0,Z1,A0,A1,B0,B1,EN,S0);
A0
Truth Table:
B0
Z0
Gray areas (EN) apply only to MUX22E.
B1
Z1
Input
A1
EN
Output
S0
EN
S0
Z0
Z1
1
1
0
0
1
x
A0
B0
0
A1
B1
0
A0..An-1 = inputs, B0..Bn-1 = inputs,
x = don’t care.
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Multiplexers
MUX24 and MUX24E
MUX24
Function:
MUX24:
MUX24E:
Dual 1 of 4 input mux with common select line.
Dual 1 of 4 input mux with common select line and
enable.
A0
A1
B0
B1
Availability:
Both MUX24 and MUX24E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
C0
C1
Type: Soft
D0
D1
Z0
Z1
Macro Port Definition:
MUX24 (Z0,Z1,A0,A1,B0,B1,C0,C1,D0,D1,S0,S1);
MUX24E (Z0,Z1,A0,A1,B0,B1,C0,C1,D0,D1,EN,S0,S1);
S0
S1
Truth Table:
MUX24E
Gray areas (EN) apply only to MUX24E.
Input
Output
EN
S1
S0
Z0
Z1
1
1
1
1
0
0
0
1
1
x
0
1
0
1
x
A0
B0
C0
D0
0
A1
B1
C1
D1
0
A0..An-1 = inputs, B0..Bn-1 = inputs,
x = don’t care.
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A0
A1
B0
B1
C0
C1
Z0
Z1
D0
D1
EN
S0
S1
332
Multiplexers
MUX42 and MUX42E
Function:
MUX24
MUX42:
MUX42E:
Quad 1 of 2 input mux with common select line.
Quad 1 of 2 input mux with common select line and
enable.
A0
A1
B0
B1
Availability:
Both MUX42 and MUX42E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
C0
C1
Type: Soft
D0
D1
Z0
Z1
Macro Port Definition:
MUX42 ([Z0..Z3],[A0..A3],[B0..B3],S0);
MUX42E ([Z0..Z3],[A0..A3],[B0..B3],EN,S0);
Truth Table:
S0
S1
MUX24E
Gray areas (EN) apply only to MUX42E.
Input
A0
A1
Output
EN
S0
Z0
Z1
Z2
Z3
1
1
0
0
1
x
A0
B0
0
A1
B1
0
A2
B2
0
A3
B3
0
A0..An-1 = inputs, B0..Bn-1 = inputs,
x = don’t care.
B0
B1
C0
C1
Z0
Z1
D0
D1
EN
S0
S1
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Multiplexers
MUX44 and MUX44E
MUX44
Function:
MUX44:
MUX44E:
Quad 1 of 4 input mux with common select line.
Quad 1 of 4 input mux with common select line
and enable.
Availability:
Both MUX44 and MUX44E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
A0
A0
A1
A1
A2
A2
A3
A3
B0
B0
B1
B1
B2
B2
B3
B3
C0
C1
Macro Port Definition:
C2
MUX44 ([Z0..Z3],[A0..A3],[B0..B3],
[C0..C3],[D0..D3],S0,S1);
MUX44_1 (Z0,Z1,A0,A1,B0,B1,C0,C1,
D0,D1,S0,S1);
MUX44_2 (Z2,Z3,A2,A3,B2,B3,C2,C3,
D2,D3,S0,S1);
MUX44E ([Z0..Z3],[A0..A3],[B0..B3],
[C0..C3],[D0..D3],EN,S0,S1);
MUX44E_1 (Z0,Z1,A0,A1,B0,B1,C0,C1,
D0,D1,EN,S0,S1);
MUX44E_2 (Z2,Z3,A2,A3,B2,C3,C2,C3,
D2,D3,EN,S0,S1);
MUX44E
C3
Z0
Z1
Z2
Z3
C0
C1
C2
C3
D0
D0
D1
D1
D2
D2
D3
D3
Z0
Z1
Z2
Z3
EN
S0
S0
S1
S1
Truth Table:
Gray areas (EN) apply only to MUX44E.
Input
Output
EN
S1
S0
Z0
Z1
Z2
Z3
1
1
1
1
0
0
0
1
1
x
0
1
0
1
x
A0
B0
C0
D0
0
A1
B1
C1
D1
0
A2
B2
C2
D2
0
A3
B3
C3
D3
0
A0..An-1 = inputs, B0..Bn-1 = inputs, x = don’t care, C0..Cn-1 = inputs,
D0..Dn-1 = inputs.
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Multiplexers
MUX44A and MUX44AE
MUX44A
Function:
MUX44A:
MUX44AE:
Quad 1 of 4 input mux with common
select line.
Quad 1 of 4 input mux with common
select line and enable.
Availability:
Both MUX44A and MUX44AE can be used with 1000,
2000, 3000, 5000, and 8000 devices.
A0
A0
A1
A1
A2
A2
A3
A3
B0
B0
B1
B1
B2
B2
B3
B3
Schematics appear on the following pages.
C0
Type: Soft
C1
C2
Macro Port Definition:
C3
([Z0..Z3],[A0..A3],[B0..B3],
[C0..C3],[D0..D3],S0,S1);
MUX44AE ([Z0..Z3],[A0..A3],[B0..B3],
[C0..C3],[D0..D3],EN,S0,S1);
MUX44AE
Z0
Z1
C0
Z2
C1
Z3
C2
C3
Z0
Z1
Z2
Z3
MUX44A
D0
D0
D1
D1
D2
D2
D3
D3
Truth Table:
Gray areas (EN) apply only to MUX44AE.
EN
S0
Input
Output
S1
EN
S1
S0
Z0
Z1
Z2
Z3
1
1
1
1
0
0
0
1
1
x
0
1
0
1
x
A0
B0
C0
D0
0
A1
B1
C1
D1
0
A2
B2
C2
D2
0
A3
B3
C3
D3
0
S0
S1
A0..An-1 = inputs, B0..Bn-1 = inputs, x = don’t care,
C0..Cn-1 = inputs, D0..Dn-1 = inputs.
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Multiplexers
MUX44A
A0
A0
B0
A1
C0
A2
D0
A3
Z0
Z0
S0
S1
MUX4
A1
A0
B1
A1
C1
A2
D1
A3
Z0
Z1
S0
S1
MUX4
A2
A0
B2
A1
C2
A2
D2
A3
Z0
Z2
S0
S1
MUX4
A3
A0
B3
A1
C3
A2
D3
A3
Z0
S0
S0
S1
S1
Z3
MUX4
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Multiplexers
MUX44AE
A0
A0
B0
A1
C0
A2
D0
A3
Z0
Z0
EN
S0
S1
MUX4E
A1
A0
B1
A1
C1
A2
D1
A3
Z0
Z1
EN
S0
S1
MUX4E
A2
A0
B2
A1
C2
A2
D2
A3
Z0
Z2
EN
S0
S1
MUX4E
A3
A0
B3
A1
C3
A2
D3
A3
EN
EN
S0
S0
S1
S1
Z0
Z3
MUX4E
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Multiplexers
MUX82 and MUX82E
MUX82
Function:
MUX82:
MUX82E:
Octal 1 of 2 input mux with common select line.
Octal 1 of 2 input mux with common select line
and enable.
Availability:
Both MUX82 and MUX82E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
Macro Port Definition:
MUX82 ([Z0..Z7],[A0..A7],[B0..B7],S0);
MUX82_1 ([Z0..Z3],[A0..A3],[B0..B3],S0);
MUX82_2 ([Z4..Z7],[A4..A7],[B4..B7],S0);
MUX82E ([Z0..Z7],[A0..A7],[B0..B7],EN,S0);
MUX82E_1 ([Z0..Z3],[A0..A3],[B0..B3],EN,S0);
MUX82E_2 ([Z4..Z7],[A4..A7],[B4..B7],EN,S0);
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
S0
MUX82E
Truth Table:
Gray areas (EN) apply only to MUX82E.
Input
Output
EN
S0
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
1
1
0
0
1
x
A0
B0
0
A1
B1
0
A2
B2
0
A3
B3
0
A4
B4
0
A5
B5
0
A6
B6
0
A7
B7
0
A0..An-1 = inputs, B0..Bn-1 = inputs, x = don’t care.
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
EN
S0
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Demultiplexers
Demultiplexers
DMUX2 and DMUX2E
DMUX2
Function:
A0
DMUX2:
DMUX2E:
1 of 2 output demux.
1 of 2 output demux with enable.
Z0
Z1
S0
Availability:
Both DMUX2 and DMUX2E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
DMUX2E
Type: Soft
A0
Macro Port Definition:
Z0
Z1
EN
DMUX2 (Z0,Z1,A0,S0);
DMUX2E Z0,Z1,A0,EN,S0);
S0
Truth Table:
Gray areas (EN) apply only to DMUX2E.
Input
Output
EN
S0
Z0
Z1
1
1
0
0
1
x
A0
0
0
0
A0
0
A0..An-1 = inputs, x = don’t care.
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Demultiplexers
DMUX4 and DMUX4E
DMUX4
Function:
DMUX4:
DMUX4E:
A0
1 of 4 output demux.
1 of 4 output demux with enable.
Z1
Z2
S0
Availability:
Z0
Z3
S1
Both DMUX4 and DMUX4E can be used with 1000, 2000,
3000, 5000, and 8000 devices.
DMUX4E
Type: Soft
A0
Macro Port Definition:
Z0
Z1
DMUX4 ([Z0..Z3],A0,S0,S1);
DMUX4E ([Z0..Z3],A0,EN,S0,S1);
EN
Z2
S0
Z3
S1
Truth Table:
Gray areas (EN) apply only to DMUX4E.
Input
Output
EN
S1
S0
Z0
Z1
Z2
Z3
1
1
1
1
0
0
0
1
1
x
0
1
0
1
x
A0
0
0
0
0
0
A0
0
0
0
0
0
A0
0
0
0
0
0
A0
0
A0..An-1 = inputs, x = don’t care.
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Demultiplexers
DMUX22 and DMUX22E
DMUX22
Function:
DMUX22:
Dual 1 of 2 output demux with common select line.
DMUX22E: Dual 1 of 2 output demux with common select line
and enable.
A0
Y0
A1
Y1
Z0
Availability:
S0
Z1
Both DMUX22 and DMUX22E can be used with 1000,
2000, 3000, 5000, and 8000 devices.
DMUX22E
Type: Soft
Macro Port Definition:
DMUX22 (Y0,Y1,Z0,Z1,A0,A1,S0);
DMUX22E (Y0,Y1,Z0,Z1,A0,A1,EN,S0);
Truth Table:
A0
Y0
A1
Y1
EN
Z0
S0
Z1
Gray areas (EN) apply only to DMUX22E.
Input
Output
EN
S0
Y0
Y1
Z0
Z1
1
1
0
0
1
x
A0
0
0
A1
0
0
0
A0
0
0
A1
0
A0..An-1 = inputs, x = don’t care.
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Demultiplexers
DMUX24 and DMUX24E
DMUX24
Function:
DMUX24:
Dual 1 of 4 output demux with common select line.
DMUX24E: Dual 1 of 4 output demux with common select line
and enable.
A0
W0
A1
W1
X0
X1
Availability:
Y0
Both DMUX24 and DMUX24E can be used with 1000,
2000, 3000, 5000, and 8000 devices.
Y1
Type: Soft
S0
Z0
S1
Z1
Macro Port Definition:
DMUX24 (W0,W1,X0,X1,Y0,Y1,Z0,Z1,A0,A1,S0,S1);
DMUX24_1 (W0,X0,Y0,Z0,A0,S0,S1);
DMUX24_2 (W1,X1,Y1,Z1,A1,S0,S1);
DMUX24E (W0,W1,X0,X1,Y0,Y1,Z0,Z1,A0,A1,EN,S0,S1);
DMUX24E_1 (W0,X0,Y0,Z0,A0,EN,S0,S1);
DMUX24E_2 (W1,X1,Y1,Z1,A1,EN,S0,S1);
DMUX24E
A0
W0
A1
W1
X0
X1
Truth Table:
Gray areas (EN) apply only to DMUX24E.
Y0
Y1
Input
EN
1
1
1
1
S1
0
0
1
1
Output
S0
0
1
0
1
x
W0 W1
A0
0
0
0
0
A1
0
0
0
0
X0
0
A0
0
0
0
X1
0
A1
0
0
0
Y0
0
0
A0
0
0
EN
Y1
0
0
A1
0
0
Z0
0
0
0
A0
0
Z1
0
0
0
A1
0
S0
Z0
S1
Z1
A0..An-1 = inputs, x = don’t care.
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Demultiplexers
DMUX42 and DMUX42E
DMUX42
Function:
DMUX42:
Quad 1 of 2 output demux with common select line.
DMUX42E: Quad 1 of 2 output demux with common select line
and enable.
A0
Y0
A1
Y1
A2
Y2
A3
Y3
Availability:
Z0
Both DMUX42 and DMUX42E can be used with 1000,
2000, 3000, 5000, and 8000 devices.
Z1
Z2
S0
Z3
Type: Soft
Macro Port Definition:
DMUX42E
DMUX42 ([Y0..Y3],[Z0..Z3],[A0..A3],S0);
DMUX42_1 (Y0,Y1,Z0,Z1,A0,A1,S0);
DMUX42_2 (Y2,Y3,Z2,Z3,A2,A3,S0);
DMUX42E ([Y0..Y3],[Z0..Z3],[A0..A3],EN,S0);
DMUX42E_1 (Y0,Y1,Z0,Z1,A0,A1,EN,S0);
DMUX42E_2 (Y2,Y3,Z2,Z3,A2,A3,EN,S0);
A0
Y0
A1
Y1
A2
Y2
A3
Y3
Z0
Truth Table:
Z1
Gray areas (EN) apply only to DMUX42E.
Input
EN
Z2
S0
Z3
Output
EN
S0
Y0
Y1
Y2
Y3
Z0
Z1
Z2
Z3
1
1
0
0
1
x
A0
0
0
A1
0
0
A2
0
0
A3
0
0
0
A0
0
0
A1
0
0
A2
0
0
A3
0
A0..An-1 = inputs, x = don’t care.
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Demultiplexers
DMUX44 and DMUX44E
DMUX44
Function:
A0
W0
A0
W0
DMUX44:
A1
W1
A1
W1
A2
W2
A2
W2
A3
W3
A3
W3
Quad 1 of 4 output demux with common
select line.
DMUX44E: Quad 1 of 4 output demux with common
select line enable.
Availability:
Both DMUX44 and DMUX44E can be used with 1000,
2000, 3000, 5000, and 8000 devices.
Type: Soft
Macro Port Definition:
DMUX44 ([W0..W3],[X0..X3],[Y0..Y3],
[Z0..Z3],[A0..A3],S0,S1);
DMUX44_1 (W0,X0,Y0,Z0,A0,S0,S1);
DMUX44_2 (W1,X1,Y1,Z1,A1,S0,S1);
DMUX44_3 (W2,X2,Y2,Z2,A2,S0,S1);
DMUX44_4 (W3,X3,Y3,Z3,A3,S0,S1);
DMUX44E ([W0..W3],[X0..X3],[Y0..Y3],
[Z0..Z3],[A0..A3],EN,S0,S1);
DMUX44E_1 (W0,X0,Y0,Z0,A0,EN,S0,S1);
DMUX44E_2 (W1,X1,Y1,Z1,A1,EN,S0,S1);
DMUX44E_3 (W2,X2,Y2,Z2,A2,EN,S0,S1);
DMUX44E_4 (W3,X3,Y3,Z3,A3,EN,S0,S1);
DMUX44E
X0
X0
X1
X1
X2
X2
X3
X3
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Z0
Z0
Z1
EN
Z1
S0
Z2
S0
Z2
S1
Z3
S1
Z3
Truth Table:
Gray areas (EN) apply only to DMUX44E.
Input
Output
EN S1 S0 W0 W1 W2 W3 X0 X1 X2 X3 Y0 Y1 Y2 Y3 Z0 Z1 Z2 Z3
1
1
1
1
0
0
0
1
1
x
0
1
0
1
x
A0 A1 A2 A3 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 A0 A1 A2 A3 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 A0 A1 A2 A3 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 A0 A1 A2 A3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A0..An-1 = inputs, x = don’t care.
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Demultiplexers
DMUX82 and DMUX82E
Function:
DMUX82:
Octal 1 of 2 output demux with common
select line.
DMUX82E: Octal 1 of 2 output demux with common
select line and enable.
Availability:
DMUX82
DMUX82E
A0
A1
A2
A3
A4
A5
A6
A7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
A1
A2
A3
A4
A5
A6
A7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
S0
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
EN
S0
Z0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Both DMUX82 and DMUX82E can be used with 1000,
2000, 3000, 5000, and 8000 devices.
Type: Soft
Macro Port Definition:
DMUX82 ([Y0..Y7],[Z0..Z7],[A0..A7],S0);
DMUX82_1 (Y0,Y1,Z0,Z1,A0,A1,S0);
DMUX82_2 (Y2,Y3,Z2,Z3,A2,A3,S0);
DMUX82_3 (Y4,Y5,Z4,Z5,A4,A5,S0);
DMUX82_4 (Y6,Y7,Z6,Z7,A6,A7,S0);
DMUX82E ([Y0..Y7],[Z0..Z7],[A0..A7],EN,S0);
DMUX82E_1 (Y0,Y1,Z0,Z1,A0,A1,EN,S0);
DMUX82E_2 (Y2,Y3,Z2,Z3,A2,A3,EN,S0);
DMUX82E_3 (Y4,Y5,Z4,Z5,A4,A5,EN,S0);
DMUX82E_4 (Y6,Y7,Z6,Z7,A6,A7,EN,S0);
Truth Table:
Gray areas (EN) apply only to DMUX82E.
Input
Output
EN S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7
1
1
0
0
1
x
A0 A1 A2 A3 A4 A5 A6 A7 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 A0 A1 A2 A3 A4 A5 A6 A7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A0..An-1 = inputs, x = don’t care.
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Registers
This chapter contains information on the following macros:
■
■
■
■
■
■
D Flip-Flops
JK Flip-Flops
Toggle Flip-Flops
D Latches
SR Latches
Shift Registers
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346
D Flip-flops
D Flip-flops
FD11
FD11, FD14, and FD18
D
Function:
FD11:
FD14:
FD18:
Q
1-bit D flip-flop.
4-bit D flip-flop.
8-bit D flip-flop.
Availability:
FD11, FD14, and FD18 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
FD14
Type:
Logic Primitive: FD11
Soft:
FD14 and FD18
D0
Q0
D1
Q1
Logic Resources:
D2
Q2
D3
Q3
*
Macro
PT
GLB
Output
Level
FD11
1*
.25
1
1
Add 1 PT per GLB if Product Term Clock is used.
FD18
Macro Port Definition:
FD11 (Q0,D0,CLK);
FD14 ([Q0..Q3],[D0..D3],CLK);
FD18 ([Q0..Q7],[D0..D7],CLK);
D0
Q0
D1
Q1
Output
D2
Q2
Truth Table:
Input
D0~Dn-1
CLK
Q0~Qn-1
D3
Q3
d
x
x
↑
0
1
d
Q0’~Qn’
Q0’~Qn’
D4
Q4
D5
Q5
D6
Q6
D7
Q7
d = any pattern of 1s and 0s in an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
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D Flip-flops
FD21, FD24, and FD28
FD21
Function:
FD21:
FD24:
FD28:
D
1-bit D flip-flop with asynchronous clear.
4-bit D flip-flop with asynchronous clear.
8-bit D flip-flop with asynchronous clear.
Q
CD
Availability:
FD21, FD24, and FD28 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type:
Logic Primitive: FD21
Soft:
FD24 and FD28
Logic Resources:
*
Macro
PT
GLB
Output
Level
FD21
1*
.25
1
1
Add 1 PT per GLB for CD and 1 per GLB if Product
Term Clock is used.
Macro Port Definition:
FD21 (Q0,D0,CLK,CD);
FD24 ([Q0..Q3],[D0..D3],CLK,CD);
FD28 ([Q0..Q7],[D0..D7],CLK,CD);
Truth Table:
Input
Output
CD
D0~Dn-1
CLK
Q0~Qn-1
1
0
0
0
x
d
x
x
x
0
d
Q0’~Qn’
Q0’~Qn’
↑
0
1
FD24
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CD
FD28
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
CD
d = any pattern of 1s and 0s in an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
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348
D Flip-flops
FD31, FD34, and FD38
FD31
Function:
FD31:
FD34:
FD38:
1-bit D flip-flop with synchronous preset.
4-bit D flip-flop with synchronous preset.
8-bit D flip-flop with synchronous preset.
D
PS
Q
Availability:
FD31, FD34, and FD38 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
FD34
Macro Port Definition:
FD31 (Q0,D0,CLK,PS);
FD34 ([Q0..Q3],[D0..D3],CLK,PS);
FD38 ([Q0..Q7],[D0..D7],CLK,PS);
Truth Table:
Input
Output
PS
D0~Dn-1
CLK
Q0~Qn-1
1
0
x
x
x
d
x
x
↑
↑
0
1
1
d
Q0’~Qn’
Q0’~Qn’
PS
D0
Q0
D1
Q1
D2
Q2
D3
Q3
FD38
d = any pattern of 1s and 0s in an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
PS
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
349
D Flip-flops
FD41, FD44, and FD48
FD41
Function:
FD41:
FD44:
FD48:
1-bit D flip-flop with asynchronous clear
dominant over synchronous preset.
4-bit D flip-flop with asynchronous clear
dominant over synchronous preset.
8-bit D flip-flop with asynchronous clear
dominant over synchronous preset.
D
PS
Q
CD
Availability:
FD41, FD44, and FD48 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
FD44
Type: Soft
PS
Macro Port Definition:
FD41 (Q0,D0,CLK,PS,CD);
FD44 ([Q0..Q3],[D0..D3],CLK,PS,CD);
FD48 ([Q0..Q7],[D0..D7],CLK,PS,CD);
D0
Q0
D1
Q1
D2
Q2
Truth Table:
D3
Q3
Input
CD
Output
CD
PS
D0~Dn-1
CLK
Q0~Qn-1
1
0
0
0
0
x
1
0
x
x
x
x
d
x
x
x
0
1
d
Q0’~Qn’
Q0’~Qn’
↑
↑
0
1
d = any pattern of 1s and 0s in an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
FD48
PS
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
CD
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D Flip-flops
FD51, FD54, and FD58
FD51
Function:
FD51:
FD54:
FD58:
1-bit D flip-flop with synchronous preset
dominant over synchronous clear.
4-bit D flip-flop with synchronous preset
dominant over synchronous clear.
8-bit D flip-flop with synchronous preset
dominant over synchronous clear.
Availability:
D
PS
Q
CS
FD54
FD51, FD54, and FD58 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
Macro Port Definition:
FD51 (Q0,D0,CLK,PS,CS);
FD54 ([Q0..Q3],[D0..D3],CLK,PS,CS);
FD58 ([Q0..Q7],[D0..D7],CLK,PS,CS);
PS
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CS
Truth Table:
FD58
Input
Output
PS
CS
D0~Dn-1
CLK
Q0~Qn-1
1
0
0
x
x
x
1
0
x
x
x
x
d
x
x
↑
↑
↑
0
1
1
0
d
Q0’~Qn’
Q0’~Qn’
d = any pattern of 1s and 0s in an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
PS
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
CS
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D Flip-flops
FD61, FD64, and FD68
FD61
Function:
FD61:
FD64:
FD68:
1-bit D flip-flop with scan.
4-bit D flip-flop with scan.
8-bit D flip-flop with scan.
D
TI
Q
TE
Availability:
FD61, FD64, and FD68 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
FD64
Macro Port Definition:
FD61 (Q0,D0,TI0,CLK,TE);
FD64 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,TE);
FD68 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,TE);
Truth Table:
Input
Output
TE
TI0~TIn-1
D0~Dn-1
CLK
Q0~Qn-1
0
1
x
x
x
d
x
x
d
x
x
x
↑
↑
0
1
d
d
Q0’~Qn’
Q0’~Qn’
d = any pattern of 1s and 0s in an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
TE
D0
TI0
D1
TI1
D2
TI2
D3
TI3
Q0
Q1
Q2
Q3
FD68
TE
D0
TI0
D1
TI1
D2
TI2
D3
TI3
D4
TI4
D5
TI5
D6
TI6
D7
TI7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
352
D Flip-flops
FD71, FD74, and FD78
FD71
Function:
FD71:
FD74:
FD78:
1-bit D flip-flop with scan and asynchronous clear.
4-bit D flip-flop with scan and asynchronous clear.
8-bit D flip-flop with scan and asynchronous clear.
Availability:
D
TI
Q
TE
CD
FD71, FD74, and FD78 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
FD74
Macro Port Definition:
FD71 (Q0,D0,TI0,CLK,CD,TE);
FD74 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,CD,TE);
FD78 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,CD,TE);
Truth Table:
Input
Output
CD
TE
TI0~TIn-1
D0~Dn-1
CLK
Q0~Qn-1
1
0
0
0
0
x
0
1
x
x
x
x
d
x
x
x
d
x
x
x
x
0
d
d
Q0’~Qn’
Q0’~Qn’
↑
↑
0
1
d = any pattern of 1s and 0s in an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
TE
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
CD
FD78
TE
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
D4 Q4
TI4
D5 Q5
TI5
D6 Q6
TI6
D7 Q7
TI7
CD
353
D Flip-flops
FD81, FD84, and FD88
FD81
Function:
FD81:
FD84:
FD88:
1-bit D flip-flop with scan and synchronous preset.
4-bit D flip-flop with scan and synchronous preset.
8-bit D flip-flop with scan and synchronous preset.
Availability:
PS
Q
D
TI
TE
FD81, FD84, and FD88 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
FD84
Macro Port Definition:
FD81 (Q0,D0,TI0,CLK,PS,TE);
FD84 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,PS,TE);
FD88 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,PS,TE);
Truth Table:
Input
Output
PS
TE
TI0~TIn-1
D0~Dn-1
CLK
Q0~Qn-1
1
0
0
x
x
x
0
1
x
x
x
x
d
x
x
x
d
x
x
x
↑
↑
↑
0
1
1
d
d
Q0’~Qn’
Q0’~Qn’
PS
TE
D0
TI0
D1
TI1
D2
TI2
D3
TI3
Q1
Q2
Q3
FD88
d = any pattern of 1s and 0s in an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
PS
TE
D0
TI0
D1
TI1
D2
TI2
D3
TI3
D4
TI4
D5
TI5
D6
TI6
D7
TI7
ispLSI Macro Library Reference Manual
Q0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
354
D Flip-flops
FD91, FD94, and FD98
FD91
Function:
FD91:
FD94:
FD98:
1-bit D flip-flop with scan and asynchronous clear
dominant over synchronous preset.
4-bit D flip-flop with scan and asynchronous clear
dominant over synchronous preset.
8-bit D flip-flop with scan and asynchronous clear
dominant over synchronous preset.
PS
D
TI
Q
TE
CD
Availability:
FD91, FD94, and FD98 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
FD94
Type: Soft
PS
Macro Port Definition:
FD91 (Q0,D0,TI0,CLK,PS,CD,TE);
FD94 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,PS,CD,TE);
FD98 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,PS,CD,TE);
Truth Table:
Input
Output
CD
PS
TE
TI0~TIn-1
D0~Dn-1
1
0
0
0
0
0
x
1
0
0
x
x
x
x
0
1
x
x
x
x
x
d
x
x
x
x
d
x
x
x
TE
D0 Q0
TI0
D1
Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
CD
CLK Q0~Qn-1
x
↑
↑
↑
0
1
0
1
d
d
Q0’~Qn’
Q0’~Qn’
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
FD98
PS
TE
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
D4 Q4
TI4
D5 Q5
TI5
D6 Q6
TI6
D7 Q7
TI7
CD
355
D Flip-flops
FDA1, FDA4, and FDA8
FDA1
Function:
FDA1:
FDA4:
FDA8:
1-bit D flip-flop with scan and synchronous preset
dominant over synchronous clear.
4-bit D flip-flop with scan and synchronous preset
dominant over synchronous clear.
8-bit D flip-flop with scan and synchronous preset
dominant over synchronous clear.
PS
D
TI
Q
TE
CS
Availability:
FDA1, FDA4, and FDA8 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
FDA4
Type: Soft
PS
Macro Port Definition:
FDA1 (Q0,D0,TI0,CLK,PS,CS,TE);
FDA4 ([Q0..Q3],[D0..D3],[TI0..TI3],CLK,PS,CS,TE);
FDA8 ([Q0..Q7],[D0..D7],[TI0..TI7],CLK,PS,CS,TE);
Truth Table:
Input
Output
PS
CS
TE
TI0~TIn-1
D0~Dn-1
CLK
Q0~Qn-1
1
0
0
0
x
x
x
1
0
0
x
x
x
x
0
1
x
x
x
x
x
d
x
x
x
x
d
x
x
x
↑
↑
↑
↑
0
1
1
0
d
d
Q0’~Qn’
Q0’~Qn’
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch,
x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
TE
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
CS
FDA8
PS
TE
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
D4 Q4
TI4
D5 Q5
TI5
D6 Q6
TI6
D7 Q7
TI7
CS
356
JK Flip-flops
JK Flip-flops
FJK11 and FJK21
FJK11
Function:
FJK11:
FJK21:
JK flip-flop.
JK flip-flop with asynchronous clear.
J
Q
K
Availability:
Both FJK11 and FJK21 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
FJK21
Type: Soft
Macro Port Definition:
Q
J
FJK11 (Q0,J0,K0,CLK);
FJK21 (Q0,J0,K0,CLK,CD);
K
Truth Table:
CD
Gray areas (CD) apply only to FJK21.
Input
Output
CD
J0
K0
CLK
CD
1
0
0
0
0
0
0
x
0
0
1
1
x
x
x
0
1
0
1
x
x
x
0
Q0’
0
1
↑
↑
↑
↑
0
1
Q0’
Q0’
Q0’
Q0’ = previous output of flip-flop or latch,
Q0’ = inverse of Q0’, x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
357
JK Flip-flops
FJK31 and FJK41
FJK31
Function:
FJK31:
FJK41:
JK flip-flop with scan.
JK flip-flop with scan and asynchronous clear.
Q
J
TI
Availability:
Both FJK31 and FJK41 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
TE
K
Type: Soft
Macro Port Definition:
FJK31 (Q0,J0,K0,TI0,CLK,TE);
FJK41 (Q0,J0,K0,TI0,CLK,CD,TE);
FJK41
Truth Table:
Gray areas (CD) apply only to FJK41.
J
Input
Output
CD
TE
TI0
J0
K0
CLK
Q0
1
0
0
0
0
0
0
0
x
0
0
0
0
1
x
x
x
x
x
x
x
d
x
x
x
0
0
1
1
x
x
x
x
0
1
0
1
x
x
x
x
0
Q0’
0
1
↑
↑
↑
↑
↑
0
1
Q
TI
TE
K
CD
Q0’
d
Q0’
Q0’
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’ = previous output of flip-flop or latch, Q0’ = inverse of Q0’,
x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
358
JK Flip-flops
FJK51
FJK51
Function:
JK flip-flop with asynchronous clear and synchronous
preset.
PS
J
Availability:
Q
FJK51 can be used with 1000, 2000, 3000, 5000, and
8000 devices.
K
Type: Soft
CD
Macro Port Definition:
FJK51 (Q0,J0,K0,CLK,PS,CD);
Truth Table:
Input
Output
CD
PS
J0
K0
CLK
Q0
1
0
0
0
0
0
0
0
x
1
0
0
0
0
x
x
x
x
0
0
1
1
x
x
x
x
0
1
0
1
x
x
x
0
1
Q0’
0
1
↑
↑
↑
↑
↑
0
1
Q0’
Q0’
Q0’
Q0’ = previous output of flip-flop or latch,
Q0’ = inverse of Q0’, x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
359
Toggle Flip-flops
Toggle Flip-flops
FT11
FT11 and FT21
D
Q
Function:
FT11:
FT21:
Toggle flip-flop with asynchronous clear.
Toggle flip-flop with synchronous clear and
preset, preset dominant.
CD
Availability:
FT21
Both FT11 and FT21 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
Type: Soft
PS
D
Q
Macro Port Definition:
FT11 (Q0,D0,CLK,CD);
FT21 (Q0,D0,CLK,PS,CS);
CS
Truth Table:
FT11
Input
CD
1
0
0
0
0
Output
D0 CLK
x
0
1
x
x
FT21
x
↑
↑
0
1
Input
Q
PS
CS
0
Q0’
1
0
0
0
x
x
x
1
0
0
x
x
Q0’
Q0’
Q0’
Output
D0 CLK
x
x
0
1
x
x
↑
↑
↑
↑
0
1
Q
1
0
Q0’
Q0’
Q0’
Q0’
Q0’ = previous output of flip-flop or latch,
Q0’ = inverse of Q0’, x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
360
D Latches
D Latches
LD11
LD11, LD14, and LD18
Function:
D
LD11:
LD14:
LD18:
G
1-bit D latch.
4-bit D latch.
8-bit D latch.
Q
Availability:
LD11, LD14, and LD18 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
LD14
G
Type: Hard
Logic Resources:
Macro
PT
GLB
Output
Level
LD11
LD14
LD18
3
3/out
3/out
1
1
2
1
4
8
1
1
1
Macro Port Definition:
D0
Q0
D1
Q1
D2
Q2
D3
Q3
LD18
LD11 (Q0,D0,G);
LD14 ([Q0..Q3],[D0..D3],G);
LD18 ([Q0..Q7],[D0..D7],G);
D0
Q0
D1
Q1
Output
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
Truth Table:
Input
G
D0~Dn-1
G
Q0~Qn-1
d
x
1
0
d
Q0’~Qn’
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
361
D Latches
LD21, LD24, and LD28
Function:
LD21:
LD24:
LD28:
LD11
1-bit D latch with asynchronous clear.
4-bit D latch with asynchronous clear.
8-bit D latch with asynchronous clear.
D
Q
G
Availability:
LD21, LD24, and LD28 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Hard
LD14
Logic Resources:
G
Macro
PT
GLB
Output
Level
LD21
LD24
LD28
3
3/out
3/out
1
1
2
1
4
8
1
1
1
D0
Q0
D1
Q1
D2
Q2
D3
Q3
Macro Port Definition:
LD21 (Q0,D0,G,CD);
LD24 ([Q0..Q3],[D0..D3],G,CD);
LD28 ([Q0..Q7],[D0..D7],G,CD);
LD18
Truth Table:
G
Input
Output
CD
D0~Dn-1
G
Q0~Qn-1
1
0
0
x
d
x
x
1
0
0
d
Q0’~Qn’
d = any pattern of 1s and 0s on input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
362
D Latches
LD31, LD34, and LD38
LD31
Function:
LD31:
LD34:
LD38:
1-bit D latch with asynchronous preset.
4-bit D latch with asynchronous preset.
8-bit D latch with asynchronous preset.
D
PD
Q
G
Availability:
LD31, LD34, and LD38 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
LD34
Type: Hard
G
Logic Resources:
Macro
PT
GLB
Output
Level
LD31
LD34
LD38
4
4/out
4/out
1
2
2
1
4
8
1
1
1
Macro Port Definition:
PD
D0
Q0
D1
Q1
D2
Q2
D3
Q3
LD38
LD31 (Q0,D0,G,PD);
LD34 ([Q0..Q3],[D0..D3],G,PD);
LD38 ([Q0..Q7],[D0..D7],G,PD);
G
Truth Table:
Input
Output
PD
D0~Dn-1
G
Q0~Qn-1
1
0
0
x
d
x
x
1
0
1
d
Q0’~Qn’
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
PD
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
363
D Latches
LD41, LD44, and LD48
LD41
Function:
LD41:
LD44:
LD48:
1-bit D latch with asynchronous clear dominant
over asynchronous preset.
4-bit D latch with asynchronous clear dominant
over asynchronous preset.
8-bit D latch with asynchronous clear dominant
over asynchronous preset.
Availability:
D
PD
Q
G
CD
LD44
LD41, LD44, and LD48 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
G
Type: Hard
Logic Resources:
Macro
PT
GLB
Output
Level
LD41
LD44
LD48
4
4/out
4/out
1
2
2
1
4
8
1
1
1
PD
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CD
LD48
Macro Port Definition:
LD41 (Q0,D0,G,PD,CD);
LD44 ([Q0..Q3],[D0..D3],G,PD,CD);
LD48 ([Q0..Q7],[D0..D7],G,PD,CD);
G
Truth Table:
Input
Output
CD
PD
D0~Dn-1
G
Q0~Qn-1
1
0
0
0
x
1
0
0
x
x
d
x
x
x
1
0
0
1
d
Q0’~Qn’
PD
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
CD
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
364
D Latches
LD51, LD54, and LD58
LD51
Function:
LD51:
LD54:
LD58:
1-bit D latch with asynchronous preset
dominant over asynchronous clear.
4-bit D latch with asynchronous preset
dominant over asynchronous clear.
8-bit D latch with asynchronous preset
dominant over asynchronous clear.
D
PD
Q
G
CD
Availability:
LD51, LD54, and LD58 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Hard
LD54
G
Logic Resources:
Macro
PT
GLB
Output
Level
LD51
LD54
LD58
4
4/out
4/out
1
2
2
1
4
8
1
1
1
Macro Port Definition:
PD
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CD
LD58
LD51 (Q0,D0,G,PD,CD);
LD54 ([Q0..Q3],[D0..D3],G,PD,CD);
LD58 ([Q0..Q7],[D0..D7],G,PD,CD);
G
Truth Table:
Input
Output
PD
CD
D0~Dn-1
G
Q0~Qn-1
1
0
0
0
x
1
0
0
x
x
d
x
x
x
1
0
1
0
d
Q0’~Qn’
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
PD
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
CD
365
D Latches
LD61, LD64, and LD68
FD61
Function:
LD61:
LD64:
LD68:
1-bit D latch with scan.
4-bit D latch with scan.
8-bit D latch with scan.
D
TI
G
TG
Q
Availability:
LD61, LD64, and LD68 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
FD64
Type: Soft
Macro Port Definition:
LD61 (Q0,D0,TI0,G,TG);
LD64 ([Q0..Q3],[D0..D3],[TI0..TI3],G,TG);
LD68 ([Q0..Q7],[D0..D7],[TI0..TI7],G,TG);
Truth Table:
Input
*
Output
D0~Dn-1
G
TI0~TIn-1
TG
Q0~Qn-1
x
x
d
1
x
0
0
0
1
1
1
1
x
d
x
x
1
0
0
1
0
1
1
1
Q0’~Qn’
d
d
1*
1*
0*
In proper operation, G and TG should NOT both be 1 at the same time.
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
G
TG
D0
TI0
D1
TI1
D2
TI2
D3
TI3
Q0
Q1
Q2
Q3
FD68
G
TG
D0
TI0
D1
TI1
D2
TI2
D3
TI3
D4
TI4
D5
TI5
D6
TI6
D7
TI7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
366
D Latches
LD71, LD74, and LD78
LD71
Function:
LD71:
LD74:
LD78:
1-bit D latch with scan and asynchronous clear.
4-bit D latch with scan and asynchronous clear.
8-bit D latch with scan and asynchronous clear.
D
TI
G
TG
Q
CD
Availability:
LD71, LD74, and LD78 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
LD74
Type: Soft
Macro Port Definition:
LD71 (Q0,D0,TI0,G,CD,TG);
LD74 ([Q0..Q3],[D0..D3],[TI0..TI3],G,CD,TG);
LD78 ([Q0..Q7],[D0..D7],[TI0..TI7],G,CD,TG);
Truth Table:
Input
*
Output
CD
D0~Dn-1
G
TI0~TIn-1
TG
Q0~Qn-1
1
0
0
0
0
0
0
x
x
x
d
1
x
0
x
0
0
1
1
1
1
x
x
d
x
x
1
0
x
0
1
0
1
1
1
0
Q0’~Qn’
d
d
1*
1*
0*
In proper operation, G and TG should NOT both be 1 at the same time.
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
G
TG
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
CD
LD78
G
TG
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
D4 Q4
TI4
D5 Q5
TI5
D6 Q6
TI6
D7 Q7
TI7
CD
367
D Latches
LD81, LD84, and LD88
LD81
Function:
LD81:
LD84:
LD88:
1-bit D latch with scan and asynchronous preset.
4-bit D latch with scan and asynchronous preset.
8-bit D latch with scan and asynchronous preset.
Availability:
PD
D
TI
G
TG
Q
LD81, LD84, and LD88 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
Type: Soft
LD84
Macro Port Definition:
LD81 (Q0,D0,TI0,G,PD,TG);
LD84 ([Q0..Q3],[D0..D3],[TI0..TI3],G,PD,TG);
LD88 ([Q0..Q7],[D0..D7],[TI0..TI7],G,PD,TG);
Truth Table:
Input
*
Output
PD
D0~Dn-1
G
TI0~TIn-1
TG
Q0~Qn-1
1
0
0
0
0
0
0
x
x
x
d
1
x
0
x
0
0
1
1
1
1
x
x
d
x
x
1
0
x
0
1
0
1
1
1
1
Q0’~Qn’
d
d
1*
1*
0*
In proper operation, G and TG should NOT both be 1 at the same time.
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
PD
G
TG
D0
TI0
D1
TI1
D2
TI2
D3
TI3
Q0
Q1
Q2
Q3
LD88
PD
G
TG
D0
TI0
D1
TI1
D2
TI2
D3
TI3
D4
TI4
D5
TI5
D6
TI6
D7
TI7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
368
D Latches
LD91, LD94, and LD98
LD91
Function:
LD91:
LD94:
LD98:
1-bit D latch with scan and asynchronous clear
dominant over asynchronous preset.
4-bit D latch with scan and asynchronous clear
dominant over asynchronous preset.
8-bit D latch with scan and asynchronous clear
dominant over asynchronous preset.
PD
D
TI
G
TG
Q
CD
Availability:
LD91, LD94, and LD98 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
LD94
Type: Soft
PD
Macro Port Definition:
LD91 (Q0,D0,TI0,G,PD,CD,TG);
LD94 ([Q0..Q3],[D0..D3],[TI0..TI3],G,PD,CD,TG);
LD98 ([Q0..Q7],[D0..D7],[TI0..TI7],G,PD,CD,T
Truth Table:
Input
*
Output
CD
PD
D0~Dn-1
G
TI0~TIn-1
TG
Q0~Qn-1
1
0
0
0
0
0
0
0
x
1
0
0
0
0
0
0
x
x
x
x
d
1
x
0
x
x
0
0
1
1
1
1
x
x
x
d
x
x
1
0
x
x
0
1
0
1
1
1
0
1
Q0’~Qn’
d
d
1*
1*
0*
In proper operation, G and TG should NOT both be 1 at the same time.
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
G
TG
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
CD
LD98
PD
G
TG
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
D4 Q4
TI4
D5 Q5
TI5
D6 Q6
TI6
D7 Q7
TI7
CD
369
D Latches
LDA1, LDA4, and LDA8
LDA1
Function:
LDA1:
LDA4:
LDA8:
1-bit D latch with scan and asynchronous preset
dominant over asynchronous clear.
4-bit D latch with scan and asynchronous preset
dominant over asynchronous clear.
8-bit D latch with scan and asynchronous preset
dominant over asynchronous clear.
PD
D
TI
G
TG
Q
CD
Availability:
LDA1, LDA4, and LDA8 can be used with 1000, 2000,
3000, 5000, and 8000 devices.
LDA4
Type: Soft
Macro Port Definition:
LDA1 (Q0,D0,TI0,G,PD,CD,TG);
LDA4 ([Q0..Q3],[D0..D3],[TI0..TI3],G,PD,CD,TG);
LDA8 ([Q0..Q7],[D0..D7],[TI0..TI7],G,PD,CD,TG);
Truth Table:
Input
*
Output
PD
CD
D0~Dn-1
G
TI0~TIn-1
TG
Q0~Qn-1
1
0
0
0
0
0
0
0
x
1
0
0
0
0
0
0
x
x
x
x
d
1
x
0
x
x
0
0
1
1
1
1
x
x
x
d
x
x
1
0
x
x
0
1
0
1
1
1
1
0
Q0’~Qn’
d
d
1*
1*
0*
In proper operation, G and TG should NOT both be 1 at the same time.
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’~Qn’ = previous output of flip-flop or latch, x = don’t care.
ispLSI Macro Library Reference Manual
PD
G
TG
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
CD
LDA8
PD
G
TG
D0 Q0
TI0
D1 Q1
TI1
D2 Q2
TI2
D3 Q3
TI3
D4 Q4
TI4
D5 Q5
TI5
D6 Q6
TI6
D7 Q7
TI7
CD
370
SR Latches
SR Latches
LSR1 and LSR2
LSR1
Function:
LSR1:
LSR2:
Simple SR latch.
SR latch with OR on S and R inputs.
S
Availability:
Q
R
Both LSR1 and LSR2 can be used with 1000, 2000, 3000,
5000, and 8000 devices.
Type: Soft
Macro Port Definition:
LSR2
LSR1 (Q0,S0,R0);
LSR2 (Q0,S0,S1,R0,R1);
Truth Tables:
LSR1
S0
Q
LSR2
S1
Input
S0 R0
1
1
0
1
1
0
0
0
*
**
Output
Q0
Q0
1
0
1*
Input
S** R**
1
1
0
1
1
0
0
0
Output
Q0
Q0
1
0
1*
R0
R1
These outputs are not entirely stable. They may not remain when both
S and R return to 1.
S = 1 when S0 or S1 = 1. S = 0 when S0 and S1 = 0.
R = 1 when R0 or R1 = 1. R=0 when R0 and R1 = 0.
Q0 = output of flip-flop or latch.
ispLSI Macro Library Reference Manual
371
Shift Registers
Shift Registers
SRR11, SRR14, and SRR18
SRR11
Function:
CAI Q0
SRR11: 1-bit right shift register with asynchronous reset.
SRR14: 4-bit right shift register with asynchronous reset.
SRR18: 8-bit right shift register with asynchronous reset.
CD
Availability:
SRR11, SRR14, and SRR18 can be used with 1000,
2000, 3000, 5000, and 8000 devices.
SRR14
Schematics appear on the following pages.
CAI Q0
Q1
Type: Soft
Q2
Macro Port Definition:
Q3
CD
SRR11 (Q0,CAI,CLK,CD);
SRR14 ([Q0..Q3],CAI,CLK,CD);
SRR18 ([Q0..Q7],CAI,CLK,CD);
SRR18_1 ([Q0..Q3],CAI,CLK,CD);
SRR18_2 ([Q4..Q7],Q3,CLK,CD);
SRR18
CAI Q0
Truth Table:
Q1
The SRR11 has only Q0 as an output. The SRR14 has Q0 to Q3.
The SRR18 has Q0 to Q7.
Input
CD
1
0
0
0
Q3
Output
CAI CLK Q0
x
d
x
x
Q2
x
↑
0
1
0
d
Q0’
Q0’
Q4
Q1
Q2
Q3
Q4
Q5
Q6
Q7
0
Q0’
Q1’
Q1’
0
Q1’
Q2’
Q2’
0
Q2’
Q3’
Q3’
0
Q3’
Q4’
Q4’
0
Q4’
Q5’
Q5’
0
Q5’
Q6’
Q6’
0
Q6’
Q7’
Q7’
Q5
Q6
Q7
CD
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’ = previous output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
372
Shift Registers
SRR11
CAI
D
Q
Q0
CLK
CD
FD21
CD
ispLSI Macro Library Reference Manual
373
Shift Registers
SRR14
CAI
CAI Q0
Q0
CLK
CD
SRR11
CD
CAI Q0
Q1
CD
SRR11
CAI Q0
Q2
CD
SRR11
CAI Q0
Q3
CD
SRR11
ispLSI Macro Library Reference Manual
374
Shift Registers
SRR11
CAI
CAI
Q0
Q0
CLK
CD
SRR11
CD
CAI
Q0
Q1
CD
SRR11
CAI
Q0
Q2
CD
SRR11
CAI
Q0
Q3
CD
SRR11
CAI
Q0
Q4
CD
SRR11
CAI
Q0
Q5
CD
SRR11
CAI
Q0
Q6
CD
SRR11
CAI
Q0
Q7
CD
SRR11
ispLSI Macro Library Reference Manual
375
Shift Registers
SRR21, SRR24, and SRR28
SRR21
Function:
CAI Q0
SRR21: 1-bit right shift register with asynchronous reset
and enable.
SRR24: 4-bit right shift register with asynchronous reset
and enable.
SRR28: 8-bit right shift register with asynchronous reset
and enable.
EN
CD
Availability:
SRR24
SRR21, SRR24, and SRR28 can be used with 1000,
2000, 3000, 5000, and 8000 devices.
CAI Q0
Q1
Schematics appear on the following pages.
EN
Q2
Q3
CD
Type: Soft
Macro Port Definition:
SRR21 (Q0,CAI,CLK,EN,CD);
SRR24 ([Q0..Q3],CAI,CLK,EN,CD);
SRR28 ([Q0..Q7],CAI,CLK,EN,CD);
SRR28_1 ([Q0..Q3],CAI,CLK,EN,CD);
SRR28_2 ([Q4..Q7],Q3,CLK,EN,CD);
SRR28
CAI Q0
Q1
Truth Table:
Q2
The SRR21 has only Q0 as an output. The SRR24 has Q0 to Q3.
The SRR28 has Q0 to Q7.
Q3
Input
CD
EN
1
0
0
0
0
x
1
0
x
x
Q5
Output
CAI CLK Q0
x
d
x
x
x
Q4
x
↑
↑
0
1
0
d
Q0’
Q0’
Q0’
Q1
Q2
Q3
Q4
Q5
Q6
Q7
0
Q0’
Q1’
Q1’
Q1’
0
Q1’
Q2’
Q2’
Q2’
0
Q2’
Q3’
Q3’
Q3’
0
Q3’
Q4’
Q4’
Q4’
0
Q4’
Q5’
Q5’
Q5’
0
Q5’
Q6’
Q6’
Q6’
0
Q6’
Q7’
Q7’
Q7’
EN
Q6
Q7
CD
d = any pattern of 1s and 0s on an input or set of inputs,
Q0’ = previous output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
376
Shift Registers
SRR21
CAI
EN
D
CLK
Q
Q0
CD
FD21
CD
ispLSI Macro Library Reference Manual
377
Shift Registers
SRR24
CAI
EN
CAI
Q0
Q0
EN
CLK
CD
SRR21
CD
CAI
Q0
Q1
EN
CD
SRR21
CAI
Q0
Q2
EN
CD
SRR21
CAI
Q0
Q3
EN
CD
SRR21
ispLSI Macro Library Reference Manual
378
Shift Registers
SRR28
CAI
EN
CAI
Q0
Q0
EN
CLK
CD
SRR21
CD
CAI
Q0
Q1
EN
CD
SRR21
CAI
Q0
Q2
EN
CD
SRR21
CAI
Q0
Q3
EN
CD
SRR21
CAI
Q0
Q4
EN
CD
SRR21
CAI
Q0
Q5
EN
CD
SRR21
CAI
Q0
Q6
EN
CD
SRR21
CAI
Q0
Q7
EN
CD
SRR21
ispLSI Macro Library Reference Manual
379
Shift Registers
SRR31, SRR34, and SRR38
SRR31
SRR34
SRR38
PS
PS
CAI
PS
CAI
D0
Q0
D0
Q0
D1
Q1
D1
Q1
D2
Q2
D2
Q2
D3
Q3
D3
Q3
D4
Q4
D5
Q5
LD
D6
Q6
EN
D7
Q7
Function:
1-, 4-, and 8-bit right shift registers with
asynchronous reset, enable, parallel data load,
and synchronous preset.
CAI
D0
Q0
Availability:
LD
SRR31, SRR34, and SRR38 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
EN
Schematics appear on the following pages.
CD
Type: Soft
Macro Port Definition:
CD
SRR31 (Q0,D0,CAI,CLK,PS,LD,EN,CD);
SRR34 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);
SRR38 ([Q0..Q7],[D0..D7],CAI,CLK,PS,LD,EN,CD);
SRR38_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CD);
SRR38_2 ([Q4..Q7],[D4..D7],Q3,CLK,PS,LD,EN,CD);
LD
EN
CD
Truth Table:
The SRR31 has only Q0 as an output. The SRR34 has Q0 to Q3. The SRR38 has Q0 to Q7.
Input
Output
CD
PS
LD
D0~D7
EN
CAI
CLK
Q0
Q1
Q2
Q3
Q4
Q5
1
0
0
0
0
0
0
x
1
0
0
0
x
x
x
x
1
0
0
x
x
x
x
d
x
x
x
x
x
x
x
1
0
x
x
x
x
x
d
x
x
x
x
0
1
D0
d
Q0’
Q0’
Q0’
0
1
D1
Q0’
Q1’
Q1’
Q1’
0
1
D2
Q1’
Q2’
Q2’
Q2’
0
1
D3
Q2’
Q3’
Q3’
Q3’
0
1
D4
Q3’
Q4’
Q4’
Q4’
0
1
D5
Q4’
Q5’
Q5’
Q5’
↑
↑
↑
↑
0
1
d = any pattern of 1s and 0s on an input or set of inputs,
D0..Dn-1 = load inputs for counters and shift registers,
Q0’ = previous output of flip-flop or latch, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
380
Shift Registers
SRR31
EN
CAI
D
Q
Q0
LD
D0
PS
CLK
CD
FD21
CD
ispLSI Macro Library Reference Manual
381
Shift Registers
SRR34.
PS
CAI
PS
CAI
D0
D0
LD
LD
EN
EN
Q0
Q0
CLK
CD
SRR31
CD
PS
CAI
D1
D0
Q0
Q1
LD
EN
CD
SRR31
PS
CAI
D2
D0
Q0
Q2
LD
EN
CD
SRR31
PS
CAI
D3
D0
Q0
Q3
LD
EN
CD
SRR31
ispLSI Macro Library Reference Manual
382
Shift Registers
SRR38
PS
CAI
PS
CAI
PS
CAI
Q0
D4
Q0
Q4
D0
D0
D0
LD
LD
LD
EN
EN
EN
Q0
CLK
CD
CD
SRR31
SRR31
CD
PS
CAI
PS
CAI
Q1
D1
D0
D5
Q0
Q5
D0
LD
LD
EN
EN
CD
SRR31
CD
SRR31
PS
CAI
PS
CAI
Q2
D2
D0
D6
Q0
Q6
D0
LD
LD
EN
EN
CD
SRR31
PS
CAI
Q3
D0
Q0
Q0
CD
SRR31
PS
CAI
D3
Q0
D7
Q7
D0
LD
LD
EN
EN
CD
SRR31
ispLSI Macro Library Reference Manual
Q0
CD
SRR31
383
Shift Registers
SRR41, SRR44, and SRR48
SRR41
SRR44
PS
CAI
PS
CAI
D0
D0
Q0
D1
Q1
D2
Q2
D3
Q3
SRR48
Function:
1-, 4-, and 8-bit right shift registers with
synchronous reset, enable, parallel data load,
and synchronous preset.
Q0
Availability:
SRR41, SRR44, and SRR48 can be used with
1000, 2000, 3000, 5000, and 8000 devices.
LD
PS
CAI
EN
Schematics appear on the following pages.
CS
LD
Type: Soft
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
EN
Macro Port Definition:
CS
SRR41 (Q0,D0,CAI,CLK,PS,LD,EN,CS);
SRR44 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);
SRR48 ([Q0..Q7],[D0..D7],CAI,CLK,PS,LD,EN,CS);
SRR48_1 ([Q0..Q3],[D0..D3],CAI,CLK,PS,LD,EN,CS);
SRR48_2 ([Q4..Q7],[D4..D7],Q3,CLK,PS,LD,EN,CS);
LD
EN
CS
Truth Table:
The SRR41 has only Q0 as an output. The SRR44 has Q0 to Q3. The SRR48 has Q0 to Q7.
Input
Output
PS
CS
LD
D0~D7
EN
1
0
0
0
0
x
x
x
1
0
0
0
x
x
x
x
1
0
0
x
x
x
x
d
x
x
x
x
x
x
x
1
0
x
x
CAI CLK
x
x
x
d
x
x
x
↑
↑
↑
↑
↑
0
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
1
0
D0
d
Q0’
Q0’
Q0’
1
0
D1
Q0’
Q1’
Q1’
Q1’
1
0
D2
Q1’
Q2’
Q2’
Q2’
1
0
D3
Q2’
Q3’
Q3’
Q3’
1
0
D4
Q3’
Q4’
Q4’
Q4’
1
0
D5
Q4’
Q5’
Q5’
Q5’
1
0
D6
Q5’
Q6’
Q6’
Q6’
d = any pattern of 1s and 0s on an input or set of inputs,
D0..Dn-1 = load inputs for shift registers,
Q0’ = previous output of flip-flop, x = don’t care,
↑ = rising clock edge.
ispLSI Macro Library Reference Manual
384
Shift Registers
SRR41
EN
CAI
D
Q
Q0
LD
CS
D0
PS
CLK
FD11
ispLSI Macro Library Reference Manual
385
Shift Registers
SRR44
PS
CAI
PS
CAI
D0
D0
LD
LD
EN
EN
Q0
Q0
CLK
CS
SRR41
CS
PS
CAI
D1
D0
Q0
Q1
LD
EN
CS
SRR41
PS
CAI
D2
D0
Q0
Q2
LD
EN
CS
SRR41
PS
CAI
D3
D0
Q0
Q3
LD
EN
CS
SRR41
ispLSI Macro Library Reference Manual
386
Shift Registers
SRR48
PS
CAI
PS
CAI
PS
CAI
Q0
D4
Q0
Q4
D0
D0
D0
LD
LD
LD
EN
EN
EN
Q0
CLK
CS
CS
SRR41
SRR41
CS
PS
CAI
PS
CAI
Q1
D1
D0
D5
Q0
Q5
D0
LD
LD
EN
EN
CS
SRR41
CS
SRR41
PS
CAI
PS
CAI
Q2
D2
D0
D6
Q0
Q6
D0
LD
LD
EN
EN
CS
SRR41
PS
CAI
Q3
D0
Q0
Q0
CS
SRR41
PS
CAI
D3
Q0
D7
Q7
D0
LD
LD
EN
EN
CS
SRR41
ispLSI Macro Library Reference Manual
Q0
CS
SRR41
387
Shift Registers
SRRL1, SRRL4, and SRRL8
SRRL1
Function:
1-, 4-, and 8-bit right/left shift registers with asynchronous
reset, enable, parallel data load, synchronous preset, and
synchronous reset.
PS
CAIR
Availability:
CAIL
SRRL1, SRRL4, and SRRL8 can be used with 1000,
2000, 3000, 5000, and 8000 devices.
R/L
An additional symbol and schematics appear on the
following pages.
D0
Q0
PS
CAIR
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CAIL
LD
R/L
EN
LD
EN
CD CS
Type: Soft
SRRL4
CD CS
Macro Port Definition:
SRRL1 (Q0,D0,CAIR,CAIL,CLK,PS,LD,EN,RL,CD,CS);
SRRL4 ([Q0..Q3],[D0..D3],CAIR,CAIL,CLK,PS,LD,EN,RL,CD,CS);
SRRL4_1 (Q0,Q1,D0,D1,CAIR,Q2,CLK,PS,LD,EN,RL,CD,CS);
SRRL4_2 (Q2,Q3,D2,D3,Q1,CAIL,CLK,PS,LD,EN,RL,CD,CS);
SRRL8 ([Q0..Q7],[D0..D7],CAIR,CAIL,CLK,PS,LD,EN,RL,CD,CS);
SRRL8_1 ([Q0..Q2],[D0..D2],CAIR,Q3,CLK,PS,LD,EN,RL,CD,CS);
SRRL8_2 ([Q3..Q5],[D3..D5],Q2,Q6,CLK,PS,LD,EN,RL,CD,CS);
SRRL8_3 (Q6,Q7,D6,D7,Q5,CAIL,CLK,PS,LD,EN,RL,CD,CS);
ispLSI Macro Library Reference Manual
388
Shift Registers
Truth Table:
SRRL8
The SRRL1 has only Q0 as an output. The SRRL4 has Q0 to Q3.
The SRRL8 has Q0 to Q7.
Input
CD
PS
CS
LD
D0~D7
RL
EN
1
0
0
0
0
0
0
0
0
x
1
0
0
0
0
0
x
x
x
x
1
0
0
0
0
x
x
x
x
x
1
0
0
0
x
x
x
x
x
d
x
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
1
1
0
x
x
CAIR CAIL CLK
x
x
x
x
x
d
x
x
x
x
x
x
x
d
x
x
x
x
x
↑
↑
↑
↑
↑
↑
0
1
PS
CAIR
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
CAIL
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
R/L
0
1
0
D0
Q1
CAIR
Q0
Q0
Q0
0
1
0
D1
Q2
Q0
Q1
Q1
Q1
0
1
0
D2
Q3
Q1
Q2
Q2
Q2
0
1
0
D3
Q4
Q2
Q3
Q3
Q3
0
1
0
D4
Q5
Q3
Q4
Q4
Q4
0
1
0
D5
Q6
Q4
Q5
Q5
Q5
0
1
0
D6
Q7
Q5
Q6
Q6
Q6
0
1
0
D7
CAIL
Q6
Q7
Q7
Q7
LD
EN
CD CS
CAIL = shift left serial input, CAIR = shift right serial input,
d = any pattern of 1s and 0s on an input or set of inputs,
D0..Dn-1 = input to D or T flip-flop/latch; load inputs for counters and shift registers,
Q0’ = previous output of flip-flop or latch, x = don’t care, ↑ = rising clock edge.
ispLSI Macro Library Reference Manual
389
Shift Registers
SRRL1
EN
RL
CAIR
LD
D
Q
Q0
CAIL
CLK
CD
FD21
CS
CD
D0
PS
Note:
. EN=HI & RL=HI & LD=LO : Shift CAIR to the right
. EN=HI & RL=LO & LD=LO : Shift CAIL to the left
. EN=LO : Keep the previous state
. LD=HI : Parallel data load
. CS & PS & CD are active hi
ispLSI Macro Library Reference Manual
390
Shift Registers
SRRL4
PS
CAIR
D0
PS
CAIR
D0
Q0
Q0
CAIL
RL
R/L
LD
LD
EN
EN
Note:
CLK
CD
CS
SRRL1
CD
CS
EN=HI
&
RL=HI
&
LD=LO:
Shift
CAIR
to
the
right
EN=HI
&
RL=LO
&
LD=LO:
Shift
CAIL
to
the
left
EN=LO:
Keep
LD=HI:
Parallel
CS
&
PS
&
CD
the
previous
data
are
state
load
active
hi
PS
CAIR
D1
D0
Q0
Q1
CAIL
R/L
LD
EN
CD
CS
SRRL1
PS
CAIR
D2
D0
Q0
Q2
CAIL
R/L
LD
EN
CD
CS
SRRL1
PS
CAIR
D3
CAIL
D0
Q0
Q3
CAIL
R/L
LD
EN
CD
CS
SRRL1
ispLSI Macro Library Reference Manual
391
Shift Registers
SRRL8
PS
CAIR
D0
PS
CAIR
D0
PS
CAIR
Q0
Q0
D4
D0
Q0
CAIL
CAIL
RL
R/L
R/L
LD
LD
LD
EN
EN
EN
Q4
Note:
EN=HI & RL=HI & LD=LO: Shift CAIR to the right
EN=HI & RL=LO & LD=LO: Shift CAIL to the left
CLK
CD CS
SRRL1
CD CS
SRRL1
CD
EN=LO: Keep the previous state
LD=HI: Parallel data load
CS & PS & CD are active hi
CS
PS
CAIR
D1
D0
PS
CAIR
Q0
Q1
D5
D0
Q0
CAIL
CAIL
R/L
R/L
LD
LD
EN
EN
CD CS
SRRL1
CD CS
SRRL1
PS
PS
CAIR
D2
D0
CAIR
Q0
Q2
D6
D0
CAIL
CAIL
R/L
R/L
LD
LD
EN
EN
CD CS
SRRL1
D0
Q0
CAIL
Q0
Q6
CD CS
SRRL1
PS
CAIR
D3
Q5
PS
CAIR
Q3
D7
CAIL
D0
R/L
LD
LD
EN
EN
CD CS
SRRL1
ispLSI Macro Library Reference Manual
Q0
Q7
CAIL
R/L
CD CS
SRRL1
392
Index
A
ADDF1 39
ADDF16A 39
ADDF2 39
ADDF4 39
ADDF8 39
ADDF8A 39
ADDH16A 54
ADDH2 54
ADDH3 54
ADDH4 54
ADDH8 54
ADDH8A 54
AND2 through AND18 316
Arithmetic Functions 38
B
BI11 284
BI14 284
BI18 284
BI21 285
BI24 285
BI28 285
BI31 286
BI34 286
BI38 286
BI41 287
BI44 287
BI48 287
Bidirectional Pins 284
BIID11 288
BIID14 288
BIID18 288
BIID21 289
BIID24 289
BIID28 289
BIID31 290
BIID34 290
BIID38 290
BIID41 291
BIID44 291
BIID48 291
BIID51 292
BIID54 292
BIID58 292
BIID61 293
BIID64 293
BIID68 293
BIID71 294
BIID74 294
BIID78 294
BIID81 295
BIID84 295
BIID88 295
BIIL11 296
BIIL14 296
BIIL18 296
BIIL21 297
BIIL24 297
BIIL28 297
BIIL31 298
BIIL34 298
BIIL38 298
BIIL41 299
BIIL44 299
BIIL48 299
BIIL51 300
BIIL54 300
BIIL58 300
BIIL61 301
BIIL64 301
BIIL68 301
BIIL71 302
BIIL74 302
BIIL78 302
BIIL81 303
BIIL84 303
BIIL88 303
BIN27 104
Binary Counters 113
BUF 317
C
CBD11
CBD12
CBD14
CBD18
CBD21
CBD22
CBD24
113
113
113
113
119
119
119
ispLSI Macro Library Reference Manual
393
Index
CBD28 119
CBD31 125
CBD32 125
CBD34 125
CBD38 125
CBD41 132
CBD42 132
CBD44 132
CBD48 132
CBD516 139
CBD616 139
CBU11 149
CBU12 149
CBU14 149
CBU18 149
CBU21 155
CBU22 155
CBU24 155
CBU28 155
CBU31 161
CBU32 161
CBU34 161
CBU38 161
CBU41 168
CBU42 168
CBU44 168
CBU48 168
CBU516 175
CBU616 175
CBU716 184
CBUD1 190
CBUD2 190
CBUD4 190
CBUD8 190
CDD14 200
CDD18 200
CDD24 206
CDD28 206
CDD34 212
CDD38 212
CDD44 218
CDD48 218
CDU14 222
CDU18 222
CDU24 228
CDU28 228
CDU34 234
CDU38 234
CDU44 240
CDU48 240
CDUD4 246
CDUD4c 256
CDUD8 246
CDUD8c 256
CGD14 266
CGD24 269
CGU14 272
CGU24 276
CGUD4 279
CMP2 67
CMP4 67
CMP8 67
Coders 103
Comparators 67
Counters 112
D
D Flip-flops 347
D Latches 361
DEC2 106
DEC2E 106
DEC3 107
DEC3E 107
DEC4 108
DEC4E 108
Decade Counters 200
Decoders 104
Demultiplexers 339
DMUX2 339
DMUX22 341
DMUX22E 341
DMUX24 342
DMUX24E 342
DMUX2E 339
DMUX4 340
DMUX42 343
DMUX42E 343
DMUX44 344
DMUX44E 344
DMUX4E 340
DMUX82 345
DMUX82E 345
Documentation Conventions 8
E
Encoders 109
F
F3ADD 39
F3SUB 80
FD11 347
FD14 347
FD18 347
FD21 348
ispLSI Macro Library Reference Manual
394
Index
FD24 348
FD28 348
FD31 349
FD34 349
FD38 349
FD41 350
FD44 350
FD48 350
FD51 351
FD54 351
FD58 351
FD61 352
FD64 352
FD68 352
FD71 353
FD74 353
FD78 353
FD81 354
FD84 354
FD88 354
FD91 355
FD94 355
FD98 355
FDA1 356
FDA4 356
FDA8 356
FJK11 357
FJK21 357
FJK31 358
FJK41 358
FJK51 359
FT11 360
FT21 360
G
Gray Code Counters 266
I
I/O Pins 283
IB11 304
ID11 305
ID14 305
ID18 305
ID21 306
ID24 306
ID28 306
IL11 307
IL14 307
IL18 307
IL21 308
IL24 308
IL28 308
Input Pins 304
INV 317
J
JK Flip-flops 357
L
LD11 361
LD14 361
LD18 361
LD21 362
LD24 362
LD28 362
LD31 363
LD34 363
LD38 363
LD41 364
LD44 364
LD48 364
LD51 365
LD54 365
LD58 365
LD61 366
LD64 366
LD68 366
LD71 367
LD74 367
LD78 367
LD81 368
LD84 368
LD88 368
LD91 369
LD94 369
LD98 369
LDA1 370
LDA4 370
LDA8 370
Logic Gates 315, 316
Logic Resources 14
LSR1 371
LSR2 371
LXOR 322
M
MAG2 68
MAG4 68
MAG8 68
Module Macro Truth Tables 12
MULT24 70
MULT44 70
Multiplexers 324
Multipliers 70
ispLSI Macro Library Reference Manual
395
Index
P
MUX/DMUX 323
MUX16 327
MUX16E 327
MUX2 324
MUX22 331
MUX22E 331
MUX24 332
MUX24E 332
MUX2E 324
MUX4 325
MUX42 333
MUX42E 333
MUX44 334
MUX44AE 335
MUX44E 334
MUX4E 325
MUX8 326
MUX82 338
MUX82E 338
MUX8E 326
PG1 74
PG2 74
PG3 74
PG4 74
Pin Labeling 13
Preface 7
PREN10 110
PREN10E 110
PREN16 111
PREN16E 111
PREN8 109
PREN8E 109
Propagate-Generate 74
Purpose and Scope 8
R
Registers 346
S
N
NAND16 318
NAND2 through NAND12 318
NOR16 319
NOR2 through NOR12 319
O
OB11 309
OB21 310
OB24 310
OB28 310
OR16 320
OR2 through OR12 320
OT11 311
OT14 311
OT18 311
OT21 312
OT24 312
OT28 312
OT31 313
OT34 313
OT38 313
OT41 314
OT44 314
OT48 314
Output Pins 309
Overview 7
Shift Registers 372
Signal Names 9
SR Latches 371
SRR11 372
SRR14 372
SRR18 372
SRR21 376
SRR24 376
SRR28 376
SRR31 380
SRR34 380
SRR38 380
SRR41 384
SRR44 384
SRR48 384
SRRL1 388
SRRL4 388
SRRL8 388
SUBF1 80
SUBF16A 80
SUBF2 80
SUBF4 80
SUBF8 80
SUBF8A 80
SUBH1 90
SUBH16A 90
SUBH2 90
SUBH3 90
ispLSI Macro Library Reference Manual
396
Index
SUBH4 90
SUBH8 90
SUBH8A 90
Subtractors 80
T
Toggle Flip-flops 360
Truth Tables 11
U
Using the NOMIN Attribute 15
X
XNOR2 321
XNOR3 321
XNOR4 321
XNOR7 321
XNOR8 321
XNOR9 321
XOR2 322
XOR3 322
XOR4 322
XOR8 322
XOR9 322
ispLSI Macro Library Reference Manual
397