AD AD5280BRUZ20

Single/Dual, +15 V/±5 V, 256-Position,
I2C-Compatible Digital Potentiometer
AD5280/AD5282
APPLICATIONS
The AD5280/AD5282 are available in thin, surface-mounted
14-lead TSSOP and 16-lead TSSOP. All parts are guaranteed to
operate over the extended industrial temperature range of
−40°C to +85°C. For 3-wire SPI-compatible interface applications, see the AD5260/AD5262 product information on
www.analog.com.
FUNCTIONAL BLOCK DIAGRAMS
A
O1
O2
VDD
VL
VSS
RDAC REGISTER
OUTPUT REGISTER
ADDRESS
CODE
8
PWR ON
RESET
SCL
SERIAL INPUT REGISTER
SDA
GENERAL DESCRIPTION
Wiper position programming defaults to midscale at system
power-on. When powered, the VR wiper position is programmed
by an I2C-compatible, 2-wire serial data interface. The AD5280/
AD5282 feature sleep mode programmability. This allows any
level of preset in power-up and is an alternative to a costly
EEPROM solution. Both parts have additional programmable
B
SHDN
Multimedia, video, and audio
Communications
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage source
Programmable current source
Line impedance matching
The AD5280/AD5282 are single-channel and dual-channel,
256-position, digitally controlled variable resistors (VRs) 2 .
The devices perform the same electronic adjustment function
as a potentiometer, trimmer, or variable resistor. Each VR offers
a completely programmable value of resistance between the
A terminal and the wiper or the B terminal and the wiper. The
fixed A-to-B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has
a 1% channel-to-channel matching tolerance. The nominal
temperature coefficient of both parts is 30 parts per million/
degrees centigrade (ppm/°C). Another key feature is that the
parts can operate up to +15 V or ±5 V.
W
GND
AD5280
AD0
AD1
Figure 1. AD5280
A1
W1
B1
A2
W2
B2
O1
OUTPUT
REGISTER
SHDN
VDD
VL
VSS
RDAC1 REGISTER
RDAC2 REGISTER
ADDRESS
CODE
8
PWR ON
RESET
SCL
SERIAL INPUT REGISTER
SDA
GND
AD5282
AD0
02929-001
AD5280: 1 channel
AD5282: 2 channels
256 positions
+10 V to +15 V single supply; ±5.5 V dual-supply operation
Fixed terminal resistance: 20 kΩ, 50 kΩ, 200 kΩ
Low temperature coefficient: 30 ppm/°C
Power-on midscale preset 1
Programmable reset
Operating temperature: −40oC to +85oC
I2C-compatible interface
logic outputs that enable users to drive digital loads, logic gates,
LED drivers, and analog switches in their system.
02929-070
FEATURES
AD1
Figure 2. AD5282
1
Assert shutdown and program the device during power-up, then deassert
the shutdown to achieve the desired preset level.
2
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
AD5280/AD5282
TABLE OF CONTENTS
Features .............................................................................................. 1 Multiple Devices on One Bus ................................................... 17 Applications ....................................................................................... 1 Level Shift for Bidirectional Interface...................................... 18 General Description ......................................................................... 1 Level Shift for Negative Voltage Operation ............................ 18 Functional Block Diagrams ............................................................. 1 ESD Protection ........................................................................... 18 Revision History ............................................................................... 2 Terminal Voltage Operating Range ......................................... 18 Specifications..................................................................................... 3 Power-Up Sequence ................................................................... 18 Electrical Characteristics ............................................................. 3 Layout and Power Supply Bypassing ....................................... 19 Absolute Maximum Ratings............................................................ 5 Applications Information .............................................................. 20 Thermal Resistance ...................................................................... 5 Bipolar DC or AC Operation from Dual Supplies ................. 20 ESD Caution .................................................................................. 5 Gain Control Compensation .................................................... 20 Pin Configurations and Function Descriptions ........................... 6 15 V, 8-Bit I2C DAC.................................................................... 20 Typical Performance Characteristics ............................................. 7 8-Bit Bipolar DAC ...................................................................... 21 Test Circuits ..................................................................................... 12 Bipolar Programmable Gain Amplifier ................................... 21 Theory of Operation ...................................................................... 14 Programmable Voltage Source with Boosted Output ........... 21 Rheostat Operation .................................................................... 14 Programmable Current Source ................................................ 22 Potentiometer Operation........................................................... 14 Programmable Bidirectional Current Source ......................... 22 Digital Interface .............................................................................. 16 Programmable Low-Pass Filter ................................................ 23 2-Wire Serial Bus ........................................................................ 16 Programmable Oscillator .......................................................... 23 Readback RDAC Value .............................................................. 17 RDAC Circuit Simulation Model ............................................. 24 Additional Programmable Logic Output ................................ 17 Macro Model Net List for RDAC ............................................. 24 Self-Contained Shutdown Function and Programmable
Preset ............................................................................................ 17 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 26 REVISION HISTORY
7/09—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Updated Outline Dimensions, RU-14 ......................................... 25
Changes to Ordering Guide .......................................................... 26
8/07—Rev. A to Rev. B
Updated Operating Temperature Range Throughout ................... 1
Changes to the Features Section ....................................................... 1
Changes to the General Description Section .................................. 1
Changes to Table 2 .............................................................................. 3
Added the Thermal Resistance Section ........................................... 5
Changes to the Ordering Guide......................................................26
11/05—Rev. 0 to Rev. A
Updated Format ................................................................... Universal
Updated Outline Dimensions .........................................................26
Changes to Ordering Guide ............................................................27
10/02—Revision 0: Initial Version
Rev. C | Page 2 of 28
AD5280/AD5282
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = +15 V, VSS = 0 V or VDD = +5 V, VSS = −5 V; VLOGIC = 5 V, VA = +VDD, VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS–RHEOSTAT MODE
Resistor Differential NL 2
R-DNL
RWB, VA = NC
Resistor Nonlinearity2
R-INL
RWB, VA = NC
Nominal Resistor Tolerance 3
ΔRAB
TA = 25°C
VAB = VDD, wiper = no connect
Resistance Temperature
(∆RAB/RAB)/∆T x 106
Coefficient
Wiper Resistance
RW
IW = VDD/R, VDD = 3 V or 5 V
DC CHARACTERISTICS–POTENTIOMETER DIVIDER MODE (specifications apply to all VRs)
Resolution
N
Integral Nonlinearity 4
INL
Differential Nonlinearity4
DNL
Code = 0x80
(∆VW/VW)/∆T x 106
Voltage Divider Temperature
Coefficient
Full-Scale Error
VWFSE
Code = 0xFF
Zero-Scale Error
VWZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range 5
VA, VB, VW
6
Capacitance A, B
CA, CB
f = 5 MHz, measured to GND,
Code = 0x80
Capacitance W6
CW
f = 1 MHz, measured to GND,
Code = 0x80
Common-Mode Leakage
ICM
V A = VB = V W
Shutdown Current
ISHDN
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
Input Logic Low
VIL
Output Logic High (O1, O2)
VIH
Output Logic Low (O1, O2)
VIL
Input Current
IIL
VIN = 0 V or 5 V
Input Capacitance6
CIL
POWER SUPPLIES
Logic Supply
VLOGIC
Power Single-Supply Range
VDD RANGE
VSS = 0 V
Power Dual-Supply Range
VDD/SS RANGE
Logic Supply Current
ILOGIC
VLOGIC = 5 V
Positive Supply Current
IDD
VIH = 5 V or VIL = 0 V
Negative Supply Current
ISS
Power Dissipation 7
PDISS
VIH = 5 V or VIL = 0 V, VDD = +5 V, VSS = −5
V
Power Supply Sensitivity
PSS
DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth −3 dB
BW_20K
RAB = 20 kΩ, Code = 0x80
BW_50K
RAB = 50 kΩ, Code = 0x80
BW_200K
RAB = 200 kΩ, Code = 0x80
Rev. C | Page 3 of 28
Min
Typ 1
Max
Unit
−1
−1
−30
±1/4
±1/4
+1
+1
+30
LSB
LSB
%
ppm/°C
60
150
Ω
±1/4
±1/4
5
+1
+1
Bits
LSB
LSB
ppm/°C
−1
+1
0
+2
LSB
LSB
VDD
25
V
pF
55
pF
30
8
−1
−1
−2
0
VSS
1
5
0.7 × VL
0
4.9
VL + 0.5
0.3 × VL
0.4
±1
5
2.7
4.5
±4.5
nA
μA
V
V
V
V
μA
pF
0.1
0.1
0.2
VDD
16.5
±5.5
60
1
1
0.3
V
V
V
μA
μA
μA
mW
0.002
0.01
%/%
310
150
35
kHz
kHz
kHz
AD5280/AD5282
Parameter
Total Harmonic Distortion
Symbol
THDW
VW Settling Time
Crosstalk
tS
CT
Analog Crosstalk
CTA
Conditions
VA = 1 V rms, RAB = 20 kΩ
VB = 0 V dc, f = 1 kHz
VA = 5 V, VB = 5 V, ±1 LSB error band
VA = VDD, VB = 0 V, measure VW1 with
adjacent RDAC making full-scale
code change
Measure VW1 with VW2 = 5 V p-p @ f =
10 kHz
RWB = 20 kΩ, f = 1 kHz
Resistor Noise Voltage
eN_WB
INTERFACE TIMING CHARACTERISTICS (applies to all parts)6, 10, 11
SCL Clock Frequency
fSCL
t1
tBUF Bus Free Time Between
Stop and Start
t2
tHD:STA Hold Time (Repeated
After this period, the first clock pulse
Start)
is generated
tLOW Low Period of SCL Clock
t3
tHIGH High Period of SCL Clock
t4
t5
tSU:STA Setup Time for Start
Condition
tHD:DAT Data Hold Time
t6
tSU:DAT Data Setup Time
t7
t8
tF Fall Time of Both SDA and
SCL Signals
t9
tR Rise Time of Both SDA and
SCL Signals
t10
tSU:STO Setup Time for STOP
Condition
Min
Typ 1
0.014
Max
Unit
%
5
15
μs
nV-s
−62
dB
18
nV/√Hz
1.3
kHz
μs
0.6
μs
1.3
0.6
0.6
μs
μs
μs
0
0
400
0.9
300
μs
ns
ns
300
ns
100
0.6
μs
1
Typicals represent average readings at 25°C, VDD = +5 V, VSS = −5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
VAB = VDD, wiper (VW) = no connect.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use VDD = 5 V.
10
See timing diagram (Figure 3) for location of measured values.
11
Standard I2C mode operation is guaranteed by design.
2
t8
t6
t2
t9
SCL
t2
t4
t3
t8
t7
t10
t5
t9
t1
P
S
S
Figure 3. Detailed Timing Diagram
Rev. C | Page 4 of 28
P
02929-042
SDA
AD5280/AD5282
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
VDD to GND
VSS to GND
VDD to VSS
VA, VB, VW to GND
AX to BX, AX to WX, BX to WX
Intermittent 1
Continuous
VLOGIC to GND
Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
1
Rating
−0.3 V to +16.5 V
0 V to −7 V
16.5 V
VSS to VDD
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
±20 mA
±5 mA
0 V to 7 V
0 V to 7 V
−40°C to +85°C
150°C
−65°C to +150°C
260°C
20 sec to 40 sec
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. Package
power dissipation = (TJMAX − TA)/ θJA .
Table 3. Thermal Resistance
Package Type
TSSOP-14
TSSOP-16
ESD CAUTION
Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
Rev. C | Page 5 of 28
θJA
206
150
Unit
°C/W
°C/W
AD5280/AD5282
1
14
O1
O1
1
16
A2
2
13
VL
A1
2
15
W2
B
3
12
O2
W1
3
14
B2
VDD
4
11
VSS
B1
4
13
VL
SHDN
5
10
GND
VDD
5
12
VSS
SCL
6
9
AD1
SHDN
6
11
GND
SDA
7
8
AD0
SCL
7
10
AD1
SDA
8
9
AD0
AD5280
TOP VIEW
02929-002
A
W
Figure 4. AD5280 Pin Configuration
AD5282
TOP VIEW
Figure 5. AD5282 Pin Configuration
Table 4. AD5280 Pin Function Descriptions
Table 5. AD5282 Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
A
W
B
VDD
Pin No.
1
2
3
4
5
Mnemonic
O1
A1
W1
B1
VDD
5
SHDN
6
SHDN
7
8
9
SCL
SDA
AD0
10
AD1
11
12
GND
VSS
13
VL
14
15
16
B2
W2
A2
6
7
8
SCL
SDA
AD0
9
AD1
10
11
GND
VSS
12
13
O2
VL
14
O1
02929-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Description
Resistor Terminal A.
Wiper Terminal W.
Resistor Terminal B.
Positive Power Supply. Specified for
operation from 5 V to 15 V (sum of |VDD|
+ |VSS| ≤ 15 V).
Active Low, Asynchronous Connection
of Wiper W to Terminal B and Open
Circuit of Terminal A. RDAC register
contents unchanged. SHDN should tie
to VL if not used. Can also be used as a
programmable preset in power-up.
Serial Clock Input.
Serial Data Input/Output.
Programmable Address Bit 0 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
Programmable Address Bit 1 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
Common Ground.
Negative Power Supply. Specified for
operation from 0 V to −5 V (sum of |VDD|
+ |VSS| ≤ 15 V).
Logic Output Terminal O2.
Logic Supply Voltage. Needs to be less
than or equal to VDD and at the same
voltage as the digital logic controlling
the AD5280.
Logic Output Terminal O1.
Rev. C | Page 6 of 28
Description
Logic Output Terminal O1.
Resistor Terminal A1.
Wiper Terminal W1.
Resistor Terminal B1.
Positive Power Supply. Specified for
operation from 5 V to 15 V (sum of |VDD|
+ |VSS| ≤ 15 V).
Active Low, Asynchronous Connection
of Wiper W to Terminal B and Open
Circuit of Terminal A. RDAC register
contents unchanged. SHDN should tie
to VL if not used. Can be also used as a
programmable preset in power-up.
Serial Clock Input.
Serial Data Input/Output.
Programmable Address Bit 0 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
Programmable Address Bit 1 for
Multiple Package Decoding. Bit AD0
and Bit AD1 provide four possible
addresses.
Common Ground.
Negative Power Supply. Specified for
operation from 0 V to −5 V (sum of |VDD|
+ |VSS| ≤ 15 V).
Logic Supply Voltage. Needs to be less
than or equal to VDD and at the same
voltage as the digital logic controlling
the AD5282.
Resistor Terminal B2.
Wiper Terminal W2.
Resistor Terminal A2.
AD5280/AD5282
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
RAB = 20kΩ
TA = 25°C
POTENTIOMETER MODE DNL (LSB)
0.6
+5V
0.4
0.2
0
–0.2
±5V
–0.4
+15V
–0.6
–0.8
–1.0
0
32
64
96
128
160
CODE (Decimal)
192
224
RAB = 20kΩ
0.4
02929-004
RHEOSTAT MODE R-INL (LSB)
0.8
0.3
0.2
TA = –40°C
0.1
0
–0.1
–0.2
–0.3
TA = +25°C
–0.4
–0.5
256
0
32
Figure 6. R-INL vs. Code vs. Supply Voltages
224
256
+15V
0.1
0
–0.1
–0.2
+5V
–0.3
0
32
64
96
128
160
CODE (Decimal)
192
224
RAB = 20kΩ
TA = 25°C
0.6
±5V
0.4
+5V
0.2
+15V
0
–0.2
–0.4
–0.6
02929-008
POTENTIOMETER MODE INL (LSB)
±5V
0.2
02929-005
RHEOSTAT MODE R-DNL (LSB)
192
0.8
0.3
–0.8
–0.8
–1.0
256
0
Figure 7. R-DNL vs. Code vs. Supply Voltages
32
64
96
128
160
CODE (Decimal)
192
224
256
Figure 10. INL vs. Code vs. Supply Voltages
1.0
0.5
RAB = 20kΩ
TA = +85°C
0.2
0
–0.2
TA = –40°C
–0.4
TA = +25°C
02929-006
–0.6
–0.8
0
32
64
96
128
160
CODE (Decimal)
192
224
0.3
+5V
0.2
±5V
0.1
+15V
0
–0.1
–0.2
–0.3
02929-009
0.6
0.4
RAB = 20kΩ
TA = 25°C
0.4
POTENTIOMETER MODE INL (LSB)
0.8
POTENTIOMETER MODE INL (LSB)
96
128
160
CODE (Decimal)
1.0
RAB = 20kΩ
TA = 25°C
0.4
–1.0
64
Figure 9. DNL vs. Code, VDD/VSS = ±5 V
0.5
–0.5
TA = +85°C
02929-007
1.0
–0.4
–0.5
256
Figure 8. INL vs. Code, VDD/VSS = ±5 V
0
32
64
96
128
160
CODE (Decimal)
192
224
Figure 11. DNL vs. Code vs. Supply Voltages
Rev. C | Page 7 of 28
256
AD5280/AD5282
1.0
2.0
RAB = 20kΩ
TA = 25°C
AVG +3σ
AVG –3σ
0
02929-010
–0.5
5
10
|VDD – VSS| (V)
15
1.2
1.0
0.4
0.2
0
–40
20
60
AVG +3σ
IDD/ISS SUPPLY CURRENT (nA)
R-INL (LSB)
20
40
TEMPERATURE (°C)
RAB = 20kΩ
AVG
0.5
AVG –3σ
0
–0.5
–1.0
0
5
10
|VDD – VSS| (V)
100
15
VLOGIC = +5V
VIH = +5V
VIL = 0V
100
[email protected]/VSS = +15V/0V
10
1
–40
20
[email protected]/VSS = ±5V
–7
26
TEMPERATURE (°C)
59
85
Figure 16. Supply Current vs. Temperature
Figure 13. R-INL Over Supply Voltage
26.0
0
RAB = 20kΩ
–0.2
RAB = 20kΩ
25.5
–0.4
VDD/VSS = +15V/0V
VDD/VSS = +15V/0V
–0.6
25.0
–1.0
ILOGIC (µA)
–0.8
VDD/VSS = ±5V
–1.2
–1.4
24.5
24.0
VDD/VSS = +5V/0V
VDD/VSS = ±5V
–1.6
02929-012
23.5
–1.8
–2.0
–40
80
[email protected]/VSS = ±5V
02929-011
–1.5
FULL-SCALE ERROR (LSB)
0
1000
1.0
–2.0
–20
Figure 15. Zero-Scale Error
RAB = 20kΩ
TA = 25°C
1.5
VDD/VSS = +15V/0V
0.6
Figure 12. INL Over Supply Voltage
2.0
VDD/VSS = ±5V
0.8
02929-014
0
VDD/VSS = +5V/0V
1.4
–20
0
20
40
TEMPERATURE (°C)
60
80
23.0
–40
100
02929-015
INL (LSB)
AVG
02929-013
ZERO-SCALE ERROR (LSB)
1.6
0.5
–1.0
RAB = 20kΩ
1.8
–7
26
TEMPERATURE (°C)
59
Figure 17. VLOGIC Supply Current vs. Temperature
Figure 14. Full-Scale Error
Rev. C | Page 8 of 28
85
AD5280/AD5282
1000
0
RAB = 20kΩ
TA = 25°C
80H
–6
40H
20H
–18
100
10H
–24
08H
–30
04H
–36
02H
01H
–42
–48
0
1
2
3
4
TA = 25°C
VA = 50mV rms
VDD/VSS = ±5V
–54
–60
5
0
VIH (V)
Figure 18. VLOGIC Supply Current vs. Digital Input Voltage
0
80H
–6
40H
–12
20H
–18
GAIN (dB)
400
300
20kΩ
200
50kΩ
200kΩ
100
10H
–24
08H
–30
04H
–36
02H
–42
0
01H
–48
–100
0
32
64
96
128
CODE (Decimal)
192
224
TA = 25°C
VA = 50mV rms
VDD/VSS = ±5
–54
–60
256
0
1M
Figure 22. Gain vs. Frequency vs. Code, RAB = 50 kΩ
Figure 19. Rheostat Mode Tempco ΔRWB/ΔT vs. Code, VDD/VSS = ±5 V
0
120
TA = 25°C
80H
–6
100
40H
–12
80
60
20H
–18
20kΩ
GAIN (dB)
50kΩ
200kΩ
40
20
10H
–24
08H
–30
04H
–36
02H
–42
0
01H
–48
–20
02929-018
POTENTIOMETER MODE TEMPCO (ppm/°C)
10k
100k
FREQUENCY (Hz)
02929-020
500
02929-017
RHEOSTAT MODE TEMPCO (ppm/°C)
TA = 25°C
600
–40
1M
Figure 21. Gain vs. Frequency vs. Code, RAB = 20 kΩ
700
–200
10k
100k
FREQUENCY (Hz)
0
32
64
96
128
CODE (Decimal)
192
224
TA = 25°C
VA = 50mV rms
VDD/VSS = ±5V
–54
–60
256
0
10k
100k
FREQUENCY (Hz)
Figure 23. Gain vs. Frequency vs. Code, RAB = 200 kΩ
Figure 20. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code,
VDD/VSS = ±5 V
Rev. C | Page 9 of 28
02929-021
10
02929-016
VDD/VSS = 5V/0V
VLOGIC = 3V
02929-019
VDD/VSS = 5V/0V
VLOGIC = 5V
GAIN (dB)
ILOGIC (µA)
–12
1M
AD5280/AD5282
0
80
R = 20kΩ
310kHz
–6
CODE = 80H, VA = VDD, VB = 0V
–12
PSRR (dB)
R = 200kΩ
35kHz
–36
40
–42
+PSRR @ VDD/VSS = ±5V
DC ±10% p-p AC
–60
0
02929-022
TA = 25°C
VDD/VSS = ±5V
VA = 50mV rms
–54
10k
100k
FREQUENCY (Hz)
02929-025
20
–48
0
100
1M
1000
100k
1M
Figure 27. PSRR vs. Frequency
Figure 24. −3 dB Bandwidth
TA = 25°C
VDD/VSS = ±5V
A2
1.2V
852.0µs
R = 20kΩ
–6dB
R = 50kΩ
R = 200kΩ
02929-023
NOMINALIZED GAIN FLATNESS (0.1dB/DIV)
10k
FREQUENCY (MHz)
100
1k
10k
FREQUENCY (Hz)
02929-026
GAIN (dB)
–24
–30
–PSRR @ V DD/VSS = ±5V
DC ±10% p-p AC
60
R = 50kΩ
150kHz
–18
2.04µs
100k
Figure 25. Normalized Gain Flatness vs. Frequency
Figure 28. Midscale Glitch Energy Code 0x80 to 0x7F
500
T
TA = 25°C
VDD/VSS = ±5V
+5V
VW
1
300
–5V
CODE = 55H
200
CS
100
0
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 26. VLOGIC Supply Current vs. Frequency
2
02929-027
CODE = 55H
02929-024
ILOGIC (mA)
400
CH1 5.00V
CH2 5.00V
M100ns
A CH1
Figure 29. Large Signal Settling Time
Rev. C | Page 10 of 28
0V
AD5280/AD5282
40
A2
1.0V
33.41µs
FREQUENCY (MHz)
30
CODES SET TO
MIDSCALE
3 LOTS
SAMPLE SIZE = 135
20
02929-030
0.2
0.1
0.15
0
0.05
–0.05
–0.1
–0.2
–0.15
–0.3
–0.25
–0.4
–0.35
0
–0.5
1.50µs
–0.45
02929-028
10
LONG TERM CHANNEL-TO-CHANNEL RAB MATCH (%)
Figure 30. Digital Feedthrough vs. Time
VA = VB = OPEN
TA = 25°C
10
1.0
RAB = 20kΩ
RAB = 50kΩ
0.1
RAB = 200kΩ
0.01
02929-029
THEORETICAL |WB_MAX (mA)
100
Figure 32. Channel-to-Channel Resistance Matching (AD5282)
0
32
64
96
128
CODE (Decimal)
192
224
256
Figure 31. IWB_MAX vs. Code
Rev. C | Page 11 of 28
AD5280/AD5282
TEST CIRCUITS
Figure 33 to Figure 43 define the test conditions used in the product specification table.
DUT
VIN
B
VMS
B
5V
W
W
OP279
OFFSET
GND
02929-031
A
V+
A
V+ = VDD
1LSB = V+/2N
OFFSET
BIAS
Figure 37. Inverting Gain
Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL)
5V
NO CONNECT
IW
OP279
VIN
W
VMS
A
VW
W
B
Figure 38. Noninverting Gain
VIN
+15V
W
DUT
VOUT
AD8610
OFFSET
GND
02929-033
VMS1
RW = [VMS1 –VMS2]/IW
B
)
ΔVMS%
ΔVDD%
W
B
VMS
0.1V
RSW = I
SW
DUT
02929-034
V+
W
(
ΔVMS
ΔVDD
ISW
VSS TO VDD
Figure 36. Power Supply Sensitivity (PSS, PSSR)
0.1V
02929-038
PSRR (dB) = 20 LOG
A
Figure 39. Gain vs. Frequency
V+ = VDD ±10%
PSS (%/%) =
–15V
2.5V
Figure 35. Wiper Resistance
VA
B
02929-037
B
VDD
DUT
IW = VDD/RNOMINAL
DUT
VMS2
A
OFFSET
BIAS
Figure 34. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
A
W
OFFSET
GND
02929-032
B
VOUT
02929-036
DUT
A
VOUT
02929-035
DUT
Figure 40. Incremental On Resistance
Rev. C | Page 12 of 28
AD5280/AD5282
A
VSS
B
GND
W
ICM
VIN
VCM
NC
02929-039
VDD
DUT
VDD
A1
NC = NO CONNECT
N/C
RDAC 1
W1
B1
A2
RDAC 2
W2
VSS
CTA = 20 LOG [VOUT/VIN]
B2
Figure 43. Analog Crosstalk (AD5282 Only)
Figure 41. Common-Mode Leakage Current
VLOGIC
VOUT
02929-041
NC
ILOGIC
SCL
SCA
02929-040
DIGITAL INPUT
VOLTAGE
Figure 42. VLOGIC Current vs. Digital Input Voltage
Rev. C | Page 13 of 28
AD5280/AD5282
THEORY OF OPERATION
The AD5280/AD5282 are single-channel and dual-channel,
256-position, digitally controlled variable resistors (VRs). To
program the VR settings, see the Digital Interface section. Both
parts have an internal power-on preset that places the wiper at
midscale during power-on, which simplifies the fault condition
recovery at power-up. Operation of the power-on preset function
also depends on the state of the VL pin.
SWA
AX
SHDN
RS
RDAC
LATCH
AND
DECODER
RS
0xFF
RS
WX
0x01
RS
SWB
0x00
BX
02929-045
D7
D6
D5
D4
D3
D2
D1
D0
Figure 44. AD5280/AD5282 Equivalent RDAC Circuit
RHEOSTAT OPERATION
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final
two or three digits of the part number determine the nominal
resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, and
200 kΩ = 200. The nominal resistance (RAB) of the VR has
256 contact points accessed by the wiper terminal, plus the B
terminal contact. The eight-bit data in the RDAC latch is
decoded to select one of the 256 possible settings. Assuming
that a 20 kΩ part is used, the wiper’s first connection starts at
the B terminal for data 0x00. Because there is a 60 Ω wiper
contact resistance, such a connection yields a minimum of 60 Ω
resistance between Terminal W and Terminal B.
The second connection is the first tap point that corresponds to
138 Ω (RWB = RAB/256 + RW = 78 Ω + 60 Ω) for data 0x01. The
third connection is the next tap point representing 216 Ω (78 ×
2 + 60) for data 0x02, and so on. Each LSB data value increase
moves the wiper up the resistor ladder until the last tap point is
reached at 19,982 Ω (RAB – 1 LSB + RW). Figure 46 shows a
simplified diagram of the equivalent RDAC circuit where the
last resistor string is not accessed; therefore, there is 1 LSB less
of the nominal resistance at full scale in addition to the wiper
resistance.
The general equation determining the digitally programmed
output resistance between W and B is
RWB (D ) =
D
× RAB + RW
256
(1)
where:
D is the decimal equivalent of the binary code loaded in the 8bit RDAC register.
RAB is the nominal end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
Note that in the zero-scale condition, a finite wiper resistance
of 60 Ω is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
As in the mechanical potentiometer, the resistance of the RDAC
between Wiper W and Terminal A also produces a digitally
controlled complementary resistance, RWA. When these terminals
are used, the B terminal can be opened. Setting the resistance
value for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value. The
general equation for this operation is
256 − D
(2)
RWA (D ) =
× RAB + RW
256
The typical distribution of the nominal resistance, RAB, from
channel to channel matches within ±1%. Device-to-device
matching is process lot dependent, and it is possible to have a
±30% variation. Because the resistance element is processed in
thin film technology, the change in RAB with temperature is very
small (30 ppm/°C).
POTENTIOMETER OPERATION
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A to be proportional to the input voltage
at A to B. Unlike the polarity of VDD – VSS, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity, provided that VSS is powered by a negative supply.
If the effect of the wiper resistance for approximation is ignored,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across A to B divided by the 256 positions of the
potentiometer divider. Because the AD5280/AD5282 can be
supplied by dual supplies, the general equation defining the
output voltage at VW with respect to ground for any valid
Rev. C | Page 14 of 28
AD5280/AD5282
input voltage applied to Terminal A and Terminal B is
D
256 − D
VW (D ) =
VA +
VB
256
256
Operation of the digital potentiometer in divider mode results
in a more accurate operation over temperature. Unlike rheostat
mode, the output voltage is dependent mainly on the ratio of
the internal resistors RWA and RWB and not on the absolute
values; therefore, the temperature drift reduces to 5 ppm/°C.
(3)
For a more accurate calculation that includes the effect of wiper
resistance, VW can be found as
VW (D ) =
R (D )
RWB ( D )
VA + WA
VB
RAB
RAB
(4)
1
9
1
9
1
9
SCL
1
0
1
1 AD1 AD0 R/W
A/B
RS
SD
O1
O2
X
X
ACK. BY
AD5280/5282
START BY
MASTER
X
D7
D6
D5
D4
D3
D2
D1
ACK. BY
AD5280/AD5282
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
D0
ACK. BY
AD5280/5282
STOP BY
MASTER
FRAME 3
DATA BYTE
02929-043
0
SDA
Figure 45. Writing to the RDAC Register
9
1
1
9
SCL
1
0
1
1
AD1 AD0 R/W
D7
D6
D5
D4
D3
D2
D1
D0
A
ACK. BY
AD5280/AD5282
START BY
MASTER
NO ACK. BY
MASTER
FRAME 2
STOP BY
DATA BYTE FROM PREVIOUSLY SELECTED
MASTER
FRAME 1
SLAVE ADDRESS BYTE
02929-044
0
SDA
Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode
Table 6. Serial Format of Data Accepted from the I2C Bus
S
0
1
0
1 1
AD1
AD
0
Slave Address Byte
R/
W
A
A/B
RS
S
D
O1
O2
X X X
Instruction Byte
A
D7
D6
D
5
D
4
D
3
D
2
D
1
Data Byte
where:
Abbreviation
S
P
A
X
AD1, AD0
R/W
A/B
RS
SD
O2, O1
D7, D6, D5, D4, D3, D2, D1, D0
Equals
Start condition
Stop condition
Acknowledge
Don’t care
Package pin programmable address bits
Read enable at high and write enable at low
RDAC subaddress select; 0 = RDAC1 and 1 = RDAC2
Midscale reset, active high (only affects selected channel)
Shutdown; same as SHDN pin operation except inverse logic (only affects selected channel)
Output logic pin latched values; default Logic 0
Data bits
Rev. C | Page 15 of 28
D
0
A
P
AD5280/AD5282
DIGITAL INTERFACE
2-WIRE SERIAL BUS
The AD5280/AD5282 are controlled via an I2C-compatible serial
bus. The RDACs are connected to this bus as slave devices. As
shown in Figure 45, Figure 46, and Table 6, the first byte of the
AD5280/AD5282 is a slave address byte. It has a 7-bit slave
address and an R/W bit.
The 5 MSBs are 01011, and the two bits that follow are determined by the state of the AD0 pin and the AD1 pin of the
device. AD0 and AD1 allow the user to place up to four of the
I2C-compatible devices on one bus. The 2-wire I2C serial bus
protocol operates as follows.
The master initiates data transfer by establishing a start condition, which happens when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 45). The following
byte is the slave address byte, which consists of the 7-bit slave
address followed by an R/W bit (this bit determines whether
data is read from or written to the slave device).
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits for
data to be written to or read from its serial register. If the R/W bit
is high, the master reads from the slave device. On the other
hand, if the R/W bit is low, the master writes to the slave device.
A write operation contains one instruction byte more than a
read operation. Such an instruction byte in write mode follows
the slave address byte. The most significant bit (MSB) of the
instruction byte labeled A/B is the RDAC subaddress select. A
low selects RDAC1 and a high selects RDAC2 for the dual
channel AD5282. Set A/B low for the AD5280.
RS, the second MSB, is the midscale reset. A logic high on this
bit moves the wiper of a selected channel to the center tap
where RWA = RWB. This feature effectively writes over the
contents of the register and thus, when taken out of reset mode,
the RDAC remains at midscale.
SD, the third MSB, is a shutdown bit. A logic high causes the
selected channel to open circuit at Terminal A while shorting
the wiper to Terminal B. This operation yields almost 0 Ω in
rheostat mode or 0 V in potentiometer mode. This SD bit serves
the same function as the SHDN pin except that the SHDN pin
reacts to active low. Also, the SHDN pin affects both channels
(AD5282) as opposed to the SD bit, which affects only the
channel that is being written to. Note that the shutdown
operation does not disturb the contents of the register. When
brought out of shutdown, the previous setting is applied to
the RDAC.
The following two bits are O1 and O2. They are extra programmable logic outputs that can be used to drive other digital loads,
logic gates, LED drivers, analog switches, and so on. The three
LSBs are don’t care bits (see Figure 45).
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 45).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, the transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 46).
When all data bits have been read or written, a stop condition is
established by the master. A stop condition is defined as a lowto-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the tenth clock
pulse to establish a stop condition (see Figure 45). In read
mode, the master issues a no acknowledge for the ninth clock
pulse (that is, the SDA line remains high). The master then
brings the SDA line low before the 10th clock pulse, which goes
high to establish a stop condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte updates
the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output
updates after these two bytes. If another byte is written to the
RDAC while it is still addressed to a specific slave device with the
same instruction, this byte updates the output of the selected slave
device. If different instructions are needed, the write mode has to
start with a new slave address, instruction, and data byte again.
Similarly, a repeated read function of RDAC is also allowed.
Rev. C | Page 16 of 28
AD5280/AD5282
READBACK RDAC VALUE
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5280/AD5282 feature additional programmable logic
outputs, O1 and O2, which can be used to drive a digital load,
analog switches, and logic gates. O1 and O2 default to Logic 0. The
logic states of O1 and O2 can be programmed in Frame 2 under
write mode (see Figure 45). These logic outputs have adequate
current driving capability to sink/source milliamperes of load.
In addition, shutdown can be implemented with the device
digital output as shown in Figure 47. In this configuration, the
device is shut down during power-up, but the user is allowed to
program the device at any preset levels. When it is done, the
user programs O1 high with the valid coding and the device
exits from shutdown and responds to the new setting. This selfcontained shutdown function allows absolute shutdown during
power-up, which is crucial in hazardous environments, without
adding extra components. Also, the sleep mode programming
feature during shutdown allows the AD5280/AD5282 to have a
programmable preset at any level, a solution that can be as
effective as using other high cost EEPROM devices. Because of
the extra power drawn on RPD, note that a high value should be
chosen for the RPD.
O1
SHDN
RPD
SDA
SCL
Users can also activate O1 and O2 in three ways without
affecting the wiper settings by programming as follows:
•
•
Figure 47. Shutdown by Internal Logic Output
Perform start, slave address, acknowledge, and instruction
bytes with O1 and O2 specified, acknowledge, stop.
Complete the write cycle with stop, then start, slave address
byte, acknowledge, instruction byte with O1 and O2
specified, acknowledge, stop.
Not complete the write cycle by not issuing the stop, then
start, slave address byte, acknowledge, instruction byte
with O1 and O2 specified, acknowledge, stop.
MULTIPLE DEVICES ON ONE BUS
Figure 48 shows four AD5282 devices on the same serial bus.
Each has a different slave address because the states of their Pin
AD0 and Pin AD1 are different. This allows each RDAC within
each device to be written to or read from independently. The
master device output bus line drivers are open-drain pulldowns in a fully I2C-compatible interface.
5V
RP
SELF-CONTAINED SHUTDOWN FUNCTION AND
PROGRAMMABLE PRESET
RP
SDA
MASTER
Shutdown can be activated by strobing the SHDN pin or
programming the SD bit in the write mode instruction byte.
As shown in Figure 44, when shutdown is asserted, the
AD5280/AD5282 open SWA to let the A terminal float and
short the W terminal to the B terminal. The AD5280/AD5282
consume negligible power during shutdown mode, resuming
the previous setting once the SHDN pin is released.
Rev. C | Page 17 of 28
SCL
SDA SCL
AD1
AD0
AD5282
5V
SDA SCL
AD1
AD0
AD5282
5V
SDA SCL
AD1
5V
SDA SCL
AD1
AD0
AD0
AD5282
AD5282
Figure 48. Multiple AD5282 Devices on One Bus
02929-047
•
02929-046
The AD5280/AD5282 allow the user to read back the RDAC
values in read mode. However, for the dual-channel AD5282,
the channel of interest is the one that is previously selected in
the write mode. When users need to read the RDAC values of
both channels in the AD5282, they can program the first
subaddress in write mode and then change to read mode to read
the first channel value. After that, they can change back to write
mode with the second subaddress and read the second channel
value in read mode again. It is not necessary for users to issue
the Frame 3 data byte in write mode for subsequent readback
operation. Users should refer to Figure 45 and Figure 46 for the
programming format.
AD5280/AD5282
LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE
VDD
While most old systems can be operated at one voltage, a new
component can be optimized at another. When two systems
operate the same signal at two different voltages, proper level
shifting is needed. For instance, a 3.3 V EEPROM can interface
with a 5 V digital potentiometer. A level-shift scheme is needed
to enable a bidirectional communication so that the setting of
the digital potentiometer can be stored to and retrieved from
the EEPROM. Figure 49 shows one of the implementations.
M1 and M2 can be any N-channel signal FETs or low threshold
FDV301N if VDD falls below 2.5 V.
0
S
SDA1
RP
G
RP
D
G
S
SCL1
D
SCL2
M2
3.3V
EEPROM
5V
AD5282
Q2
R3
10kΩ
VOUT
0
–5V
VSS = –5V
02929-050
R2
10kΩ
Figure 51. Level Shift for Bipolar Potential Operation
ESD PROTECTION
SDA2
M1
0
0
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures, as shown in Figure 52. The
protection applies to digital inputs SDA, SCL, and SHDN.
02929-048
RP
Q3
Q1
VDD2 = 5V
RP
VIN
340Ω
LOGIC
Figure 49. Level Shift for Different Potential Operation
LEVEL SHIFT FOR NEGATIVE VOLTAGE
OPERATION
02929-051
VDD1 = 3.3V
+5V
VSS
Figure 52. ESD Protection of Digital Pins
The digital potentiometer is popular in laser diode driver
applications and certain telecommunications equipment levelsetting applications. These applications are sometimes
operated between ground and a negative supply voltage such
that the systems can be biased at ground to avoid large bypass
capacitors that may significantly impede the ac performance.
Like most digital potentiometers, the AD5280/AD5282 can be
configured with a negative supply (see Figure 50).
TERMINAL VOLTAGE OPERATING RANGE
The AD5280/AD5282 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on
Resistor Terminal A, Resistor Terminal B, and Wiper Terminal
W that exceed VDD or VSS are clamped by the internal forwardbiased diodes (see Figure 53).
A
W
B
VSS
GND
LEVEL SHIFTED
SDA
LEVEL SHIFTED
SCL
VSS
Figure 53. Maximum Terminal Voltages Set by VDD and VSS
02929-049
–5V
02929-053
VDD
VDD
Figure 50. Biased at Negative Voltage
POWER-UP SEQUENCE
However, the digital inputs must also be level shifted to allow
proper operation because the ground is referenced to the
negative potential. Figure 51 shows one implementation with a
few transistors and a few resistors. When VIN is below the Q3
threshold value, Q3 is off, Q1 is off, and Q2 is on. In this state,
VOUT approaches 0 V. When VIN is above 2 V, Q3 is on, Q1 is on,
and Q2 is turned off. In this state, VOUT is pulled down to VSS.
Be aware that proper time shifting is also needed for successful
communication with the device.
Because there are ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W (see
Figure 53), it is important to power VDD/VSS before applying any
voltage to the A, B, and W terminals. Otherwise, the diode is
forward biased such that VDD/VSS is unintentionally powered,
which may affect the rest of the user’s circuit. The ideal powerup sequence is the following: GND, VDD, VSS, digital inputs, and
VA/VB/VW. The order of powering VA/VB/VW and digital inputs
is not important as long as they are powered after VDD/VSS.
Rev. C | Page 18 of 28
AD5280/AD5282
LAYOUT AND POWER SUPPLY BYPASSING
VDD
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and filter low frequency
ripple (see Figure 54). Notice that the digital ground should also
be joined remotely to the analog ground at one point to
minimize digital ground bounce.
Rev. C | Page 19 of 28
C3
10µF
+
C4
10µF
VSS
+
VDD
C1
0.1µF
AD5280/
AD5282
C2
0.1µF
VSS
GND
02929-054
It is a good practice to design a layout with compact, minimum
lead lengths. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Figure 54. Power Supply Bypassing
AD5280/AD5282
APPLICATIONS INFORMATION
BIPOLAR DC OR AC OPERATION FROM DUAL
SUPPLIES
The AD5280/AD5282 can be operated from dual supplies
enabling control of ground-referenced ac signals or bipolar
operation. The ac signal, as high as VDD/VSS, can be applied
directly across Terminal A to Terminal B with the output taken
from Terminal W. See Figure 55 for a typical circuit connection.
+5.0V
SCL
A1
SDA
W1
±2.5V p-p
±5V p-p
B1
D–80 H
AD5282
GND
Similarly, there are W and A terminal capacitances connected to
the output (not shown); fortunately, their effect at this node is less
significant and the compensation can be avoided in most cases.
A2
W2
15 V, 8-BIT I2C DAC
VDD
02929-055
B2
VSS
–5.0V
VDD
RBIAS
Figure 55. Bipolar Operation from Dual Supplies
U1A
GAIN CONTROL COMPENSATION
V+
The digital potentiometer is commonly used in gain control
applications such as the noninverting gain amplifier shown in
Figure 56.
B
200kΩ
ADR512
AD8512
D1
U2
AD5280
200kΩ
V–
B
A
U1B
AD8512
VO
R2
W
R1
02929-057
VDD
SCLK
MICROCONTROLLER
MOSI
GND
Depending on the op amp GBP, reducing the feedback resistor
may extend the zero’s frequency far enough to overcome the
problem. A better approach is to include a compensation
capacitor C2 to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not
an option unless C2 is scaled as if R2 were at its maximum
value. Doing so may overcompensate and compromise the
performance slightly when R2 is set at low values. However, it
avoids the gain peaking, ringing, or oscillation at the worst case.
For critical applications, C2 should be found empirically to suit
the need. In general, C2 in the range of a few picofarads (pF) to
no more than a few tenths of a picofarad is usually adequate for
the compensation.
C2
4.7pF
Figure 57. 8-Bit I2C DAC
47kΩ
C1
25pF
VI
U1
AD5280/AD5282 can be configured as a high voltage DAC, as
high as 15 V. The output is
VO
02929-056
R1
VO ( D ) =
Figure 56. Typical Noninverting Gain Amplifier
Notice that the RDAC B terminal parasitic capacitance is
connected to the op amp noninverting node. It introduces a 0
for the 1/βO term with 20 dB/decade (dec), whereas a typical op
amp GBP has −20 dB/dec characteristics. A large R2 and finite
C1 can cause the 0 frequency to fall well below the crossover
frequency. Thus the rate of closure becomes 40 dB/dec, and the
system has a 0° phase margin at the crossover frequency. The
output may ring or oscillate if the input is a rectangular pulse or
step function. Similarly, it is also likely to ring when switching
between two gain values because this is equivalent to a step
change at the input.
Rev. C | Page 20 of 28
D
R
[1.2V × (1 + 2 )]
R1
256
(5)
AD5280/AD5282
8-BIT BIPOLAR DAC
+15V
U2
OP2177
W
U1
VIN
B
GND
TRIM
A
R
R
–15V
–5VREF
+15V
+5VREF
VO
A2
–
ADR425
If R2 is large, a compensation capacitor having a few pF may be
needed to avoid any gain peaking.
OP2177
+
U2 – AD5280
A1
–15V
02929-058
VOUT
–
Figure 58. 8-Bit Bipolar DAC
Figure 58 shows a low cost, 8-bit, bipolar DAC. It offers the same
number of adjustable steps but not the precision of conventional
DACs. The linearity and temperature coefficients, especially at
low value codes, are skewed by the effects of the digital potentiometer wiper resistance. The output of this circuit is
2D
VO = ⎛⎜
− 1⎞⎟ × VREF
⎝ 256 ⎠
(6)
BIPOLAR PROGRAMMABLE GAIN AMPLIFIER
VDD
+
W2
A2
A1
V1
AD5282
+
V+
VDD
VO
V–
A2
B1
W1
U1
–
D
R1 = ∞, R2 = 0
R1 = R2
R2 = 9R1
0
64
128
192
255
−1
−0.5
0
0.5
0.968
−2
−1
0
1
1.937
−10
−5
0
5
9.680
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
OP2177
B2
Table 7. Result of Bipolar Gain Amplifier
C1
For applications that require high current adjustments, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 60).
R2
VS8 A2
–kVI
R1
VI
5V
V+
VO
N1
OP2177
–
A1
V–
VS8
02929-059
U2
AD5282
Table 7 shows the result of adjusting D, with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and a 256-step
resolution.
U1
Figure 59. Bipolar Programmable Gain Amplifier
where K is the ratio of RWB1/RWA1 set by U1.
(7)
RBIAS
IL
SIGNAL
+
B
V+
A1
–
For applications that require bipolar gain, Figure 59 shows one
implementation similar to the previous circuit. The digital
potentiometer, U1, sets the adjustment range. The wiper voltage
at W2 can therefore be programmed between Vi and –KVi at a
given U2 setting. Configuring A2 in noninverting mode allows
linear gain and attenuation. The transfer function is
VO ⎛
R2 ⎞ ⎛ D2
⎞
= ⎜1 +
× (1 + K ) − K ⎟
⎟×⎜
Vi ⎝
R1 ⎠ ⎝ 256
⎠
A W
CC
LD
V–
U1 = AD5280
A1 = AD8501, AD8605, AD8541
N1 = FDV301N, 2N7002
02929-060
V1
As in the previous example, in the simpler and more common
case where K = 1, a single digital AD5280 potentiometer is
used. U1 is replaced by a matched pair of resistors to apply
Vi and −Vi at the ends of the digital potentiometer. The
relationship becomes
R2 ⎞⎛ 2 D2 ⎞
⎛
(7)
VO = ⎜ 1 +
− 1⎟ × Vi
⎟⎜
R1 ⎠⎝ 256
⎝
⎠
+
Figure 60. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the
VBIAS to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the
N-channel FET N1. The N1 power handling must be adequate
to dissipate (Vi – VO) × IL power. This circuit can source a
maximum of 100 mA with a 5 V supply. A1 needs to be a railto-rail input type. For precision applications, a voltage reference
such as ADR423, ADR292, or AD1584 can be applied at the
input of the digital potentiometer.
Rev. C | Page 21 of 28
AD5280/AD5282
PROGRAMMABLE CURRENT SOURCE
PROGRAMMABLE BIDIRECTIONAL CURRENT
SOURCE
+5V
SLEEP
VOUT 6
REF191
GND
0 TO (2.048 + VL)
B
C1
1µF
+15V
W
+5V
–2.048V TO VL
C1
10pF
V+
RS
102Ω
A
4
AD5280
R2I
15kΩ
+5V
OP2177
V–
+15V
A2
A
V+
AD5280
OP8510
OP8510
U2
U2
V–
5V
W
VL
RL
100Ω
IL
V+
OP2177
V–
–5V
R2B
50kΩ
–15V
R1
150kΩ
A1
R2A
14.95kΩ
VL
RL
500kΩ
–15V
|L
Figure 61. Programmable Current Source
02929-062
VIN
02929-061
3
R1I
150kΩ
U1
2
Figure 62. Programmable Bidirectional Current Source
A programmable current source can be implemented with the
circuit shown in Figure 61. REF191 is a unique, low supply
headroom and high current handling precision reference that
can deliver 20 mA at 2.048 V. The load current is simply the
voltage across Terminal B to Terminal W of the digital
potentiometer divided by RS.
IL =
VREF × D
RS × 2N
For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution (see Figure 62). If the resistors are matched, the load
current is
(R2 A + R2B )
IL =
(8)
The circuit is simple, but attention must be paid to two things.
First, dual-supply op amps are ideal because the ground
potential of REF191 can swing from −2.048 V at zero scale to VL
at full scale of the potentiometer setting. Although the circuit
works under single supply, the programmable resolution of the
system is reduced.
For applications that demand higher current capabilities, a
few changes to the circuit in Figure 61 produce an adjustable
current in the range of hundreds of milliamps. First, the voltage
reference needs to be replaced with a high current, low dropout
regulator, such as the ADP3333, and the op amp needs to be
swapped with a high current dual-supply model, such as the
AD8532. Depending on the desired range of current, an
appropriate value for RS must be calculated. Because of the high
current flowing to the load, the user must pay attention to the
load impedance so as not to drive the op amp beyond the
positive rail.
R1
R2B
× VW
(9)
In theory, R2B can be made as small as needed to achieve the
current needed within the A2 output current driving capability.
In this circuit, the OP2177 can deliver ±5 mA in either direction,
and the voltage compliance approaches 15 V. It can be shown
that the output impedance is
R1' ×R2B (R1 + R2A )
(10)
ZO =
R1× R2' − R1' (R2A + R2B )
This output impedance can be infinite if Resistor R1' and
Resistor R2' match precisely with R1 and R2A + R2B,
respectively. On the other hand, it can be negative if the
resistors are not matched. As a result, C1 must be in the range
of 1 pF to 10 pF to prevent the oscillation.
Rev. C | Page 22 of 28
AD5280/AD5282
PROGRAMMABLE LOW-PASS FILTER
1
ωO =
R1R2C1C2
(12)
1
1
+
R1C1 R2C2
(13)
Q=
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, R1 and R2 can be
adjusted to the same settings to achieve the desirable bandwidth.
At resonance, setting the following balances the bridge:
R2
=2
R1
Once the frequency is set, the oscillation amplitude can be
tuned by R2B because
2
(17)
VO = I D R2B + V D
3
VO, ID, and VD are interdependent variables. With proper
selection of R2B, an equilibrium is reached such that VO
converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be
too large to prevent saturation of the output.
FREQUENCY
ADJUSTMENT
C1
CI
VP 2.2nF
C
A
B
A
R2
W
R
B
V+
R
10kΩ
A
VO
W
C
–2.5V
OP1177
U1
ADJUSTED TO
SAME SETTING
R1 = R1I = R2B = AD5282
D1 = D2 = 1N4148
VN
Figure 63. Sallen Key Low-Pass Filter
PROGRAMMABLE OSCILLATOR
R1
1kΩ
In a classic Wien-bridge oscillator (Figure 64), the Wien
network (R, R', C, C') provides positive feedback, while R1
and R2 provide negative feedback. At the resonant frequency, fO,
the overall phase shift is 0, and the positive feedback causes the
circuit to oscillate. With R = R', C = C', and R2 = R2A//(R2B +
Rdiode), the oscillation frequency is
ωO =
1
1
or f o =
RC
2πRC
(14)
where R is equal to RWA such that
R=
256 − D
RAB
256
A
W
+2.5V
V+
V–
R
C2
C
2.2nF
AD8601
W
RI
10kΩ
B
+2.5V
02929-063
VI
R1
(16)
In practice, R2/R1 should be set slightly larger than 2 to ensure
that oscillation can start. On the other hand, the alternate turnon of Diode D1 and Diode D2 ensures that R2/R1 are smaller
than 2 momentarily and, therefore, stabilizes the oscillation.
(15)
Rev. C | Page 23 of 28
B
U1
VO
V–
–2.5V
R2A
R2B 2.1kΩ
10kΩ
D1
A
D2
B
W
AMPLITUDE
ADJUSTMENT
02929-064
In analog-to-digital conversion applications, it is common to
include an antialiasing filter to band-limit the sampling signal.
Dual-channel digital potentiometers can be used to construct
a second-order Sallen key low-pass filter (see Figure 63). The
design equations are
VO
ωO 2
(11)
=
ω
Vi
S 2 + O S + ωO 2
Q
Figure 64. Programmable Oscillator with Amplitude Control
AD5280/AD5282
RDAC CIRCUIT SIMULATION MODEL
MACRO MODEL NET LIST FOR RDAC
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5280
(20 kΩ resistor) measures 310 kHz at half scale. Figure 24
provides the Bode plot characteristics of the three available
resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic
simulation model is shown in Figure 65. A macro model net list
for the 20 kΩ RDAC is provided.
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA
A
0
RWA
A
W
CW
W
0
RWB
W
B
CB
B
0
*
.ENDS DPOT
RDAC
20kΩ
A
B
CA
25pF
CW
85pF
02929-068
CA
25pF
Figure 65. RDAC Circuit Simulation Model for RDAC = 20 kΩ
Rev. C | Page 24 of 28
25E-12
{(1-D/256)*RDAC+60}
55E-12
{D/256*RDAC+60}
25E-12
AD5280/AD5282
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
0.30
0.19
8°
0°
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 66. 14-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 67. 16-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-16)
Dimensions shown in millimeters
Rev. C | Page 25 of 28
0.75
0.60
0.45
AD5280/AD5282
ORDERING GUIDE
Model 1
AD5280BRU20
AD5280BRU20-REEL7
AD5280BRU50
AD5280BRU50-REEL7
AD5280BRU200-REEL7
AD5280BRUZ20 2
AD5280BRUZ20-REEL72
AD5280BRUZ502
AD5280BRUZ50-REEL72
AD5280BRUZ2002
AD5280BRUZ200-R72
AD5282BRU20
AD5282BRU20-REEL7
AD5282BRU50
AD5282BRU50-REEL7
AD5282BRU200
AD5282BRU200-REEL7
AD5282BRUZ202
AD5282BRUZ20-REEL72
AD5282BRUZ502
AD5282BRUZ50-REEL72
AD5282BRUZ2002
AD5282BRUZ200-R72
AD5282-EVAL
1
2
No. of
Channels
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
RAB (kΩ)
20
20
50
50
200
20
20
50
50
200
200
20
20
50
50
200
200
20
20
50
50
200
200
20
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Package
Option
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
Line 1 contains model number, Line 2 contains ADI logo followed by the end-to-end resistance value, and Line 3 contains date code YYWW.
Z = RoHS Compliant Part.
Rev. C | Page 26 of 28
Ordering Quantity
96
1,000
96
1,000
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
96
1,000
AD5280/AD5282
NOTES
Rev. C | Page 27 of 28
AD5280/AD5282
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02929-0-7/09(C)
Rev. C | Page 28 of 28