a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz A OUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability 3.3 V or 5 V Single-Supply Operation Low Power: 380 mW @ 125 MHz (5 V) Low Power: 155 mW @ 110 MHz (3.3 V) Power-Down Function Ultrasmall 28-Lead SSOP Packaging APPLICATIONS Frequency/Phase—Agile Sine Wave Synthesis Clock Recovery and Locking Circuitry for Digital Communications Digitally Controlled ADC Encode Generator Agile Local Oscillator Applications GENERAL DESCRIPTION The AD9850 is a highly integrated device that uses advanced DDS technology coupled with an internal high speed, high performance D/A converter and comparator to form a complete, digitally programmable frequency synthesizer and clock generator function. When referenced to an accurate clock source, the AD9850 generates a spectrally pure, frequency/phase programmable, analog output sine wave. This sine wave can be used directly as a frequency source, or it can be converted to a square wave for agile-clock generator applications. The AD9850’s innovative high speed DDS core provides a 32-bit frequency tuning word, which results in an output tuning resolution of 0.0291 Hz for a 125 MHz reference clock input. The AD9850’s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62.5 MHz), and the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second. The device also provides five bits of digitally controlled phase modulation, which enables phase shifting of its output in increments of 180°, 90°, 45°, 22.5°, CMOS, 125 MHz Complete DDS Synthesizer AD9850 FUNCTIONAL BLOCK DIAGRAM +VS DAC RSET REF CLOCK IN HIGH SPEED DDS MASTER RESET 32-BIT TUNING WORD FREQUENCY UPDATE/ DATA REGISTER RESET WORD LOAD CLOCK GND 10-BIT DAC PHASE AND CONTROL WORDS ANALOG OUT ANALOG IN FREQUENCY/PHASE DATA REGISTER CLOCK OUT CLOCK OUT DATA INPUT REGISTER SERIAL LOAD COMPARATOR PARALLEL LOAD AD9850 1-BIT 40 LOADS 8-BITS 5 LOADS FREQUENCY, PHASE, AND CONTROL DATA INPUT 11.25°, and any combination thereof. The AD9850 also contains a high speed comparator that can be configured to accept the (externally) filtered output of the DAC to generate a low jitter square wave output. This facilitates the device’s use as an agile clock generator function. The frequency tuning, control, and phase modulation words are loaded into the AD9850 via a parallel byte or serial loading format. The parallel load format consists of five iterative loads of an 8-bit control word (byte). The first byte controls phase modulation, power-down enable, and loading format; Bytes 2 to 5 comprise the 32-bit frequency tuning word. Serial loading is accomplished via a 40-bit serial data stream on a single pin. The AD9850 Complete DDS uses advanced CMOS technology to provide this breakthrough level of functionality and performance on just 155 mW of power dissipation (3.3 V supply). The AD9850 is available in a space-saving 28-lead SSOP, surface-mount package. It is specified to operate over the extended industrial temperature range of –40°C to +85°C. REV. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. AD9850–SPECIFICATIONS (V = 5 V ⴞ 5% except as noted, R S Parameter SET = 3.9 k⍀) Temp Test Level Min Full Full IV IV 1 1 25°C 25°C IV IV 3.2 4.1 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C V V I V I V I I V IV IV I 25°C 25°C 25°C IV IV IV 25°C 25°C 25°C 25°C IV IV IV IV COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Input Voltage Range Comparator Offset* 25°C 25°C 25°C 25°C Full V IV I IV VI COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage 5 V Supply Logic 1 Voltage 3.3 V Supply Logic 0 Voltage Propagation Delay, 5 V Supply (15 pF Load) Propagation Delay, 3.3 V Supply (15 pF Load) Rise/Fall Time, 5 V Supply (15 pF Load) Rise/Fall Time, 3.3 V Supply (15 pF Load) Output Jitter (p-p) Full Full Full 25°C 25°C 25°C 25°C 25°C VI VI VI V V V V V CLOCK OUTPUT CHARACTERISTICS Clock Output Duty Cycle (Clk Gen. Config.) 25°C IV CLOCK INPUT CHARACTERISTICS Frequency Range 5 V Supply 3.3 V Supply Pulse Width High/Low 5 V Supply 3.3 V Supply DAC OUTPUT CHARACTERISTICS Full-Scale Output Current RSET = 3.9 kΩ RSET = 1.95 kΩ Gain Error Gain Temperature Coefficient Output Offset Output Offset Temperature Coefficient Differential Nonlinearity Integral Nonlinearity Output Slew Rate (50 Ω, 2 pF Load) Output Impedance Output Capacitance Voltage Compliance Spurious-Free Dynamic Range (SFDR) Wideband (Nyquist Bandwidth) 1 MHz Analog Out 20 MHz Analog Out 40 MHz Analog Out Narrowband 40.13579 MHz ± 50 kHz 40.13579 MHz ± 200 kHz 4.513579 MHz ± 50 kHz/20.5 MHz CLK 4.513579 MHz ± 200 kHz/20.5 MHz CLK –2– AD9850BRS Typ Max 125 110 –10 +10 150 10 50 0.5 0.5 400 120 0.75 1 8 1.5 63 50 46 MHz MHz ns ns 10.24 20.48 50 Unit mA mA % FS ppm/°C µA nA/°C LSB LSB V/µs kΩ pF V 72 58 54 dBc dBc dBc 80 77 84 84 dBc dBc dBc dBc 3 pF kΩ µA V mV 500 –12 0 30 +12 VDD 30 4.8 3.1 5.5 7 3 3.5 80 V V V ns ns ns ns ps 50 ± 10 % 0.4 REV. H AD9850 AD9850BRS Min Typ Max Parameter Temp Test Level CMOS LOGIC INPUTS (Including CLKIN) Logic 1 Voltage, 5 V Supply Logic 1 Voltage, 3.3 V Supply Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance 25°C 25°C 25°C 25°C 25°C 25°C I IV IV I I V Full Full Full Full VI VI VI VI 30 47 44 76 48 60 64 96 mA mA mA mA Full Full Full Full VI VI VI VI 100 155 220 380 160 200 320 480 mW mW mW mW Full Full V V 30 10 POWER SUPPLY (AOUT = 1/3 CLKIN) +VS Current @ 62.5 MHz Clock, 3.3 V Supply 110 MHz Clock, 3.3 V Supply 62.5 MHz Clock, 5 V Supply 125 MHz Clock, 5 V Supply PDISS @ 62.5 MHz Clock, 3.3 V Supply 110 MHz Clock, 3.3 V Supply 62.5 MHz Clock, 5 V Supply 125 MHz Clock, 5 V Supply PDISS Power-Down Mode 5 V Supply 3.3 V Supply 3.5 2.4 0.8 12 12 3 Unit V V V µA µA pF mW mW *Tested by measuring output duty cycle variation. Specifications subject to change without notice. TIMING CHARACTERISTICS*(V = 5 V ⴞ 5% except as noted, R S Parameter tDS tDH tWH tWL tWD tCD tFH tFL tCF tFD tRH tRL tRS tOL tRR (Data Setup Time) (Data Hold Time) (W_CLK Minimum Pulse Width High) (W_CLK Minimum Pulse Width Low) (W_CLK Delay after FQ_UD) (CLKIN Delay after FQ_UD) (FQ_UD High) (FQ_UD Low) (Output Latency from FQ_UD) Frequency Change Phase Change (FQ_UD Minimum Delay after W_CLK) (CLKIN Delay after RESET Rising Edge) (RESET Falling Edge after CLKIN) (Minimum RESET Width) (RESET Output Latency) (Recovery from RESET) Wake-Up Time from Power-Down Mode SET Temp Test Level AD9850BRS Min Typ Max Unit Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV 3.5 3.5 3.5 3.5 7.0 3.5 7.0 7.0 ns ns ns ns ns ns ns ns Full Full Full Full Full Full Full Full 25°C IV IV IV IV IV IV IV IV V 18 13 7.0 3.5 3.5 5 13 2 CLKIN Cycles CLKIN Cycles ns ns ns CLKIN Cycles CLKIN Cycles CLKIN Cycles µs *Control functions are asynchronous with CLKIN. Specifications subject to change without notice. REV. H = 3.9 k⍀) –3– 5 AD9850 ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS Digital Output Continuous Current . . . . . . . . . . . . . . . 5 mA DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C SSOP θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 82°C/W Test Level I 100% Production Tested. III Sample Tested Only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI All devices are 100% production tested at 25°C. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices. *Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9850 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE Application Note: Users are cautioned not to apply digital input signals prior to power-up of this device. Doing so may result in a latch-up condition. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9850BRS AD9850BRS-REEL AD9850BRSZ* AD9850BRSZ-REEL* AD9850/CGPCB AD9850/FSPCB –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Shrink Small Outline Package (SSOP) Shrink Small Outline Package (SSOP) Shrink Small Outline Package (SSOP) Shrink Small Outline Package (SSOP) Evaluation Board Clock Generator Evaluation Board Frequency Synthesizer RS-28 RS-28 RS-28 RS-28 *Z = Pb-free part. –4– REV. H AD9850 PIN CONFIGURATION D3 1 28 D4 D2 2 27 D5 D1 3 26 D6 LSB D0 4 25 D7 MSB/SERIAL LOAD DGND 5 24 DGND DVDD 6 W CLK 7 FQ UD 8 (Not to Scale) 21 IOUT 23 DVDD AD9850 TOP VIEW 22 RESET 9 20 IOUTB AGND 10 19 AGND AVDD 11 18 AVDD CLKIN RSET 12 17 DACBL (NC) QOUTB 13 16 VINP QOUT 14 15 VINN NC = NO CONNECT Table I. PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 4 to 1, 28 to 25 D0 to D7 8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/ control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data-word. 5, 24 DGND Digital Ground. These are the ground return leads for the digital circuitry. 6, 23 DVDD Supply Voltage Leads for Digital Circuitry. 7 W_CLK Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words. 8 FQ_UD Frequency Update. On the rising edge of this clock, the DDS updates to the frequency (or phase) loaded in the data input register; it then resets the pointer to Word 0. 9 CLKIN Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at 1/2 V supply. The rising edge of this clock initiates operation. 10, 19 AGND Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator). 11, 18 AVDD Supply Voltage for the Analog Circuitry (DAC and Comparator). 12 RSET DAC’s External RSET Connection. This resistor value sets the DAC full-scale output current. For normal applications (FS IOUT = 10 mA), the value for RSET is 3.9 kΩ connected to ground. The RSET/IOUT relationship is IOUT = 32 (1.248 V/RSET). 13 QOUTB Output Complement. This is the comparator’s complement output. 14 QOUT Output True. This is the comparator’s true output. 15 VINN Inverting Voltage Input. This is the comparator’s negative input. 16 VINP Noninverting Voltage Input. This is the comparator’s positive input. 17 DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should normally be considered a no connect for optimum performance. 20 IOUTB Complementary Analog Output of the DAC. 21 IOUT Analog Current Output of the DAC. 22 RESET Reset. This is the master reset function; when set high, it clears all registers (except the input register), and the DAC output goes to cosine 0 after additional clock cycles—see Figure 7. REV. H –5– AD9850–Typical Performance Characteristics Spectrum CH1 S AD9850 10dB/REF –8.6dBm CH1 S 76.642 dB CLOCK 125MHz Fxd Spectrum 10dB/REF –10dBm 59.925 dB CLOCK 125MHz AD9850 Fxd 0 0 RBW # 100Hz START 0Hz VBW 100Hz RBW # 300Hz START 0Hz ATN # 30dB SWP 762 sec STOP 62.5MHz VBW 300Hz ATN # 30dB SWP 182.6 sec STOP 62.5MHz TPC 1. SFDR, CLKIN = 125 MHz/fOUT = 1 MHz TPC 4. SFDR, CLKIN = 125 MHz/fOUT = 20 MHz CH1 S CH1 S Spectrum AD9850 10dB/REF –10dBm 54.818 dB Fxd CLOCK 125MHz Spectrum 12dB/REF 0dBm –85.401 dB –23 kHz AD9850 Mkr 0 0 RBW # 300Hz START 0Hz VBW 300Hz ATN # 30dB RBW # 3Hz VBW 3Hz CENTER 4.513579MHz SWP 182.6 sec STOP 62.5MHz ATN # 20dB SWP 399.5 sec SPAN 400kHz TPC 5. SFDR, CLKIN = 20.5 MHz/fOUT = 4.5 MHz TPC 2. SFDR, CLKIN = 125 MHz/fOUT = 41 MHz Tek Run: 100GS/s ET Sample –105 PN.3RD –110 : 300ps @: 25.26ns –115 –120 dBc –125 –130 –135 –140 –145 –150 1 Ch 1 500mV⍀ M 20.0ns D 500ps –155 100 Ch 1 1.58V Runs After TPC 3. Typical Comparator Output Jitter, AD9850 Configured as Clock Generator with 42 MHz LP Filter (40 MHz AOUT/125 MHz CLKIN) 10k 1k OFFSET FROM 5MHz CARRIER – Hz 100k TPC 6. Output Residual Phase Noise (5 MHz AOUT/125 MHz CLKIN) –6– REV. H AD9850 Tek Run: 50.0GS/s ET Average Tek Run: 50.0GS/s ET Average Ch 1 Rise 2.870ns Ch 1 Fall 3.202ns 1 1 Ch1 1.00V⍀ M 1.00ns Ch 1 1.74V Ch1 1.00V⍀ TPC 7. Comparator Output Rise Time (5 V Supply/15 pF Load) M 1.00ns Ch 1 1.74V TPC 10. Comparator Output Fall Time (5 V Supply/15 pF Load) 68 90 fOUT = 1/3 OF CLKIN 80 64 70 SUPPLY CURRENT – mA 66 SFDR – dB 62 60 58 VCC = 5V 56 VCC = 3.3V 54 52 0 20 40 60 80 CLKIN – MHz 100 120 50 40 VCC = 3.3V 30 10 140 0 20 40 60 80 100 CLOCK FREQUENCY – MHz 120 140 TPC 11. Supply Current vs. CLKIN Frequency (AOUT = 1/3 of CLKIN) 75 90 fOUT = 1MHz 70 80 VCC = 5V 65 70 SFDR – dB SUPPLY CURRENT – mA VCC = 5V 20 TPC 8. SFDR vs. CLKIN Frequency (AOUT = 1/3 of CLKIN) 60 50 30 60 fOUT = 20MHz 55 VCC = 3.3V fOUT = 40MHz 50 40 45 0 10 20 30 FREQUENCY OUT – MHz 40 TPC 9. Supply Current vs. AOUT Frequency (CLKIN = 125/110 MHz for 5 V/3.3 V Plot) REV. H 60 5 10 15 DAC IOUT – mA 20 TPC 12. SFDR vs. DAC IOUT (AOUT = 1/3 of CLKIN) –7– AD9850 +VS IF FREQUENCY IN 5-POLE ELLIPTICAL 42MHz LOW-PASS 200⍀ IMPEDANCE GND LOW-PASS FILTER IOUT 200⍀ 100k⍀ 8-b ⴛ 5 PARALLEL DATA, DATA OR 1-b ⴛ 40 SERIAL DATA, 470pF PROCESSOR BUS RESET, AND 2 CLOCK LINES 100k⍀ 100⍀ AD9850 IOUTB VINN XTAL CLK VINP OSC QOUT CMOS QOUTB CLOCK OUTPUTS RSET COMP FILTER 125MHz AD9850 COMPLETE DDS Rx IF IN 3a. Frequency/Phase–Agile Local Oscillator 200⍀ 125MHz REFERENCE CLOCK TRUE VCA ADC CLOCK FREQUENCY LOCKED TO Tx CHIP/ SYMBOL PN RATE 125MHz REFERENCE CLOCK AD9850 COMPLETE DDS FILTER PHASE COMPARATOR LOOP FILTER RF FREQUENCY OUT VCO DIVIDE-BY-N TUNING WORD 3b. Frequency/Phase–Agile Reference for PLL REF FREQUENCY Rx BASEBAND DIGITAL DATA OUT DIGITAL DEMODULATOR TUNING WORD REFERENCE Figure 1. Basic AD9850 Clock Generator Application with Low-Pass Filter I 8 I/Q MIXER AD9059 AND LOW-PASS Q DUAL 8-BIT 8 ADC FILTER RF FREQUENCY OUT FILTER PHASE COMPARATOR VCO PROGRAMMABLE DIVIDE-BY-N FUNCTION FILTER AGC LOOP FILTER RF FREQUENCY OUT AD9850 ADC ENCODE COMPLETE DDS AD9850 32 CLOCK GENERATOR CHIP/SYMBOL/PN RATE DATA TUNING WORD 3c. Digitally-Programmable Divide-by-N Function in PLL Figure 2. AD9850 Clock Generator Application in a Spread-Spectrum Receiver Figure 3. AD9850 Complete DDS Synthesizer in Frequency Up-Conversion Applications The frequency tuning word sets the modulus of the counter, which effectively determines the size of the increment (∆ Phase) that is added to the value in the phase accumulator on the next clock pulse. The larger the added increment, the faster the accumulator overflows, which results in a higher output frequency. The AD9850 uses an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate COS value. This unique algorithm uses a much reduced ROM look-up table and DSP techniques to perform this function, which contributes to the small size and low power dissipation of the AD9850. The relationship of the output frequency, reference clock, and tuning word of the AD9850 is determined by the formula THEORY OF OPERATION AND APPLICATION The AD9850 uses direct digital synthesis (DDS) technology, in the form of a numerically controlled oscillator, to generate a frequency/ phase-agile sine wave. The digital sine wave is converted to analog form via an internal 10-bit high speed D/A converter, and an on-board high speed comparator is provided to translate the analog sine wave into a low jitter TTL/CMOS compatible output square wave. DDS technology is an innovative circuit architecture that allows fast and precise manipulation of its output frequency under full digital control. DDS also enables very high resolution in the incremental selection of output frequency; the AD9850 allows an output frequency resolution of 0.0291 Hz with a 125 MHz reference clock applied. The AD9850’s output waveform is phase continuous when changed. fOUT = (∆ Phase × CLKIN)/232 The basic functional block diagram and signal flow of the AD9850 configured as a clock generator is shown in Figure 4. where: ∆ Phase is the value of the 32-bit tuning word. CLKIN is the input reference clock frequency in MHz. fOUT is the frequency of the output signal in MHz. The DDS circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock divided by the 2N number of bits in the tuning word. The phase accumulator is a variable-modulus counter that increments the number stored in it each time it receives a clock pulse. When the counter overflows, it wraps around, making the phase accumulator’s output contiguous. The digital sine wave output of the DDS block drives the internal high speed 10-bit D/A converter that reconstructs the sine wave in analog form. This DAC has been optimized for dynamic performance and low glitch energy as manifested in the low jitter performance of the AD9850. Because the output of the –8– REV. H AD9850 REF CLOCK DDS CIRCUITRY N PHASE ACCUMULATOR AMPLITUDE/COS CONV. ALGORITHM D/A CONVERTER LP COMPARATOR CLK OUT TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REF CLOCK FREQUENCY COS (x) IN DIGITAL DOMAIN Figure 4. Basic DDS Block Diagram and Signal Flow of AD9850 AD9850 is a sampled signal, its output spectrum follows the Nyquist sampling theorem. Specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the reference clock frequency ± the selected output frequency. A graphical representation of the sampled spectrum, with aliased images, is shown in Figure 5. SIGNAL AMPLITUDE fOUT sin(x)/x ENVELOPE x=()fo/fc fc – fo fc + fo 2fc – fo fc 2fc + fo 3fc – fo and automatically places itself in the power-down mode. When in this state, if the clock frequency again exceeds the threshold, the device resumes normal operation. This shutdown mode prevents excessive current leakage in the dynamic registers of the device. The D/A converter output and comparator inputs are available as differential signals that can be flexibly configured in any manner desired to achieve the objectives of the end system. The typical application of the AD9850 is with single-ended output/ input analog signals, a single low-pass filter, and the generation of the comparator reference midpoint from the differential DAC output as shown in Figure 1. Programming the AD9850 120MHz 20MHz 80MHz 2ND IMAGE FUNDAMENTAL 1ST IMAGE 100MHz REFERENCE CLOCK FREQUENCY 180MHz 3RD IMAGE 220MHz 4TH IMAGE 280MHz 5TH IMAGE Figure 5. Output Spectrum of a Sampled Signal In this example, the reference clock is 100 MHz and the output frequency is set to 20 MHz. As can be seen, the aliased images are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized D/A converter output. In fact, depending on the fo/reference clock relationship, the first aliased image can be on the order of –3 dB below the fundamental. A low-pass filter is generally placed between the output of the D/A converter and the input of the comparator to further suppress the effects of aliased images. Obviously, consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted (and unexpected) output anomalies. To apply the AD9850 as a clock generator, limit the selected output frequency to <33% of reference clock frequency, and thereby avoid generating aliased signals that fall within, or close to, the output band of interest (generally dc-selected output frequency). This practice eases the complexity (and cost) of the external filter requirement for the clock generator application. The reference clock frequency of the AD9850 has a minimum limitation of 1 MHz. The device has internal circuitry that senses when the minimum clock rate threshold has been exceeded REV. H The AD9850 contains a 40-bit register that is used to program the 32-bit frequency control word, the 5-bit phase modulation word, and the power-down function. This register can be loaded in a parallel or serial mode. In the parallel load mode, the register is loaded via an 8-bit bus; the full 40-bit word requires five iterations of the 8-bit word. The W_CLK and FQ_UD signals are used to address and load the registers. The rising edge of FQ_UD loads the (up to) 40-bit control data-word into the device and resets the address pointer to the first register. Subsequent W_CLK rising edges load the 8-bit data on words [7:0] and move the pointer to the next register. After five loads, W_CLK edges are ignored until either a reset or an FQ_UD rising edge resets the address pointer to the first register. In serial load mode, subsequent rising edges of W_CLK shift the 1-bit data on Pin 25 (D7) through the 40 bits of programming information. After 40 bits are shifted through, an FQ_UD pulse is required to update the output frequency (or phase). The function assignments of the data and control words are shown in Table III; the detailed timing sequence for updating the output frequency and/or phase, resetting the device, and powering up/down, are shown in the timing diagrams of Figures 6 through 12. Note: There are specific control codes, used for factory test purposes, that render the AD9850 temporarily inoperable. The user must take deliberate precaution to avoid inputting the codes listed in Table II. –9– AD9850 Table II. Factory Reserved Internal Test Control Codes Loading Format Factory Reserved Codes Parallel 1) W0 = XXXXXX10 2) W0 = XXXXXX01 Serial 1) W32 = 1; W33 = 0 2) W32 = 0; W33 = 1 3) W32 = 1; W33 = 1 t CD W0* DATA t DS W1 W2 tWH tDH W3 W4 tWL W CLK t FD t FL t FH FQ UD CLKIN tCF VALID DATA COS OUT OLD FREQ (PHASE) *OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK SYMBOL tDS tDH tWH tWL tCD tFH tFL tFD tCF DEFINITION MINIMUM DATA SETUP TIME 3.5ns DATA HOLD TIME 3.5ns W CLK HIGH 3.5ns W CLK LOW 3.5ns CLK DELAY AFTER FQ_UD 3.5ns FQ UD HIGH 7.0ns FQ UD LOW 7.0ns FQ UD DELAY AFTER W CLK 7.0ns NEW FREQ (PHASE) OUTPUT LATENCY FROM FQ UD FREQUENCY CHANGE 18 CLOCK CYCLES PHASE CHANGE 13 CLOCK CYCLES Figure 6. Parallel Load Frequency/Phase Update Timing Sequence Table III. 8-Bit Parallel Load Data/Control Word Functional Assignment Word Data[7] Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0] W0 Phase-b4 (MSB) Phase-b3 Phase-b2 Phase-b1 Phase-b0 (LSB) Power-Down Control Control W1 Freq-b31 (MSB) Freq-b30 Freq-b29 Freq-b28 Freq-b27 Freq-b26 Freq-b25 Freq-b24 W2 Freq-b23 Freq-b22 Freq-b21 Freq-b20 Freq-b19 Freq-b18 Freq-b17 Freq-b16 W3 Freq-b15 Freq-b14 Freq-b13 Freq-b12 Freq-b11 Freq-b10 Freq-b9 Freq-b8 W4 Freq-b7 Freq-b6 Freq-b5 Freq-b4 Freq-b3 Freq-b2 Freq-b1 Freq-b0 (LSB) –10– REV. H AD9850 CLKIN tRL tRH tRR RESET tRS tOL COS (0) COS OUT NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT HAVE TO BE SYNCHRONOUS WITH THE CLKIN IF THE MINIMAL TIME IS NOT REQUIRED. SYMBOL tRH tRL tRR tRS tOL DEFINITION MINIMUM CLK DELAY AFTER RESET RISING EDGE 3.5ns RESET FALLING EDGE AFTER CLK 3.5ns RECOVERY FROM RESET 2 CLK CYCLES MINIMUM RESET WIDTH 5 CLK CYCLES RESET OUTPUT LATENCY 13 CLK CYCLES RESULTS OF RESET: – FREQUENCY/PHASE REGISTER SET TO 0 – ADDRESS POINTER RESET TO W0 – POWER-DOWN BIT RESET TO 0 – DATA INPUT REGISTER UNEFFECTED Figure 7. Master Reset Timing Sequence DATA (W0) XXXXX100 W CLK FQ UD CLKIN DAC STROBE INTERNAL CLOCKS DISABLED Figure 8. Parallel Load Power-Down Sequence/Internal Operation DATA (W0) XXXXX000 W CLK FQ UD CLKIN INTERNAL CLOCKS ENABLED Figure 9. Parallel Load Power-Up Sequence/Internal Operation REV. H –11– AD9850 DATA (W0) (PARALLEL) XXXXX011 DATA (SERIAL) REQUIRED TO RESET CONTROL REGISTERS W32 = 0 W33 = 0 NOTE: W32 AND W33 SHOULD ALWAYS BE SET TO 0. W CLK FQ UD LOAD 40-BIT SERIAL WORD ENABLE SERIAL MODE NOTE: FOR DEVICE START-UP IN SERIAL MODE, HARDWIRE PIN 2 AT 0, PIN 3 AT 1, AND PIN 4 AT 1 (SEE FIGURE 11). Figure 10. Serial Load Enable Sequence 2 3 +V SUPPLY AD9850BRS 4 Figure 11. Pins 2 to 4 Connection for Default Serial Mode Operation DATA – W0 W1 W2 W3 W39 FQ UD W CLK 40 W CLK CYCLES Figure 12. Serial Load Frequency/Phase Update Sequence Table IV. 40-Bit Serial Load Word Function Assignment W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 Freq-b0 (LSB) Freq-b1 Freq-b2 Freq-b3 Freq-b4 Freq-b5 Freq-b6 Freq-b7 Freq-b8 Freq-b9 Freq-b10 Freq-b11 Freq-b12 Freq-b13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 Freq-b14 Freq-b15 Freq-b16 Freq-b17 Freq-b18 Freq-b19 Freq-b20 Freq-b21 Freq-b22 Freq-b23 Freq-b24 Freq-b25 Freq-b26 Freq-b27 –12– W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 Freq-b28 Freq-b29 Freq-b30 Freq-b31 (MSB) Control Control Power-Down Phase-b0 (LSB) Phase-b1 Phase-b2 Phase-b3 Phase-b4 (MSB) REV. H AD9850 DATA (7) – W32 = 0 W33 = 0 W34 = 1 W35 = X W36 = X W37 = X W38 = X W39 = X FQ UD W CLK Figure 13. Serial Load Power-Down Sequence VCC VCC VCC VCC QOUT/ QOUTB DIGITAL IN VINP/ VINN IOUT IOUTB DAC Output Comparator Output Comparator Input Digital Inputs Figure 14. AD9850 I/O Equivalent Circuits PCB LAYOUT INFORMATION Analog Devices, Inc. applications engineering support is available to answer additional questions on grounding and PCB layout. Call 1-800-ANALOGD or contact us at www.analog.com/dds. The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 15 through 18) represent typical implementations of the AD9850 and exemplify the use of high frequency/high resolution design and layout practices. The printed circuit board that contains the AD9850 should be a multilayer board that allows dedicated power and ground planes. The power and ground planes should be free of etched traces that cause discontinuities in the planes. It is recommended that the top layer of the multilayer board also contain an interspatial ground plane, which makes ground available for surface-mount devices. If separate analog and digital system ground planes exist, they should be connected together at the AD9850 for optimum results. Evaluation Boards Avoid running digital lines under the device because these couple noise onto the die. The power supply lines to the AD9850 should use as large a track as possible to provide a low impedance path and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signal paths. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the circuit board. Use microstrip techniques where possible. Good decoupling is also an important consideration. The analog (AVDD) and digital (DVDD) supplies to the AD9850 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with high quality ceramic capacitors. To achieve best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD supplies of the AD9850, it is recommended that the system’s AVDD supply be used. REV. H Two versions of evaluation boards are available for the AD9850, which facilitate the implementation of the device for benchtop analysis and serve as a reference for PCB layout. The AD9850/FSPCB is used in applications where the device is used primarily as a frequency synthesizer. This version facilitates connection of the AD9850’s internal D/A converter output to a 50 Ω spectrum analyzer input; the internal comparator on the AD9850 DUT is not enabled (see Figure 15 for an electrical schematic of AD9850/FSPCB). The AD9850/CGPCB is used in applications using the device in the clock generator mode. It connects the AD9850’s DAC output to the internal comparator input via a single-ended, 42 MHz low-pass, 5-pole elliptical filter. This model facilitates the access of the AD9850’s comparator output for evaluation of the device as a frequency- and phase-agile clock source (see Figure 17 for an electrical schematic of AD9850/CGPCB). Both versions of the AD9850 evaluation board are designed to interface to the parallel printer port of a PC. The operating software runs under Microsoft® Windows® and provides a userfriendly and intuitive format for controlling the functionality and observing the performance of the device. The 3.5 inch floppy provided with the evaluation board contains an executable file that loads and displays the AD9850 function-selection screen. The evaluation board can be operated with 3.3 V or 5 V supplies. The evaluation boards are configured at the factory for an external reference clock input; if the on-board crystal clock source is used, remove R2. –13– AD9850 AD9850 Evaluation Board Instructions Required Hardware/Software • IBM compatible computer operating in a Windows environment. • Printer port, 3.5 inch floppy drive, and Centronics compatible printer cable. • XTAL clock or signal generator—if using a signal generator, dc offset the signal to one-half the supply voltage and apply at least 3 V p-p signal across the 50 Ω (R2) input resistor. Remove R2 for high Z clock input. • AD9850 evaluation board software disk and AD9850/FSPCB or AD9850/CGPCB evaluation board. • 5 V voltage supply. Setup 1. Copy the contents of the AD9850 disk onto your hard drive (there are three files). 2. Connect the printer cable from your computer to the AD9850 evaluation board. 3. Apply power to AD9850 evaluation board. The AD9850 is powered separately from the connector marked DUT +V. The AD9850 may be powered with 3.3 V to 5 V. 4. Connect external 50 Ω clock or remove R2 and apply a high Z input clock such as a crystal can oscillator. 5. Locate the file called 9850REV2.EXE and execute that program. 6. Monitor should display a control panel to allow operation of the AD9850 evaluation board. Operation On the control panel, locate the box called COMPUTER I/O. Point to and click the selection marked LPT1 and then point to the TEST box and click. A message will appear telling users if their choice of output ports is correct. Choose other ports as necessary to achieve a correct setting. If they have trouble getting their computer to recognize any printer port, they should try the following: connect three 2 kΩ pull-up resistors from Pins 9, 8, and 7 of U3 to 5 V. This will assist weak printer port outputs in driving the heavy capacitance load of the printer cable. If troubles persist, try a different printer cable. Locate the CLOCK box and place the cursor in the frequency box. Type in the clock frequency (in MHz) that the user will be applying to the AD9850. Click the LOAD button or press enter on the keyboard. Move the cursor to the OUTPUT FREQUENCY box and type in the desired output frequency (in MHz). Click the LOAD button or press the enter key. The BUS MONITOR section of the control panel will show the 32-bit word that was loaded into the AD9850. Upon completion of this step, the AD9850 output should be active and outputting the user's frequency information. Changing the output phase is accomplished by clicking on the down arrow in the OUTPUT PHASE DELAY box to make a selection and then clicking the LOAD button. Other operational modes (frequency sweeping, sleep, serial input) are available to the user via keyboard/mouse control. The AD9850/FSPCB provides access into and out of the on-chip comparator via test point pairs (each pair has an active input and a ground connection). The two active inputs are labeled TP1 and TP2. The unmarked hole next to each labeled test point is a ground connection. The two active outputs are labeled TP5 and TP6. Unmarked ground connections are adjacent to each of these test points. The AD9850/CGPCB provides BNC inputs and outputs associated with the on-chip comparator and the on-board, fifth-order, 200 Ω input/output Z, elliptic, 45 MHz, low-pass filter. Jumpering (soldering a wire) E1 to E2, E3 to E4, and E5 to E6 connects the on-board filter and the midpoint switching voltage to the comparator. Users may elect to insert their own filter and comparator threshold voltage by removing the jumpers and inserting a filter between J7 and J6 and then providing a threshold voltage at E1. If users choose to use the XTAL socket to supply the clock to the AD9850, they must remove R2 (a 50 Ω chip resistor). The crystal oscillator must be either TTL or CMOS (preferably) compatible. Locate the MASTER RESET button with the mouse and click it. This will reset the AD9850 to 0 Hz, 0° phase. The output should be a dc voltage equal to the full-scale output of the AD9850. –14– REV. H AD9850 C36CRPX J1 1 U2 74HCT574 RRESET 2 9 3 8 4 7 5 6 6 5 7 4 8 3 9 2 10 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q 13 14 15 16 17 18 19 +V D0 BANANA J3 JACKS D1 5V J4 GND D2 D3 D4 11 14 1 D4 28 D4 2 D2 D5 27 D5 D1 3 D1 D0 4 D0 WCLK 7 W CLK D7 FQUD 8 FQ UD CLKIN 9 CLKIN R1 3.9k⍀ FFQUD 12 RSET 16 TP5 17 COMPARATOR TP6 OUTPUTS TP7 GND TP8 GND 18 U3 74HCT574 20 RRESET 21 22 WWCLK 23 FFQUD 24 RRESET 25 9 8 7 6 5 4 26 3 27 2 28 8D 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q CLK 29 11 30 31 32 8Q WWCLK 12 13 14 15 CHECK 16 R5 25⍀ IOUT 21 IOUTB 20 AGND 19 GND +V AVDD 18 DACBL 17 13 QOUTB VINP 16 14 QOUT VINN 15 TP1 TP2 COMPARATOR GND TP3 INPUTS GND TP4 R6 1k⍀ +V J5 R7 1k⍀ CLKIN WCLK R2 50⍀ REMOVE WHEN USING Y1 GND +5V 17 14 18 XTAL OSC 19 VCC Y1 OUT OE GND 1 7 8 5V R10 2.2k⍀ STROBE +V CHECK 5V RRESET 36 5V +V C6 10F 35 C7 10F C2 0.1F C3 0.1F C4 0.1F C5 0.1F C8 0.1F C9 0.1F STROBE Figure 15. AD9850/FSPCB Electrical Schematic COMPONENT LIST Integrated Circuits U1 U2, U3 AD9850BRS (28-Lead SSOP) 74HCT574 H-CMOS Octal Flip-Flop Capacitors C2 to C5, C8 to C10 C6, C7 0.1 µF Ceramic Chip Capacitor 10 µF Tantalum Chip Capacitor Resistors R1 R2, R4 R3, R8, R9, R10 R5 R6, R7 3.9 kΩ Resistor 50 Ω Resistor 2.2 kΩ Resistor 25 Ω Resistor 1 kΩ Resistor Connectors J1 J2, J3, J4 J5, J6 REV. H 36-Pin D Connector Banana Jack BNC Connector –15– R9 2.2k⍀ FFQUD 33 34 DAC OUT TO 50⍀ R4 50⍀ RESET 22 RESET RESET FQUD J6 DVDD 23 +V +V 11 AVDD 10mA RSET 26 D6 DGND 24 GND 6 DVDD GND 10 AGND STROBE MOUNTING HOLES D7 25 D7 D6 1 19 U1 D6 AD9850 +V 15 P O R T 1 D3 D5 12 13 D3 D2 GND 5 DGND CLK OE 11 H1 H2 H3 H4 No. 6 No. 6 No. 6 No. 6 J2 12 C10 0.1F R8 2.2k⍀ WWCLK R3 2.2k⍀ STROBE AD9850 16c. AD9850/FSPCB Power Plane 16a. AD9850/FSPCB Top Layer 16d. AD9850/FSPCB Bottom Layer 16b. AD9850/FSPCB Ground Plane Figure 16. AD9850/FSPCB Evaluation Board Layout –16– REV. H AD9850 C36CRPX J1 1 2 J2 +V RRESET 9 3 8 4 7 5 6 6 5 7 4 8 3 9 2 10 8Q 8D 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q CLK 11 BANANA J3 JACKS U2 74HCT574 11 14 GND D0 13 15 16 17 18 19 D2 D3 1 D3 D4 28 D4 D3 D2 2 D2 D5 27 D5 D4 D1 3 D1 D5 D0 4 D0 D6 GND 5 DGND DGND 24 GND D7 +V 6 DVDD DVDD 23 +V STROBE FFQUD 17 P O 18 R T 19 20 1 21 CLKIN 9 CLKIN IOUTB 20 GND 10 AGND AGND 19 +V 11 AVDD AVDD 18 J8 12 RSET 13 QOUTB VINP 16 14 QOUT VINN 15 L2 1008CS 680nH 1 2 C12 3.3pF C14 8.2pF C11 22pF C13 33pF C15 22pF R8 100⍀ GND +V DACBL 17 R7 200⍀ J6 C1 470pF J9 E1 E2 E4 E3 J5 5V CLKIN R9 2.2k⍀ U3 74HCT574 24 25 RRESET 26 WWCLK 27 FFQUD 28 RRESET 9 8 7 6 29 5 30 4 31 3 WWCLK CHECK 2 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2Q 2D 1D 1Q 12 13 14 15 RESET RRESET 11 R10 2.2k⍀ FFQUD R11 2.2k⍀ WWCLK R3 2.2k⍀ STROBE 5V 14 FQUD VCC XTAL OSC CHECK 16 Y1 19 STROBE 8 7 18 1 OUT GND 17 35 R2 50⍀ REMOVE WHEN USING Y1 WCLK OE CLK 34 36 R6 200⍀ L1 1008CS 910nH 1 2 R5 100k⍀ IOUT 21 BNC 23 33 R4 100k⍀ W CLK RESET 22 RESET BNC E5 E6 J7 BNC FQ UD 22 32 26 D6 D7 25 D7 FQUD 8 R1 3.9k⍀ 10mA RSET U1 D6 AD9850 WCLK 7 1 16 200⍀ Z 42MHz ELLIPTIC LOW-PASS FILTER D1 14 OE 15 MOUNTING HOLES J4 12 12 13 H1 H2 H3 H4 No. 6 No. 6 No. 6 No. 6 5V +V +V 5V C6 10F C7 10F C2 0.1F C3 0.1F 5V C4 0.1F C5 0.1F C8 0.1F C9 0.1F STROBE Figure 17. AD9850/CGPCB Electrical Schematic COMPONENT LIST Integrated Circuits U1 U2, U3 Resistors AD9850BRS (28-Lead SSOP) 74HCT574 H-CMOS Octal Flip-Flop Capacitors C1 C2 to C5, C8 to C10 C6, C7 C11 C12 C13 C14 C15 REV. H 470 pF Ceramic Chip Capacitor 0.1 µF Ceramic Chip Capacitor 10 µF Tantalum Chip Capacitor 22 pF Ceramic Chip Capacitor 3.3 pF Ceramic Chip Capacitor 33 pF Ceramic Chip Capacitor 8.2 pF Ceramic Chip Capacitor 22 pF Ceramic Chip Capacitor R1 R2 R3, R9, R10, R11 R4, R5 R6, R7 R8 3.9 kΩ Resistor 50 Ω Resistor 2.2 kΩ Resistor 100 kΩ Resistor 200 Ω Resistor 100 Ω Resistor Connectors J2, J3, J4 J5 to J9 Banana Jack BNC Connector Inductors L1 L2 –17– 910 nH Surface Mount 680 nH Surface Mount C10 0.1F AD9850 18a. AD9850/CGPCB Top Layer 18c. AD9850/CGPCB Power Plane 18b. AD9850/CGPCB Ground Plane 18d. AD9850/CGPCB Bottom Layer Figure 18. AD9850/CGPCB Evaluation Board Layout –18– REV. H AD9850 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 5.30 5.00 8.20 7.80 7.40 14 1 1.85 1.75 1.65 2.00 MAX 0.10 COPLANARITY 0.25 0.09 0.05 MIN 0.65 BSC 0.38 0.22 SEATING PLANE 8ⴗ 4ⴗ 0ⴗ COMPLIANT TO JEDEC STANDARDS MO-150AH REV. H –19– 0.95 0.75 0.55 AD9850 Revision History Location Page 2/04—Data Sheet changed from REV. G to REV. H. 12/03—Data Sheet changed from REV. F to REV. G. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11/03—Data Sheet changed from REV. E to REV. F. Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 –20– REV. H C00632–0–2/04(H) Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3