LTC1410 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1410 is a 0.65µs, 1.25Msps, 12-bit sampling A/D converter that draws only 160mW from ±5V supplies. This easy-to-use device includes a high dynamic range sample-and-hold, a precision reference and requires no external components. Two digitally selectable power shutdown modes provide flexibility for low power systems. 1.25Msps Sample Rate Power Dissipation: 160mW 71dB S/(N + D) and 82dB THD at Nyquist No Pipeline Delay Nap (7mW) and Sleep (10µW) Shutdown Modes Operates with Internal 15ppm/°C Reference or External Reference True Differential Inputs Reject Common Mode Noise 20MHz Full Power Bandwidth Sampling ±2.5V Bipolar Input Range 28-Pin SO Wide Package The LTC1410’s full-scale input range is ±2.5V. Maximum DC specifications include ±1LSB INL and ±1LSB DNL over temperature. Outstanding AC performance includes 71dB S/(N + D) and 82dB THD at the Nyquist input frequency of 625kHz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 20MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. UO APPLICATI ■ ■ ■ ■ ■ ■ S Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems The ADC has a µP compatible, 12-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. , LTC and LT are registered trademarks of Linear Technology Corporation. UO TYPICAL APPLICATI Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency Complete 1.25MHz, 12-Bit Sampling A/D Converter 27 12 10µF 26 25 10µF 24 23 22 74 + –5V µP CONTROL LINES 21 20 68 0.1µF NYQUIST 10 62 0.1µF 56 8 50 6 4 S/(N + D) (dB) 10µF 5V 28 EFFECTIVE BITS + LTC1410 DIFFERENTIAL 1 AVDD +AIN ANALOG INPUT (–2.5V TO 2.5V) 2 –AIN DVDD 2.50V 3 V VSS VREF OUTPUT 4 REF REFCOMP BUSY 5 0.1µF AGND CS 6 D11(MSB) CONVST 7 D10 RD 8 D9 SHDN 9 D8 NAP/SLP 10 D7 OGND 11 12-BIT D6 D0 PARALLEL 12 D5 D1 BUS 13 D4 D2 14 DGND D3 19 18 2 17 16 fSAMPLE = 1.25MHz 0 1k 15 10k 100k 1M INPUT FREQUENCY (Hz) 10M LTC1410 • TA02 1410 TA01 1 LTC1410 U U RATI GS W W W W AXI U PACKAGE/ORDER I FOR ATIO AVDD = DVDD = VDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) .................................. VSS – 0.3V to VDD + 0.3V Digital Input Voltage (Note 4) ............ VSS – 0.3V to 10V Digital Output Voltage ................... – 0.3V to VDD + 0.3V Power Dissipation ............................................. 500mW Operating Temperature Range LTC1410C .............................................. 0°C to 70°C LTC1410I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U ABSOLUTE +AIN 1 28 AVDD –AIN 2 27 DVDD VREF 3 26 VSS REFCOMP 4 AGND 5 24 CS D11(MSB) 6 23 CONVST D10 7 22 RD D9 8 21 SHDN D8 9 20 NAP/SLP D7 10 19 OGND D6 11 18 D0 D5 12 17 D1 D4 13 16 D2 DGND 14 15 D3 G PACKAGE 28-LEAD PLASTIC SSOP LTC1410CG LTC1410CSW LTC1410IG LTC1410ISW 25 BUSY SW PACKAGE 28-LEAD PLASTIC SO WIDE TJMAX = 110°C, θJA = 90°C/W (SW) TJMAX = 110°C, θJA = 95°C/W (G) Consult factory for Military grade parts. U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6) PARAMETER CONDITIONS Resolution (No Missing Codes) Integral Linearity Error TYP MAX ● ±0.3 ±1 ● ±0.3 ±1 LSB ±2 ±6 ±8 LSB LSB ±15 LSB ● (Note 7) Differential Linearity Error Offset Error MIN 12 (Note 8) Bits ● Full-Scale Error Full-Scale Tempco IOUT(REF) = 0 ±15 ● UNITS LSB ppm/°C U U A ALOG I PUT The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (Note 9) 4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V ● IIN Analog Input Leakage Current CS = High ● CIN Analog Input Capacitance Between Conversions During Conversions t ACQ Sample-and-Hold Acquisition Time t AP Sample-and-Hold Aperture Delay Time tjitter Sample-and-Hold Aperture Delay Time Jitter CMRR Analog Input Common Mode Rejection Ratio 2 MIN TYP ±2.5 ±1 50 –1.5 UNITS V 17 5 ● – 2.5V < (– AIN = AIN) < 2.5V MAX µA pF pF 100 ns ns 5 psRMS 60 dB LTC1410 W U DY A IC ACCURACY The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL S/(N + D) PARAMETER Signal-to-(Noise + Distortion) Ratio THD Total Harmonic Distortion IMD Peak Harmonic or Spurious Noise Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth CONDITIONS 100kHz Input Signal (Note 12) 600kHz Input Signal (Note 12) 100kHz Input Signal, First 5 Harmonics 600kHz Input Signal, First 5 Harmonics 600kHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz ● ● MIN 70 68 ● ● (S/(N + D) ≥ 68dB) U U U I TER AL REFERE CE CHARACTERISTICS TYP 72.5 71.0 – 85 – 82 – 84 – 84 20 2.5 MAX – 74 – 74 UNITS dB dB dB dB dB dB MHz MHz The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V IOUT ≤ 0.1mA IOUT = 0 MIN 2.480 TYP 2.500 ±15 0.01 0.01 2 4.06 MAX 2.520 UNITS V ppm/°C LSB/V LSB/V kΩ V U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage High-Z Output Leakage D11 to D0 High-Z Output Capacitance D11 to D0 Output Source Current Output Sink Current W U POWER REQUIRE E TS CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD ● MIN 2.4 TYP MAX 0.8 ±10 ● ● 5 VDD = 4.75V IO = – 10µA IO = – 200µA VDD = 4.75V IO = 160µA IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9 ) VOUT = 0V VOUT = VDD UNITS V V µA pF 4.5 ● V V 4.0 0.05 0.10 ● ● ● 0.4 ±10 15 – 10 10 V V µA pF mA mA The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL VDD VSS IDD ISS PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Nap Mode Sleep Mode Negative Supply Current Nap Mode Sleep Mode CONDITIONS (Notes 10, 11) (Note 10) CS = RD = CONVST = 5V SHDN = 0V, NAP/SLP = 5V SHDN = 0V, NAP/SLP = 0V CS = RD = CONVST = 5V SHDN = 0V, NAP/SLP = 5V SHDN = 0V, NAP/SLP = 0V MIN 4.75 – 4.75 ● ● TYP 12 1.5 1 20 10 1 MAX 5.25 – 5.25 16 2.3 100 30 200 100 UNITS V V mA mA µA mA µA µA 3 LTC1410 W U POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PD PARAMETER Power Dissipation Nap Mode Sleep Mode CONDITIONS MIN SHDN = 0V, NAP/SLP = 5V SHDN = 0V, NAP/SLP = 0V TYP 160 7.5 0.01 MAX 230 12 1 UNITS mW mW mW WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER fSAMPLE(MAX) tCONV Maximum Sampling Frequency Conversion Time CONDITIONS ● MIN TYP MAX UNITS ● 650 750 MHz ns tACQ tACQ+CONV t1 Acquisition Time Throughput Time (Acquisition + Conversion) CS to RD Setup Time ● 50 100 800 ns ns (Notes 9, 10) ● 0 ns t2 t3 CS↓ to CONVST↓ Setup Time NAP/SLP↓ to SHDN↓ Setup Time (Notes 9, 10) (Notes 9, 10) ● 10 10 ns ns t4 t5 SHDN↑ to CONVST↓ Wake-Up Time (Note 10) CONVST Low Time (Notes 10, 11) t6 CONVST to BUSY Delay 1.25 ● ● 200 ● 40 CL = 25pF 10 50 ● t7 Data Ready Before BUSY↑ ● t8 t9 Delay Between Conversions Wait Time RD↓ After BUSY↑ (Note 10) (Note 10) t10 Data Access Time After RD↓ CL = 25pF ● ● 20 15 35 ns ns 15 CL = 100pF 20 ● Bus Relinquish Time 8 Commercial Industrial ● ● t12 RD Low Time ● t 10 t13 t14 CONVST High Time Aperture Delay of Sample-and-Hold ● 40 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 1.25MHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended +AIN input with – AIN grounded. 4 ns ns ns ns 40 –5 ● t11 ns ns – 1.5 25 35 35 50 ns ns ns ns 20 25 30 ns ns ns ns ns ns Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best results ensure that CONVST returns high either within 425ns after the start of the conversion or after BUSY rises. Note 12: Signal-to-noise ratio (SNR) is measured at 100kHz and distortion is measured at 600kHz. These results are used to calculate signal-to-noise plus distortion (SINAD). LTC1410 U W TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude Signal-to-Noise Ratio vs Input Frequency 80 70 SIGNAL-TO-NOISE RATIO (dB) VIN = 0dB 60 VIN = –20dB 50 40 30 20 AMPLITUDE (dB BELOW THE FUNDAMENTAL) 70 SIGNAL/(NOISE + DISTORTION) (dB) Distortion vs Input Frequency 80 VIN = –60dB 10 60 50 40 30 20 10 fSAMPLE = 1.25MHz 0 0 1k 1M 10k 100k INPUT FREQUENCY (Hz) 10M 1M 10k 100k INPUT FREQUENCY (Hz) 1k 1410 G01 –10 –20 –30 –40 –50 –60 3RD THD –70 –80 2ND –90 –100 1k 1M 10k 100k INPUT FREQUENCY (Hz) Differential Nonlinearity vs Output Code Intermodulation Distortion Plot 0 0 1.0 fSAMPLE = 1.25MHz fIN1 = 88.19580078kHz fIN2 = 111.9995117kHz –10 –20 –20 AMPLITUDE (dB) –40 –50 –60 –70 DNL ERROR (LSB) 0.5 –30 –40 –60 –80 0 –0.5 –80 –100 –90 –100 10k –120 100k 1M INPUT FREQUENCY (Hz) 10M 0 100 200 300 400 500 –1.0 600 0 FREQUENCY (kHz) 512 1024 1536 2048 2560 3072 3504 4096 OUTPUT CODE 1410 G04 1410 G06 1.0 0.5 0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3504 4096 OUTPUT CODE 1410 G07 Power Supply Feedthrough vs Ripple Frequency Input Common Mode Rejection vs Input Frequency 0 80 VRIPPLE = 0.1V COMMON MODE REJECTION (dB) Integral Nonlinearity vs Output Code AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) 1410 G05 INL ERROR (LSB) 10M 1410 G03 1410 G02 Spurious-Free Dynamic Range vs Input Frequency SPURIOUS-FREE DYNAMIC RANGE (dB) 10M 0 –20 –40 –60 VSS –80 VDD DGND –100 –120 70 60 50 40 30 20 10 0 1k 10k 100k 1M RIPPLE FREQUENCY (Hz) 10M 1410 G08 1k 1M 10k 100k INPUT FREQUENCY (Hz) 10M 1410 G09 5 LTC1410 U U U PI FU CTIO S + AIN (Pin 1): Positive Analog Input, ±2.5V. – AIN (Pin 2): Negative Analog Input, ±2.5V. VREF (Pin 3): 2.50V Reference Output. REFCOMP (Pin 4): 4.06V Reference Bypass Pin. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. AGND (Pin 5): Analog Ground. D11 to D4 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND. D3 to D0 (Pins 15 to 18): Three-State Data Outputs. OGND (Pin 19): Digital Ground for Output Drivers. Tie to AGND. NAP/SLP (Pin 20): Power Shutdown Mode. Selects the mode invoked by the SHDN pin. Low selects Sleep mode and high selects quick wake-up Nap mode. SHDN (Pin 21): Power Shutdown Input. A low logic level will invoke the Shutdown mode selected by the NAP/SLP pin. RD (Pin 22): Read Input. This enables the output drivers when CS is low. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. BUSY (Pin 25): The BUSY output shows the converter status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY. VSS (Pin 26): – 5V Negative Supply. Bypass to AGND with 10µF tantalum in parallel 0.1µF ceramic. DVDD (Pin 27): 5V Positive Supply. Short to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. U U W FU CTIO AL BLOCK DIAGRA CSAMPLE +AIN AVDD CSAMPLE – AIN VREF 2k DVDD ZEROING SWITCHES 2.5V REF VSS + REF AMP COMP 12-BIT CAPACITIVE DAC – REFCOMP (4V) SUCCESSIVE APPROXIMATION REGISTER AGND DGND INTERNAL CLOCK OUTPUT LATCHES • • • D11 D0 CONTROL LOGIC NAP/SLP SHDN CONVST RD CS 6 12 BUSY LTC1410 • BD LTC1410 TEST CIRCUITS Load Circuits for Output Float Delay Load Circuits for Access Timing 5V 5V 1k 1k DBN DBN DBN 1k CL 1k CL (A) Hi-Z TO VOH AND VOL TO VOH DBN 100pF 100pF (A) VOH TO Hi-Z (B) Hi-Z TO VOL AND VOH TO VOL (B) VOL TO Hi-Z 1410 TC02 1410 TC01 U W U U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1410 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. onto the summing junctions. This input charge is successively compared with the binarily-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the + AIN and – AIN input charges. The SAR contents (a 12-bit data word) which represent the difference of + AIN and – AIN are loaded into the 12-bit output latches. +CSAMPLE +AIN SAMPLE HOLD ZEROING SWITCHES –CSAMPLE During the conversion, the internal differential 12-bit capacitive DAC output is sequenced by the SAR from the Most Significant Bit (MSB) to the Least Significant Bit (LSB). Referring to Figure 1, the + AIN and – AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum duration of 100ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSAMPLE capacitors to ground, transferring the differential analog input charge – AIN HOLD SAMPLE HOLD HOLD +CDAC + –CDAC COMP – +VDAC –VDAC 12 SAR OUTPUT LATCHES • • • D11 D0 1410 F01 Figure 1. Simplified Block Diagram 7 LTC1410 U W U U APPLICATIONS INFORMATION DYNAMIC PERFORMANCE The LTC1410 has excellent high speed sampling capability. Fast Four Transform (FFT) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. 0 fSAMPLE = 1.25MHz fIN = 100.098kHz SFDR = 90.1dB SINAD = 72.4dB AMPLITUDE (dB) –20 –40 –60 –80 to frequencies from above DC and below half the sampling frequency. Figures 2a and 2b shows a typical spectral content with a 1.25MHz sampling rate for 100kHz and 600kHz inputs. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 625kHz and beyond. Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76] / 6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 1.25MHz the LTC1410 maintains very good ENOBs up to the Nyquist input frequency of 625kHz and beyond. Refer to Figure 3. –100 12 74 –120 0 100 200 300 400 500 FREQUENCY (kHz) 68 600 NYQUIST 10 62 56 0 fSAMPLE = 1.25MHz fIN = 599.975kHz SFDR = 84.7dB SINAD = 71.7dB AMPLITUDE (dB) –20 8 50 6 4 S/(N + D) (dB) Figure 2a. LTC1410 Nonaveraged 4096 Point FFT, 100kHz Input EFFECTIVE BITS 1410 F02a 2 –40 fSAMPLE = 1.25MHz 0 1k –60 10k 100k 1M INPUT FREQUENCY (Hz) 10M LTC1410 • TA02 –80 Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency –100 –120 0 100 200 300 400 500 FREQUENCY (kHz) 600 1410 F02b Figure 2b. LTC1410 Nonaveraged 4096 Point FFT, 600kHz Input Signal-to-Noise Ratio The Signal-to-Noise plus Distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the ADC output. The output is band limited 8 Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20 log V22 + V32 + V42 + . . .Vn2 V1 LTC1410 U U W U APPLICATIONS INFORMATION 0 0 (fa) (fb) fSAMPLE = 1.25MHz fIN1 = 88.19580078kHz fIN2 = 111.9995117kHz –20 AMPLITUDE (dB) AMPLITUDE (dB BELOW THE FUNDAMENTAL) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure 4. The LTC1410 has good distortion performance up to the Nyquist frequency and beyond. –40 –60 –80 (2fb–fa) (fa+fb) (2fa+fb) (2fa) (2fb) (fa+2fb) (3fa) (3fb) (2fa–fb) (fb–fa) –10 –100 –20 –30 –120 –40 –60 3RD 100 200 300 400 500 600 1410 F05 THD Figure 5. Intermodulation Distortion Plot –70 –80 2ND –90 –100 0 FREQUENCY (MHz) –50 Peak Harmonic or Spurious Noise 1k 1M 10k 100k INPUT FREQUENCY (Hz) 10M 1410 G03 Figure 4. Distortion vs Input Frequency The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibel relative to the RMS value of a full-scale input signal. Full Power and Full Linear Bandwidth Intermodulation Distortion (IMD) If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce Intermodulation Distortion in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: ( ) IMD fa + fb = 20 log ( ) Amplitude at fa ± fb Amplitude at f a The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1410 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) does not become dominated by distortion until frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1410 are easy to drive. The inputs may be driven differentially or as a single-ended input (i.e., the – AIN input is grounded). The + AIN and – AIN inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold 9 LTC1410 U W U U APPLICATIONS INFORMATION capacitors at the end of conversion. During conversion the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1410 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 100ns for full throughput rate). sample-and-hold circuit is 20MHz. Any noise that is present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is usually sufficient. For example, Figure 7 shows a 1000pF capacitor from + AIN to ground and a 100Ω source resistor will limit the input bandwidth to 1.6MHz. Simple RC filters work well for AC applications, but they will limit the transient response. For full speed operation, amplifiers with fast settling and low noise should be chosen. 100Ω ANALOG INPUT 10 1 ACQUISITION TIME (µs) 1000pF 2 3 1 4 10µF 0.1µF 5 +AIN –AIN VREF REFCOMP AGND 0.1 LTC1410 1410 F07 0.01 10 1k 10k 100 SOURCE RESISTANCE (Ω) Figure 7. RC Input Filter 100k 1410 F06 Internal Reference Figure 6. Acquisition Time vs Source Resistance Choosing an input amplifier is easy if a few requirements are taken into consideration. First, choose an amplifier that has a low output impedance (< 100Ω) at the closedloop bandwidth frequency. For example, if an amplifier is used in a gain of +1 and has a closed-loop bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 20MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC’s inputs include the LT ®1360, LT1220, LT1223, LT1224 and LT1227 op amps. The noise and the distortion of the input amplifier must also be considered since they will add to the LTC1410 noise and distortion. The small-signal bandwidth of the 10 The LTC1410 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3). See Figure 8a. A 2k resistor is in series with the output so that it can be 1 ANALOG INPUT 2 +AIN LTC1410 –AIN R1 2k 3 VREF 2.500V 4.06V 10µF + 4 REFCOMP 0.1µF BANDGAP REFERENCE – R2 40k 5 AGND R3 64k 1410 F08a Figure 8a. LTC1410 Reference Circuit LTC1410 U U W U APPLICATIONS INFORMATION applied to AIN and R2 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. 011...111 BIPOLAR ZERO 011...110 OUTPUT CODE easily overdriven in applications where an external reference is required. The reference amplifier provides buffering between the internal reference and the capacitive DAC. The reference amplifier compensation pin REFCOMP (Pin 4), must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater. For the best noise performance, a 10µF tantalum in parallel with 0.1µF ceramic is recommended. The VREF pin can be driven with an external reference (Figure 8b), a DAC or other means to provide input span adjustment. The VREF should be kept in the range of 2.25V to 2.75V for specified linearity. 000...001 000...000 111...111 111...110 FS = 2.5V 2FS 1LSB = 4096 100...001 100...000 –1 0V 1 FS – LSB LSB LSB INPUT VOLTAGE, (+AIN) – (–AIN) (V) –FS 5V VIN 1 ANALOG INPUT 2 LT1019A-2.5 VOUT 3 4 10µF 0.1µF 5 +AIN 1410 F09 –AIN Figure 9. LTC1410 Transfer Characteristics VREF REFCOMP – 5V AGND LTC1410 1410 F08b Figure 8b. Using the LT1019-2.5 as an External Reference R1 50k R4 100Ω R6 24k 2 4 5 10µF In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 10 shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the – AIN input. For zero offset error apply – 0.61mV (i.e., – 0.5LSB) at +AIN and adjust the offset at the – AIN input until the output code flickers between 0000 0000 0000 and 1111 1111 1111. For full-scale adjustment, an input voltage of 2.49817V (FS – 1.5LSBs) is 1 3 R5 R2 47k 50k Full-Scale and Offset Adjustment Figure 9 shows the ideal input/output characteristics for the LTC1410. The code transitions occur midway between successive integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB, . . . FS – 1.5LSB, FS – 0.5LSB).The output is two’s complement binary with 1LSB = [(+FS) – (– FS)]/4096 = 5V/4096 = 1.22mV. ANALOG INPUT R3 47k 0.1µF +AIN –AIN VREF REFCOMP AGND LTC1410 1410 F10 Figure 10. Offset and Full-Scale Adjust Circuit BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1410, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. Particular care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. 11 LTC1410 U U W U APPLICATIONS INFORMATION ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the ADC data bus. High quality tantalum and ceramic bypass capacitors should be used at the VDD, VSS and REFCOMP pins as shown in the Typical Application on the first page of this data sheet. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1410 has differential inputs to minimize noise coupling. Common mode noise on the + AIN and – AIN leads will be rejected by the input CMRR. The – AIN input can be used as a ground sense for the + AIN input; the LTC1410 will hold and convert the difference voltage between + AIN and – AIN. The leads to + AIN (Pin 1) and – AIN (Pin 2) should be kept as short as possible. In applications where this is not possible, the + AIN and – AIN traces should be run side by side to equalize coupling. DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock A single point analog ground separate from the logic system ground should be established with an analog ground plane at Pin 5 (AGND) or as close as possible to the ADC. Pin 14 and Pin 19 (ADC’s DGND) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the 1 ANALOG INPUT CIRCUITRY + 2 + AIN The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 0.65µs and a maximum conversion time over the full operating temperature range of 0.75µs. No external adjustments are required. The guaranteed maximum acquisition time is 100ns. In addition, throughput time of 800ns and a minimum sampling rate of 1.25Msps is guaranteed. DIGITAL SYSTEM LTC1410 – AIN REFCOMP AVDD DVDD DGND OGND VSS AGND 26 4 28 27 14 19 – 10µF 0.1µF 10µF 0.1µF 10µF 0.1µF 1410 F11 Figure 11. Power Supply Grounding Practice 12 LTC1410 U W U U APPLICATIONS INFORMATION Power Shutdown Timing and Control The LTC1410 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. In Sleep mode all bias currents are shut down and only leakage current remains –– about 1µA. Wake-up time from Sleep mode is Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A logic “0” applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. NAP/SLP t3 SHDN 1410 F12a Figure 12a. NAP/SLP to SHDN Timing Figures 14 through 18 show several different modes of operation. In modes 1a and 1b (Figures 14 and 15) CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 16) CS is tied low. The falling edge of CONVST signal again starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus. SHDN t4 CONVST 1410 F12b Figure 12b. SHDN to CONVST Wake-Up Timing much slower since the reference circuit must power up and settle to 0.01% for full 12-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 10ms with the recommended 10µF capacitor. Shutdown is controlled by Pin 21 (SHDN), the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 20 (NAP/SLP); high selects Nap. CS In slow memory and ROM modes (Figures 17 and 18) CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). In slow memory mode the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low forcing the processor into a wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. t2 CONVST t1 RD 1410 F12 Figure 13. CS to CONVST Setup Timing 13 LTC1410 U U W U APPLICATIONS INFORMATION t CONV CS = RD = 0 t5 CONVST t6 t8 BUSY t7 DATA N DB11 TO DB0 DATA (N – 1) DB11 TO DB0 DATA DATA (N + 1) DB11 TO DB0 1410 F14 Figure 14. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) tCONV CS = RD = 0 t8 t5 t13 CONVST t6 t6 BUSY t7 DATA DATA (N – 1) DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 1410 F15 Figure 15. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) t13 tCONV t8 t5 CONVST t6 BUSY t9 t 12 t 11 RD t 10 DATA DATA N DB11 TO DB0 1410 F16 Figure 16. Mode 2. CONVST Starts a Conversion. Data is Read by RD 14 LTC1410 W U U UO APPLICATI S I FOR ATIO t8 t CONV RD = CONVST t6 t 11 BUSY t 10 t7 DATA (N – 1) DB11 TO DB0 DATA DATA N DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11-DB0 1410 F17 Figure 17. Slow Memory Mode Timing t CONV t8 RD = CONVST t6 t 11 BUSY t 10 DATA N DB11 TO DB0 DATA (N – 1) DB11 TO DB0 DATA 1410 F18 Figure 18. ROM Mode Timing U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.397 – 0.407* (10.07 – 10.33) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.022 – 0.037 (0.55 – 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.0256 (0.65) BSC 0.010 – 0.015 (0.25 – 0.38) 0.002 – 0.008 (0.05 – 0.21) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. G28 SSOP 0694 15 LTC1410 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 1 2 3 4 5 6 7 8 9 10 11 12 13 0.037 – 0.045 (0.940 – 1.143) 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 14 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) TYP 0.004 – 0.012 (0.102 – 0.305) 0.014 – 0.019 (0.356 – 0.482) TYP NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS S28 (WIDE) 0996 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS 12-Bit Sampling A/D Converters PART NUMBER DESCRIPTION COMMENTS LTC1273/75/76 Complete 5V Sampling 12-Bit ADCs with 70dB SINAD at Nyquist Lower Power and Cost Effective for fSAMPLE ≤ 300ksps LTC1274/77 Low Power 12-Bit ADCs with Nap and Sleep Mode Shutdown Lowest Power for fSAMPLE ≤ 100ksps LTC1278/79 High Speed Sampling 12-Bit ADCs with Shutdown Cost Effective 12-Bit ADCs –– Best for 2-Pair HDSL, fSAMPLE ≤ 500ksps/600ksps LTC1282 Complete 3V 12-Bit ADCs with 12mW Power Dissipation Fully Specified for 3V-Powered Applications, fSAMPLE ≤ 140ksps 16 Linear Technology Corporation 1410fa LT/TP 0399 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1995