TABLE OF CONTENTS 1 GENERAL DESCRIPTION................................................................................................................. 1 2 FEATURES ........................................................................................................................................ 2 3 ORDERING INFORMATION .............................................................................................................. 2 4 BLOCK DIAGRAM ............................................................................................................................. 3 5 DIE ARRANGEMENT ........................................................................................................................ 4 6 PIN DESCRIPTION ............................................................................................................................ 8 6.1 RES ............................................................................................................................................ 8 6.2 PS0-2 ........................................................................................................................................... 8 6.3 CS ............................................................................................................................................... 8 6.4 D/ C ............................................................................................................................................. 8 6.5 R/ W ( WR )................................................................................................................................... 8 6.6 E( RD ).......................................................................................................................................... 8 6.7 D0 -D15 .......................................................................................................................................... 8 6.8 OSC1 ........................................................................................................................................... 9 6.9 REF.............................................................................................................................................. 9 6.10 DVDD, AVDD .................................................................................................................................. 9 6.11 VDD ............................................................................................................................................... 9 6.12 DVSS, AVSS ................................................................................................................................... 9 6.13 VSS ............................................................................................................................................... 9 6.14 VCI ................................................................................................................................................ 9 6.15 VCC ............................................................................................................................................... 9 6.16 C1P, C1N, C3P, C2P, C2N, and C4P ................................................................................................... 9 6.17 VL7 ................................................................................................................................................ 9 i 6.18 VEXT .............................................................................................................................................. 9 6.19 VL7, VL6, VL5, VL4, VL3 and VL2 ....................................................................................................... 9 6.20 COM0 – COM159 ...................................................................................................................... 10 6.21 SEG0 – SEG127........................................................................................................................ 10 6.22 CAP, CAN, CBP, CBN, CCP, CCN, CDP, and CDN ............................................................................... 10 6.23 N/C............................................................................................................................................. 10 7 FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................ 11 7.1 Command Decoder and Command Interface........................................................................ 11 7.2 MPU Parallel 6800-series Interface ........................................................................................ 11 7.3 MPU Parallel 8080-series Interface ........................................................................................ 11 7.4 MPU Serial 4-wire Interface..................................................................................................... 12 7.5 MPU Serial 3-wire interface..................................................................................................... 12 7.6 Graphic Display Data RAM (GDDRAM).................................................................................. 12 7.7 Oscillator Circuit...................................................................................................................... 12 7.8 LCD Driving Voltage Generator and Regulator .................................................................... 13 7.9 288 Bit Latch ............................................................................................................................ 13 7.10 Level selector ........................................................................................................................... 14 7.11 HV Buffer Cell (Level Shifter).................................................................................................. 14 7.12 Default Setting after Reset...................................................................................................... 15 7.13 Command Table....................................................................................................................... 22 7.14 Read Status Byte ..................................................................................................................... 25 7.15 Data Read / Write ..................................................................................................................... 25 8 COMMAND DESCRIPTIONS .......................................................................................................... 26 8.1 Set Lower Column Address [00~0F] ...................................................................................... 26 8.2 Set Higher Column Address [10~17] .................................................................................... 26 8.3 Set Master/Slave Mode [18~19] .............................................................................................. 26 8.4 Set Internal Regulator Resistors Ratio [20~27] .................................................................... 26 ii 9 8.5 Set Power Control Register [28~2F] ...................................................................................... 27 8.6 Set Display Start Line [40~43] ................................................................................................ 27 8.7 Set Display Offset [44~47] ...................................................................................................... 27 8.8 Set Multiplex Ratio [48~4B] .................................................................................................... 27 8.9 Set N-line Inversion [4C~4F]................................................................................................... 28 8.10 Set LCD Bias [50~57]............................................................................................................... 28 8.11 Set Upper Window Corner (ax, ay) [60~61] ........................................................................... 28 8.12 Set Lower Window Corner (bx, by) [62~63] .......................................................................... 28 8.13 Set DC-DC Converter Factor [64~67] ..................................................................................... 28 8.14 Set Contrast Control Register [81]......................................................................................... 28 8.15 Set Gray Scale Mode (White/Light Gray/Dark Gray/Black) [88~8F] .................................... 28 8.16 Set Segment Re-map [A0~A1] ................................................................................................ 29 8.17 Set Entire Display On/Off [A4~A5] ......................................................................................... 29 8.18 Set Normal/Reverse Display [A6~A7] .................................................................................... 29 8.19 Set Power Save Mode [A9]...................................................................................................... 29 8.20 Start Internal Oscillator [AB] .................................................................................................. 29 8.21 Set Display On/Off [AE~AF]................................................................................................... 29 8.22 Set Page Address [B0~BF] .................................................................................................... 29 8.23 Set COM Output Scan Direction [C0~CF].............................................................................. 30 8.24 Exit Power Save Mode [E1]..................................................................................................... 30 8.25 Software Reset [E2] ................................................................................................................. 30 8.26 Exit N-line Inversion [E4] ........................................................................................................ 30 8.27 Enable Scroll Buffer RAM [E6~E7]......................................................................................... 30 8.28 Set Display Data Length [E8].................................................................................................. 30 8.29 Set Temperature Coefficient (TC) Value [E9] ........................................................................ 30 8.30 Set Test Mode [F0~FF] ............................................................................................................ 30 MAXIMUM RATINGS ....................................................................................................................... 31 iii 10 DC CHARACTERISTICS ................................................................................................................. 32 11 AC CHARACTERISTICS ................................................................................................................. 34 12 APPLICATION CIRCUIT.................................................................................................................. 38 13 12.1 DC-DC Converter Circuit Configuration ................................................................................ 39 12.2 Bias Divider Circuit Configuration......................................................................................... 39 12.3 Parallel Interface Configuration (Read / Write) ..................................................................... 40 12.4 Serial Interface Configuration (Write Only)........................................................................... 40 APPENDIXA..................................................................................................................................... 41 iv TABLE OF FIGURES Figure 1 - Block Diagram .............................................................................................................................. 3 Figure 2 - SSD1854Z Pin Assignment .......................................................................................................... 4 Figure 3 - Display Data Read with the insertion of Dummy Read .............................................................. 11 Figure 4 - Oscillator Circuitry....................................................................................................................... 13 Figure 5 - SSD1854 Graphic Display Data RAM (GDDRAM) Address Map .............................................. 16 o Figure 6 - Contrast Control Voltage Range Curve (TC=-0.1%/ C; VDD=2.7V; VCI=2.7V) ........................... 27 Figure 7 - Contrast Control Flow Set Segment Re-map ............................................................................. 28 Figure 8 - Oscillation Frequency at different VDD at 25°C ......................................................................... 34 Figure 9 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) ............................... 35 Figure 10 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) .............................. 36 Figure 11- Serial Timing Characteristics (PS0 = L) .................................................................................... 37 Figure 12 - LCD Pins Connection of SSD1854Z......................................................................................... 38 Figure 13 - SSD1854U COF Drawing 1...................................................................................................... 41 Figure 14 - SSD1854U COF Drawing 2...................................................................................................... 42 LIST OF TABLE Table 1 - Ordering Information ...................................................................................................................... 2 Table 2 - SSD1854 Series Die Pad Coordinates .......................................................................................... 5 Table 3 - PS0-2 Interface .............................................................................................................................. 8 Table 4 - Modes of Operation ..................................................................................................................... 12 Table 5 - Command Table .......................................................................................................................... 22 Table 6 - Read Status Byte ......................................................................................................................... 25 Table 7 - Address Increment Table............................................................................................................. 25 Table 8 - Commands Required for R/W (WR#) Actions on RAM ............................................................... 25 Table 9 - Maximum Ratings ........................................................................................................................ 31 Table 10 - DC Characteristics ..................................................................................................................... 32 Table 11 - AC Characteristics ..................................................................................................................... 34 Table 12 - Parallel Timing Characteristics 1 ............................................................................................... 35 Table 13 - Parallel Timing Characteristics 2 ............................................................................................... 36 Table 14 - Serial Timing Characteristics ..................................................................................................... 37 v SOLOMON SYSTECH LIMITED SEMICONDUCTOR TECHNICAL DATA SSD1854 Advance Information LCD Segment / Common Driver with Controller CMOS 1 General Description SSD1854 is a single-chip CMOS 4 gray scale LCD driver with controller for liquid crystal dot-matrix graphic display system. It consists of 288 high voltage driving output pins for driving maximum 128 Segments and 160 Commons, customized for 2-sides COF modules. SSD1854 displays data directly from its internal 128x176x2 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through a hardware selectable 6800-/8080series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface. SSD1854 designed with multi-line-addressing (MLA) scheme to improve the display quality and reduce the system power consumption. SSD1854 embeds a DC-DC Converter, a LCD Voltage Regulator, an On-Chip Bias Divider and an On-Chip oscillator, which reduce the number of external components. With the special design on minimizing power consumption and die/package layout, SSD1854 is suitable for any portable batterydriven applications requiring a long operation period and a compact size. This document contains information on a new product. Specification and information herein are subject to change without notice. Copyright 2002 SOLOMON Systech Limited Rev 1.0 08/2002 2 FEATURES • 128 x 160 4 gray-levels Graphic Display • Programmable Multiplex ratio (partial display) [16Mux - 160Mux] • Single Supply Operation, 1.8 V - 3.3V • Low Current Sleep Mode (<1.0uA) • On-Chip Voltage Generator / Regulator & Bias Dividers • Software selectable 3X / 4X / 5X On-Chip DC-DC Converter • On-Chip Oscillator • Maximum +17.0V LCD Driving Output Voltage • Hardware pin selectable for 8/16-bit 6800-series Parallel Interface, 8/16-bit 8080-series Parallel Interface, 3-wire Serial Peripheral Interface or 4-wire Serial Peripheral Interface • Software Selectable On-Chip Bias Dividers • On-Chip 128 x 176 x 2 Graphic Display Data RAM • Re-mapping of Row and Column Drivers • Programmable Window with Vertical Scrolling • Display Offset Control • 64 Levels Internal Contrast Control • Maximum 17MHz SPI or 6MHz PPI operation • Selectable LCD Driving Voltage Temperature Coefficients (4 settings) [-0.10%/oC (POR)] 3 ORDERING INFORMATION Table 1 - Ordering Information Ordering Part Number SSD1854Z SSD1854U SSD1854 Series Rev 1.0 08/2002 Seg 128 128 Com 160 160 Package Form Gold Bump Die Die on COF 2 SOLOMON 4 BLOCK DIAGRAM COM0 to COM159 SEG0~SEG127 HV Buffer Cell Level Shifter Level Selector VL7 VL6 VL5 VL4 VL3 VL2 VSS 288 Bit Latch Display Timing Generator VCC LCD Driving Voltage Generator Oscillator OSC1 3X / 4X / 5X DC/DC Converter, Voltage Regulator, Bias Divider, Contrast Control, Temperature Compensation GDDRAM 128 X 160 X 2 Bits C1P C2P C3P C4P C1N C2N REF VCI VEXT CAP CAN CBP CBN CCP CCN CDP CDN Command Decoder VSS VDD DVDD AVDD Command Interface RES# PS0-2 CS# DC RW/ (WR#) Parallel / Serial Interface E (RD#) D8-15 D7 D6 D5 D4 D3 D2 D1 D0 (SDA) (SCK) Figure 1 - Block Diagram 3 SSD1854 Series Rev 1.0 08/2002 SOLOMON DIE Arrangement N/C COM68 COM69 COM70 COM71 : : : : : COM106 COM107 COM108 COM109 N/C 5 Pad324 Size: 94 × 94 um2 Centre: -4455, -928 y x Size: 70 × 70 um2 Centre: 1986, 676 Size: 94 × 94 um2 Centre: 4796, -928 Size: 116 × 116 um2 Centre: 3005, 673 Pad126 COM67 COM66 COM65 COM64 COM63 COM62 COM61 COM60 : : : : : : : : : : COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 : : : : : : : : : : : : : : : : : : : : : : : : : SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 COM110 COM111 COM112 COM113 COM114 : : : : : : : : : : : : : : : : : : : : COM155 COM156 COM157 COM158 COM159 VSS VSS N/C CDN CDP CCN CCP CBN CBP CAN CAP VL7 VL6 VL5 VL4 VL3 VL2 VSS VSS N/C VDD VEXT REF AVSS DVSS VSS C4P C2N C2P C1P C1N C3P VCC VSS VSS VCI AVDD DVDD D15 D14 D13 D12 D11 D10 D9 D8 D7(SDA) D6(SCK) D5 D4 D3 D2 D1 D0 VDD E(RD#) R/W(WR#) VSS D/C RES# VDD CS# N/C VSS PS1 VDD VSS PS2 PS0 N/C OSC1 VDD N/C N/C N/C N/C Note: 1. Diagram showing the die face up. 2. Coordinates are reference to center of the chip. 3. Unit of coordinates and Size of all alignment marks are in um. 4. All alignment keys do not contain gold bump. Chip Size Chip Thickness Bump Size Bump Height X 10.72 Y 2.77 723.9 ± 25 Pad # 1–4 43 – 51 59 – 75 77 – 126 171 – 324 5 – 42 52 – 58 76 127 – 170 325 – 368 Unit mm µm X Y 40 70 µm 50 60 70 40 18 (Typ.) µm Pad1 N/C SEG86 SEG87 SEG88 SEG89 : : : : : : SEG124 SEG125 SEG126 SEG127 N/C Pad171 Figure 2 – SSD1854Z Pin Assignment SSD1854 Series Rev 1.0 08/2002 4 SOLOMON Table 2 - SSD1854 Series Die Pad Coordinates Pad # Pad Name X-pos Y-pos Pad # Pad Name X-pos Y-pos Pad # Pad Name X-pos Y-pos 1 2 3 4 5 6 7 8 9 10 11 12 13 14 N/C N/C N/C N/C VDD OSC1 N/C PS0 PS2 VSS VDD PS1 VSS N/C -4520.2 -4451.6 -4383.0 -4314.4 -4233.3 -4144.2 -4055.1 -3966.0 -3876.9 -3787.8 -3698.7 -3609.6 -3520.5 -3431.4 -1239.7 -1239.7 -1239.7 -1239.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VSS DVSS AVSS REF VEXT VDD N/C VSS VSS VL2 VL3 VL4 VL5 VL6 -287.1 -206.0 -106.7 -7.5 81.6 170.7 259.8 348.9 430.0 499.4 568.0 636.6 705.2 773.8 -1239.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1239.7 -1239.7 -1239.7 -1239.7 -1239.7 -1239.7 101 102 103 104 105 106 107 108 109 110 111 112 113 114 COM135 COM134 COM133 COM132 COM131 COM130 COM129 COM128 COM127 COM126 COM125 COM124 COM123 COM122 3223.1 3282.5 3341.9 3401.3 3460.7 3520.1 3579.5 3638.9 3698.3 3757.7 3817.1 3876.5 3935.9 3995.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 15 16 CS VDD -3342.3 -3253.2 -1243.7 -1243.7 65 66 VL7 CAP 868.4 963.0 -1239.7 -1239.7 115 116 COM121 COM120 4054.7 4114.1 -1214.3 -1214.3 17 RES -3164.1 -1243.7 67 CAN 1031.6 -1239.7 117 COM119 4173.5 -1214.3 18 19 D/ C -3075.0 -2985.9 -1243.7 -1243.7 68 69 CBP CBN 1100.3 1168.8 -1239.7 -1239.7 118 119 COM118 COM117 4232.9 4292.3 -1214.3 -1214.3 20 ( WR ) -2896.8 -1243.7 70 CCP 1237.4 -1239.7 120 COM116 4351.7 -1214.3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 E( RD ) -2807.7 -2718.6 -2629.5 -2540.4 -2451.3 -2362.2 -2273.1 -2184.0 -2094.9 -2005.8 -1916.7 -1827.6 -1738.5 -1649.4 -1560.3 -1471.2 -1382.1 -1293.0 -1203.9 -1104.7 -1005.5 -916.4 -835.9 -767.3 -698.7 -630.1 -561.5 -492.9 -424.3 -355.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1243.7 -1239.7 -1239.7 -1239.7 -1239.7 -1239.7 -1239.7 -1239.7 -1239.7 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 CCN CDP CDN N/C VSS VSS COM159 COM158 COM157 COM156 COM155 COM154 COM153 COM152 COM151 COM150 COM149 COM147 COM147 COM146 COM145 COM144 COM143 COM142 COM141 COM140 COM139 COM138 COM137 COM136 1306.0 1374.6 1443.2 1511.8 1580.4 1661.5 1797.5 1856.9 1916.3 1975.7 2035.1 2094.5 2153.9 2213.3 2272.7 2332.1 2391.5 2450.9 2510.3 2569.7 2629.1 2688.5 2747.9 2807.3 2866.7 2926.1 2985.5 3044.9 3104.3 3163.7 -1239.7 -1239.7 -1239.7 -1239.7 -1239.7 -1243.7 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 COM115 COM114 COM113 COM112 COM111 COM110 N/C COM109 COM108 COM107 COM106 COM105 COM104 COM103 COM102 COM101 COM100 COM99 COM98 COM97 COM96 COM95 COM94 COM93 COM92 COM91 COM90 COM89 COM88 COM87 4411.1 4470.5 4529.9 4589.3 4648.7 4708.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1214.3 -1277.1 -1217.7 -1158.3 -1098.9 -1039.5 -980.1 -920.7 -861.3 -801.9 -742.5 -683.1 -623.7 -564.3 -504.9 -445.5 -386.1 -326.7 -267.3 -207.9 -148.5 -89.1 -29.7 29.7 89.1 VSS R/ W 5 SSD1854 Series VDD D0 D1 D2 D3 D4 D5 D6 (SCK) D7 (SDA) D8 D9 D10 D11 D12 D13 D14 D15 DVDD AVDD VCI VSS VSS VCC C3P C1N C1P C2P C2N C4P Rev 1.0 08/2002 SOLOMON Pad # Pad Name X-pos Y-pos Pad # Pad Name X-pos Y-pos Pad # Pad Name X-pos Y-pos 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 COM86 COM85 COM84 COM83 COM82 COM81 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 COM71 COM70 COM69 COM68 N/C COM67 COM66 COM65 COM64 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 5192.1 4708.1 4648.7 4589.3 4529.9 4470.5 4411.1 4351.7 4292.3 4232.9 4173.5 4114.1 4054.7 3995.3 3935.9 3876.5 3817.1 3757.7 3698.3 3638.9 3579.5 3520.1 3460.7 3401.3 3341.9 3282.5 3223.1 3163.7 3104.3 3044.9 2985.5 148.5 207.9 267.3 326.7 386.1 445.5 504.9 564.3 623.7 683.1 742.5 801.9 861.3 920.7 980.1 1039.5 1098.9 1158.3 1217.7 1277.1 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 2926.1 2866.7 2807.3 2747.9 2688.5 2629.1 2569.7 2510.3 2450.9 2391.5 2332.1 2272.7 2213.3 2153.9 2094.5 2035.1 1975.7 1916.3 1856.9 1797.5 1738.1 1678.7 1619.3 1559.9 1500.5 1441.1 1381.7 1322.3 1262.9 1203.5 1144.1 1084.7 1025.3 965.9 906.5 847.1 787.7 728.3 550.1 490.7 431.3 371.9 312.5 253.1 193.7 134.3 74.9 15.5 -43.9 -103.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 -162.7 -222.1 -281.5 -340.9 -400.3 -459.7 -519.1 -578.5 -637.9 -697.3 -756.7 -816.1 -875.5 -934.9 -994.3 -1053.7 -1113.1 -1172.5 -1231.9 -1291.3 -1350.7 -1410.1 -1469.5 -1528.9 -1588.3 -1647.7 -1707.1 -1766.5 -1825.9 -1885.3 -1944.7 -2004.1 -2063.5 -2122.9 -2182.3 -2241.7 -2301.1 -2360.5 -2419.9 -2479.3 -2538.7 -2598.1 -2657.5 -2716.9 -2776.3 -2835.7 -2895.1 -2954.5 -3013.9 -3073.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 SSD1854 Series Rev 1.0 08/2002 6 SOLOMON 7 Pad # Pad Name X-pos Y-pos 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 N/C SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 -3132.7 -3192.1 -3251.5 -3310.9 -3370.3 -3429.7 -3489.1 -3548.5 -3607.9 -3667.3 -3726.7 -3786.1 -3845.5 -3904.9 -3964.3 -4023.7 -4083.1 -4142.5 -4201.9 -4261.3 -4320.7 -4380.1 -4439.5 -4498.9 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1214.3 1277.1 1217.7 1158.3 1098.9 1039.5 980.1 920.7 861.3 801.9 742.5 683.1 623.7 564.3 504.9 445.5 386.1 326.7 267.3 207.9 148.5 89.1 29.7 -29.7 -89.1 -148.5 -207.9 SSD1854 Series Rev 1.0 08/2002 Pad # Pad Name X-pos Y-pos 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 N/C -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -5192.1 -267.3 -326.7 -386.1 -445.5 -504.9 -564.3 -623.7 -683.1 -742.5 -801.9 -861.3 -920.7 -980.1 -1039.5 -1098.9 -1158.3 -1217.7 -1277.1 Y Pad324 Pad171 X SSD1854 IC Pad126 Pad1 Pad Pitch Pad Space Pad # 1–4 43 – 51 60 – 64 66 – 75 4–5 51 – 52 58 – 59 75 – 76 5 – 39 41 – 42 54 – 58 39 – 41 53 – 54 42 – 43 52 – 53 59 – 60 64 – 66 76 – 77 77 – 126 127 – 170 171 – 238 239 – 324 325 – 368 238 – 239 Diff. Unit 68.6 81.1 89.1 99.2 µm 80.6 99.3 69.5 94.6 136 59.4 178.2 19.4 (min) µm SOLOMON 6 PIN DESCRIPTION 6.1 RES This pin is reset signal input. When the pin is low, initialization of the chip is executed. 6.2 PS0-2 These 3 pins use together to determine the interface protocol between the driver and MCU according to the following table. Table 3 - PS0-2 Interface PS0 PS1 PS2 Interface L L X 3-wire SPI (write only) L H H L H H 6.3 X 4-wire SPI (write only) H 8080 parallel interface (8-bits read and 16-bits write) L 8080 parallel interface (8-bits read and 8-bits write) H 6800 parallel interface (8-bits read and 16-bits write) L 6800 parallel interface (8-bits read and 8-bits write) CS This pin is chip select input. The chip is enabled for display data/command transfer only when CS is low. For 6800-series parallel mode, when E pin is pulled high, the read/write cycle is initiated by pulling low of this CS pin. 6.4 D/ C This input pin is to identify display data/command cycle. When the pin is high, the data written to the driver will be written into display RAM. When the pin is low, the data will be interpreted as command. This pin must be connected to VSS when 3-lines SPI interface is used. 6.5 R/ W ( WR ) This pin is microprocessor interface signal. When interfacing to an 6800-series microprocessor, the signal indicates read mode when high and write mode when low. When interfacing to an 8080microprocessor, a data write operation is initiated when R/W ( WR ) is low and the chip is selected. 6.6 E( RD ) This pin is microprocessor interface signal. When interfacing to an 6800-series microprocessor, a data operation is initiated when E( RD ) is high and the chip is selected. When interfacing to an 8080microprocessor, a data read operation is initiated when E( RD ) is low and the chip is selected. 6.7 D0 -D15 D0-D7 are bi-directional and D8-D15 are input only data pins to be connected to the microprocessor’s data bus. When serial mode is selected, D7 is the serial data input SDA and D6 is the serial clock input SCK. All unused data pins must be connected to ground. SSD1854 Series Rev 1.0 08/2002 8 SOLOMON 6.8 OSC1 This pin is for oscillator frequency selection. A resistor must be connected between this pin and VDD when using the internal oscillator. The suggested value of the resistor is 680K ohm. Please refer to the Figure 8 for details. 6.9 REF This pin is an input pin to enable the internal reference voltage used for the internal regulator. When it is high, an internal reference voltage source will be used. When it is low, and external reference must be provided in VEXT. 6.10 DVDD, AVDD Digital and Analog power supply pins, must be connected to same external source. 6.11 VDD Internally connected to DVDD for pull high purpose. Can be connected to DVDD externally or float. 6.12 DVSS, AVSS Digital and Analog ground, must be connected to external ground. 6.13 VSS Internally connected to DVSS for pull low purpose. 6.14 VCI Reference voltage input for internal DC-DC converter. The voltage of generated VCC equals to the multiple factor (3X, 4X or 5X) times VCI with respect to VSS. Note: Voltage at this input pin must be larger than or equal to AVDD and DVDD. 6.15 VCC Voltage at this pin must be greater then VL4 + 2V. It can be supplied externally or generated by the internal DC-DC converter. When using internal DC-DC converter as generator, voltage at this pin is for internal reference only. It CANNOT be used for driving external circuitries. 6.16 C1P, C1N, C3P, C2P, C2N, and C4P When internal DC-DC voltage converter is used, external capacitor(s) is/are connected among these pins. 6.17 VL7 This pin is the most positive LCD driving voltage. It can be generated by the internal regulator or supply externally when internal regulator and divider are turned off. 6.18 VEXT This pin is an input to provide an external voltage reference for the internal voltage regulator when REF pin is pulled low. 6.19 VL7, VL6, VL5, VL4, VL3 and VL2 LCD driving voltages. They can be supplied externally or generated by the internal regulator and divider or supplied externally when regulator and divider are turned off. They have the following relationship: VL7 > VL6 > VL5 > VL4 > VL3 > VL2 > VSS 9 SSD1854 Series Rev 1.0 08/2002 SOLOMON 6.20 COM0 – COM159 These pins provide the row driving signal COM0 – COM159 to the LCD panel. 6.21 SEG0 – SEG127 These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode. 6.22 CAP, CAN, CBP, CBN, CCP, CCN, CDP, and CDN These pins are connected to four capacitors when internal divider is enabled. 6.23 N/C These No Connection pins should NOT be connected to any signals nor shorted together. These N/C pins should be left open. SSD1854 Series Rev 1.0 08/2002 10 SOLOMON 7 FUNCTIONAL BLOCK DESCRIPTIONS 7.1 Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/ C pin. If D/ C is high, data is written to Graphic Display Data RAM (GDDRAM). If D/ C is low, the input at D0-D15 is interpreted as a Command and it will be decoded and written to the corresponding command register. Reset is of the same function as Power ON Reset (POR). Once RES receives a negative reset pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command Description section for more information. 7.2 MPU Parallel 6800-series Interface The parallel interface consists of 8/16 data pins (D0 - D15), R/ W( WR ), D/ C , E( RD ) and CS . R/ W ( WR ) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/ W( WR ) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/ C input. The E( RD ) and CS input serves as data latch signal (clock) when they are high and low respectively. Refer to Figure 9 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 3 below. R/W(WR) E(RD) data bus N writ e column address n dummy read data read1 n+1 n+2 data read 2 data read 3 Figure 3 – Display Data Read with the insertion of Dummy Read 7.3 MPU Parallel 8080-series Interface The parallel interface consists of 8/16 data pins (D0-D15), R/ W( WR ), E( RD ), D/ C and CS . The CS input serves as data latch signal (clock) when it is low. Whether it is display data or status register read is controlled by D/ C . R/ W( WR ) and E( RD ) input indicates a write or read cycle when CS is low. Refer to Figure 10 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read. 11 SSD1854 Series Rev 1.0 08/2002 SOLOMON 7.4 MPU Serial 4-wire Interface The serial interface consists of serial clock SCK, serial data SDA, D/ C and CS . SDA is shifted into an 8-bit shift register on every rising edge of SCL in the order of D7, D6, ... D0. D/ C is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. No extra clock or command is required to end the transmission. 7.5 MPU Serial 3-wire interface Operation is similar to 4-wire serial interface while D/ C is not been used. The Display Data Length instruction is used to indicate that a specified number display data byte(s) (1-256) are to be transmitted. Next byte after the display data string is handled as a command. It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in the serial communication, a hardware reset pulse at RES pin is required to initialize the chip for re-synchronization. Table 4 -Modes of Operation 6800 Parallel 8080 Parallel Serial Data Read 8-bitys 8-bits No Data Write 8/16-bits 8/16-bits 8-bits Command Read Status only Status only No Command Write Yes Yes Yes 7.6 Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 x 176 x 2 = 45,056bits. Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs are provided. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the RAM data to be mapped to the display. Figure 5 shows the case in which the display start line register is set at 30H. For those GDDRAM out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage. 7.7 Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator. SSD1854 Series Rev 1.0 08/2002 12 SOLOMON Oscillator enable enable enable Oscillation Circuit Buffer (CL) Internal Resistor OSC1 OSCE Figure 4 - Oscillator Circuitry 7.8 LCD Driving Voltage Generator and Regulator This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of: 1. 3X, 4X and 5X DC-DC voltage converter: The booster output at VCC equals to n time VCI where n is the booster ration. The VCC voltage must be greater than 2V + VL4 or 2V + ½ VL7. Please refer to application notes for details. 2. Voltage Regulator Feedback gain control for initial LCD voltage. Internal resistors are connected between VSS and VR (internal contrast voltage reference), and between VR and VL7. These resistors are chosen to give the desired VL7 according to the following equation: R2 V L 7 = 1 + × Vcon R1 and (63 − α ) Vcon = 1 − × Vref 210 where: Vref is the internally generated reference voltage (1+R2/R1) is the software programmable IRS value α is the software contrast level from 0 to 63 3. 4. 5. 6. 7.9 Bias Divider There is an on-chip bias divider inside the chip selected by software which generate all VL2~VL7 levels automatically. Contrast Control Software control of 64 voltage levels of LCD voltage. Bias Ratio Selection circuitry Software control of different bias ratios to match the characteristic of LCD panel. Self adjust temperature compensation circuitry Provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Defaulted temperature coefficient (TC) value is -0.1%/°C. 288 Bit Latch A register carries the display signal information. In 128 X 160 display-mode, data will be fed to the HV-buffer Cell and level-shifted to the required level. 13 SSD1854 Series Rev 1.0 08/2002 SOLOMON 7.10 Level selector Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform. 7.11 HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter which translated the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock, which comes from the Display Timing Generator. The voltage levels are given by the level selector, which is synchronized with the internal M signal. For a panel with N rows and M columns, the optimal LCD driving voltage are given as: N N × × Vth 4 2 N −1 4 × (VL 7 − VL 4 ) = VL 4 − VL 2 = N VL 7 − VL 4 = VL 4 − VSS = VL 6 − V L 4 ( ) And VL 5 − VL 4 = V L 4 − VL 3 = V L 6 − VL 4 2 where: Vth is the threshold voltage of the LCD panel VL7 is the maximum (Row) driving level with reference to VSS (The peak-to-peak Row driving voltage is given by VL7-VSS) VL4 is the middle of all driving levels VL6, VL5, VL3 and VL2 are the other Column driving levels (The peak-to-peak Column driving voltage is given by VL6-VSS) Relationship between the levels: VL7 > VL6 > VL5 > VL4 > VL3 > VL2 > VSS and VCC > VL4 + 2V SSD1854 Series Rev 1.0 08/2002 14 SOLOMON 7.12 Default Setting after Reset When RES input is low, the chip is initialized to the following: Register Default Value Descriptions Page address 0 Column address 0 Display ON/OFF 0 Display OFF Display Start Line 0 GDDRAM page 0,D0 Display Offset 0 COM0 is mapped to ROW0 Mux Ratio A0H 160 Mux Normal/Reverse Display 0 Normal Display N-line Inversion 0 No N-line Inversion Entire Display 0 Entire Display is OFF Power Control 0,0,0 Booster, regulator & divider are both disabled DC-DC booster 0 3X booster is selected Internal Resistor Ratio 0 Gain = 3.2 (IR0) Contrast 20H Middle LCD Bias Ratio 6 Optimized for 160 Mux Scan direction of COM 0 Normal Scan direction Segment Re-map 0 Segment re-map is disabled Internal oscillator 0 Internal oscillator is OFF Power save mode 0 Power save mode is OFF Data display length 0 FRC, PWM Mode 0 4FRC, 9PWM White Palette (0, 0, 0, 0) Light Gray Palette (0, 0, 0, 0) Dark Gray Palette (9, 9, 9, 9) Black Palette (9, 9, 9, 9) Test mode 0 Test mode is OFF o Temperature coefficient 2 TC2 (-0.1%/ C) Upper window corner 0,0 Lower window corner 127,159 When RESET command is issued, the following parameters are initialized only: Register Default Value Descriptions Page address 0 Column address 0 Display Start Line 0 GDDRAM page 0,D0 Internal Resistor Ratio 0 Gain = 3.2 (IR0) Contrast 20H Data display length 0 FRC, PWM Mode 0 4FRC, 9PWM White Palette (0, 0, 0, 0) Light Gray Palette (0, 0, 0, 0) Dark Gray Palette (9, 9, 9, 9) Black Palette (9, 9, 9, 9) 15 SSD1854 Series Rev 1.0 08/2002 SOLOMON 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• - - •••••• 51 50 49 48 47 46 45 44 43 42 41 40 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 123 124 125 126 127 128 129 130 131 132 133 134 140 141 142 143 144 145 - 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 Remappe Normal Remappe Normal Normal Remappe Remappe Normal 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 36 35 34 33 32 31 30 29 28 27 26 25 19 18 17 16 15 14 - 127 128 129 130 131 132 133 134 135 136 137 138 145 146 147 148 149 150 - •••• 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 159 158 157 156 155 154 23 22 21 20 153 152 151 150 149 148 •••• 108 109 110 111 112 113 114 115 116 117 118 119 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• 00h 01h 02h 03h 04h 05h 0 1 2 3 4 5 136 137 138 139 6 7 8 9 10 11 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) Int. Col. Addr. 3 2 1 0 159 158 157 156 155 154 153 152 151 150 149 148 •••• Int. Row Addr 156 157 158 159 0 1 2 3 4 5 6 7 8 9 10 11 •••• Note : 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 •••• Page 21 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 •••• Page 20 •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••••• •••• Page 19 7Fh 00h 127 5* 146 05h (0,6) (127,139) 5 •••• Page 18 7Eh 01h 126 •••• Page 17 7Dh 02h 125 •••• Page 16 •••••• •••••• •••••• Common Output Pins 2 3 4 146 160 160 14h 14h 05h (0,6) (0,0) (0,6) (127,159) (127,139) (127,139) 0 0 0 Remappe Page 3 02h 7Dh 2 1 160 00h (0,0) (127,159) 0 Normal Page 2 01h 7Eh 1 •••• A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh Page 1 •••• •••• 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Page 0 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) First Byte 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 00h 7Fh 0 Second Byte Column Seg Normal Address Seg Remapped Segment Output Pins Example Multiplex Ratio Display Start Line Upper Window Corner Lower Window Corner Display Offset 135 136 137 138 139 - 24 23 22 21 20 - 140 141 142 143 144 - 19 18 17 16 15 - 32 31 30 29 28 27 26 25 24 23 22 21 14 13 12 11 10 9 - FAh FBh FCh FDh FEh FFh * COM4 & COM151 display OFF pixels disregard the RAM content. Figure 5 - SSD1854 Graphic Display Data RAM (GDDRAM) Address Map SSD1854 Series Rev 1.0 08/2002 16 SOLOMON Example 1 – Display Start Line = 0, Multiplex Ratio = 160, Display Offset = 0. Upper Window Row = (0,0), Lower Window Row = (127,159) 17 SSD1854 Series Rev 1.0 08/2002 SOLOMON Example 2 – Display Start Line = 14h, Multiplex Ratio = 160, Display Offset = 0. Upper Window Row = (0,0), Lower Window Row = (127,159) SSD1854 Series Rev 1.0 08/2002 18 SOLOMON Example 3 – Display Start Line = 14h, Multiplex Ratio = 160, Display Offset = 0. Upper Window Row = (0,6), Lower Window Row = (127,139) 19 SSD1854 Series Rev 1.0 08/2002 SOLOMON Example 4 – Display Start Line = 5, Multiplex Ratio = 146, Display Offset = 0. Upper Window Row = (0,6), Lower Window Row = (127,139) SSD1854 Series Rev 1.0 08/2002 20 SOLOMON Example 5 – Display Start Line = 5, Multiplex Ratio = 146, Display Offset = 5. Upper Window Row = (0,6), Lower Window Row = (127,139) 21 SSD1854 Series Rev 1.0 08/2002 SOLOMON 7.13 Command Table Table 5 - COMMAND TABLE Hex 00~0F Bit Pattern 0000 C3C2C1C0 10~17 0001 0C6C5C4 18~19 0001 100M0 1A~1F 20~27 0010 0R2R1R0 28~2F 0010 1VCVRVF 30~3F 40~43 Command Set Lower Column Address Set Upper Column Address Set Master/Slave Mode Reserved Set Internal Regulator Resistor Ratio Set Power Control Register 0100 00XX L7L6L5L4 L3L2L1L0 Reserved Set Display Start Line 44~47 0100 01XX C7C6C5C4 C3C2C1C0 Set Display Offset 48~4B 0100 10XX D7D6D5D4 D3D2D1D0 Set Multiplex Ratio 4C~4F 0100 11XX XXN5N4 N3N2N1N0 Set N-line Inversion 50~57 0101 0B2B1B0 Set LCD Bias 58~5F SSD1854 Series Reserved Rev 1.0 08/2002 Description Set the lower nibble of the column address pointer for RAM access. The pointer is reset to 0 after reset. Set the upper nibble of the column address pointer for RAM access. The pointer is reset to 0 after reset. M0=0: Master operation mode (POR) M0=1: Slave operation mode Reserved The internal regulator gain increases as R2R1R0 is increased from 000b to 111b. The factor, 1+R2/R1, is given by: R2R1R0 = 000: 3.2 (POR) R2R1R0 = 001: 3.9 R2R1R0 = 010: 4.6 R2R1R0 = 011: 5.3 R2R1R0 = 100: 6.0 R2R1R0 = 101: 6.7 R2R1R0 = 110: 7.4 R2R1R0 = 111: 8.1 (Refer to section 8.4) VC=0: turn OFF the internal voltage booster (POR) VC=1: turn ON the internal voltage booster VR=0: turn OFF the internal regulator (POR) VR=1: turn ON the internal regulator VF=0: turn OFF the output op-amp buffer (POR) VF=1: turn ON the output op-amp buffer Reserved The second command specifies the row address pointer of the RAM data to be displayed in first row of window. The value must be within 0 to window row number + 15. See the RAM Mapping Table for examples. The second command specifies the mapping of first display line (COM0) to one of ROW0~159. COM0 is mapped to ROW0 after reset. The second command specifies the number of lines to be displayed. Duties 1/16~1/160 could be selected. The duty ratio is set to 1/160 after reset. See the Ram Mapping Table for examples. The second command sets the n-line inversion register from 1 to 63 lines to reduce display crosstalk. Register values from 00001b to 11111b are mapped to 1 line to 63 lines respectively. Value 00000b disables the N-line inversion. Sets the LCD bias corresponding to different mux number. B2B1B0: 000: 32mux 010: 96mux 100: 128mux 110: 160mux (POR) Reserved 22 SOLOMON 60 0110 0000 0A6A5A4 A3A2A1A0 61 0110 0001 A7A6A5A4 A3A2A1A0 62 0110 0010 0B6B5B4 B3B2B1B0 63 0110 0011 B7B6B5B4 B3B2B1B0 64~67 0110 01B1B0 68~80 81 1000 0001 XXC5C4 C3C2C1C0 82~87 88 1000 1000 89 1000 1001 8A 1000 1010 WB3WB2WB1WB0 WA3WA2WA1WA0 WD3WD2WD1WD0 WC3WC2WC1WC0 LB3LB2LB1LB0 LA3LA2LA1LA0 8B 1000 1011 LD3LD2LD1LD0 LC3LC2LC1LC0 8C 1000 1100 DB3DB2DB1DB0 DA3DA2DA1DA0 8D 1000 1101 DD3DD2DD1DD0 DC3DC2DC1DC0 8E 1000 1110 BB3BB2BB1BB0 BA3BA2BA1BA0 8F 1000 1111 BD3BD2BD1BD0 BC3BC2BC1BC0 90~97 1001 0 FRC PWM1 PWM0 98~9F A0~A1 1010 000S0 A2~A3 A4~A5 1010 010E0 23 SSD1854 Series Rev 1.0 08/2002 Set Upper Window Corner ax Set Upper Window Corner ay Set Lower Window Corner bx Set Lower Window Corner by Set DC-DC Converter Factor Reserved Set Contrast Control Register Reserved Set White Mode, nd st Frame 2 & 1 Set White Mode, th rd Frame 4 & 3 Set Light Gray nd Mode, Frame 2 st &1 Set Light Gray th Mode, Frame 4 rd &3 Set Dark Gray nd Mode, Frame 2 st &1 Set Dark Gray th Mode, Frame 4 rd &3 Set Black Mode, nd st Frame 2 & 1 Set Black Mode, th rd Frame 4 & 3 Set PWM and FRC Reserved Set Segment Remap Reserved Set Entire Display On/Off The second command sets the first column of the scroll window. It is set to 0 after POR. The second command sets the first row of the scroll window. It is set to 0 after POR. The second command sets the last column of the scroll window. It is set to 0 after POR. The second command sets the last row of the scroll window. It is set to 0 after POR. Set the DC-DC multiplying factor from 3X to 5X according to B1B0. B1B0: 00: 3X (POR) 01: 4X 10: 5X 11: 5X Reserved The second command sets one of the 64 contrast levels. The darkness increase as the contrast level increase. Reserved Grey palette programming. These are two-byte commands used to specify the contrast levels for the gray scale, 4 levels available. The relationship between gray mode and data in RAM is as follow: Memory Content st Gray Mode nd 1 Byte 2 Byte 0 0 1 1 0 1 0 1 White Light gray Dark gray Black Set PWM and FRC for gray-scale operation. FRC = 0: 4-frames (POR) FRC = 1: 3-frames PWM = 00: 9-levels (POR) PWM = 01: 9-levels PWM = 10: 12-levels PWM = 11: 15-levels Reserved S0=0: column address 00H is mapped to SEG0 (POR) S0=1: column address 7FH is mapped to SEG0 Reserved E0=0: Normal display (display according to RAM contents, POR) E0=1: All pixels are ON regardless of the RAM contents SOLOMON A6~A7 1010 011R0 A8 A9 1010 1001 Reversed Set Power Save Mode AA AB 1010 1011 Reserved Start Internal Oscillator AE~AF 1010 111D0 B0~BF 1011 XXXX 000P4 P3P2P1P0 C0~CF 1100 S0XXX D0~E0 E1 1110 0001 E2 E3 E4 E5 E6~E7 1110 0010 1110 0100 1110 011 S0 Set Normal/Reverse Display Set Display On/Off Set Page Address Set COM Output Scan Direction Reserved Exit Power-save Mode Software Reset Reserved Exit N-line Inversion Reserved Enable Scroll Buffer RAM E8 1110 1000 D7D6D5D4 D3D2D1D0 Set Display Data Length E9 0011 1001 XXXX XT2T1T0 Set TC value EA~EF F0~FF SSD1854 Series 1111 XXXX Rev 1.0 08/2002 Reserved Extended Features R0=0: Normal display (display according to RAM contents, POR) R0=1: Reverse display (ON and OFF pixels are inverted) Reversed Oscillator: OFF LCD Power Supply: OFF COM/SEG Outputs: VSS Reserved This command starts the internal oscillator. Note that the oscillator is OFF after reset, until this command is issued. D0=0: Display OFF (POR) D0=1: Display ON Selects the page of display RAM to be addressed. The second command specifies the page address pointer (0~21) of the RAM data to be written. The values other than (0~21) are reversed. S0=0: Normal mode (POR) S0=1: Remapped mode (COM0 to COM[N-1] becomes COM159 to COM[159-N+1]) Reserved Return the driver/controller from the sleep mode. Initialize some internal registers. Reserved Release the driver/controller from N-line inversion mode. Reserved This command enable/disable the use of RAM page 20 and 21 during scrolling. S0=0: Enable Scroll Buffer RAM (POR) S0=1: Disable Scroll Buffer RAM This command is used in 3-line SPI mode (PS0=PS1=L). The next command specifies the number of bytes (1 to 256 bytes) of display data to be written after this composite command. D7~D0=00; 1byte | | D7~D0=FF; 256bytes This command selects the Temperature Coefficient setting for fitting different LCD panel characteristics. T2T1T0: o 000: -0.05%/ C (TC0) 001: Reserved o 010: -0.10%/ C (TC2, POR) 011: Reserved o 100: -0.15%/ C (TC4) 101: Reserved o 110: -0.21%/ C (TC6) 111: Reserved Reserved Test mode commands and Extended features 24 SOLOMON 7.14 Read Status Byte An 8 bits status byte will be placed to the data bus if a read operation is performed if D/ C is low. The status byte is defined as follow. Table 6 - Read Status Byte D7 D6 D5 D4 D3 D2 D1 D0 Command BUSY ON RES 0 1 0 1 1 Read Status Comment BUSY=0: Chip is idle BUSY=1: Chip is executing instruction ON=0: Display is OFF ON=1: Display is ON RES=0: Chip is idle RES=1: Chip is executing reset 7.15 Data Read / Write To read data from the GDDRAM, input High to R/ W( WR ) pin and D/ C pin for 6800-series parallel mode. Low to E( RD ) pin and High to D/ C pin for 8080-series parallel mode. A complete data read cycle must issue two clocks to read both First Byte and Second Byte from GDDRAM. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each complete data read cycle. Also, a dummy read is required before the first data is read. See Figure 3 in Functional Description. To write data to the GDDRAM, input Low to R/ W( WR ) pin and High to D/ C pin for 6800-series parallel mode. High to E( RD ) pin and Low to D/ C pin for 8080-series parallel mode. A complete data write cycle must issue two clocks to write both First Byte and Second Byte to GDDRAM. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each complete data write cycle. The column address will be reset to 0 in next data read/write operation is executed when it is 127. Table 7 - Address Increment Table (Automatic) D/ C R/ W ( WR ) Comment Address Increment 0 0 1 1 0 1 0 1 Write Command Read Status Write Data Read Data No No Yes Yes Address Increment is done automatically after two data read/write. The column address pointer of GDDRAM is also affected. It will be reset to 0 after 127. It should be noted that the page address will NOT be changed when this warp round happens. Table 8 - Commands Required for R/ W ( WR ) Actions on RAM R/ W ( WR ) Actions on RAMs Commands Required Read/write Data from/to GDDRAM Set GDDRAM Page Address Set GDDRAM Column Address Read/Write Data (1011XXXX)* (X7X6X5X4X3X2X1X0)* (00010X2X1X0)* (0000X3X2X1X0)* (X7X6X5X4X3X2X1X0) * No need to resend the command again if it is set previously. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content whether the target RAM content is being displayed or not. 25 SSD1854 Series Rev 1.0 08/2002 SOLOMON 8 COMMAND DESCRIPTIONS 8.1 Set Lower Column Address [00~0F] This command specifies the lower nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>127). 8.2 Set Higher Column Address [10~17] This command specifies the higher nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>127). 8.3 Set Master/Slave Mode [18~19] This command is used in Cascade function, programming the driver into slave mode. The Osc clock and M clock (frame) will be received externally to synchronize the COM/SEG waveform. 8.4 Set Internal Regulator Resistors Ratio [20~27] This command is to enable any one of the eight internal resistor (IRS) settings for different regulator gains when using internal regulator resistor network. The Contrast Control Voltage Range curves is referred to the following formula: R Vout = 1 + 2 *Vcon R1 63 − α Vcon = 1 − * Vref 210 SSD1854 Series Rev 1.0 08/2002 , where Vref = 2.1V 26 SOLOMON VL7 (V) Contrast Cruve 16 14 12 10 8 6 4 2 0 IRS Setting 000 001 010 011 100 101 110 0 20 40 Contrast [0~63] 111 60 o Figure 6 - Contrast Control Voltage Range Curve (TC=-0.1%/ C; VDD=2.7V; VCI=2.7V) 8.5 Set Power Control Register [28~2F] This command turns on/off the various power circuits associated with the chip. All the function blocks can be turn-on independently, but a 10ms-time must be wait between turn ON the Regulator and Divider. 8.6 Set Display Start Line [40~43] The second byte sent specifies which row of the RAM is to be displayed in the first row of window defined by Set Upper/Lower Window Corner commands. Vertical window scrolling is achieved by setting this value from 0 up to window row number + 15. The content outside the Upper and Lower Window Row will not be affected. Refer to Page 21, example 5 for more information. 8.7 Set Display Offset [44~47] The second byte sent specifies the mapping of display start line (COM0 if display start line register equals to 0) to one of ROW0-159. COM0 is mapped to ROW0 after reset. 8.8 Set Multiplex Ratio [48~4B] This command switches default 160 multiplex modes to any multiplex from 16 to 160. The chip pads ROW0-ROW159 will be switched to corresponding COM signal output. Examples were given in the RAM map table. If the input value is not a number of 160, 128, 64 or 32, the higher number of mux will be applied to the COMx pins and the RAM content of the additional lines will be masked out from the display. Thus the actual display effect will be equal to the input value. Suitable bias ration must be set by using Set LCD Bias command after this command is issued. 27 SSD1854 Series Rev 1.0 08/2002 SOLOMON 8.9 Set N-line Inversion [4C~4F] Number of line inversion is set by this command for reducing crosstalk noise. 1 to 63-line inversion operations could be selected. At POR, this operation is disabled. 8.10 Set LCD Bias [50~57] This command selects a suitable bias ratio required for driving the particular LCD panel in use. The POR default for SSD1854 is et to the optimization for 160 mux display mode. 8.11 Set Upper Window Corner (ax, ay) [60~61] These commands are used to define the upper left corner of the window for vertical scrolling. After POR, these registers are set to (0, 0). The actual window position will be offset by the Set Display Offset command. 8.12 Set Lower Window Corner (bx, by) [62~63] These commands are used to define the lower right corner of the window for vertical scrolling. After POR, these registers are set to (127, 159). These registers must be smaller than the multiplex ration as defined by Set Multiplex Ratio. 8.13 Set DC-DC Converter Factor [64~67] Internal DC-DC converter factor is set by this command. For SSD1854, 3X to 5X multiplying factors could be selected. 8.14 Set Contrast Control Register [81] This command adjusts the contrast of the LCD panel by changing VL7 of the LCD drive voltage provided by the On-Chip power circuits. VL7 is set with 64 steps (6-bit) contrast control register. It is a compound commands: Set Contrast Control Register Contrast Level Data No Changes Complete? Yes Figure 7 - Contrast Control Flow Set Segment Re-map 8.15 Set Gray Scale Mode (White/Light Gray/Dark Gray/Black mode) [88~8F] Four gray scale modes – White, Light gray, Dark gray and Black – can be set. Each consists of four registers namely A, B, C and D which correspond to four frames in FRC. Each of the 4-bits in register A, B, C and D are used to define the width of PWM. SSD1854 Series Rev 1.0 08/2002 28 SOLOMON For 4 FRC, Memory Content st nd 1 Byte 2 Byte 0 0 0 1 1 0 1 1 Gray Mode White Light Gray Dark Gray Black st 2 WB LB DB BB st 2 WB LB DB BB 1 WA LA DA BA nd FRAME rd 4 WD LD DD BD th rd 4 (No use) WD (XX) LD (XX) DC (XX) BC (XX) 3 WC LC DC BC For 3 FRC, Memory Content st nd 1 Byte 2 Byte 0 0 0 1 1 0 1 1 Gray Mode White Light Gray Dark Gray Black 1 WA LA DA BA nd FRAME 3 WC LC DC BC th 8.16 Set Segment Re-map [A0~A1] This commands changes the mapping between the display data column address and segment driver. It allows flexibility in layout during LCD module assembly. Refer to Figure 5. 8.17 Set Entire Display On/Off [A4~A5] This command forces the entire display to be illuminated regardless of the contents of the GDDRAM. This command has priority than the “Set Normal/Reverse Display” but lower priority than the “Set Display On/Off” command. 8.18 Set Normal/Reverse Display [A6~A7] This command sets the display to be either normal/reverse. In reverse display, a RAM data of ‘0’ indicates an “ON” pixel while in normal display; a RAM data of ‘0’ indicates an “OFF” pixel. This command has lower priority than both “Set Display On/Off” and “Set Entire Display On/Off”. 8.19 Set Power Save Mode [A9] This command is to force the chip to enter Sleep Mode. The internal oscillator and LCD power supply will be turn off when enter to such mode. 8.20 Start Internal Oscillator [AB] After POR, the internal oscillator is OFF. It should be turned ON by sending this command to the chip. 8.21 Set Display On/Off [AE~AF] This command is used to turn the display on or off, by the value of the LSB. It has the highest priority over other commands regarding the display effect. 8.22 Set Page Address [B0~BF] This command positions the page address of 0 to 21 possible positions in GDDRAM. Refer to Figure 5. During 16-bits write operation, the last bit of the page address is ignored, D0-D7 always writes to even page and D8-D15 always writes to odd address. 29 SSD1854 Series Rev 1.0 08/2002 SOLOMON 8.23 Set COM Output Scan Direction [C0~CF] This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. 8.24 Exit Power Save Mode [E1] This command releases the chip from Sleep Mode and return to normal operation. 8.25 Software Reset [E2] This command causes some of the internal status of the chip to be initialized: Register Default Value Descriptions Page address 0 Column address 0 Display Start Line 0 GDDRAM page 0,D0 Internal Resistor Ratio 0 Gain = 3.2 (IRS0) Contrast 20H Data display length 0 FRC, PWM Mode 0 4FRC, 9PWM White Palette (0, 0, 0, 0) Light Gray Palette (0, 0, 0, 0) Dark Gray Palette (9, 9, 9, 9) Black Palette (9, 9, 9, 9) 8.26 Exit N-line Inversion [E4] This command releases the chip from N-line inversion mode. The driving waveform will be inverted once per frame after issuing this command. 8.27 Enable Scroll Buffer RAM [E6~E7] This command is used in enable RAM page 20 and 21 for a smooth window scrolling. When this is enabled, D0 of page 20 will appear right after the last row as defined by Set Lower Window Corner command. The next display data after D7 of page 21 is defined by Set Upper Window Corner command. When this is disabled, the data in RAM page 20 and 21 will not be displayed and the display data defined by Set Upper Window Corner command will be displayed right after the display data defined by Set Lower Window Corner command. After POR, the scroll buffer RAM is enabled. 8.28 Set Display Data Length [E8] This two-bytes command only valid when 3-wire SPI configuration is set by H/W input (PS0=PS1=L). The second byte is used to indicate that a specified number display data byte(s) (1-256) are to be transmitted. Next byte after the display data string is handled as a command. 8.29 Set Temperature Coefficient (TC) Value [E9] This command is to set 1 out of 4 different temperature coefficients in order to match various liquid crystal temperature grades. 8.30 Set Test Mode [F0~FF] This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command. SSD1854 Series Rev 1.0 08/2002 30 SOLOMON 9 MAXIMUM RATINGS Table 9 - Maximum Ratings (Voltage Referenced to VSS, TA = 25°C) Symbol VDD VCC VCI Vin I TA Tstg Parameter Supply Voltage Booster Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Range Value -0.3 to +4.0 VSS -0.3 to VSS +17.0 -0.3 to +4.0 VSS -0.3 to VDD +0.3 25 -20 to +85 -65 to +150 Unit V V V V mA °C °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to range VSS < or = (Vin or Vout) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either VSS or VDD). Unused outputs must be open. This device may be light sensitive. Caution should be taken to avoid exposure of this device any light source during normal operation. This device is not radiation protected. 31 SSD1854 Series Rev 1.0 08/2002 SOLOMON 10 DC CHARACTERISTICS Table 10 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V, TA = -20 to 85°C) Symbol VDD VCI VREF Parameter Logic Circuit Supply Voltage Range Booster Voltage Supply Pin Internal Reference Voltage o o (25 C, -0.10%/ C) IAC Access Mode Supply Current Drain (VDD Pin) IDP1 Display Mode Supply Current Drain (VDD & VCI Pins) ISB Standby Mode Supply Current Drain ISLEEP VCC VOH1 VOL1 VL7 VL7 Sleep Mode Supply Current Drain (VDD Pins) LCD Driving Voltage Generator Output (VCC Pin) Output High Voltage (D0-D15) Output Low Voltage (D0-D15) Most positive LCD Driving Voltage Source (VL7 Pin) VIH1 Most positive LCD Driving Voltage Source (VL7 Pin) Input high voltage VIL1 ( RES , PS0-2, CS , E, D/ C , R/W, D0-D15, REF) Input low voltage VL7 VL6 VL5 VL4 VL3 VL2 VL7 ( RES , PS0-2, CS , E, D/ C , R/W, D0-D15, REF) LCD Display Voltage Output (VL7, VL6, VL5, VL4, VL3, VL2 Pins) LCD Display Voltage Input (VL7, VL6, VL5, VL4, VL3, VL2 Pins) VL6 VL5 VL4 VL3 VL2 SSD1854 Series Rev 1.0 08/2002 Test Condition (Absolute value referenced to VSS) Internal Reference Voltage Source Enabled (REF pin pulled High), VEXT pin NC. VDD = 2.7V, Voltage Generator On, 4X DC-DC Converter Enabled, Write accessing, Tcyc =3.3MHz, Osc. Freq.=120kHz, Display On. VDD = VCI = 2.7V, Voltage Generator On, 4X DC-DC Converter Enabled. Read/Write Halt, Osc. Freq. = 120kHz, Display On, VL7 = 13.8V. VDD = 2.7V, LCD Driving Waveform Off, Oscillating Freq. = 120kHz, Read/Write halt. VDD = 2.7V, LCD Driving Waveform Off, Oscillator Off, Read/Write halt. Display On, Voltage Generator Enabled, DC/DC Converter Enabled, Regulator Enabled, Osc. Freq. = 120kHz, Iout = +100µA Iout = -100µA Regulator and Bias Divider Enabled (VL7 voltage depends on Internal contrast Control) Regulator and Bias Divider Disable Regulator and Bias Divider Enabled Voltage reference to VSS, External Voltage Generator, Bias Diver Disabled Min 1.8 Typ - Max 3.3 - 2.1 - - 450 550 µA - 550 900 µA - 90 130 µA - - 2 µA VDD - 17.0 V 0.8*VDD 0 VDD - VDD 0.2*VDD 17.0 VLCD V V - Floating - V 0.8*VDD - VDD V 0 - 0.2*VDD V - - 17 V VL6 - 14.5 11.5 8.5 7.15 5.8 17 V V V V V V VL5 VL4 VL3 VL2 VSS - VL7 VL6 VL5 VL4 VL3 V V V V V 32 SOLOMON Unit V Symbol IOH IOL IOZ IIL /IIH CIN ∆VL7 TC0 TC2 TC4 TC6 Parameter Output High Current Source (D0-D15) Output Low Current Drain (D0-D15) Output Tri-state Current Source (D0-D15) Input Current ( RES , PS0-2, CS , E, D/ C , R/W, D0-D15, REF) Input Capacitance (all logic pins) Variation of VL7 Output (1.8V < VDD < 3.5V) Temperature Coefficient 0* Temperature Coefficient 2* (POR) Temperature Coefficient 4* Temperature Coefficient 6* Test Condition Output Voltage=V DD -0.4V Output Voltage = 0.4V Min 50 Typ - Max - Unit µA - - -50 µA -1 - 1 µA -1 - 1 µA - 5 7.5 pF Regulator and Bias Divider Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 32 Voltage Regulator Enabled Voltage Regulator Enabled -2 0 +2 % -0.06 -0.11 -0.05 -0.10 -0.04 -0.09 % % Voltage Regulator Enabled Voltage Regulator Enabled -0.16 -0.22 -0.15 -0.21 -0.14 -0.20 % % * The formula for the temperature coefficient is: 1 TC(%)=VREF at 50ºC – VREF at 0ºC × ×100% VREF at 25ºC 50ºC – 0ºC 33 SSD1854 Series Rev 1.0 08/2002 SOLOMON 11 AC CHARACTERISTICS Table 11 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD, VCI = 2.7V, TA = -20 to 85°C) Symbol ∆Fosc Parameter Variation of Oscillation Frequency Frame Frequency = where Test Condition Oscillator Resistor = 680KΩ Min -10 Typ - Max +10 Unit % FOSC (PWM + 1) × MUX Fosc is the oscillation Frequency PWM is the Pulse Width Modulation level MUX is the multiplex ratio Example 1: Fosc = 120KHz; PWM = 9 level; MUX = 160 Frame Frequency = 75 Hz Example 2: Fosc = 120KHz; PWM = 15 level; MUX = 128 Frame Frequency = 58.6 Hz Oscillation Frequency (KHz) Oscillation Frequency at different VDD 210.00 470K 560K 680K 820K 1000K 180.00 150.00 120.00 90.00 60.00 1.8 2.1 2.4 2.7 3 3.3 VDD (V) Figure 8 - Oscillation Frequency at different VDD at 25°C SSD1854 Series Rev 1.0 08/2002 34 SOLOMON Table 12 – Parallel Timing Characteristics 1 (TA = -20 to 85°C, VDD = 1.8 to 3.3V, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 166 0 0 30 5 15 70 70 70 40 40 - Typ - Max 50 140 140 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns R/ W D/ C tAH tAS E t cycle PW CSL PW CSH CS tR tF tDSW D0 -D7 (Write data to driv er) tDHW Valid Data tACC D 0-D 7 (Read data f rom driv er) t DHR Valid Data tOH Figure 9 – Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) 35 SSD1854 Series Rev 1.0 08/2002 SOLOMON Table 13 – Parallel Timing Characteristics 2 (TA = -20 to 85°C, VDD = 1.8 to 3.3V, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 166 0 0 30 5 15 70 70 70 40 40 - Typ - Max 25 50 140 140 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns D/C tAH tAS WR (R/W) RD (E) tcycl e PWCSL PW CSH CS tF tR tD SW D0-D7 (Write dat a to driver) t DH W Valid Data tAC C D0 -D7 (Read data from driver) t D HR Valid Data tOH Figure 10 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) SSD1854 Series Rev 1.0 08/2002 36 SOLOMON Table 14 – Serial Timing Characteristics (TA = -20 to 85°C, VDD = 1.8 to 3.3V, VSS =0V) Symbol tcycle tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH tR tF Parameter Min 58.8 14 30 30 ½*tcycle 30 30 30 30 - Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time Typ - Max 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns D/C (Required if PS1 = H) tAH tAS CS tCSS tCS H t c ycle tC LK L tC L KH SCK tF tR tDSW SDA tDHW Valid Data CS SCK D7 SDA D6 D5 D4 D3 D2 D1 D0 Figure 11- Serial Timing Characteristics (PS0 = L) 37 SSD1854 Series Rev 1.0 08/2002 SOLOMON 12 APPLICATION CIRCUIT DISPLAY PANEL 128 X 160 COM0 COM1 COM2 : : : : : : : SIZE : : : : : : : : : : : COM157 COM158 COM159 Remapped COM SCAN Direction [Command: C8] SEG0…………………………………………….………….SEG127 : : : : : : : : : : : : : SEG1 SEG0 COM0 COM1 COM2 COM3 : : : : : : : : : : : : : : : : : : : : : : : : Segment Remapped [Command: A1] SSD1854 IC CONTROL CIRCUIT REGULATOR DIVIDER CIRCUIT COM159 COM158 COM157 : : : : : : : VCC C3P C1N C1P C2P C2N C4P VL2 VL3 VL4 VL5 VL6 VL7 CAP CAN CBP CBN CCP CCN CDP CDN CS# D0-D15 160 MUX (DIE FACE IP) RES# PS0 PS1 PS2 D/C R/W E REF : : : : : : SEG126 SEG127 : : : : : : : : BOOSTER CIRCUIT Figure 12 – LCD Pins Connection of SSD1854Z SSD1854 Series Rev 1.0 08/2002 38 SOLOMON 12.1 DC-DC Converter Circuit Configuration 3x Converter 4x Converter 5x Converter + + + + + + + + + + + Vss Vcc SSD1854 IC C3P C1N C1P C2P C2N + C4P *Note: Capacitor value = 1µF to 4.7µF, which is depended on the LCD panel characteristic 12.2 Bias Divider Circuit Configuration Internal Regulator and Bias Divider [COMMAND: 2F] SSD1854 IC CAP CAN CBP CBN CCP CCN CDP CDN VL7 VL6 VL5 VL4 VL3 VL2 39 SSD1854 Series Rev 1.0 08/2002 + + Capacitor value for CAP~CDN = 1µF to 2.2µF + + + VSS + + + + Capacitor value for VL2~VL7 = 1µF + SOLOMON 12.3 Parallel Interface Configuration (Read / Write) 8080 Parallel Interface (8-bits read and write) D8-D15 D0-D7 VSS CS RES E R/ W SSD1854 D/ C IC REF PS0 PS1 PS2 6800 Parallel Interface (8-bits read and 16-bits write) MCU Control signal VDD MCU Control signal VDD VSS 12.4 Serial Interface Configuration (Write Only) 3-wire Interface D7(SDA) D6(SCK) CS 4-wire Interface MCU Control signal MCU Control signal VDD VDD RES REF E SSD1854 IC R/ W ( WR ) D/ C PS0 PS1 PS2 SSD1854 Series Rev 1.0 08/2002 VSS VSS 40 SOLOMON 13 APPENDIXA Figure 13 – SSD1854U COF Drawing 1 41 SSD1854 Series Rev 1.0 08/2002 SOLOMON Note: PS0, PS1, AVDD, DVDD, REF are connected to VDD PS2 is connected to VSS Set Conditions 6800 8-bits Parallel Interface, Internal Reference Voltage Source NC NC SEG0 SEG1 . . . . SEG126 SEG127 NC NC NC NC COM0 COM1 COM2 . . . . COM157 COM158 COM159 NC NC NC NC CS# RES# D/C RW(WR#) E(RD#) D0 D1 D2 D3 D4 D5 D6(SCK) D7(SDA) VDD VCI VSS NC NC Figure 14 – SSD1854U COF Drawing 2 SSD1854 Series Rev 1.0 08/2002 42 SOLOMON Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part. 43 SSD1854 Series Rev 1.0 08/2002 SOLOMON