Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter AD9229 FEATURES Four ADCs in 1 package Serial LVDS digital output data rates to 780 Mbps (ANSI-644) Data and frame clock outputs SNR = 69.5 dB (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) 400 MHz full power analog bandwidth Power dissipation 1,350 mW at 65 MSPS 985 mW at 50 MSPS 1 V p-p to 2 V p-p input voltage range 3.0 V supply operation Power-down mode Digital test pattern enable for timing alignments FUNCTIONAL BLOCK DIAGRAM PDWN DTP DRVDD DRGND AD9229 VIN+A VIN–A SHA PIPELINE ADC SHA PIPELINE ADC SHA PIPELINE ADC SHA PIPELINE ADC VIN+B VIN–B VIN+C VIN–C VIN+D VIN–D 12 12 12 12 SERIAL LVDS D+A SERIAL LVDS D+B SERIAL LVDS D+C SERIAL LVDS D+D D–A D–B D–C D–D VREF SENSE FCO+ 0.5V FCO– REFT REFB DATA RATE MULTIPLIER REF SELECT DCO+ AGND Digital beam-forming systems for ultrasound Wireless and wired broadband communications Communication test equipment LVDSBIAS CLK 04418-001 DCO– APPLICATIONS Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at up to a 65 MSPS conversion rate and is optimized for outstanding dynamic performance in applications where a small package size is critical. 1. Four ADCs are contained in a small, space-saving package. 2. A data clock out (DCO) is provided, which operates up to 390 MHz and supports double-data rate operation (DDR). 3. The outputs of each ADC are serialized LVDS with data rates up to 780 Mbps (12 bits × 65 MSPS). 4. The AD9229 operates from a single 3.0 V power supply. 5. Packaged in a Pb-free, 48-lead LFCSP package. 6. The internal clock duty cycle stabilizer maintains performance over a wide range of input clock duty cycles. The ADC requires a single 3 V power supply and TTL-/CMOScompatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported and typically consumes 3 mW when enabled. Fabricated with an advanced CMOS process, the AD9229 is available in a Pb-free, 48-lead LFCSP package. It is specified over the industrial temperature range of –40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005–2010 Analog Devices, Inc. All rights reserved. AD9229 TABLE OF CONTENTS Features .............................................................................................. 1 Equivalent Circuits ......................................................................... 10 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 11 Functional Block Diagram .............................................................. 1 Terminology .................................................................................... 16 General Description ......................................................................... 1 Theory of Operation ...................................................................... 18 Revision History ............................................................................... 2 Analog Input Considerations ................................................... 18 Specifications..................................................................................... 3 Clock Input Considerations ...................................................... 19 AC Specifications.......................................................................... 4 Evaluation Board ............................................................................ 24 Digital Specifications ................................................................... 5 Power Supplies ............................................................................ 24 Switching Specifications .............................................................. 6 Input Signals................................................................................ 24 Timing Diagram ............................................................................... 7 Output Signals ............................................................................ 24 Absolute Maximum Ratings............................................................ 8 Default Operation and Jumper Selection Settings ................. 25 Explanation of Test Levels ........................................................... 8 Alternate Analog Input Drive Configuration ......................... 25 ESD Caution .................................................................................. 8 Outline Dimensions ....................................................................... 39 Pin Configuration and Function Descriptions ............................. 9 Ordering Guide .......................................................................... 39 REVISION HISTORY 5/10—Rev. A to Rev. B Change to Item 47 in Table 11 ...................................................... 38 Updated Outline Dimensions ....................................................... 39 Change to Ordering Guide ............................................................ 39 9/05—Rev. 0 to Rev. A Change to Specifications .................................................................. 3 Changes to Differential Input Configurations Section.............. 19 Changes to Exposed Paddle Thermal Heat Slug Recommendations Section ........................................................ 23 Changes to Evaluation Board Section .......................................... 24 Changes to Table 11 ........................................................................ 36 3/05—Revision 0: Initial Version Rev. B | Page 2 of 40 AD9229 SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 1. AD9229-50 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error 1 Gain Matching1 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error1 Reference Voltage, VREF = 1 V REFERENCE Output Voltage Error, VREF = 1 V Load Regulation @ 1.0 mA, VREF = 1 V Output Voltage Error, VREF = 0.5 V Load Regulation @ 0.5 mA, VREF = 0.5 V Input Resistance ANALOG INPUTS Differential Input Voltage Range VREF = 1 V Differential Input Voltage Range VREF = 0.5 V Common Mode Voltage Input Capacitance 2 Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD DRVDD Power Dissipation 3 Power-Down Dissipation CROSSTALK 4 AD9229-65 Temperature Test Level Full Full Full Full Full 25°C Full 25°C Full VI VI VI VI VI V VI V VI Guaranteed ±5 ±5 ±0.3 ±0.2 ±0.3 ±0.3 ±0.6 ±0.6 Full Full Full V V V ±2 ±12 ±16 Full Full Full Full VI V VI V ±10 3 ±8 0.2 Full V 7 7 kΩ Full VI 2 2 V p-p Full VI 1 1 V p-p Full Full Full V V V 1.5 7 400 1.5 7 400 V pF MHz Full Full Full Full Full Full Full IV IV VI VI VI V V Min 12 2.7 2.7 Typ 3.0 3.0 300 28 985 3 –95 1 Max Min 12 Typ Guaranteed ±5 ±5 ±0.3 ±0.2 ±0.3 ±0.3 ±0.4 ±0.4 ±25 ±25 ±2.5 ±1.5 ±0.6 ±1 Max Unit Bits ±25 ±25 ±2.5 ±1.5 mV mV % FS % FS LSB LSB LSB LSB ±0.7 ±1 ±3 ±12 ±16 ±30 ±10 3 ±8 0.2 ±17 3.6 3.6 330 31 1083 2.7 2.7 3.0 3.0 420 29 1350 3 –95 ppm/°C ppm/°C ppm/°C ±30 ±17 3.6 3.6 455 33 1465 mV mV mV mV V V mA mA mW mW dB Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input. Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 3 Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS. 4 Typical specification over the first Nyquist zone. 2 Rev. B | Page 3 of 40 AD9229 AC SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 2. AD9229-50 Parameter SIGNAL-TO-NOISE RATIO (SNR) SIGNAL-TO-NOISE RATIO (SINAD) EFFECTIVE NUMBER OF BITS (ENOB) SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST HARMONIC (Second or Third) WORST OTHER (Excluding Second or Third) TWO-TONE INTERMODULATION DISTORTION (IMD) AIN1 and AIN2 = –7.0 dBFS fIN = 2.4 MHz fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz Temperature Full 25°C Full Full 25°C Full 25°C Full Full 25°C Full Test Level IV V VI VI V V V VI VI V V fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz 25°C Full Full 25°C Full V VI VI V V fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN1 = 15 MHz 25°C Full Full 25°C Full 25°C Full Full 25°C Full 25°C Full Full 25°C 25°C V VI VI V V V VI VI V V V VI VI V V fIN2 = 16 MHz fIN1 = 69 MHz fIN2 = 70 MHz 25°C V Rev. B | Page 4 of 40 Min 69.5 68.7 Typ 70.4 70.4 69.6 68.4 67.2 70.0 70.0 69.4 Max AD9229-65 Min 69.0 Typ 70.2 70.2 68.0 69.5 67.1 69.8 69.8 67.3 69.0 66.7 11.3 66.8 11.3 11.1 11.3 11.2 11.3 10.9 10.8 85 76 85 85 11.2 10.8 85 85 77 –85 –85 –76 –85 –77 –90 –90 –73 –88 –83 –73 –79.7 –85 –73 –68.5 –68.5 –78 –90 –90 –88 Unit dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits dBc 85 73 78 –85 –85 –85 Max –81.7 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9229 DIGITAL SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 3. AD9229-50 Parameter CLOCK INPUT Logic Compliance High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC INPUTS (PDWN) Logic 1 Voltage Logic 0 Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUTS (D+, D–) Logic Compliance Differential Output Voltage Output Offset Voltage Output Coding Temperature Test Level Full Full Full Full 25°C IV IV VI VI V Full Full Full Full 25°C IV IV IV IV V Full Full Full VI VI VI Min Typ AD9229-65 Max TTL/CMOS 2.0 0.8 ±10 ±10 2.0 Max Unit 0.8 ±10 ±10 V V μA μA pF 0.5 0.5 2 0.8 ±10 ±10 V V μA μA pF 440 1.35 mV V 2.0 0.5 0.5 2 Rev. B | Page 5 of 40 Typ TTL/CMOS 2.0 0.5 0.5 2 LVDS 260 1.15 Min 1.25 Offset binary 0.8 ±10 ±10 440 1.35 0.5 0.5 2 LVDS 260 1.15 1.25 Offset binary AD9229 SWITCHING SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 4. AD9229-50 AD9229-65 Temp Test Level Full Full Full VI IV VI 8 10 6.2 Full VI 8 10 Full Full VI V 3.3 6.5 250 Full V 250 250 ps Full V 6.5 6.5 ns Full V IV tFCO + (tSAMPLE/24) (tSAMPLE/24) ns Full tFCO + (tSAMPLE/24) (tSAMPLE/24) DCO-to-FCO Delay (tFRAME) Full IV Data-to-Data Skew (tDATA-MAX – tDATA-MIN) Wake-Up Time Pipeline Latency Full IV ±100 25°C Full V IV 4 10 4 10 ms CLK cycles 25°C 25°C V V 1.8 <1 1.8 <1 25°C V 2 2 ns ps rms CLK cycles Parameter CLOCK Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) DCO-to-Data Delay (tDATA) APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) OUT-OF-RANGE RECOVERY TIME Min Typ Max 50 Min Typ Max Unit 10 7.7 MSPS MSPS ns 6.2 7.7 ns 3.3 6.5 250 65 10 (tSAMPLE/24) – 250 (tSAMPLE/24) – 250 (tSAMPLE/24) 7.9 (tSAMPLE/24) + 250 (tSAMPLE/24) + 250 ±250 Rev. B | Page 6 of 40 (tSAMPLE/24) – 250 (tSAMPLE/24) – 250 (tSAMPLE/24) ±100 7.9 (tSAMPLE/24) + 250 (tSAMPLE/24) + 250 ±250 ns ps ps ps ps AD9229 TIMING DIAGRAM N–1 AIN N tA tEH tEL CLK tCPD DCO– DCO+ tFCO tFRAME FCO– FCO+ D+ MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 9) (N – 9) Figure 2. Timing Diagram Rev. B | Page 7 of 40 04418-002 tDATA tPD D– AD9229 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D+, D–, DCO+, DCO–, FCO+, FCO–) LVDSBIAS CLK VIN+, VIN– PDWN, DTP REFT, REFB VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Thermal Impedance 1 With Respect To Rating AGND DRGND DRGND DRVDD DRGND –0.3 V to +3.9 V –0.3 V to +3.9 V –0.3 V to +0.3 V –3.9 V to +3.9 V –0.3 V to DRVDD DRGND AGND AGND AGND AGND AGND –0.3 V to DRVDD –0.3 V to AVDD –0.3 V to AVDD –0.3 V to AVDD –0.3 V to AVDD –0.3 V to AVDD –40°C to +85°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS I. 100% production tested. II. 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. 150°C VI. 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. 300°C –65°C to +150°C 25°C/W 1 θJA for a 4-layer PCB with a solid ground plane in still air. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 8 of 40 AD9229 48 47 46 45 44 43 42 41 40 39 38 37 DCO+ DCO– FCO+ FCO– D+A D–A D+B D–B D+C D–C D+D D–D PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 NC 3 DTP 4 AVDD 5 AGND 6 PDWN 7 AVDD 8 AGND 9 VIN+A 10 VIN–A 11 AGND 12 EXPOSED PADDLE, PIN 0 (Bottom of Package) AD9229 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 DRGND DRVDD LVDSBIAS AGND AVDD AGND CLK AVDD AGND VIN+D VIN–D AGND 04418-003 VIN–B VIN+B AGND AVDD SENSE VREF REFB REFT AVDD AGND VIN+C VIN–C NC = NO CONNECT PIN 1 INDICATOR 13 14 15 16 17 18 19 20 21 22 23 24 DRGND DRVDD Figure 3. LFCSP Top View Table 6. Pin Function Descriptions Pin No. 5, 8, 16, 21, 29, 32 6, 9, 12, 15, 22, 25, 28, 31, 33 2, 35 1, 36 0 Mnemonic AVDD Description Analog Supply Pin No. 26 Mnemonic VIN–D AGND Analog Ground DRVDD DRGND AGND VIN+D CLK LVDSBIAS 37 D–D 3 4 7 NC DTP PDWN 38 39 D+D D–C 40 41 D+C D–B 10 11 VIN+A VIN–A 42 43 D+B D–A 13 VIN–B 14 17 18 19 20 23 24 VIN+B SENSE VREF REFB REFT VIN+C VIN–C Digital Output Supply Digital Ground Exposed Paddle/Thermal Heat Slug (Located on Bottom of Package) No Connect Digital Test Pattern Enable Power-Down Selection (AVDD = Power Down) ADC A Analog Input—True ADC A Analog Input— Complement ADC B Analog Input— Complement ADC B Analog Input—True Reference Mode Selection Voltage Reference Input/Output Differential Reference (Bottom) Differential Reference (Top) ADC C Analog Input—True ADC C Analog Input— Complement 27 30 34 44 45 D+A FCO– 46 FCO+ 47 DCO– 48 DCO+ Rev. B | Page 9 of 40 Description ADC D Analog Input— Complement ADC D Analog Input—True Input Clock LVDS Output Current Set Resistor Pin ADC D Complement Digital Output ADC D True Digital Output ADC C Complement Digital Output ADC C True Digital Output ADC B Complement Digital Output ADC B True Digital Output ADC A Complement Digital Output ADC A True Digital Output Frame Clock Indicator— Complement Output Frame Clock Indicator—True Output Data Clock Output— Complement Data Clock Output—True AD9229 EQUIVALENT CIRCUITS AVDD DRVDD VIN+, VIN– V V AGND D+ V V DRGND Figure 4. Equivalent Analog Input Circuit 04418-007 04418-004 D– Figure 7. Equivalent Digital Output Circuit AVDD AVDD DTP AGND 04418-005 170Ω AGND Figure 5. Equivalent Clock Input Circuit Figure 8. Equivalent DTP Input Circuit AVDD PDWN 04418-006 375Ω AGND 100kΩ 04418-051 375Ω CLK Figure 6. Equivalent Digital Input Circuit Rev. B | Page 10 of 40 AD9229 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –0.5dBFS SNR = 70.4dB ENOB = 11.4 BITS SFDR = 85.8dBC –20 AMPLITUDE (dBFS) –40 –60 –80 0 4.1 8.1 12.2 16.3 20.3 FREQUENCY (MHz) 24.4 28.4 –120 32.5 Figure 9. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 65 MSPS 0 4.1 8.1 12.2 16.3 20.3 FREQUENCY (MHz) 24.4 28.4 32.5 Figure 12. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS 0 90 1V p-p, SFDR (dBc) AIN = –0.5dBFS SNR = 69.6dB ENOB = 11.3 BITS SFDR = 82.4dBC 85 2V p-p, SFDR (dBc) SNR/SFDR (dB) –40 –60 80 75 2V p-p, SNR (dB) 70 –100 65 04418-010 –80 –120 0 4.1 8.1 12.2 16.3 20.3 FREQUENCY (MHz) 24.4 28.4 1V p-p, SNR (dB) 04418-013 –20 AMPLITUDE (dBFS) –80 04418-012 –120 AIN = –0.5dBFS 60 10 32.5 Figure 10. Single-Tone 32k FFT with fIN = 30 MHz, fSAMPLE = 65 MSPS 15 20 25 30 35 ENCODE (MSPS) 40 45 50 Figure 13. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 50 MSPS 0 90 1V p-p, SFDR (dBc) AIN = –0.5dBFS SNR = 68.5dB ENOB = 11.1 BITS SFDR = 81.3dBC –20 85 SNR/SFDR (dB) –40 –60 80 2V p-p, SNR (dB) 70 –100 65 –120 0 4.1 8.1 12.2 16.3 20.3 FREQUENCY (MHz) 24.4 28.4 32.5 Figure 11. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS Rev. B | Page 11 of 40 2V p-p, SFDR (dBc) 75 –80 04418-011 AMPLITUDE (dBFS) –60 –100 04418-009 –100 –40 1V p-p, SNR (dB) AIN = –0.5dBFS 60 10 15 20 25 30 35 ENCODE (MSPS) 40 45 Figure 14. SNR/SFDR vs. fSAMPLE, fIN = 25 MHz, fSAMPLE = 50 MSPS 04418-014 AMPLITUDE (dBFS) –20 AIN = –0.5dBFS SNR = 68.1dB ENOB = 11.0 BITS SFDR = 77.0dBC 50 AD9229 95 90 1V p-p, SFDR (dBc) 2V p-p, SFDR (dBc) 80 90 1V p-p, SFDR (dBc) 70 SNR/SFDR (dB) SNR/SFDR (dB) 85 2V p-p, SFDR (dBc) 80 75 2V p-p, SNR (dB) 60 50 40 80 dB REFERENCE 30 70 20 04418-015 1V p-p, SNR (dB) AIN = –0.5dBFS 60 10 15 20 25 30 35 40 45 ENCODE (MSPS) 50 55 60 10 0 –60 65 Figure 15. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 65 MSPS 2V p-p, SNR (dB) 04418-018 65 1V p-p, SNR (dB) –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 0 Figure 18. SNR/SFDR vs. Analog Input Level, fIN =25 MHz, fSAMPLE = 50 MSPS 85 90 2V p-p, SFDR (dBc) 2V p-p, SFDR (dBc) 80 70 SNR/SFDR (dB) 75 2V p-p, SNR (dB) 70 60 50 40 04418-016 1V p-p, SNR (dB) AIN = –0.5dBFS 30 15 20 25 30 35 40 45 ENCODE (MSPS) 50 55 60 10 0 –60 65 Figure 16. SNR/SFDR vs. fSAMPLE, fIN = 30 MHz, fSAMPLE = 65 MSPS 2V p-p, SFDR (dBc) –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 0 70 1V p-p, SFDR (dBc) SNR/SFDR (dB) 60 50 40 80 dB REFERENCE 30 20 04418-017 1V p-p, SNR (dB) –40 –30 –20 ANALOG INPUT LEVEL (dBFS) 1V p-p, SFDR (dBc) 60 50 40 80 dB REFERENCE 30 20 2V p-p, SNR (dB) –50 2V p-p, SFDR (dBc) 80 70 SNR/SFDR (dB) –50 90 80 0 –60 2V p-p, SNR (dB) 1V p-p, SNR (dB) Figure 19. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 65 MSPS 90 10 80 dB REFERENCE 20 65 60 10 1V p-p, SFDR (dBc) –10 0 10 0 –60 2V p-p, SNR (dB) 04418-020 SNR/SFDR (dB) 1V p-p, SFDR (dBc) 04418-019 80 1V p-p, SNR (dB) –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 Figure 20. SNR/SFDR vs. Analog Input Level, fIN = 30 MHz, fSAMPLE = 65 MSPS Figure 17. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 50 MSPS Rev. B | Page 12 of 40 0 AD9229 90 80 85 70 SFDR (dBc) 2V p-p, SFDR (dBc) 60 75 SFDR (dB) 70 SNR (dB) 65 50 80 dB REFERENCE 40 30 60 1V p-p, SFDR (dBc) 20 55 10 04418-021 50 45 1 10 100 FREQUENCY (MHz) 0 –60 –56 –52 –48 –44 –40 –36 –32 –28 –23 –19 –15 –10 ANALOG INPUT LEVEL (dBFS) 1000 Figure 21. SNR/SFDR vs. fIN, fSAMPLE = 65 MHz 04418-024 SNR/SFDR (dB) 80 –7 Figure 24. Two-Tone SFDR vs. Analog Input Level, fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 65 MSPS 0 80 AIN1 AND AIN2= –7.0dBFS SFDR = 73.0dBc IMD2 = 80.5dBc IMD3 = 73.0dBc –20 70 2V p-p, SFDR (dBc) –40 SFDR (dB) AMPLITUDE (dBFS) 60 –60 50 80 dB REFERENCE 40 1V p-p, SFDR (dBc) 30 –80 20 04418-022 10 –120 0 4.1 8.1 12.2 16.3 20.3 FREQUENCY (MHz) 24.4 28.4 0 –60 –56 –52 –48 –44 –40 –36 –32 –28 –23 –19 –15 –10 ANALOG INPUT LEVEL (dBFS) 32.5 Figure 22. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 65 MSPS –7 Figure 25. Two-Tone SFDR vs. Analog Input Level, fIN1 = 69 MHz and fIN2 = 70 MHz, fSAMPLE = 65 MSPS 0 90 AIN1 AND AIN2= –7.0dBFS SFDR = 68.5dBc IMD2 = 77.0dBc IMD3 = 68.5dBc –20 1V p-p, SFDR (dBc) 85 2V p-p, SFDR (dBc) –40 SNR/SFDR (dB) –60 –80 80 75 2V p-p, SINAD (dB) 70 –100 04418-023 65 –120 0 4.1 8.1 12.2 16.3 20.3 FREQUENCY (MHz) 24.4 28.4 32.5 Figure 23. Two-Tone 32k FFT with fIN1 = 69 MHz and fIN2 = 70 MHz, fSAMPLE = 65 MSPS Rev. B | Page 13 of 40 60 –40 1V p-p, SINAD (dB) –20 0 20 40 TEMPERATURE (°C) 04418-026 AMPLITUDE (dBFS) 04418-025 –100 60 80 Figure 26. SINAD/SFDR vs. Temperature, fIN 10.3 MHz, fSAMPLE = 65 MSPS AD9229 –40 15 –50 5 CMRR (dB) 0 –5 –10 –60 –70 –20 –40 04418-027 –15 –20 0 20 40 TEMPERATURE (°C) 60 04418-031 GAIN ERROR (ppm/°C) 10 –80 0 80 5 10 15 20 FREQUENCY (MHz) 25 30 Figure 30. CMRR vs. Frequency, fSAMPLE = 65 MSPS Figure 27. Gain Error vs. Temperature 0.5 10 0.4 9 0.3 8 NUMBER OF HITS (1M) 0.36LSB rms 0.1 0 –0.1 –0.2 –0.3 7 6 5 4 3 04418-028 2 –0.4 –0.5 0 512 1024 1536 2048 CODE 2560 3072 3584 04418-039 INL (LSB) 0.2 1 0 N–3 4095 Figure 28. Typical INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS N–2 N CODE N+1 N+2 N+3 Figure 31. Input Referred Noise Histogram, fSAMPLE = 65 MSPS 0.5 0 NPR = 60.8dB NOTCH = 18MHz NOTCH WIDTH = 3MHz 0.4 –20 0.3 AMPLITUDE (dBFS) 0.2 0.1 0 –0.1 –0.2 –40 –60 –80 –0.3 –0.4 –0.5 0 512 1024 1536 2048 CODE 2560 3072 3584 4095 04418-035 –100 04418-030 DNL (LSB) N–1 –120 0 4.1 8.1 12.2 16.3 20.3 FREQUENCY (MHz) 24.4 28.4 Figure 32. Noise Power Ratio (NPR), fSAMPLE = 65 MSPS Figure 29. Typical DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS Rev. B | Page 14 of 40 32.5 AD9229 0 –2 –3 –4 –5 –6 –7 04418-038 FUNDAMENTAL LEVEL (dB) –1 –8 0 50 100 150 200 250 300 350 FREQUENCY (MHz) 400 450 500 Figure 33. Full Power Bandwidth vs. Frequency, fSAMPLE = 65 MSPS Rev. B | Page 15 of 40 AD9229 TERMINOLOGY Analog Bandwidth Analog bandwidth is the analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB from full scale. Aperture Delay Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the 50% point rising edge of the clock input to the time at which the input signal is held for conversion. Aperture Uncertainty (Jitter) Aperture jitter is the variation in aperture delay for successive samples and can be manifested as frequency-dependent noise on the ADC input. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Common Mode Rejection Ratio (CMRR) CMRR is defined as the amount of rejection on the differential analog inputs when a common signal is applied. Typically expressed as 20 log (differential gain/common-mode gain). Crosstalk Crosstalk is defined as the measure of any feedthrough coupling onto the quiet channel when all other channels are driven by a full-scale signal. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a pin and subtracting the voltage from a second pin that is 180° out of phase. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to an n-bit resolution indicates that all 2n codes, respectively, must be present over all operating ranges. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to obtain a measure of performance expressed as N, the effective number of bits: Full Power Bandwidth Full power bandwidth is the measured –3 dB point at the analog front-end input relative to the frequency measured. Gain Error The largest gain error is specified and is considered the difference between the measured and ideal full-scale input voltage range. Gain Matching Expressed as a percentage of FSR and computed using the following equation: Gain Matching = FSR max − FSR min ⎛ FSR max + FSR min ⎞ ⎜ ⎟ 2 ⎝ ⎠ × 100% where FSRMAX is the most positive gain error of the ADCs, and FSRMIN is the most negative gain error of the ADCs. Input-Referred Noise Input-referred noise is a measure of the wideband noise generated by the ADC core. Histograms of the output codes are created while a dc signal is applied to the ADC input. Inputreferred noise is calculated using the standard deviation of the histograms and presented in terms of LSB rms. Integral Nonlinearity (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1.5 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Noise Power Ratio (NPR) NPR is the full-scale rms noise power injected into the ADC vs. the rejected band of interest (notch depth measured). Offset Error The largest offset error is specified and is considered the difference between the measured and ideal voltage at the analog input that produces the midscale code at the outputs. Offset Matching Expressed in millivolts and computed using the following equation: Offset Matching = OFFMAX − OFFMIN where OFFMAX is the most positive offset error, and OFFMIN is the most negative offset error. N = (SINAD – 1.76)/6.02 Rev. B | Page 16 of 40 AD9229 Out-of-Range Recovery Time Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Output Propagation Delay The delay between the clock logic threshold and the time when all bits are within valid logic levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference in decibels between the rms amplitude of the input signal and the peak spurious signal. Second and Third Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the second or third harmonic component, reported in decibels relative to the carrier. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Signal-to Noise and Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in decibels relative to the carrier (that is, degrades as signal levels are lowered) or in decibels relative to full scale (always related back to converter full scale). Rev. B | Page 17 of 40 AD9229 THEORY OF OPERATION The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clock. The analog inputs of the AD9229 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. For optimum performance, set the device so that VCM = AVDD/2; however, the device can function over a wider range with reasonable performance (see Figure 35 and Figure 36). 90 2V p-p, SFDR (dBc) 85 1V p-p, SFDR (dBc) 75 2V p-p, SNR (dB) 70 65 1V p-p, SNR (dB) 60 ANALOG INPUT CONSIDERATIONS 0 The analog input to the AD9229 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance. An input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. 0.5 1.0 1.5 2.0 2.5 ANALOG INPUT COMMON-MODE VOLTAGE (V) 3.0 Figure 35. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, fSAMPLE = 65 MSPS 90 2V p-p, SFDR (dBc) 85 80 1V p-p, SFDR (dBc) SNR/SFDR (dB) 75 H S 80 04418-053 Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent on the application. SNR/SFDR (dB) The AD9229 architecture consists of a front-end switched capacitor sample-and-hold amplifier (SHA) followed by a pipelined ADC. The pipelined ADC is divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. S VIN+ 2V p-p, SNR (dB) 70 65 1V p-p, SNR (dB) 60 55 CPAR 04418-054 50 45 S 40 0 CPAR 04418-029 VIN– S H Figure 34. Switched-Capacitor SHA Input The clock signal alternately switches the SHA between sample mode and hold mode (see Figure 34). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half 0.5 1.0 1.5 2.0 2.5 ANALOG INPUT COMMON-MODE VOLTAGE (V) 3.0 Figure 36. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz, fSAMPLE = 65 MSPS For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. Rev. B | Page 18 of 40 AD9229 AVDD R 2V p-p 49.9Ω VIN+ C AVDD VIN– AGND 1kΩ REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD − VREF) Span = 2 × (REFT − REFB) = 2 × VREF AD9229 R 04418-033 An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that defines the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as 1kΩ 0.1μF Figure 38. Differential Transformer—Coupled Configuration It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. Single-Ended Input Configuration The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range, as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved by setting the AD9229 to the largest input span of 2 V p-p. A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 39 details a typical single-ended input configuration. 10μF 1kΩ 2V p-p 49.9Ω 0.1μF R 1kΩ C AVDD Differential Input Configurations 1kΩ Optimum performance is achieved by driving the AD9229 in a differential input configuration. For ultrasound applications, the AD8332 differential driver provides excellent performance and a flexible interface to the ADC (see Figure 37). 10μF 0.1μF R 1kΩ AVDD VIN+ AD9229 VIN– AGND 04418-034 The SHA should be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined in Figure 35 and Figure 36. Figure 39. Single-Ended Input Configuration 0.1μF AVDD LOP 1V p-p VOH 187Ω 0.1μF AVDD R VIN+ 1.0kΩ 22p LNA AD8332 VGA 374Ω LMD VOL LON 18nF 274Ω VIN 187nH AD9229 C 1.0kΩ 0.1μF CLOCK INPUT CONSIDERATIONS VIP INH R VIN– 0.1μF 0.1μF 10μF VREF AGND 04418-032 0.1μF 120nH 0.1μF Figure 37. Differential Input Configuration Using the AD8332 However, the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9229. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example of this is shown in Figure 38. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Typically, a 10% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9229 has a self-contained clock duty cycle stabilizer that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9229. An on-board phase-locked loop (PLL) multiplies the input clock rate for the purpose of shifting the serial data out. The stability criteria for the PLL limits the minimum sample clock rate of the ADC to 10 MSPS. Assuming steady state operation of the input clock, any sudden change in the sampling rate could create an out-of-lock condition leading to invalid outputs at the DCO, FCO, and data out pins. Rev. B | Page 19 of 40 AD9229 1400 High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fA) due only to aperture jitter (tA) can be calculated with the following equation: IAVDD 400 300 TOTAL POWER 250 1100 200 1000 150 100 900 IDRVDD The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9229. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Power Dissipation and Power-Down Mode As shown in Figure 40 and Figure 41, the power dissipated by the AD9229 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 1200 350 300 1100 IAVDD CURRENT (mA) POWER (mW) 250 1000 200 TOTAL POWER 900 150 800 700 50 IDRVDD 600 10 15 20 25 30 35 ENCODE (MSPS) 40 45 50 0 04418-056 100 Figure 40. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS CURRENT (mA) 350 1200 800 10 20 30 40 ENCODE (MSPS) 50 50 60 0 04418-055 In the equation, the rms aperture jitter, tA, represents the root sum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Applications that require undersampling are particularly sensitive to jitter. 450 1300 POWER (mW) SNR degradation = 20 × log 10 [1/2 × π × fA × tA] 500 Figure 41. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS By asserting the PDWN pin high, the AD9229 is placed in power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9229 to normal operating mode. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 4 ms to restore full operation. Digital Outputs The AD9229’s differential outputs conform to the ANSI-644 LVDS standard. To set the LVDS bias current, place a resistor (RSET is nominally equal to 4.0 kΩ) to ground at the LVDSBIAS pin. The RSET resistor current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. To adjust the differential signal swing, simply change the resistor to a different value, as shown in Table 7. Table 7. LVDSBIAS Pin Configuration RSET 3.7 kΩ 4.0 kΩ (default) 4.3 kΩ Rev. B | Page 20 of 40 Differential Output Swing 375 mV p-p 350 mV p-p 325 mV p-p AD9229 The AD9229’s LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. It is recommended to keep the trace length no longer than 12 inches and to keep differential output traces close together and at equal lengths. Table 9. Digital Test Pattern Pin Settings The format of the output data is offset binary. An example of the output coding format can be found in Table 8. Voltage Reference Table 8. Digital Output Coding Code 4095 2048 2047 0 (VIN+) − (VIN−), Input Span = 2 V p-p (V) 1.000 0 −0.000488 −1.00 (VIN+) − (VIN−), Input Span = 1 V p-p (V) 0.500 0 −0.000244 −0.5000 Digital Output Offset Binary (D11 ... D0) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 Timing Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 bps (12 bits × 65 MSPS = 780 bps). The lowest typical conversion rate is 10 MSPS. Two output clocks are provided to assist in capturing data from the AD9229. The DCO is used to clock the output data and is equal to six times the sampling clock (CLK) rate. Data is clocked out of the AD9229 and can be captured on the rising and falling edges of the DCO that supports double-data rate (DDR) capturing. The frame clock out (FCO) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. DTP Pin The digital test pattern (DTP) pin can be enabled for two types of test patterns, as summarized in Table 9. When the DTP is tied to AVDD/3, all the ADC channel outputs shift out the following pattern: 1000 0000 0000. When the DTP is tied to 2 × AVDD/3, all the ADC channel outputs shift out the following pattern: 1010 1010 1010. The FCO and DCO outputs still work as usual while all channels shift out the test pattern. This pattern allows the user to perform timing alignment adjustments between the FCO, DCO, and the output data. For normal operation, this pin should be tied to AGND. Selected DTP Normal operation DTP1 AVDD/3 Resulting D+ and D– Normal operation 1000 0000 0000 DTP2 2 × AVDD/3 1010 1010 1010 Restricted AVDD N/A DTP Voltage AGND Resulting FCO and DCO Normal operation Normal operation Normal operation N/A A stable and accurate 0.5 V voltage reference is built into the AD9229. The input range can be adjusted by varying the reference voltage applied to the AD9229, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic, low ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9229. The recommended capacitor values and configurations for the AD9229 reference pin can be found in Figure 42 and Figure 43. Table 10. Reference Settings Selected Mode External Reference Internal, 1 V p-p FSR Programmable Internal, 2 V p-p FSR SENSE Voltage AVDD Resulting VREF (V) N/A VREF 0.2 V to VREF AGND to 0.2 V 0.5 0.5 × (1 + R2/R1) 1.0 Resulting Differential Span (V p-p) 2 × external reference 1.0 2 × VREF 2.0 Internal Reference Connection A comparator within the AD9229 detects the potential at the SENSE pin and configures the reference into four possible states (summarized in Table 10). If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 42), setting VREF to 1 V. Connecting the SENSE pin to the VREF pin switches the amplifier output to the SENSE pin, configuring the internal op amp circuit as a voltage follower and providing a 0.5 V reference output. If an external resistor divider is connected as shown in Figure 43, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode and defines the VREF output as R2 ⎞ VREF = 0.5 × ⎛⎜1 + ⎟ R1 ⎠ ⎝ In all reference configurations, REFT and REFB establish their input span of the ADC core. The analog input full-scale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration. Rev. B | Page 21 of 40 AD9229 External Reference Operation VIN+ VIN– REFT 0.1μF ADC CORE + 0.1μF 10μF REFB The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 45 shows the typical drift characteristics of the internal reference. 0.10 0.1μF VREF 0.08 0.1μF 0.5V 0.06 04418-036 SENSE VREF ERROR (%) SELECT LOGIC 0.04 0.02 VREF = 0.5V 0 –0.02 –0.04 Figure 42. Internal Reference Configuration VREF = 1.0V –0.06 04418-057 10μF –0.08 VIN+ VIN– –0.10 –40 REFT 0.1μF ADC CORE + 0.1μF 0.1μF 0.5V SENSE R1 04418-037 If the internal reference of the AD9229 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 44 depicts how the internal reference voltage is affected by loading. 0.05 –0.05 When connecting power to the AD9229, it is recommended that two separate 3.0 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length. VREF = 0.5V –0.10 –0.15 –0.20 VREF = 1.0V –0.25 –0.30 04418-058 VREF ERROR (%) 80 A single PC board ground plane should be sufficient when using the AD9229. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum performance is easily achieved. 0 –0.35 0.2 65 Power and Ground Recommendations Figure 43. Programmable Reference Configuration 0 50 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 7 kΩ load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a maximum of 1 V. SELECT LOGIC R2 5 20 35 TEMPERATURE (°C) Figure 45. Typical VREF Drift 0.1μF VREF –10 10μF REFB + 10μF –25 0.4 0.6 0.8 1.0 1.2 ILOAD (mA) 1.4 1.6 1.8 2.0 Figure 44. VREF Accuracy vs. Load Rev. B | Page 22 of 40 AD9229 It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9229. A continuous exposed copper plane on the PCB should mate to the AD9229 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder or epoxy filled (plugged). To maximize the solder coverage and adhesion between the ADC and PCB, overlay a silkscreen to partition the continuous copper plane on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no silkscreen partitions only guarantees one tie point between the ADC and PCB. See Figure 46 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, visit www.analog.com. Rev. B | Page 23 of 40 SILKSCREEN PARTITION PIN 1 INDICATOR 04418-052 Exposed Paddle Thermal Heat Slug Recommendations Figure 46. Typical PCB Layout AD9229 EVALUATION BOARD power supply. This enables the user to individually bias each section of the board. Use P501 to connect a different supply for each section. At least one 3.0 V supply is needed with a 1 A current capability for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply is needed in addition to the other 3.0 V supplies. The 5.0 V supply, or AVDD_VGA, should have a 1 A current capability as well. The AD9229 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a transformer (default) or through the AD8332 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8332 drive circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 48 to Figure 52). Figure 47 shows the typical bench characterization setup used to evaluate the ac performance of the AD9229. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the ultimate performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent. Use 1 m long, shielded, RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Dial in the desired frequency and amplitude within the ADC’s specifications tables. Typically, most ADI evaluation boards can accept a ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band band-pass filter with 50 Ω terminations. ADI uses TTE, Allen Avionics, and K&L types of band-pass filters. The filter should be connected directly to the evaluation board if possible. See Figure 47 to Figure 57 for complete schematics and layout plots that demonstrate the routing and grounding techniques that should be applied at the system level. POWER SUPPLIES This evaluation board comes with a wall mountable switching power supply that provides a 6 V, 2 A maximum output. Simply connect the supply to the rated 100 V to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P503. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. OUTPUT SIGNALS The default setup uses the HSC-ADC-FPGA high speed deserialization board, which deserializes the digital output data and converts it to parallel CMOS. These two channels interface directly with ADI’s standard dual-channel FIFO data capture board (HSC-ADC-EVALA-DC). Two of the four channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO. When operating the evaluation board in a nondefault condition, L504 to L506 can be removed to disconnect the switching WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz DRVDD_DUT GND XFMR INPUT + AD9229 EVALUATION BOARD ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER CLK CHA–CHD 12-BIT SERIAL LVDS HSC-ADC-FPGA HIGH SPEED DESERIALIZATION BOARD HSC-ADC-EVALA-DC FIFO DATA CAPTURE BOARD 2 CH 12-BIT PARALLEL CMOS USB CONNECTION Figure 47. Evaluation Board Connections Rev. B | Page 24 of 40 PC RUNNING ADC ANALYZER 04418-040 BAND-PASS FILTER 3.0V – GND – AVDD_VGA ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER 3.0V + + GND 5.0V – SWITCHING POWER SUPPLY AVDD_DUT 6V DC 2Amax AD9229 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS • DTP: To enable one of the two digital test patterns on digital outputs of the ADC, use JP202. If Pins 2 and 3 on JP202 are tied together (1.0 V source), this enables test pattern 1000 0000 0000. If Pins 1 and 2 on JP202 are tied together (2.0 V source), this enables test pattern 1010 1010 1010. See the DTP Pin section for more details. • LVDSBIAS: To change the level of the LVDS output level swing, simply change the value of R204. Other recommended values can be found in the Digital Outputs section. • D+, D–: If an alternate data capture method to the setup described in Figure 47 is used, optional receiver terminations, R205 to R210, can be installed next to the high speed backplane connector. The following is a list of the default and optional settings or modes allowed on the AD9229 Rev C evaluation board. • • • • • POWER: Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V to 240 V ac wall outlet at 47 Hz to 63 Hz and P503. AIN: The evaluation board is set up for a transformer coupled analog input with optimum 50 Ω impedance matching out to 400 MHz. For more bandwidth response, the 2.2 pF differential capacitor across the analog inputs could be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2. VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R224. This causes the ADC to operate in 2.0 V p-p full-scale range. A number of other VREF options are available on the evaluation board, including 1.0 V p-p fullscale range, a variable range that the user can set by choosing R219 and R220 as well as a separate external reference option using the ADR510 or ADR520. Simply populate R218 and R222 and remove C208. To use these optional VREF modes, switch the jumper setting on R221 to R224. Proper use of the VREF options is noted in the Voltage Reference section. CLOCK: The clock input circuitry is derived from a simple logic circuit using a high speed inverter that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle sine wave type inputs. If using an oscillator, two oscillator footprint options are also available (OSC200-201) to check the ADC’s performance. J203 and J204 give the user flexibility in using the enable pin, which is common on most oscillators. ALTERNATE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternate analog input drive configuration using the AD8332 dual VGA. This particular drive option may need to be populated, in which case all the necessary components are listed in Table 11. This table lists the necessary settings to properly configure the evaluation board for this option. For more details on the AD8332 dual VGA, how it works, and its optional pin settings, consult the AD8332 data sheet. To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. 1. Remove R102, R115, R128, R141, T101, T102, T103, and T1044 in the default analog input path. 2. Populate R101, R114, R127, and R140 with 0 Ω resistors in the analog input path. 3. Populate R106, R107, R119, R120, R132, R133, R144, and R145 with 10 kΩ resistors to provide an input commonmode level to the analog input. 4. Populate R105, R113, R118, R124, R131, R137, R151, and R43 with 0 Ω resistors in the analog input path. 5. Currently L305 to L312 and L405 to L412 are populated with 0 Ω resistors to allow signal connection. This area allows the user to design a filter if additional requirements are necessary. PWDN: To enable the power-down feature, simply short JP201 to AVDD on the PWDN pin. Rev. B | Page 25 of 40 AD9229 R105 0Ω DNP INH1 CHANNEL A P101 AIN R101 0Ω DNP P102 DNP R104 0Ω C101 0.1μF AIN FB101 C102 CM1 0.1μF 10 R103 0Ω R102 65Ω AVDD_DUT CH_A CM1 R111 1kΩ T101 1 6 2 5 3 4 VGA INPUT CONNECTION INH2 R152 DNP R108 33Ω VIN_A CM1 R160 499Ω FB103 10 C103 DNP C104 2.2pF R109 1kΩ C105 DNP R156 DNP R110 33Ω VIN_A R107 1kΩ DNP C106 DNP AVDD_DUT C107 0.1μF R118 0Ω DNP FB104 C108 0.1μF 10 P104 DNP AIN FB102 10 AVDD_DUT CH_B R114 0Ω DNP R115 65Ω R106 1kΩ DNP R113 0Ω DNP R112 1kΩ CHANNEL B P103 AIN AVDD_DUT CH_A VGA INPUT CONNECTION R116 0Ω R117 0Ω AVDD_DUT C109 CM2 0.1μF CH_B CM2 R125 1kΩ T102 1 6 2 5 3 4 R119 1kΩ DNP FB105 10 R153 DNP R121 33Ω VIN_B CM2 R161 499Ω FB106 10 C110 DNP R123 1kΩ C112 DNP R157 DNP R122 33Ω VIN_B R124 0Ω DNP R120 1kΩ DNP C113 DNP R126 1kΩ C111 2.2pF AVDD_DUT C114 0.1μF ANALOG INPUTS R131 0Ω DNP INH3 CHANNEL C P105 AIN R127 0Ω DNP P106 DNP R130 0Ω C115 0.1μF AIN FB107 C116 CM3 0.1μF 10 R129 0Ω R128 65Ω AVDD_DUT CH_C CM3 R138 1kΩ T103 1 6 2 5 3 4 VGA INPUT CONNECTION INH4 R154 DNP R134 33Ω VIN_C CM3 R162 499Ω FB109 10 C117 DNP C118 2.2pF R135 1kΩ C119 DNP R158 DNP R136 33Ω VIN_C R133 1kΩ DNP C120 DNP AVDD_DUT C121 0.1μF AVDD_DUT CH_D FB110 C122 0.1μF 10 P108 DNP AIN FB108 10 R151 0Ω DNP R140 0Ω DNP R141 65Ω R132 1kΩ DNP R137 0Ω DNP R139 1kΩ CHANNEL D P107 AIN AVDD_DUT CH_C VGA INPUT CONNECTION R143 0Ω R142 0Ω AVDD_DUT C123 CM4 0.1μF CH_D CM4 R149 1kΩ 6 2 5 3 4 R43 0Ω DNP FB111 10 R155 DNP R146 33Ω VIN_D CM4 R163 499Ω FB112 10 C124 DNP C125 2.2pF R148 1kΩ C126 DNP R159 DNP R147 33Ω VIN_D R145 1kΩ DNP C127 DNP AVDD_DUT C128 0.1μF 04418-041 R150 1kΩ T104 1 R144 1kΩ DNP DNP : DO NOT POPULATE Figure 48. Evaluation Board Schematic, DUT Analog Inputs Rev. B | Page 26 of 40 CHD CHD 37 D–D CHC CHC D+D 38 D–C 39 CHB 40 D–B D+C CHB 41 CHA A–D D+B 42 CHA 43 FCO D+A FCO 45 FCO– FCO+ 44 DCO 46 VIN +D VIN –A VIN –D AGND 36 GND 35 DRVDD_DUT 34 33 GND 32 R204 4.0kΩ AVDD_DUT 31 GND 30 GND DUTCLK 29 AVDD_DUT 28 GND 27 VIN_D 26 VIN_D 25 GND 24 AGND 23 22 21 REFT 20 19 13 AGND VIN –C VIN +A VIN +C AGND AVDD AGND REFB AVDD VREF 12 GND AVDD 18 11 VIN_A CLK SENSE 10 VIN_A OPTIONAL CLOCK OSCILLATOR AGND AD9229 PDWN AVDD GND AGND 17 9 AVDD 16 8 AVDD_DUT R203 10kΩ AVDD AGND 7 AVDD_DUT 47 AGND 6 GND PWDN ENABLE JP201 R228 10kΩ 4 DTP 15 3 JP202 DRVDD LVDSBIAS VIN +B 1 DRGND DNC 5 AVDD_DUT DRVDD VIN –B PIN 1 TO PIN 2 = 1010 1010 1010 PIN 2 TO PIN 3 = 1000 0000 0000 2 R202 10kΩ 3 DRGND 14 DRVDD_DUT AVDD_DUT DIGITAL TEST PATTERN ENABLE R201 10kΩ 2 DCO– U201 1 GND DCO+ 48 DCO AD9229 VIN_C VIN _C GND AVDD_DUT VREF_DUT JP203 VSENSE_DUT AVDD_DUT JP204 AVDD_DUT GND VIN_B VIN _B DIGITAL OUTPUTS OSC200 4 C209 0.1μF EOH GND DCO VCC OUTPUT 3 C204 0.1μF OSC201 1 14 C210 0.1μF NC/ENB GND VCC OUTPUT FCO 40 C9 39 58 C202 10μF REFERENCE DECOUPLING CBELV3I66MT C10 59 C203 0.1μF 2 GNDCD10 R205 60 AVDD_VGA 1 P202 CHA C201 0.1μF C8 38 57 CHB 7 C7 37 56 8 CHC R225 0Ω DNP CX3600C-65 DNP C6 36 55 CHD CLOCK CIRCUIT AVDD_DUT C5 35 DNP GNDCD9 R206 DNP GNDCD8 R207 DNP GNDCD7 R208 DNP GNDCD6 R209 DNP GNDCD5 R210 DNP GNDCD4 D10 50 D9 49 D8 48 D7 47 D6 46 D5 45 DCO FCO CHA CHB CHC CHD 54 R212 1kΩ P201 ENCODE INPUT C205 0.1μF R213 49.9Ω R211 1kΩ R229 0Ω U202 U202 1 R231 0Ω DNP 2 3 4 34 R214 22Ω AVDD_DUT:14 AVDD_DUT:14 GND:7 GND:7 C4 D4 GNDCD3 44 53 DUTCLK R230 0Ω DNP 33 C3 D3 GNDCD2 43 52 32 C2 D2 GNDCD1 42 51 31 C1 D1 GNDAB10 41 30 10 EXTERNAL REFERENCE CIRCUIT 9 REFERENCE CIRCUIT 8 VREF SELECT R218 0Ω DNP R215 2kΩ ADR510/ADR520 VREF_DUT R221 0Ω 1NV VOUT GND TRIM/NC B10 GNDAB9 20 A9 B9 GNDAB8 19 28 AVDD_DUT U203 A10 29 VREF = 1V = DEFAULT 7 VREF = 0.5V A8 B8 GNDAB7 18 27 A7 B7 GNDAB6 17 26 C206 0.1μF R216 10kΩ R217 470kΩ C207 0.1μF CW C208 10μF R219 DNP AVDD_DUT R222 0Ω R223 0Ω R224 0Ω R220 DNP 6 VREF = EXTERNAL A6 B6 GNDAB5 16 25 5 VREF = 0.5V (1 + R219/R220) 4 VREF = 1V A5 B5 GNDAB4 15 24 A4 B4 GNDAB3 14 23 VSENSE_DUT 3 A3 B3 GNDAB2 13 22 REMOVE C208 WHEN USING EXTERNAL VREF 2 A2 B2 GNDAB1 12 21 1 A1 B1 11 R205-R210 OPTIONAL OUTPUT TERMINATIONS DNP : DO NOT POPULATE Figure 49. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface Rev. B | Page 27 of 40 04418-042 1469169-1 POPULATE L305 TO L312 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER R321 DNP C303 DNP C304 DNP R318 DNP C307 0.1μF CH_C R320 DNP C305 DNP L309 DNP CH_C L306 DNP L307 DNP L310 DNP L311 DNP 1 C310 0.1μF 2 GND VG L312 DNP R307 187Ω R302 10kΩ VG CW R303 39kΩ R308 374Ω C308 0.1μF R306 187Ω L308 DNP EXT VG JP301 R319 DNP C309 0.1μF R305 374Ω R304 187Ω C306 DNP R309 187Ω AVDD_VGA C311 1nF AVDD_VGA C312 0.1μF R310 100kΩ DNP 16 RCLMP 26 15 ENBL GAIN HILO MODE 27 14 28 13 VCM2 AD8332 29 12 VIN1 VIN2 VIP1 VIP2 30 11 31 10 COM1 C321 18nF C325 0.1μF C323 22pF VPS2 LON2 C316 0.1μF R316 274Ω C319 0.1μF C320 10μF R317 10kΩ DNP C322 18nF C326 0.1μF C324 22pF L313 120nH L314 120nH C327 0.1μF C328 0.1μF DNP : DO NOT POPULATE INH4 INH3 Figure 50. Evaluation Board Schematic, Optional DUT Analog Input Drive Rev. B | Page 28 of 40 044181-003 R315 274Ω LOP2 8 7 INH2 LMD2 6 5 INH1 4 3 2 VPS1 LON1 1 C318 0.1μF AVDD_VGA C317 10μF AVDD_VGA R314 10kΩ LMD1 9 LOP1 C315 0.1μF C314 0.1μF COM2 32 MODE PIN POSITIVE GAIN SLOPE = 0V TO 1.0V NEGATIVE GAIN SLOPE = 2.25V TO 5.0V VCM1 C313 0.1μF R311 10kΩ DNP VG RCLAMP PIN HILO PIN = LO = ± 50mV HILO PIN = HI = ± 75mV AVDD_VGA COMM VOH2 17 18 19 VOL2 20 NC 22 23 21 VPSV ENBV VOL1 25 R311 10kΩ DNP VOH1 U301 COMM R312 10Ω 24 AVDD_VGA HILO PIN HI GAIN RANGE = 2.25V TO 5.0V LO GAIN RANGE = 0V TO 1.0V OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS C AND D POWER-DOWN ENABLE (0V TO 1V = DISABLE POWER) L305 DNP CH_D VARIABLE GAIN CIRCUIT (0V TO 1.0V DC) CH_D EXTERNAL VARIABLE GAIN DRIVE AD9229 AD9229 CH_B POPULATE L405 TO L412 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER CH_A R417 DNP R418 DNP C403 DNP C404 DNP C405 DNP L409 DNP CH_A R415 DNP L406 DNP L407 DNP L410 DNP L411 DNP C407 0.1μF R405 187Ω L408 DNP L412 DNP R416 DNP C410 0.1μF C409 0.1μF C408 0.1μF R404 374Ω R403 187Ω C406 DNP R407 374Ω R406 187Ω R408 187Ω C411 1nF AVDD_VGA C412 0.1μF R409 100kΩ DNP 16 RCLMP 26 15 ENBL GAIN HILO MODE 27 14 28 13 VCM2 AD8332 29 12 VIN1 VIN2 VIP1 VIP2 30 11 31 10 COM1 LON2 VPS2 R412 274Ω C423 18nF C421 0.1μF C425 22pF C416 0.1μF 8 7 INH2 LMD2 6 5 4 3 INH1 VPS1 LON1 2 1 C418 0.1μF LOP2 R413 274Ω C419 0.1μF C420 10μF R414 10kΩ DNP C424 18nF C422 0.1μF C426 22pF L413 120pH L414 120nH C427 0.1μF C428 0.1μF DNP : DO NOT POPULATE INH2 INH1 Figure 51. Evaluation Board Schematic, Optional DUT Analog Input Drive Continued Rev. B | Page 29 of 40 044181-044 C417 10μF AVDD_VGA R411 10kΩ LMD1 9 LOP1 C415 0.1μF C414 0.1μF COM2 32 MODE PIN POSITIVE GAIN SLOPE = 0V TO 1.0V NEGATIVE GAIN SLOPE = 2.25V TO 5.0V VCM1 C413 0.1μF R409 10kΩ DNP VG RCLAMP PIN HILO PIN = LO = ± 50mV HILO PIN = HI = ± 75mV AVDD_VGA COMM VOH2 17 18 19 VOL2 20 NC 22 23 21 VPSV ENBV VOL1 25 R401 10kΩ DNP VOH1 U401 COMM R402 10kΩ 24 AVDD_VGA HILO PIN HI GAIN RANGE = 2.25V TO 5.0V LO GAIN RANGE = 0V TO 1.0V OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS A AND B POWER-DOWN ENABLE (0V TO 1V = DISABLE POWER) L405 DNP CH_B AD9229 POWER SUPPLY INPUT 6V 2A MAX FER501 CHOKE_COIL F501 P503 4 1 SMDC110F 1 D502 SHOT_RECT 3A DO-214AB PWR_IN 3 2 R500 374Ω D501 S2A_RECT 2A DO-214AA C501 10μF 3 2 CR500 U501 L504 10μH ADP33339AKC-3 PWR_IN 3 INPUT OUTPUT1 2 OUTPUT4 4 C502 1μF GND 1 DUT_AVDD C503 1μF U502 L506 10μH ADP33339AKC-5 3 PWR_IN INPUT OUTPUT1 2 OUTPUT4 4 C514 1μF GND 1 VGA_AVDD C515 1μF U503 L505 10μH ADP33339AKC-3 PWR_IN 3 INPUT C506 1μF OUTPUT1 2 OUTPUT4 4 GND 1 DUT_DRVDD C507 1μF OPTIONAL POWER INPUT P501 DNP P1 P2 P3 P4 P5 P6 1 VGA_AVDD L503 10μH AVDD_VGA 5.0V 2 3 DUT_AVDD 4 5 C516 10μF DUT_DRVDD C517 0.1μF L502 10μH AVDD_DUT 3.0V 6 C508 10μF C509 0.1μF L501 10μH DNP : DO NOT POPULATE Figure 52. Evaluation Board Schematic, Power Supply Inputs Rev. B | Page 30 of 40 C505 0.1μF 04418-045 DRVDD_DUT 3.0V C504 10μF AD9229 DECOUPLING CAPACITORS DRVDD_DUT C613 0.1μF C614 0.1μF AVDD_VGA C617 0.1μF C618 0.1μF C619 0.1μF C620 0.1μF C625 0.1μF C630 0.1μF C631 0.1μF C621 0.1μF C632 0.1μF C628 0.1μF AVDD_DUT C627 0.1μF H1 H2 H3 H4 UNUSED GATES U202 GND 5 MOUNTING HOLES CONNECTED TO GROUND 6 AVDD_DUT : 14 GND : 7 U202 9 8 AVDD_DUT : 14 GND : 7 U202 11 10 AVDD_DUT : 14 GND : 7 U202 12 AVDD_DUT : 14 GND : 7 DNP : DO NOT POPULATE Figure 53. Evaluation Board Schematic, Decoupling and Miscellaneous Rev. B | Page 31 of 40 04418-046 13 04418-047 AD9229 Figure 54. Evaluation Board Layout, Primary Side Rev. B | Page 32 of 40 04418-048 AD9229 Figure 55. Evaluation Board Layout, Ground Plane Rev. B | Page 33 of 40 04418-049 AD9229 Figure 56. Evaluation Board Layout, Power Plane Rev. B | Page 34 of 40 04418-050 AD9229 Figure 57. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. B | Page 35 of 40 AD9229 Table 11. Evaluation Board Bill of Materials (BOM) Item 1 2 Qnty. per Board 1 59 3 4 4 9 5 8 6 REFDES AD9229LFCSP_REVC C327, C328, C630, C628, C629, C631, C632, C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C207, C313, C314, C315, C312, C318, C319, C412, C316, C325,C326, C413, C414, C415, C418, C419, C416, C421, C422, C427, C428, C505, C509, C517, C613, C614, C617, C618, C619, C620, C621, C625, C209, C210, C627 C104, C111, C118, C125 Device PCB Capacitor Pkg. PCB 402 Value PCB 0.1 μF, ceramic, X5R, 10 V, 10% tol Mfg. Mfg. Part Number Panasonic ECJ-0EB1A104K Capacitor 402 Murata GRM1555C1H2R2GZ01B Capacitor 805 AVX 08056D106KAT2A Capacitor 603 C0603C104K4RACTU Capacitor 402 Kemet C0402C102K3RACTU 7 4 C321, C322, C423, C424 Capacitor 402 AVX 0402YC183KAT2A 8 4 C323, C324, C425, C426 Capacitor 402 Kemet C0402C220J5GACTU 9 1 C501 Capacitor 1206 Kemet T491B106K016AS 10 6 Capacitor 603 Panasonic ECJ-1VB0J105K 11 1 C502, C503, C506, C507, C514, C515 CR500 LED 603 Panasonic LNJ314G8TRA 12 1 D502 Diode DO-214AB 0.1 μF, ceramic, X7R, 16 V, 10% tol 1000 pF, ceramic, X7R, 25 V, 10% tol 0.018 μF, ceramic, X7R, 16 V, 10% tol 22 pF, ceramic, NPO, 5% tol, 50 V 10 μF, tantalum, 16 V, 10% tol 1 μF, ceramic, X5R, 6.3 V, 10% tol Green, 4 V, 5 m candela 3 A, 30 V, SMC Kemet 2 C202, C208, C317, C320, C417, C420, C504, C508, C516 C307, C308, C309, C310, C407, C408, C409, C410 C311, C411 2.2 pF, ceramic, COG, 0.25 pF tol, 50 V 10 μF, 6.3 V ±10% ceramic X5R SK33MSCT 13 1 D501 Diode DO-214AA 2 A, 50 V, SMC 14 1 F501 Fuse 1210 15 1 FER501 2020 Murata DLW5BSN191SQ2L 16 12 Murata BLM18BA100SN1 17 2 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 JP201, JP301 Ferrite bead Ferrite bead 6.0 V, 2.2 A trip current resettable fuse 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz 10 Ω, test freq 100 MHz, 25% tol, 500 mA Micro Commercial Co. Micro Commercial Co. Tyco/Raychem Connector 2-pin Samtec TSW-102-07-G-S 18 3 JP204, JP203, JP202 Connector 3-pin Samtec TSW-103-07-G-S 603 100 mil header jumper, 2-pin 100 mil header jumper, 3-pin Rev. B | Page 36 of 40 S2A NANOSMDC110F-2 AD9229 Item 19 Qnty. per Board 6 20 REFDES L501, L502, L503, L504, L505, L506 Device Ferrite bead Pkg. 1210 Value 10 μH, bead core 3.2 × 2.5 × 1.6 SMD, 2A 120 nH, test freq 100 MHz, 5% tol, 150 mA 0 Ω, 1/8 W, 5% tol Mfg. Panasonic ECG Mfg. Part Number EXC-CL3225U1 4 L313, L314, L413, L414 Inductor 402 Murata LQG15HNR12J02B 21 12 Resistor 805 22 1 L305, L306, L307, L308, L309, L310, L405, L406, L407, L408, L409, L410, L311, L312, L411, L412 OSC200 Panasonic ERJ-6GEY0R00V Oscillator SMT Clock oscillator, 66.66 MHz, 3.3 V Sidemount SMA for 0.063" board thickness 1469169-1, right angle 2-pair, 25 mm, header assembly RAPC722, power supply connector 10 kΩ, 1/16 W, 5% tol CTS REEVES CB3LV-3C-66M6666-T 23 5 P201, P101, P103, P105, P107 Connector SMA Johnson Components 142-0711-821 24 1 P202 Connector HEADER Tyco 1469169-1 25 1 P503 Connector 0.1", PCMT Switchcraft SC1153 26 10 Resistor 402 27 7 R201, R202, R228, R203, R312, R314, R317, R402, R411, R414 R225, R129, R142, R224 Yageo America 9C04021A1002JLHF3 Resistor 402 0 Ω, 1/16 W, 5% tol 9C04021A0R00JLHF3 Resistor 402 ERJ-2RKF64R9X Resistor Resistor 603 402 Panasonic Panasonic ERJ-3GEY0R00V ERJ-2RKF1001X Resistor 402 Resistor 402 Yageo America Panasonic 9C04021A33R0JLHF3 4 R104, R116, R130, R143 R111, R112, R125, R126, R138, R139, R149, R150, R211, R212, R109, R123, R135, R148 R108, R110, R121, R122, R134, R136, R146, R147 R160, R161, R162, R163 64.9 Ω, 1/16 W, 1% tol 0 Ω, 1/10 W, 5% tol 1 kΩ, 1/16 W, 1% tol Yageo America Panasonic 28 4 R102, R115, R128, R141 29 30 4 14 31 8 32 33 1 R215 Resistor 402 9C04021A2001JLHF3 34 1 R204 Resistor 402 Yageo America Panasonic 35 1 R213 Resistor 402 Susumu RR0510R-49R9-D 36 1 R214 Resistor 402 9C04021A22R0JLHF3 37 2 R216,R302 Potentiom eter 3-lead Yageo America BC Components 38 1 R217 Resistor 402 39 1 R303 Resistor 402 40 8 R304, R306, R307, R309, R403, R405, R406, R408, Resistor 402 33 Ω, 1/16 W, 5% tol 499 Ω, 1/16 W, 1% tol 2 kΩ, 1/16 W, 5% tol 4.02 kΩ, 1/16 W, 1% tol 49.9 Ω, 1/16 W, 0.5% tol 22 Ω, 1/16 W, 5% tol 10 kΩ, Cermet trimmer potentiometer, 18 turn top adjust, 10%, ½ W 470 kΩ, 1/16 W, 5% tol 39 kΩ, 1/16 W, 5% tol 187 Ω, 1/16 W, 1% tol Rev. B | Page 37 of 40 ERJ-2RKF4990X ERJ-2RKF4021X CT-94W-103 Yageo America Susumu 9C04021A4703JLHF3 Panasonic ERJ-2RKF1870X RR0510P-393-D AD9229 Item 41 Qnty. per Board 4 42 4 REFDES R305, R308, R404, R407, R500 R315, R316, R412, R413 43 4 44 Device Resistor Pkg. 402 Resistor 402 T101, T102, T103, T104 Transforme r CD542 2 U501, U503 IC SOT-223 45 2 U301, U401 IC LFCSP, CP32 46 47 1 1 U502 U201 IC IC SOT-223 LFCSP, CP48-1 48 1 U203 IC SOT-23 49 1 U202 IC TSSOP 50 4 MP101-104 Part of assembly 51 4 MP105-108 52 4 MP109-112 Part of assembly Part of assembly Value 374 Ω, 1/16 W, 1% tol 274 Ω, 1/16 W, 1% tol ADT1-1WT, 1:1 impedance ratio transformer ADP33339AKC-3, 1.5 A, 3.0 V LDO regulator AD8332ACP, ultralow noise precision dual VGA ADP33339AKC-5 AD9229-65, quad 12-bit, 65 MSPS serial LVDS 3 V ADC ADR510AR, 1.0 V, precision low noise shunt voltage reference 74VHC04MTC, hex inverter CBSB-14-01A-RT, 7/8" height, standoffs for circuit board support SNT-100-BK-G-H, 100 mil jumpers 5-330808-3, pin sockets, closed end for OSC200 Rev. B | Page 38 of 40 Mfg. Panasonic Mfg. Part Number ERJ-2RKF3740X Panasonic ERJ-2RKF2740X Mini-Circuits ADT1-1WT ADI ADP33339AKC-3 ADI AD8332ACP ADI ADI ADP33339AKC-5 AD9229ABCPZ-65 ADI ADR510AR Fairchild 74VHC04MTC Richco CBSB-14-01A-RT Samtec SNT-100-BK-G-H AMP 5-330808-3 AD9229 OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 48 1 0.50 REF *5.55 EXPOSED PAD 5.50 SQ 5.45 (BOTTOM VIEW) 25 24 TOP VIEW 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.50 0.40 0.30 13 12 0.22 MIN 5.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. 02-23-2010-C 7.10 7.00 SQ 6.90 Figure 58. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9229ABCPZ-65 AD9229ABCPZRL7-65 AD9229ABCPZ-50 AD9229ABCPZRL7-50 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ Z = RoHS Compliant Part. Rev. B | Page 39 of 40 Package Option CP-48-8 CP-48-8 CP-48-8 CP-48-8 AD9229 NOTES © 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04418–0–5/10(B) Rev. B | Page 40 of 40