12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter AD9237 FEATURES APPLICATIONS Ultrasound and medical imaging Battery-powered instruments Hand-held scope meters Low cost digital oscilloscopes Low power digital still cameras and copiers Low power communications FUNCTIONAL BLOCK DIAGRAM DRVDD AVDD VIN+ SHA 10-STAGE 1 1/2-BIT PIPELINE MDAC1 VIN– 4 REFT A/D 15 3 A/D REFB CORRECTION LOGIC 12 MODE2 OE OTR OUTPUT BUFFERS D11 AD9237 VREF D0 CLOCK DUTY CYCLE STABILIZER SENSE REF SELECT MODE SELECT 0.5V AGND CLK PDWN MODE DGND 05455-001 Ultralow power 85 mW at 20 MSPS 135 mW at 40 MSPS 190 mW at 65 MSPS SNR = 66 dBc to Nyquist at 65 MSPS SFDR = 80 dBc to Nyquist at 65 MSPS DNL = ±0.7 LSB Differential input with 500 MHz bandwidth Flexible analog input: 1 V p-p to 4 V p-p range Offset binary, twos complement, or gray code data formats Output enable pin 2-step power-down Full power-down and sleep mode Clock duty cycle stabilizer Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9237 is a family of monolithic, single 3 V supply, 12-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converters (ADC). This family features a high performance sample-andhold amplifier (SHA) and voltage reference. The AD9237 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20 MSPS/ 40 MSPS/65 MSPS data rates and guarantees no missing codes over the full operating temperature range. 1. Evaluation boards available for all speed grades. 2. Operating at 65 MSPS, the AD9237 consumes a low 190 mW at 65 MSPS, 135 mW at 40 MSPS, and 85 mW at 20 MSPS. 3. Power scaling reduces the operating power further when running at lower speeds. 4. The AD9237 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 5. The patented SHA input maintains excellent performance for input frequencies beyond Nyquist and can be configured for single-ended or differential operation. 6. The AD9237 is optimized for selectable and flexible input ranges from 1 V p-p to 4 V p-p. 7. An output enable pin allows for multiplexing of the outputs. 8. Two-step power-down supports a standby mode in addition to a power-down mode. 9. The OTR output bit indicates when the signal is beyond the selected input range. 10. The clock duty cycle stabilizer (DCS) maintains converter performance over a wide range of clock pulse widths. With significant power savings over previously available ADCs, the AD9237 is suitable for applications in imaging and medical ultrasound. Fabricated on an advanced CMOS process, the AD9237 is available in a 32-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD9237 TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .......................................................................................9 Applications....................................................................................... 1 Equivalent Circuits......................................................................... 10 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 11 General Description ......................................................................... 1 Applying the AD9237 .................................................................... 16 Product Highlights ........................................................................... 1 Theory of Operation .................................................................. 16 Revision History ............................................................................... 2 Analog Input and Reference Overview ................................... 16 Specifications..................................................................................... 3 Voltage Reference ....................................................................... 18 DC Specifications ......................................................................... 3 Clock Input Considerations...................................................... 19 Digital Specifications ................................................................... 4 Power Dissipation, Power Scaling, and Standby Mode......... 19 AC Specifications.......................................................................... 4 Digital Outputs ........................................................................... 21 Switching Specifications .............................................................. 5 LFCSP Evaluation Board........................................................... 22 Timing Diagram ............................................................................... 6 Outline Dimensions ....................................................................... 28 Absolute Maximum Ratings............................................................ 7 Ordering Guide .......................................................................... 28 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 REVISION HISTORY 10/05—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9237 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, −0.5 dBFS input, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Guaranteed Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error1 INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA Reference Input Resistance INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span VREF = 0.5 V; MODE2 = 0 V VREF = 1.0 V; MODE2 = 0 V VREF = 0.5 V; MODE2 = AVDD VREF = 1.0 V; MODE2 = AVDD Input Capacitance 3 POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION DC Input 4 Sine Wave Input2 Power-Down Mode Standby Power Min 12 AD9237BCP-20 Typ Max 12 Min 12 AD9237BCP-40 Typ Max 12 ±1.30 ±0.70 ±0.70 ±0.90 ±1.95 ±2.10 ±0.95 ±1.35 ±5 0.8 ±2.5 0.1 7 ±5 0.8 ±2.5 0.1 7 1.35 0.70 2.7 2.25 30.5 3.0 ±0.01 85 100 1 20 3.0 2.5 ±25 ±5 0.8 ±2.5 0.1 7 1 135 150 1 20 ±25 2.7 2.25 3.0 2.5 190 210 1 20 mV mV mV mV kΩ 1 2 2 4 V p-p V p-p V p-p V p-p pF 3.6 3.6 V V 64.5 5.5 ±0.01 180 Bits % FSR % FSR LSB LSB LSB rms LSB rms 7 3.6 3.6 Unit Bits ppm/°C ppm/°C 1.35 0.70 45.5 4.5 ±0.01 120 ±1.95 ±2.25 +1.25 ±2.00 ±2 ±12 7 3.6 3.6 ±1.30 ±1.05 ±0.70 ±0.90 1 2 2 4 7 3.0 2.5 −1.00 1.35 0.70 1 2 2 4 2.7 2.25 ±1.95 ±2.10 ±0.95 ±1.35 ±2 ±12 ±25 AD9237BCP-65 Typ Max 12 ±1.30 ±0.75 ±0.70 ±0.90 ±2 ±12 Min 12 mA mA % FSR 270 mW mW mW mW Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 2 Rev. 0 | Page 3 of 28 AD9237 DIGITAL SPECIFICATIONS Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS 1 DRVDD = 3.3 V High-Level Output Voltage (IOH = 50 μA) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 μA) DRVDD = 2.5 V High-Level Output Voltage (IOH = 50 μA) High-Level Output Voltage (IOH = 0.5 mA) Low-Level Output Voltage (IOL = 1.6 mA) Low-Level Output Voltage (IOL = 50 μA) 1 AD9237BCP-20 Min Typ Max AD9237BCP-40 Min Typ Max AD9237BCP-65 Min Typ Max 2.0 2.0 2.0 0.8 +10 +10 –10 –10 0.8 +10 +10 –10 –10 2 –10 –10 2 3.29 3.25 2 3.29 3.25 3.29 3.25 0.2 0.05 2.49 2.45 0.8 +10 +10 0.2 0.05 2.49 2.45 0.2 0.05 V V μA μA pF 0.2 0.05 V V V V 0.2 0.05 V V V V 2.49 2.45 0.2 0.05 Unit Output voltage levels measured with 5 pF load on each output. AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, TMIN to TMAX, unless otherwise noted. Table 3. Parameter SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 34.2 MHz fINPUT = 70 MHz SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 34.2 MHz fINPUT = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 34.2 MHz AD9237BCP-20 Min Typ Max AD9237BCP-40 Min Typ Max AD9237BCP-65 Min Typ Max 66.8 66.6 66.5 66.5 65.6 65.3 66.6 64.0 65.1 66.0 66.3 66.1 65.9 66.7 66.5 66.4 66.3 64.4 65.8 65.8 65.2 10.6 Bits Bits Bits 10.8 10.7 Rev. 0 | Page 4 of 28 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 66.4 63.5 65.6 Unit AD9237 Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 34.2 MHz fINPUT = 70 MHz WORST HARMONIC (SECOND OR THIRD) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 34.2 MHz fINPUT = 70 MHz WORST OTHER SPUR fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 34.2 MHz fINPUT = 70 MHz AD9237BCP-20 Min Typ Max AD9237BCP-40 Min Typ Max AD9237BCP-65 Min Typ Max 88.0 87.5 83.5 85.5 72.4 72.2 82.4 69.4 −72.4 80.5 77.9 80.1 74.9 −88.0 −87.5 −83.5 −85.5 −72.2 −82.4 −69.4 −73.4 −80.5 −77.9 −80.1 −74.9 −90 −90 −90 −90 −73.1 −90 −72.0 −90 −90 −90 −90 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc SWITCHING SPECIFICATIONS Table 4. Parameter CLK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse Width High 1 CLK Pulse Width Low1 DATA OUTPUT PARAMETERS Output Delay (tPD) 2 Pipeline Delay (Latency) Output Enable Time Output Disable Time Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time (Sleep Mode) 3 Wake-Up Time (Standby Mode)3 OUT-OF-RANGE RECOVERY TIME Min AD9237BCP-20 Typ Max 20 Min AD9237BCP-40 Typ Max 40 AD9237BCP-65 Typ Max 65 1 50.0 15.0 15.0 Min 1 25.0 8.8 8.8 3.5 8 6 3 1.0 0.5 3.0 3.0 1 3.5 8 6 3 1.0 0.5 3.0 3.0 1 1 1 15.4 6.2 6.2 3.5 8 6 3 1.0 0.5 3.0 3.0 2 With duty cycle stabilizer enabled. Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. 2 Rev. 0 | Page 5 of 28 Unit MSPS MSPS ns ns ns ns Cycles ns ns ns ps rms ms μs Cycles AD9237 TIMING DIAGRAM N N+1 N+2 N–1 N+3 tA ANALOG INPUT N+8 N+7 N+4 N+5 N+6 DATA OUT N–10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 tPD Figure 2. Timing Diagram Rev. 0 | Page 6 of 28 N–1 N 05455-002 CLK AD9237 ABSOLUTE MAXIMUM RATINGS Table 5. With Respect to Pin Name ELECTRICAL AVDD AGND DRVDD DGND AGND DGND AVDD DRVDD DGND Digital Outputs, OE AGND CLK, MODE, MODE2 VIN+, VIN– AGND VREF AGND SENSE AGND REFB, REFT AGND PDWN AGND ENVIRONMENTAL 1 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature 1 Min Max Unit –0.3 –0.3 –0.3 –3.9 –0.3 +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 V V V V V −0.3 AVDD + 0.3 V –0.3 –0.3 –0.3 –0.3 –0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 V V V V V –40 +85 150 300 +150 °C °C °C °C –65 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Typical thermal impedances (32-lead LFCSP), θJA = 32.5°C/W, θJC = 32.71°C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-1. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 AD9237 32 31 30 29 28 27 26 25 AVDD AGND VIN– VIN+ AGND AVDD REFT REFB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD9237 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VREF SENSE MODE OTR D11 (MSB) D10 D9 D8 DNC = DO NOT CONNECT 05455-003 D2 D3 D4 D5 D6 D7 DGND DRVDD 9 10 11 12 13 14 15 16 MODE2 CLK OE PDWN GC DNC D0 (LSB) D1 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin Number 1 2 3 4 5 6 7 to 14, 17 to 20 15 16 Mnemonic MODE2 CLK OE PDWN GC DNC D0 (LSB) to D11 (MSB) DGND DRVDD 21 22 23 24 25 26 27, 32 OTR MODE SENSE VREF REFB REFT AVDD 28, 31 29 30 AGND VIN+ VIN− Description SHA Gain Select and Power Scaling Control (see Table 8). Clock Input Pin. Output Enable Pin (Active Low). Power-Down Function Selection (see Table 9). Gray Code Control (Active High). Do Not Connect. Data Output Bits. Digital Output Ground. Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. Out-of-Range Indicator. Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 10). Reference Mode Selection (see Table 7). Voltage Reference Input/Output (see Table 7). Differential Reference (−). Must be decoupled to REFT with a minimum 10 μF capacitor. Differential Reference (+). Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. Analog Ground. Analog Input Pin (+). Analog Input Pin (−). Rev. 0 | Page 8 of 28 AD9237 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Signal-To-Noise and Distortion (SINAD)1 The ratio of the rms signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Effective Number of Bits (ENOB) The effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD using the following formula: Aperture Jitter (tJ) The sample-to-sample variation in aperture delay. ENOB = (SINADdBFS − 1.76)/6.02 Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. Offset Error The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN–. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Power Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Total Harmonic Distortion (THD) 1 The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. Signal-to-Noise Ratio (SNR)1 The ratio of the rms signal to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR)1 SFDR is the difference in dB between the rms amplitude of the input signal and the rms value of the peak spurious signal. The peak spurious signal may not be an harmonic. Two-Tone SFDR1 The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay (tPD) The delay between the clock logic threshold and the time when all bits are within valid logic levels. Out-of-Range Recovery Time The time it takes the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. 0 | Page 9 of 28 AD9237 EQUIVALENT CIRCUITS DRVDD AVDD VIN+, VIN– 05455-006 05455-004 D11–D0, OTR Figure 6. Equivalent Digital Output Circuit Figure 4. Equivalent Analog Input Circuit 375Ω 70kΩ 375Ω 05455-007 CLK, PDWN 05455-005 MODE, MODE2, GC, OE Figure 5. Equivalent MODE, MODE2, GC, OE Input Circuit Figure 7. Equivalent CLK, PDWN Input Circuit Rev. 0 | Page 10 of 28 AD9237 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate with DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = –0.5 dBFS, VREF = 1.0 V internal, FFT length 16 K, unless otherwise noted. 90 0 SFDR –20 85 –40 80 SNR/SFDR (dBc) AMPLITUDE (dBFS) SNR = 66.9dBc SFDR = 87.0dBc –60 –80 75 70 SNR –100 –120 2 0 4 6 FREQUENCY (MHz) 8 60 10.0 10 Figure 8. AD9237-20 10 MHz FFT 05455-011 05455-008 65 12.5 15.0 17.5 CLOCK FREQUENCY (MSPS) 20.0 Figure 11. AD9237-20 SNR/SFDR vs. Clock Frequency with fIN = 10 MHz 0 90 SNR = 66.8dBc SFDR = 83.1dBc 85 SFDR –40 SNR/SFDR (dBc) –60 –80 80 75 70 05455-009 –100 –120 0 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 SNR 65 20 20 Figure 9. AD9237-40 20 MHz FFT 05455-012 AMPLITUDE (dBFS) –20 25 30 35 CLOCK FREQUENCY (MSPS) 40 Figure 12. AD9237-40 SNR/SFDR vs. Clock Frequency with fIN = 20 MHz 0 90 SNR = 66.0dBc SFDR = 78.6dBc –20 85 –40 80 SNR/SFDR (dBc) –60 –80 75 70 SNR –100 –120 0 5 10 15 20 FREQUENCY (MHz) 25 30 32.5 Figure 10. AD9237-65 70 MHz FFT 60 40 05455-013 65 05455-010 AMPLITUDE (dBFS) SFDR 45 50 55 CLOCK FREQUENCY (MSPS) 60 65 Figure 13. AD9237-65 SNR/SFDR vs. Clock Frequency with fIN = 35 MHz Rev. 0 | Page 11 of 28 AD9237 0 90 SFDR DCS ENABLED SNR = 65.6dBc SFDR = 67.1dBc 85 –20 SNR/SFDR (dBc) AMPLITUDE (dBc) 80 –40 –60 –80 SFDR DCS DISABLED 75 70 SNR DCS ENABLED 65 60 SNR DCS DISABLED –100 –120 0 5 10 15 20 FREQUENCY (MHz) 25 05455-030 05455-014 55 50 30 30 32.5 35 Figure 14. AD9237-65 100 MHz FFT 65 70 SFDR dBFS 2V p-p 80 SNR/SFDR (dBc and dBFS) SFDR dBFS 2V p-p SNR dBFS 2V p-p SNR dBFS 4V p-p 60 SFDR dBc 4V p-p SFDR dBc 2V p-p 50 70 SFDR dBc 1V p-p SNR dBFS 1V p-p 60 50 SNR dBc 1V p-p 40 05455-017 40 SFDR dBFS 1V p-p SFDR dBc 2V p-p SNR dBFS 2V p-p SNR dBc 2V p-p SNR dBc 4V p-p 30 –30 –25 –20 –15 –10 INPUT AMPLITUDE (dBFS) –5 SNR dBc 2V p-p 30 –30 0 Figure 15. AD9237-65 SNR/SFDR vs. Input Amplitude with fIN = 35 MHz 05455-018 80 –25 –20 –15 –10 INPUT AMPLITUDE (dBFS) –5 0 Figure 18. AD9237-65 SNR/SFDR vs. Input Amplitude with fIN = 35 MHz 100 100 SFDR dBFS 2V p-p SFDR dBFS 2V p-p 90 SNR/SFDR (dBc and dBFS) 90 SFDR dBc 2V p-p 80 SFDR dBFS 1V p-p SFDR dBc 1V p-p 70 60 SNR dBFS 2V p-p SNR dBFS 1V p-p 50 40 05455-019 SNR dBc 2V p-p SNR dBc 1V p-p 30 –30 –25 –20 –15 –10 INPUT AMPLITUDE (dBFS) –5 0 Figure 16. AD9237-40 SNR/SFDR vs. Input Amplitude with fIN = 20 MHz Rev. 0 | Page 12 of 28 80 SFDR dBFS 1V p-p SFDR dBc 2V p-p SFDR dBc 1V p-p 70 60 SNR dBFS 2V p-p SNR dBFS 1V p-p 50 40 SNR dBc 2V p-p 05455-020 SNR/SFDR (dBc and dBFS) 60 90 SFDR dBFS 4V p-p SNR/SFDR (dBc and dBFS) 45 50 55 DUTY CYCLE (%) Figure 17. SNR/SFDR vs. Clock Duty Cycle 90 70 40 SNR dBc 1V p-p 30 –30 –25 –20 –15 –10 INPUT AMPLITUDE (dBFS) –5 0 Figure 19. AD9237-20 SNR/SFDR vs. Input Amplitude with fIN = 10 MHz AD9237 0 100 SNR = 67.0dBFS SFDR = 87.8dBFS 90 SNR/SFDR (dBc and dBFS) –40 –60 –80 –100 0 5 10 15 20 FREQUENCY (MHz) 25 60 SFDR dBc 50 SNR dBc 30 –30 –25 30 32.5 Figure 20. AD9237-65 Two-Tone FFT, fIN1 = 45 MHz, fIN2 = 46 MHz 70 SNR dBFS 40 05455-095 –120 SFDR dBFS 80 05455-024 AMPLITUDE (dBc) –20 –20 –15 INPUT AMPLITUDE (AIN) –10 –6.5 Figure 23. AD9237-65 Two-Tone SNR/SFDR , vs. Analog Input with fIN1 = 45 MHz, fIN2 = 46 MHz 0 100 SNR = 67.2dBFS SFDR = 88.3dBFS 90 SFDR dBFS SNR/SFDR (dBc and dBFS) –40 –60 –80 –100 5 0 10 FREQUENCY (MHz) 15 60 SFDR dBc 50 SNR dBc 30 –30 –25 20 Figure 21. AD9237-40 Two-Tone FFT fIN1 = 45 MHz, fIN2 = 46 MHz 70 SNR dBFS 40 05455-021 –120 80 05455-025 AMPLITUDE (dBc) –20 –20 –15 INPUT AMPLITUDE (AIN) –10 –6.5 Figure 24. AD9237-40 Two-Tone SNR/SFDR , vs. Analog Input with fIN1 = 45 MHz, fIN2 = 46 MHz 0 100 SNR = 66.9dBFS SFDR = 84.1dBFS 90 SNR/SFDR (dBc and dBFS) –40 –60 –80 05455-094 –100 –120 0 5 10 15 20 FREQUENCY (MHz) 25 30 Figure 22. AD9237-65 Two-Tone FFT, fIN1 = 69 MHz, fIN2 = 70 MHz SFDR dBFS 80 70 SNR dBFS 60 SFDR dBc 50 40 SNR dBc 30 –30 –25 05455-098 AMPLITUDE (dBFS) –20 –20 –15 INPUT AMPLITUDE (AIN) –10 –6.5 Figure 25. AD9237-65 Two-Tone SNR/SFDR vs. Analog Input with fIN1 = 69 MHz, fIN2 = 70 MHz Rev. 0 | Page 13 of 28 AD9237 0 100 SNR = 67.1dBFS SFDR = 87.3dBFS 90 –20 SNR/SFDR (dBc and dBFS) –40 –60 –80 –100 5 0 10 FREQUENCY (MHz) 15 SFDR dBc 50 SNR dBc 30 –30 –25 20 Figure 26. AD9237-40 Two-Tone FFT fIN1 = 69 MHz, fIN2 = 70 MHz 60 40 05455-026 –120 70 SNR dBFS 05455-097 AMPLITUDE (dBc) SFDR dBFS 80 –20 –15 INPUT AMPLITUDE (AIN) –10 –6.5 Figure 29. AD9237-40 Two-Tone SNR/SFDR vs. Analog Input with fIN1 = 69 MHz, fIN2 = 70 MHz 90 90 85 85 SFDR SFDR 75 70 SNR 70 SNR 65 65 60 60 0 25 50 75 INPUT FREQUENCY (MHz) 100 55 0 125 Figure 27. AD9237-65 SNR/SFDR vs. Input Frequency 0.75 0.75 0.50 0.50 0.25 0.25 DNL (LSB) 1.00 0 –0.50 –0.50 –0.75 –0.75 05455-032 –0.25 512 1024 1536 2048 CODE 2560 3072 3584 100 125 0 –0.25 0 50 75 INPUT FREQUENCY (MHz) Figure 30. AD9237-40 SNR/SFDR vs. Input Frequency 1.00 –1.00 25 4096 Figure 28. Typical INL 05455-035 55 INL (LSB) 75 05455-016 SNR/SFDR (dBc) 80 05455-015 SNR/SFDR (dBc) 80 –1.00 0 512 1024 1536 2048 CODE 2560 Figure 31. Typical DNL Rev. 0 | Page 14 of 28 3072 3584 4096 AD9237 67.5 85 10.83 AD9237-20 SNR 10.75 AD9237-65 66.0 10.67 ENOB (Bits) 66.5 80 75 70 SFDR 65.0 10 10.59 20 30 40 50 CLOCK FREQUENCY (MSPS) 60 10.50 70 65 Figure 32. AD9237 SINAD/ENOB vs. Clock Frequency with fIN = Nyquist Rev. 0 | Page 15 of 28 60 –40 05455-063 65.5 05455-062 SINAD (dBc) AD9237-40 SNR/SFDR (dBc) 67.0 90 –20 0 20 40 TEMPERATURE (°C) 60 80 85 Figure 33. AD9237-65 SNR/SFDR vs. Temperature with fIN = 32.5MHz AD9237 APPLYING THE AD9237 90 THEORY OF OPERATION 2.5MHz SFDR The AD9237 uses a calibrated, 11-stage pipeline architecture with a patented input SHA implemented. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor digital-to-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down and stand-by operation, the output buffers go into a high impedance state. The ADC samples the analog input on the rising edge of the clock. System disturbances just prior to, or immediately following, the rising edge of the clock and/or excessive clock jitter can cause the SHA to acquire the wrong input value and should be minimized. 34.2MHz SFDR SNR/SFDR (dBc) 70 2.5MHz SNR 34.2MHz SNR 60 50 40 05455-038 The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. While the converter captures a new input sample every clock cycle, it takes eight clock cycles for the conversion to be fully processed and to appear at the output, as shown in Figure 2. 80 30 0 0.5 1.0 1.5 2.0 INPUT COMMON-MODE LEVEL (V) 2.5 3.0 Figure 34. AD9237-65 SNR/SFDR vs. Input Common-Mode Level In addition, a small shunt capacitor placed across the inputs provides dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependant on the application. In IF undersampling applications, the shunt capacitor(s) should be reduced or removed depending on the input frequency. In combination with the driving source impedance, the capacitors limit the input bandwidth. H T T 5pF VIN+ CPAR ANALOG INPUT AND REFERENCE OVERVIEW T Figure 35 shows the clock signal alternately switching the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. 5pF VIN– CPAR T H 05455-039 The analog input to the AD9237 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range and maintain excellent performance, as shown in Figure 34. An input common-mode voltage of midsupply minimizes signal-dependant errors and provides optimum performance. Figure 35. Switched-Capacitor SHA Input For best dynamic performance, the source impedances driving VIN+ and VIN– should be matched so that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, that define the span of the ADC core. Rev. 0 | Page 16 of 28 AD9237 The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and input span are defined as: 1kΩ 0.1μF 1.2kΩ 0.1μF AVDD 33Ω VIN+ + 2V p-p 15pF AD8351 49.9Ω REFT = ½(AVDD + VREF) 0.1μF – 25Ω REFB = ½(AVDD − VREF) AD9237 33Ω VIN– 0.1μF AGND 1kΩ 4 × (REFT − REFB ) 4 × VREF Span = = Span _ Factor Span _ Factor 05455-041 25Ω Figure 36. Differential Input Configuration Using the AD8351 The previous equations show that the REFT and REFB voltages are symmetrical about the midsupply voltage, and the input span is proportional to the value of the VREF voltage, see Table 7 for more details. The internal voltage reference can be pin strapped to fixed values of 0.5 V or 1.0 V, or adjusted within this range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9237 set to an input span of 2 V p-p or greater. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9237. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 37. AVDD 33Ω 2V p-p The SHA must be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as: 15pF 49.9Ω 33Ω 1kΩ 0.1μF VIN+ AD9237 VIN– AGND 05455-042 1kΩ Figure 37. Differential Transformer-Coupled Configuration VCMMIN = VREF/2 The minimum common-mode input level allows the AD9237 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source can be driven into VIN+ or VIN–. In this configuration, one input accepts the signal while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal can be applied to VIN+ while a 1 V reference is applied to VIN–. The AD9237 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and in the lower speed grade models (AD9237-40 and AD9237-20). The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can cause core saturation, which leads to distortion. Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, there is degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 38 details a typical singleended input configuration. Differential Input Configurations 0.1μF 2V p-p As previously detailed, optimum performance is achieved while driving the AD9237 in a differential input configuration. For baseband applications, the AD8351 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8351 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Figure 36 details a typical configuration using the AD8351. Rev. 0 | Page 17 of 28 1kΩ 1kΩ 1kΩ 49.9Ω 0.1μF 1kΩ 33Ω 15pF 33Ω AVDD VIN+ AD9237 VIN– AGND 25Ω 05455-099 VCMMAX = (AVDD + VREF)/2 Figure 38. Single-Ended Input Configuration AD9237 Table 7. Reference Configuration Summary Selected Mode External Reference SENSE Voltage AVDD Resulting VREF (V) N/A Span Factor 2 Resulting Differential Span (V p-p) 4 × External Reference Span _ Factor Internal Fixed Reference VREF 0.5 Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) (See Figure 40) Internal Fixed Reference AGND to 0.2 V 1.0 1 2 1 2 1.0 V 4.0 V 4 × VREF Span _ Factor 1 2 1 2.0 V 1.0 V VOLTAGE REFERENCE VIN+ A stable and accurate 0.5 V voltage reference is built into the AD9237. The input range can be adjusted by varying the reference voltage applied to the AD9237, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. REFT 0.1μF ADC CORE + 0.1μF 10μF REFB 0.1μF VREF 10μF + 0.1μF 0.5V SELECT LOGIC SENSE AD9237 05455-043 In all reference configurations, REFT and REFB drive the A/D conversion core and, in conjunction with the span factor, establish its input span. The input range of the ADC always equals four times the voltage at the reference pin divided by the span factor for either an internal or an external reference. It is required to decouple REFT to REFB with 0.1 μF and 10 μF decoupling capacitors, as shown in Figure 39. VIN– Figure 39. Internal Reference Configuration Internal Reference Connection VIN+ VIN– REFT 0.1μF ADC CORE + 0.1μF 10μF REFB 0.1μF VREF 10μF R2 ⎞ VREF = 0.5 × ⎛⎜1 + ⎟ R1 ⎠ ⎝ + 0.1μF R2 0.5V SELECT LOGIC SENSE R1 AD9237 Figure 40. Programmable Reference Configuration Rev. 0 | Page 18 of 28 05455-044 A comparator within the AD9237 detects the potential at the SENSE pin and configures the reference into one of four possible states, which are summarized in Table 7. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider, setting VREF to 1 V (see Figure 39). Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected, as shown in Figure 40, then the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as AD9237 External Reference Operation CLOCK INPUT CONSIDERATIONS The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 41 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. When multiple ADCs track one another, a single reference (internal or external) reduces gain matching errors. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, can be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9237 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling, or falling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9237. As shown in Figure 17, noise and distortion performance are nearly flat over a 30% range of duty cycle with the DCS enabled. When the SENSE pin is connected to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 kΩ load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always four times the value of the reference voltage divided by the span factor; therefore, the external reference must be limited to a maximum of 1 V. 0.7 High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to rms aperture jitter (tJ) can be calculated by 0.6 0.5 VREF ERROR (%) The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. 1V REFERENCE 0.4 ⎡ 1 SNR Degradation = 20 log 10 ⎢ ⎢⎣ 2πf INPUT t J 0.3 0.2 0.5V REFERENCE 0 –40 05455-046 0.1 –20 0 20 40 TEMPERATURE (°C) 60 80 85 Figure 41. Typical VREF Drift If the internal reference of the AD9237 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 42 shows how the internal reference voltage is affected by loading. A 2 mA load is the maximum recommended load. 0.05 ⎤ ⎥ ⎥⎦ In this equation, the rms aperture jitter represents the rootsum-square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input should be treated as an analog signal in cases where aperture jitter can affect the dynamic range of the AD9237. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (such as gating, dividing, or other methods), then it should be retimed by the original clock at the last step. The lowest typical conversion rate of the AD9237 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade. 0 POWER DISSIPATION, POWER SCALING, AND STANDBY MODE 0.5V ERROR (%) –0.10 1V ERROR (%) –0.15 –0.20 05455-093 ERROR (%) –0.05 –0.25 0 0.5 1.0 1.5 LOAD (mA) 2.0 2.5 3.0 As shown in Figure 43, the power dissipated by the AD9237 is proportional to its sample rate. The digital power dissipation does not vary substantially between the three speed grades because it is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current can be calculated as I DRVDD = VDRVDD × C LOAD × f CLK × N Figure 42. VREF Accuracy vs. Load where N is 12, the number of output bits. Rev. 0 | Page 19 of 28 AD9237 190 This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the encode rate and the characteristics of the analog input signal. 170 AD9237-65 POWER (mW) 150 190 130 110 170 AD9237-40 POWER (mW) AD9237-20 70 10 130 AD9237-65 20 30 40 50 SAMPLE RATE (MSPS) 60 65 Figure 44. Total Power vs. Sample Rate with Power Scaling Enabled 110 AD9237-40 05455-047 90 AD9237-20 70 10 05455-096 90 150 20 30 40 50 SAMPLE RATE (MSPS) 60 65 The MODE2 pin is a multilevel input that controls the span factor and power scaling modes. The MODE2 pin is internally pulled down to AGND by a 70 kΩ resistor. The input threshold and corresponding mode selections are outlined in Table 8. Table 8. MODE2 Selection Figure 43. Total Power vs. Sample Rate with fIN = 10 MHz For the AD9237-20 speed grade, the digital power consumption can represent as much as 10% of the total dissipation. Digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 43 was taken with a 5 pF load on each output driver. The AD9237 is designed to provide excellent performance with minimum power. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency, as shown in Figure 43. The power scaling feature provides an additional power savings when enabled, as shown in Figure 44. The power scaling mode cannot be enabled if the clock is varied during operation. This is because the internal circuitry cannot quickly track a changing clock, and the part does not have enough power to operate properly. MODE2 Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) Span Factor 1 1 2 2 Power Scaling Disabled Enabled Enabled Disabled The PDWN pin is a multilevel input that controls the power states. The input threshold values and corresponding power states are outlined in Table 9. Table 9. PDWN Selection PDWN Voltage AVDD 1/3 AVDD AGND (Default) Power State Power-Down Mode Standby Mode Normal Operation Power (mW) 1 20 Based on speed grade By asserting the PDWN pin high, the AD9237 is placed in power-down mode. In this state, the ADC typically dissipates 1 mW. During power-down, the output drivers are placed in a high impedance state. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, clock, and duty cycle stabilizer circuitry. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in power-down mode and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation. Rev. 0 | Page 20 of 28 AD9237 DIGITAL OUTPUTS The AD9237 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that can affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9237; these transients can detract from the converter’s dynamic performance. As detailed in Table 10, the data format can be selected for either offset binary, twos complement, or gray code. completed. By logically AND-ing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table 11 is a truth table for the overrange/ underrange circuit in Figure 46, which uses NAND gates. Systems requiring programmable gain condition of the AD9237 can, after eight clock cycles, detect an out-of-range condition; therefore, eliminating gain selection iterations. In addition, OTR can be used for digital offset and gain calculation. OTR DATA OUTPUTS 1 1111 1111 1111 0 1111 1111 1111 0 1111 1111 1110 +FS – 1 LSB +FS –FS + 1/2 LSB 0 0000 0000 0001 0 0000 0000 0000 0 0000 0000 0000 –FS –FS – 1/2 LSB Operational Mode Selection Table 11. Output Data Format OTR 0 0 1 1 The gray code output format is obtained by connecting GC to AVDD. When the part is in gray code mode, the MODE pin controls the DCS function only. The GC pin is internally pulled down to AGND by a 70 kΩ resistor. MSB Table 10. MODE Selection MSB Data Format Twos Complement Twos Complement Offset Binary Offset Binary Duty Cycle Stabilizer Disabled Enabled Enabled Disabled Out of Range (OTR) An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. The OTR pin is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Therefore, the OTR pin has the same pipeline latency as the digital data. OTR is low when the analog input voltage is within the analog input range, and high when the analog input voltage exceeds the input range, as shown in Figure 45. OTR remains high until the analog input returns to within the input range and another conversion is –FS – 1/2 LSB Figure 45. OTR Relation to Input Voltage and Output Data MSB 0 1 0 1 Analog Input Is Within range Within range Underrange Overrange OVER = 1 OTR UNDER = 1 05455-050 The AD9237 can output data in either offset binary, twos complement, or gray code format. There is also a provision for enabling or disabling the duty cycle stabilizer (DCS). The MODE pin is a multilevel input that controls the data format (except for gray code) and DCS state. The MODE pin is internally pulled down to AGND by a 70 kΩ resistor. The input threshold values and corresponding mode selections are outlined in Table 10. MODE Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) OTR 05455-049 By asserting the PDWN pin to AVDD/3, the AD9237 is placed in standby mode. In this state, the ADC typically dissipates 20 mW. The output drivers are placed in a high impedance state. The reference circuitry is enabled, allowing for a quick start upon bringing the ADC into normal operating mode. Figure 46. Overrange/Underrange Logic Digital Output Enable Function (OE) The AD9237 has three-state ability. The OE pin is internally pulled down to AGND by a 70 kΩ resistor. If the OE pin is low, the output data drivers are enabled. If the OE pin is high, the output data drivers are placed in a high impedance state. It is not intended for rapid access to the data bus. Note that the OE pin is referenced to the digital supplies (DRVDD) and should not exceed that voltage. Timing The AD9237 provides latched data outputs with a pipeline delay of eight clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. Rev. 0 | Page 21 of 28 AD9237 An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated in production. Designers interested in evaluating the op amp with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 outputs and the AD9237 allows the user to optimize the frequency response of the op amp for the application. The typical bench setup used to evaluate the ac performance of the AD9237 is shown in Figure 47. The AD9237 can be driven single-ended or differentially through a transformer. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). 3V – 2.5V + 2.5V + – – 5V + AVDD GND DRVDD GND VDL REFIN HP8644, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER J1 ANALOG IN AD9237 EVALUATION BOARD 10MHz REFOUT HP8644, 2V p-p CLOCK SYNTHESIZER CLOCK DIVIDER J2 ENCODE Figure 47. LFCSP Evaluation Board Connections Rev. 0 | Page 22 of 28 – + VAMP P12 DATA CAPTURE AND PROCESSING 05455-051 LFCSP EVALUATION BOARD GND AMP L1 10nH 05455-080 GND 3 PRI 4 SEC XOUTB OPTIONAL XFR T2 ETC1-1-13 1 5 XFRIN XOUT 2 CT ANALOG INPUT J1 C15 0.1μF SINGLE ENDED INPUT GND NC XFRIN C6 0.1μF PLACE R19 (50Ω ON BOTTOM) R42 (0Ω), C6, C18 (0.1μF) AND R18 (25Ω) REMOVE R12, R3, C27, C17 FOR SINGLE ENDED INPUT 4 3 E29 AVDD A B C GND D XOUTB GND C16 0.1μF E45 XOUT R11 36Ω C5 0.1μF R10 36Ω C26 10pF R12 0Ω R2 XX AVDD C7 0.1μF R15 33Ω C22 10μF AVDD GND AVDD GND GND AIN AIN AVDD GND R25 1kΩ 4 3 2 GND C42 0.1μF 32 31 30 29 28 27 26 25 E25 R6 1kΩ E24 R7 1kΩ E23 R5 1kΩ E22 GND C8 0.1μF AVDD AGND VIN– VIN+ AGND AVDD REFT REFB 1 2 5 CLK 4 3 5 6 7 6 8 D3 10 D2 9 D5 12 D4 11 D7 14 D6 13 DRVDD 16 DGND 15 7 8 R8 1kΩ E11 E36 G E17 E15 E13 E16 AVDD F E12 E10 E E14 (LSB) TP1(GRAYCODE) GND DRVDD (MSB) OVER RANGE BIT 1: 2 COMP/DUTY CYCLE OFF 2: 2 COMP/DUTY CYCLE ON 3: OFFET BINARY/DUTY CYCLE ON 4: OFFET BINARY/DUTY CYCLE OFF MODE SELECT 24 23 22 21 20 19 18 17 E19 E20 E21 MODE E18 5: SHA GAIN 1/AUTO POWER CONTROL OFF 6: SHA GAIN 1/AUTO POWER CONTROL ON 7: SHA GAIN 2/AUTO POWER CONTROL ON 8: SHA GAIN 2/AUTO POWER CONTROL OFF MODE 2 R13 1kΩ C23 10pF GND GND C21 10pF R26 1kΩ C11 0.1μF GND + C19 15pF OR L1 FOR FILTER R4 33Ω R36 1kΩ C29 10μF C13 0.1μF GND C9 0.1μF C18 0.1μF R SINGLE ENDED R3 0Ω GND GND GND R18 25Ω AMPINB AMPIN GND R12, R42, C17 ONLY ONE SHOULD BE ON BOARD AT A TIME GND C12 0.1μF R3, R18, C27 ONLY ONE SHOULD BE ON BOARD AT A TIME SEC 2 5 PRI 6 1 T1 ADT1-1WT R42 0Ω GND R9 10kΩ R1 10kΩ GND E30 2 GND E1 E28 E32 E27 E33 E26 E34 3 3.0V DRVDD 1V MAX GND 1 MODE OE VREF MODE2 D11 AVDD MODE2 AVDD D10 DNC 4 GND EXTREF SENSE CLK E5 E6 D8 D1 1 AVDD 3.0V 5 GND R46 1kΩ R47 1kΩ AVDD VDL 2.5V 6 VAMP 5.0V A: EXTERNAL VOLTAGE DIVIDER B: INTERNAL 1V REFERENCE C: EXTERNAL REFERENCE D: INTERNAL 0.5V REFERENCE R45 1kΩ OTR U4 AD9237 PDWN R43 1kΩ D9 D0 R44 1kΩ GC E2 E7 E3 E8 E4 E9 Rev. 0 | Page 23 of 28 GND Figure 48. LFCSP Evaluation Board Schematic, Analog Inputs, and DUT GND + REFERENCE H4 MTHOLE6 H3 MTHOLE6 H2 MTHOLE6 H1 MTHOLE6 12 11 10 5 6 7 E. POWER DOWN F. STANDBY G. POWER UP PWDN 13 4 9 14 3 8 16 15 9 8 2 10 7 1 11 6 13 4 12 14 3 5 16 15 2 P2 1 RP1 220Ω RP2 220Ω GND D0X D1X D2X D3X D4X D5X D6X D7X D8X D9X D10X D11X D12X D13X ORX AD9237 AD9237 U1 74LVTH162374 MSB ORX D13X GND D12X D11X DRVDD D10X D9X GND D8X D7X D6X D5X GND D4X D3X DRVDD D2X D1X LSB GND D0X 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 CLKLAT/DAC 48 2CLK 2OE 2D8 2Q8 2D7 2Q7 GND7 GND3 2D6 2Q6 2D5 2Q5 VCC1 VCC2 2D4 2Q4 2D3 2Q3 GND4 GND2 2D2 2Q2 2D1 2Q1 1D8 1Q8 1D7 1Q7 GND5 GND1 1Q6 1D6 1D5 1Q5 VCC3 VCC 1D4 1Q4 1D3 1Q3 GND6 GND 1D2 1Q2 1D1 1Q1 1CLK 1OE HEADER 40 GND GND ORY 24 23 DR MSB GND 22 2 1 4 3 6 5 8 7 10 9 12 11 14 16 16 13 4 6 8 GND 21 2 10 20 12 19 14 DRVDD 18 17 18 16 20 GND 15 22 14 24 13 26 12 28 11 30 GND 10 32 9 34 8 ORY DRVDD 7 36 38 6 40 5 15 18 17 P12 20 5 7 9 11 13 15 17 19 21 22 21 24 23 26 25 28 30 27 29 29 32 31 34 36 33 35 35 38 37 40 39 23 25 27 31 33 37 39 GND GND 3 2 GND 1 R38 1kΩ R39 1kΩ VAMP POWER DOWN PLACE ALL COMPONENTS SHOWN HERE (RIGHT) USE R40 OR R41 EXCEPT R40 OR R41 VAMP GND REMOVE R12, R3, R18, R42, C6, C18 R41 10kΩ C35 0.1μF R33 100Ω GND + GND C45 0.1μF RGP1 2 AMP R35 25Ω VAMP C24 10μF R40 10kΩ C28 0.1μF AMP IN GND C44 0.1μF PWDN 1 GND 3 GND 4 TO USE AMPLIFIER R19 50Ω 19 1 U3 AD8351 9 VPOS INHI 3 8 OPHI INLO 4 7 OPLO RPG2 5 6 COMM Figure 49. LFCSP Evaluation Board Schematic, Digital Path Rev. 0 | Page 24 of 28 R14 25Ω R16 0Ω C27 0.1μF R17 0Ω C17 0.1μF AMPINB AMPIN GND R34 1.2kΩ GND GND 10 VOCM 05455-081 CLKLAT/DAC + C3 10μF AVDD GND AVDD R27 0Ω R28 0Ω Rev. 0 | Page 25 of 28 J2 GND CLK C43 0.1μF R29 50Ω GND ENCODE ENC ENCX FOR A BUFFERED ENCODE USE R28 FOR A DIRECT ENCODE USE R27 + GND R30 1kΩ R31 1kΩ VDL CLOCK TIMING ADJUSTMENTS DUT BYPASSING C4 10μF + + C10 10μF DRVDD C25 10μF C33 0.1μF Figure 50. LFCSP Evaluation Board Schematic, Clock Input VDL R21 1kΩ GND R24 1kΩ GND E43 E44 VDL R20 1kΩ GND E31 E35 VDL R32 1kΩ GND E52 E53 VDL E50 E51 ENC ANALOG BYPASSING C32 0.001μF C14 0.001μF C41 0.1μF 4A 12 4B 3B 10 13 3A 2B 2A 1B 1A 9 5 4 2 1 C2 10μF 4Y 3Y 2Y 1Y GND C36 0.1μF C39 0.001μF LATCH BYPASSING C38 0.001μF R22 0Ω Rx R37 0Ω DR SCHEMATIC SHOWS 2 GATE DELAY SETUP FOR ONE DELAY, REMOVE BOTH RESISTORS AND ATTACH ONE FROM 2Y TO DR (Rx) C34 0.1μF CLKLAT/DAC VDL R23 0Ω 14 PWR 7 GND 11 8 6 3 C31 0.1μF ENCX C30 0.001μF DIGITAL BYPASSING + U5 74VCX86 GND DRVDD GND VAMP GND VDL C1 0.1μF + + C37 0.1μF C48 0.001μF C46 10μF C20 10μF C47 0.1μF C40 0.001μF C49 0.001μF 05455-082 VDL AD9237 05455-056 05455-059 AD9237 Figure 54. LFCSP Evaluation Board Layout, Power Plane Figure 52. LFCSP Evaluation Board Layout, Secondary Side 05455-060 05455-057 Figure 51. LFCSP Evaluation Board Layout, Primary Side Figure 53. LFCSP Evaluation Board Layout, Ground Plane 05455-061 05455-058 Figure 55. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 56. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev. 0 | Page 26 of 28 AD9237 Table 12. LFCSP Evaluation Board Bill of Materials Item Qty. Omit 1 Reference Designator 1 18 C1, C5, C7, C8, C9, C11, C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 9 C6, C17, C18, C27, C28, C35, C42, C44, C45 2 8 C2, C3, C4, C10, C20, C22, C25, C29 2 C24, C46 3 8 C14, C30, C32, C38, C39, C40, C48, C49 4 1 C19 5 1 C26 2 C21, C23 6 41 E2 to E36, E43, E44, E50 to E53 2 E1, E45 4 H1, H2, H3, H4 7 2 J1, J2 8 1 L1 9 1 P2 Device Chip Capacitors Package 0603 Value 0.1 μF Tantalum Capacitors TAJD 10 μF Chip Capacitors 0603 0.001 μF Chip Capacitor Chip Capacitors 0603 0603 15 pF 10 pF Headers EHOLE SMA Connectors/50 Ω Inductor Terminal Block MTHOLE SMA 0603 TB6 10 1 HEADER40 11 5 Header, Dual 20-Pin RT Angle Chip Resistors 0603 0Ω Chip Resistors Chip Resistors 0603 0603 33 Ω 1 kΩ Chip Resistors Chip Resistors 0603 0603 36 Ω 50 Ω Resistor Pack R_742 220 Ω ADT1-1WT 74LVTH162374 CMOS Register AD9237BCP ADC (DUT) 74VCX86M AD92XXBCP/PCB AD8351 Op Amp M/A-COM Transformer Chip Resistor Chip Resistors Chip Resistors Chip Resistor Chip Resistor AWT1-1T TSSOP-48 P12 12 13 2 19 14 15 2 1 16 2 R3, R12, R23, R28, Rx R16, R17, R22, R27, R37, R42 R4, R15 R5 to R8, R13, R20, R21, R24 to R26, R30 to R32, R36, R43 to R47 R38, R39 R10, R11 R29 R19 RP1, RP2 17 18 1 1 T1 U1 19 20 21 22 23 1 1 1 U4 U5 PCB U3 T2 6 2 1 24 25 26 27 28 Total 118 1 1 1 1 3 4 1 1 40 R2 R14, R18, R35 R1, R9, R40, R41 R34 R33 LFCSP-32 SOIC-14 PCB MSOP-8 ETC1-1-13 0603 0603 0603 These items are included in the PCB design but are omitted at assembly. Rev. 0 | Page 27 of 28 Recommended Vendor/ Part Number Supplied by ADI Jumper Blocks S1031-02-ND 10 nH 1-1 TX SELECT 25 Ω 10 kΩ 1.2 kΩ 100 Ω Coilcraft/0603CS-10NXGBU Wieland/25.602.2653.0, z5-530-0625-0 Digi-Key S2131-20-ND Digi-Key CTS/742C163220JTR Mini-Circuits Analog Devices, Inc. Fairchild Analog Devices, Inc. Analog Devices, Inc. M/A-COM/ETC1-1-13 X X X AD9237 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 32 1 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 25 24 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model AD9237BCPZ-20 1, 2 AD9237BCPZRL7-201, 2 AD9237BCPZ-401, 2 AD9237BCPZRL7-401, 2 AD9237BCPZ-651, 2 AD9237BCPZRL7-651, 2 AD9237BCP-20EB AD9237BCP-40EB AD9237BCP-65EB 1 2 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Evaluation Board Evaluation Board Package Option CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 Z = Pb-free part. It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle soldered to the customer board. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05455–0–10/05(0) T T Rev. 0 | Page 28 of 28