260 MHz, 16 × 5 Buffered Video Crosspoint Switches AD8106/AD8107 FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 A0 A1 CLK A2 25-BIT REGISTER (RANK 1) UPDATE CE 25 PARALLEL LATCH (RANK 2) RESET 25 DECODE 5 × 5:16 DECODERS AD8106/AD8107 80 SWITCH MATRIX OUTPUT BUFFER G = 1, G=2 5 OUTPUTS 05774-001 16 INPUTS SET INDIVIDUAL OR RESET ALL OUTPUTS TO OFF 5 ENABLE/DISABLE 16 × 5 high speed, nonblocking switch arrays AD8106: G = 1, AD8107: G = 2 Pin compatible with AD8110/AD8111, 16 × 8 switch arrays For a 16 × 16 array, see AD8114/AD8115 For a 16 x 8 array, see AD8110/AD8111 Complete solution Buffered inputs Five output amplifiers Drives 150 Ω loads Excellent video performance 60 MHz 0.1 dB gain flatness 0.02% differential gain error (RL = 150 Ω) 0.028 differential phase error (RL = 150 Ω) Excellent ac performance −3 dB bandwidth > 260 MHz 500 V/μs slew rate Low power of 50 mA Low all-hostile crosstalk of −78 dB @ 5 MHz Output disable allows connection of multiple device outputs Reset pin allows disabling of all outputs Excellent ESD rating: Exceeds 4000 V human body model 80-lead LQFP (12 mm × 12 mm) Figure 1. Routing of high speed signals including: Composite video (NTSC, PAL, S, SECAM) Component video (YUV, RGB) Compressed video (MPEG, Wavelet) 3-level digital video (HDB3) GENERAL DESCRIPTION The AD8106 and AD8107 are high speed, 16 × 5 video crosspoint switch matrices. They offer a −3 dB signal bandwidth greater than 260 MHz, and channel switch times of less than 25 ns with 1% settling. With −78 dB of crosstalk and −97 dB isolation (@ 5 MHz), the AD8106/AD8107 are useful in many high speed applications. The differential gain and differential phase of greater than 0.02% and 0.02° respectively, along with 0.1 dB flatness out to 60 MHz, make the AD8106/AD8107 ideal for video signal switching. The AD8106 and AD8107 include five independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs, preventing off channels from loading the output bus. The AD8106 has a gain of 1, while the AD8107 offers a gain of 2. Both operate on voltage supplies of ±5 V while consuming only 30 mA of idle current. The channel switching is performed via a parallel control, allowing updating of an individual output without reprogramming the entire array. The AD8106/AD8107 are offered in an 80-lead LQFP and are available over the extended industrial temperature range of −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD8106/AD8107 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications....................................................................................... 1 Power-On Reset.......................................................................... 16 Functional Block Diagram .............................................................. 1 Initialization................................................................................ 16 General Description ......................................................................... 1 Gain Selection............................................................................. 16 Revision History ............................................................................... 2 Creating Larger Crosspoint Arrays.......................................... 16 Specifications..................................................................................... 3 Crosstalk ...................................................................................... 18 Timing Characteristics ................................................................ 5 PCB Layout ................................................................................. 19 Absolute Maximum Ratings............................................................ 6 Evaluation Board ............................................................................ 21 Maximum Power Dissipation ..................................................... 6 Controlling the Evaluation Board from a PC......................... 25 ESD Caution.................................................................................. 6 Data-Line Overshoot on Printer Ports .................................... 25 Pin Configuration and Function Descriptions............................. 8 Outline Dimensions ....................................................................... 27 I/O Schematics .................................................................................. 9 Ordering Guide .......................................................................... 27 Typical Performance Characteristics ........................................... 10 REVISION HISTORY 3/06—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD8106/AD8107 SPECIFICATIONS VS = ±5 V, TA = 25°C, RL = 1 kΩ, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Propagation Delay Slew Rate Settling Time Gain Flatness NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile Off Isolation, Input/Output Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Impedance Output Disable Capacitance Output Leakage Current Output Voltage Range Output Current Short-Circuit Current INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) Conditions Min Typ 200 mV p-p, RL = 150 Ω 2 V p-p, RL = 150 Ω 2 V p-p, RL = 150 Ω 2 V step, RL = 150 Ω 0.1%, 2 V step, RL = 150 Ω 0.05 dB, 200 mV p-p, RL = 150 Ω 0.05 dB, 2 V p-p, RL = 150 Ω 0.1 dB, 200 mV p-p, RL = 150 Ω 0.1 dB, 2 V p-p, RL = 150 Ω 300/190 Unit Reference 390/260 150 5 500 40 60/40 65/40 80/57 70/57 MHz MHz ns V/μs ns MHz MHz MHz MHz Figure 10, Figure 16 Figure 10, Figure 16 NTSC or PAL, RL = 1 kΩ NTSC or PAL, RL = 150 Ω NTSC or PAL, RL = 1 kΩ NTSC or PAL, RL = 150 Ω f = 5 MHz f = 10 MHz f = 10 MHz, RL = 150 Ω, one channel 0.01 MHz to 50 MHz 0.01 0.02 0.01 0.02 78/85 70/80 93/99 15 % % Degrees Degrees dB dB dB nV/√Hz RL = 1 kΩ RL = 150 Ω No load, channel-to-channel RL = 1 kΩ, channel-to-channel 0.04/0.1 0.15/0.25 DC, enabled Disabled Disabled Disabled, AD8106 only No load Max 0.07/0.5 Worst case (all configurations) Temperature coefficient 0.5/8 0.2 10/0.001 2 1/NA ±3 40 65 Ω MΩ pF μA V mA mA Figure 27, Figure 33 Figure 24, Figure 30 mV μV/°C V pF MΩ μA Figure 38, Figure 44 Figure 39, Figure 45 Per output selected 5 12 ±3/±1.5 2.5 10 2 50% UPDATE to 1% settling Measured at output 60 25 20/30 ±2.5/±1.25 Any switch configuration 1 Rev. 0 | Page 3 of 28 Figure 11, Figure 17 Figure 11, Figure 17 Figure 26, Figure 32 Figure 23, Figure 29 % % % % ppm/°C 0.02/1.0 0.09/1.0 ±2.5 20 Figure 15, Figure 21 Figure 10, Figure 16 Figure 10, Figure 16 Figure 10, Figure 16 Figure 10, Figure 16 20 5 ns ns mV p-p Figure 25, Figure 31 AD8106/AD8107 Parameter POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE Temperature Range θJA Conditions Min AVCC, outputs enabled, no load AVCC, outputs disabled AVEE, outputs enabled, no load AVEE, outputs disabled DVCC Typ Max Unit f = 100 kHz f = 1 MHz 30 15 30 15 11 ±4.5 to ±5.5 75/78 −55/−58 mA mA mA mA mA V dB dB Operating (still air) Operating (still air) −40 to +85 48 °C °C/W Rev. 0 | Page 4 of 28 Reference Figure 22, Figure 28 AD8106/AD8107 TIMING CHARACTERISTICS Table 2. Parameter t1 t2 t3 t4 t5 t6 – – – Limit at TMIN, TMAX 20 100 20 100 0 50 8 100 200 Unit ns min ns min ns min ns min ns min ns min ns max ns max ns min t2 Description Data setup time CLK pulse width Data hold time CLK pulse separation CLK to UPDATE delay UPDATE pulse width Propagation delay, UPDATE to switch on or off CLK, UPDATE rise and fall times RESET time t4 1 CLK 0 t1 D0 TO D4 A0 TO A2 t3 1 0 t5 05774-002 1 = LATCHED t6 UPDATE 0 = TRANSPARENT Figure 2. Timing Diagram Table 3. Logic Levels VIH RESET, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE VIL RESET, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE IIH RESET, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE IIL RESET, CLK, D0, D1, D2, D3, D4, A0, A1, A2, CE, UPDATE 2.0 V min 0.8 V max 20 μA max −400 μA min Rev. 0 | Page 5 of 28 AD8106/AD8107 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Internal Power Dissipation AD8106/AD8107 80-Lead LQFP (ST-80-1) Input Voltage Output Short-Circuit Duration θJA Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 10 sec) MAXIMUM POWER DISSIPATION Rating 12.0 V 2.6 W ±VS Observe power derating curves 48°C/W −40°C to 85°C −65°C to +125°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The maximum power that can be safely dissipated by the AD8106/AD8107 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8106/AD8107 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 3. 5 4 3 2 1 0 –50 –40 –30 –20 –10 05774-003 MAXIMUM POWER DISSIPATION (W) TJ = 150°C 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (°C) Figure 3. Maximum Power Dissipation vs. Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 28 AD8106/AD8107 Table 5. Operation Truth Table CE UPDATE CLK DATA IN DATA OUT RESET Operation/Comment 1 0 X 1 X f 0 X X NA in parallel mode X X 1 0 X D0 … D4 A0 … A2 X X X X X X 0 No change in logic. The data on the parallel data lines, D0 to D4, are loaded into the 40-bit serial shift register location addressed by A0 to A2. Data in the 40-bit shift register transfers into the parallel latches that control the switch array. Latches are transparent. Asynchronous operation. All outputs are disabled. Remainder of logic is unchanged. PARALLEL DATA (OUTPUT ENABLE) 1 D0 D1 D2 D3 D4 D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CE UPDATE A0 A1 A2 3 TO 5 DECODER OUT0 EN OUT1 EN OUT2 EN OUT3 EN OUT4 EN LE D OUT0 B0 Q LE D OUT0 B1 Q LE D OUT0 B2 Q LE D OUT0 B3 Q LE D OUT0 EN CLR Q LE D OUT1 B0 Q LE D OUT3 EN CLR Q LE D OUT4 B0 Q LE D OUT4 B1 Q LE D OUT4 B2 Q LE D OUT4 B3 Q LE D OUT4 EN CLR Q RESET (OUTPUT DISABLE) SWITCH MATRIX Figure 4. Logic Diagram Rev. 0 | Page 7 of 28 5 OUTPUT ENABLE 05774-004 DECODE 80 AD8106/AD8107 61 RESET 62 DGND 63 DVCC 64 IN00 66 IN01 65 AGND 67 AGND 68 IN02 69 AGND 70 IN03 71 AGND 73 AGND 72 IN04 74 IN05 75 AGND 77 AGND 76 IN06 78 IN07 80 DGND 79 DVCC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN08 1 60 CE AGND 2 59 RESERVED PIN 1 INDICATOR IN09 3 AGND 4 57 RESERVED IN10 5 AGND 6 56 UPDATE 55 RESERVED 7 8 IN12 9 54 A0 AD8106/AD8107 AGND 10 IN13 11 AGND 12 IN14 13 16 × 5 80L LQFP (12mm × 12mm) 53 A1 TOP VIEW (PINS DOWN) 0.5mm LEAD PITCH 50 D1 52 A2 51 D0 49 D2 48 D3 47 D4 AGND 14 IN15 15 46 AGND AGND 16 45 AVEE AVEE 17 44 AVCC AVCC 18 43 AVCC00 AVCC 19 42 AGND00 NC 20 AVEE00/01 40 AGND01 39 OUT01 38 AVCC01/02 37 AGND02 36 OUT02 35 AVEE02/03 34 AGND03 33 OUT03 32 AGND04 30 AVCC03/04 31 OUT04 29 AVEE04 28 NC 26 AGND 27 AVCC 25 NC 23 AGND 24 AGND 21 AVEE 22 41 OUT00 05774-010 IN11 AGND 58 CLK Figure 5. 80-Lead Plastic LQFP Table 6. Pin Function Descriptions Pin No. 64 , 66, 68, 70, 72, 74, 76, 78, 1, 3, 5, 7, 9, 11, 13, 15, 58 56 61 60 41, 38, 35, 32, 29 2, 4, 6, 8, 10, 12, 14, 16, 21, 24, 27, 46, 65, 67, 69, 71, 73, 75, 77 63, 79 62, 80 17, 22, 45 18, 19, 25, 44 42, 39, 36, 33, 30 43, 37, 31, 22 40, 34, 28 54 53 52 51 50 49 48 47 Mnemonic INxx Description Analog Inputs; xx = Channel Numbers 00 through 15. CLK UPDATE RESET CE OUTyy AGND Clock, TTL Compatible. Falling edge triggered. Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data latched when high. Disable Outputs, Active Low. Chip Enable, Enable Low. Must be low to clock in and latch data. Analog Outputs; yy = Channel Numbers 00 Through 04. Analog Ground for Inputs and Switch Matrix. DVCC DGND AVEE AVCC AGNDxx AVCCxx/yy AVEExx/yy A0 A1 A2 D0 D1 D2 D3 D4 5 V for Digital Circuitry. Ground for Digital Circuitry. −5 V for Inputs and Switch Matrix. +5 V for Inputs and Switch Matrix. Ground for Output Amp; xx = Output Channel Numbers 00 Through 07. Must be connected. +5 V for Output Amplifier. Shared by channel numbers xx and yy. Must be connected. −5 V for Output Amplifier. Shared by channel numbers xx and yy. Must be connected. Parallel Data Input, TTL Compatible (Output Select LSB). Parallel Data Input, TTL Compatible (Output Select). Parallel Data Input, TTL Compatible (Output Select MSB). Parallel Data Input, TTL Compatible (Input Select LSB). Parallel Data Input, TTL Compatible (Input Select). Parallel Data Input, TTL Compatible (Input Select). Parallel Data Input, TTL Compatible (Input Select MSB). Parallel Data Input, TTL Compatible (Output Enable). Rev. 0 | Page 8 of 28 AD8106/AD8107 I/O SCHEMATICS VCC VCC 20kΩ ESD ESD RESET INPUT 05774-005 AVEE 05774-007 ESD ESD DGND Figure 8. RESET Input Figure 6. Analog Input VCC VCC ESD ESD INPUT OUTPUT DGND Figure 9. Logic Input Figure 7. Analog Output Rev. 0 | Page 9 of 28 05774-008 AVEE ESD 05774-006 ESD 1kΩ (AD8107 ONLY) AD8106/AD8107 TYPICAL PERFORMANCE CHARACTERISTICS 5 RL = 150Ω 0.2 50 2 0.1 25 FLATNESS 200mV p-p 1 0 –0.1 0 GAIN 25mV/DIV 3 FLATNESS (dB) 0.3 –25 –50 –0.2 –1 2V p-p 1M 10M FREQUENCY (Hz) 100M 05774-014 –0.3 –2 –3 100k 0 05774-011 GAIN (dB) RL = 150Ω 4 1G 25ns/DIV Figure 10. AD8106 Frequency Response Figure 13. AD8106 Step Response, 100 mV Step –30 RL = 150Ω RL = 1kΩ –40 1.0 0.5 0.5V/DIV CROSSTALK (dB) –50 –60 ALL HOSTILE –70 –0.5 ADJACENT –80 05774-012 05774-015 –1.0 –90 –100 0 0.3 1 10 FREQUENCY (Hz) 100 200 25ns/DIV Figure 11. AD8106 Crosstalk vs. Frequency Figure 14. AD8106 Step Response, 2 V Step –40 RL = 150Ω VOUT = 2V p-p 2V = STEP RL = 150Ω 0.1%/DIV –60 2ND HARMONIC –70 –80 3RD HARMONIC –100 100k 05774-016 –90 05774-013 DISTORTION (dB) –50 1M 10M FREQUENCY (Hz) 100M Figure 12. AD8106 Distortion vs. Frequency 0 10 20 30 40 50 60 10ns/DIV Figure 15. AD8106 Settling Time Rev. 0 | Page 10 of 28 70 80 AD8106/AD8107 4 0.6 3 0.4 1.0 0.2 0.5 FLATNESS 200mV p-p 0 1 0 –0.2 GAIN –0.4 2V p-p –2 –3 100k 1M –0.6 10M FREQUENCY (Hz) –0.8 1G 100M –0.5 –1.0 05774-020 –1 0 05774-017 GAIN (dB) 2 25mV/DIV 0.8 FLATNESS (dB) 5 25ns/DIV Figure 16. AD8107 Frequency Response Figure 19. AD8107 Step Response, 100 mV Step –20 RL = 1kΩ –30 1.0 –50 ADJACENT 500mV/DIV CROSSTALK (dB) –40 –60 –70 –80 0.5 0 –0.5 ALL HOSTILE –1.0 05774-018 –100 05774-021 –90 –110 0.3 1 10 FREQUENCY (MHz) 100 200 25ns/DIV Figure 20. AD8107 Step Response, 2 V Step Figure 17. AD8107 Crosstalk vs. Frequency –30 –40 2V STEP RTO RL = 150Ω RL = 150Ω VOUT = 2V p-p 0.1%/DIV –60 2ND HARMONIC –70 3RD HARMONIC –90 –100 05774-022 –80 05774-019 DISTORTION (dB) –50 100k 1M 10M 100M 0 10 20 30 40 50 60 10ns/DIV FREQUENCY (Hz) Figure 21. AD8107 Settling Time Figure 18. AD8107 Distortion vs. Frequency Rev. 0 | Page 11 of 28 70 80 AD8106/AD8107 RL = 150Ω SWITCHING BETWEEN TWO INPUTS 5 –40 1V/DIV 4 –50 3 UPDATE INPUT 2 1 –60 –90 10k 100k 1M 10 0 TYPICAL VIDEO OUT (RTO) –10 10M 50ns/DIV FREQUENCY (Hz) Figure 22. AD8106 PSRR vs. Frequency Figure 25. AD8106 Switching Transient (Glitch) 100.00 –50 56.30 VIN = 2V p-p RL = 150Ω OFF ISOLATION (dB) –60 31.60 (nV/ Hz) 05774-026 –80 10mV/DIV 0 –70 05774-023 POWER SUPPLY REJECTION RATIO (dB) –30 17.80 10.00 –70 –80 –90 –100 –110 –120 –130 05774-024 3.16 10 100 1k 10k 100k 1M 05774-027 5.630 100k 10M 1M FREQUENCY (Hz) Figure 23. AD8106 Voltage Noise vs. Frequency 100M 500M Figure 26. AD8106 Off Isolation, Input/Output 10k 1M 1k OUTPUT IMPEDANCE (Ω) 100k 10k 1k 100 10 100 0.1 1 10 FREQUENCY (MHz) 100 500 0.1 100k 05774-028 1 05774-025 OUTPUT IMPEDANCE (Ω) 10M FREQUENCY (Hz) 1M 10M 100M FREQUENCY (Hz) Figure 24. AD8106 Output Impedance, Disabled Figure 27. AD8106 Output Impedance, Enabled Rev. 0 | Page 12 of 28 500M AD8106/AD8107 RL = 150Ω SWITCHING BETWEEN TWO INPUTS 5 4 1V/DIV –40 –50 3 UPDATE INPUT 2 1 0 –80 10k 100k 1M 10 0 TYPICAL VIDEO OUT (RTO) 05774-032 –70 10mV/DIV –60 05774-029 POWER SUPPLY REJECTION RATIO (dB RTI) –30 –10 10M 50ns/DIV FREQUENCY (Hz) Figure 28. AD8107 PSRR vs. Frequency Figure 31. AD8107 Switching Transient (Glitch) 100.00 –40 –50 V` OUT = 2V p-p RL = 150Ω 56.30 OFF ISOLATION (dB) –60 (nV/ Hz) 31.60 17.80 10.00 –70 –80 –90 –100 –110 –120 05774-030 3.16 10 100 1k 10k 100k 1M 05774-033 5.63 –130 100k 10M 1M 10k 100 1k 100 10 500M 100 500 10 1 0.1 100k 05774-034 OUTPUT IMPEDANCE (Ω) 1k 05774-031 OUTPUT IMPEDANCE (Ω) 100k 1 100M Figure 32. AD8107 Off Isolation, Input/Output Figure 29. AD8107 Voltage Noise vs. Frequency 10 0.1 10M FREQUENCY (Hz) FREQUENCY (Hz) 1M 10M 100M FREQUENCY (Hz) FREQUENCY (MHz) Figure 33. AD8107 Output Impedance, Enabled Figure 30. AD8107 Output Impedance, Disabled Rev. 0 | Page 13 of 28 500M AD8106/AD8107 10M INPUT 1 AT +1V 1 1V/DIV 100k VOUT 0 –1 INPUT 0 AT –1V 5 10k 100 05774-035 1k 30k 100k 1M 10M 100M UPDATE 0 05774-038 2V/DIV INPUT IMPEDANCE (Ω) 1M 500M 50ns/DIV FREQUENCY (Hz) Figure 37. AD8106 Switching Time Figure 34. AD8106 Input Impedance vs. Frequency 14 260 240 VIN = 200mV p-p RL = 150Ω 12 220 10 200 180 18pF = 7.7dB FREQUENCY 6 4 12pF = 4.5dB 2 160 140 120 100 80 60 0 –4 0.1M 40 05774-036 –2 1M 10M 100M FREQUENCY (Hz) 1G 20 0 –0.02 3G Figure 35. AD8106 Frequency Response vs. Capacitive Load –0.01 0 OFFSET VOLTAGE (V) 0.02 0.01 Figure 38. AD8106 Offset Voltage Distribution 2.0 0.7 VIN = 200mV p-p RL = 150Ω 0.6 1.5 0.5 1.0 0.4 VOS (mV) 0.5 0.3 CL = 18pF 0.2 0 –0.5 0.1 –1.0 0 CL = 12pF –0.2 0.1M –1.5 1M 10M 100M FREQUENCY (Hz) 1G Figure 36. AD8106 Flatness vs. Capacitance Load –2.0 3G 05774-040 –0.1 05774-037 FLATNESS (dB) 05774-039 GAIN (dB) 8 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 39. AD8106 Offset Voltage vs. Temperature (Normalized at 25°C) Rev. 0 | Page 14 of 28 AD8106/AD8107 10M INPUT 1 AT +1V 1 1V/DIV 100k VOUT 0 –1 INPUT 0 AT –1V 5 10k 100 05774-041 1k 30k 1M 100k 10M 100M UPDATE 0 05774-044 2V/DIV INPUT IMPEDANCE (Ω) 1M 500M 50nS/DIV FREQUENCY (Hz) Figure 40. AD8107 Input Impedance vs. Frequency Figure 43. AD8107 Switching Time 12 480 440 10 400 8 320 FREQUENCY GAIN (dB) 360 18pF 6 4 2 12pF 0 280 240 200 160 120 –2 05774-042 –6 0.1M 1M 10M 100M 1G 05774-045 80 –4 40 0 –0.02 3G –0.01 FREQUENCY (Hz) 0 OFFSET VOLTAGE (V) 0.01 0.02 Figure 44. AD8107 Offset Voltage Distribution (RTI) Figure 41. AD8107 Frequency Response vs. Capacitive Load 0.7 2.0 VIN = 100mV RL = 150Ω 0.6 1.5 0.5 1.0 0.5 VOS (mV) 18pF 0.3 0.2 0.1 0 –0.5 12pF 0 –1.0 –0.1 1M 10M 100M FREQUENCY (Hz) Figure 42. AD8107 Flatness vs. Capacitive Load 1G –2.0 3G 05774-046 –0.2 –0.3 0.1M –1.5 05774-043 GAIN (dB) 0.4 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 45. AD8107 Offset Voltage Drift vs. Temperature (Normalized at 25°C) Rev. 0 | Page 15 of 28 AD8106/AD8107 THEORY OF OPERATION The AD8106 (G = 1) and AD8107 (G = 2) share a common core architecture consisting of an array of 80 transconductance (gm) input stages that are organized as five 16:1 multiplexers with a common, 16-line analog input bus. Each multiplexer is essentially a folded-cascode high speed voltage, feedback amplifier with 16 input stages. The input stages are NPN differential pairs whose differential current outputs are combined at the output stage, which contains the high impedance node, compensation, and a complementary emitter follower output buffer. In the AD8106, the output of each multiplexer is fed directly back to the inverting inputs of its 16 gm stages. In the AD8107, the feedback network is a voltage divider consisting of two equal-value resistors. This switched-gm architecture results in a low power crosspoint switch that is able to directly drive a back-terminated video load (150 Ω) with low distortion (differential gain and differential phase errors are better than 0.02% and 0.02°, respectively). This design also achieves high input resistance and low input capacitance without the signal degradation and power dissipation of additional input buffers. However, the small input bias current at any input increases almost linearly with the number of outputs programmed to that input. INITIALIZATION The AD8106/AD8107 should be initialized after power up to control the supply and bias currents, and to make sure that no unexpected program states are encountered. Initialization is performed by writing a data word of 00000 into all address locations 00 to 07 (000 to 111 binary). GAIN SELECTION The 16 × 5 crosspoints come in two versions depending on the desired gain of the analog circuit paths. The AD8106 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. The AD8106 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used. The AD8106 outputs have very high impedance when their outputs are disabled. For devices that drive a terminated cable with its outputs, the AD8107 can be used. This device has a built-in gain of two that eliminates the need for a gain-of-two buffer to drive a video line. Because of the presence of the feedback network in these devices, the disabled output impedance is about 1 kΩ. CREATING LARGER CROSSPOINT ARRAYS The output disable feature of these crosspoints allows larger switch matrices to be built simply by busing together the outputs of multiple 16 × 5 ICs. However, while the disabled output impedance of the AD8106 is very high (10 MΩ), the AD8107 output impedance is limited by the resistive feedback network, which has a nominal total resistance of 1 kΩ and appears in parallel with the disabled output. If the outputs of multiple AD8107s are connected through separate back termination resistors, the loading lowers the effective back termination impedance of the overall matrix because of these finite output impedances. This problem is eliminated if the outputs of multiple AD8107s are connected directly and share a single back-termination resistor for each output of the overall matrix. This configuration increases the capacitive loading of the disabled AD8107 on the output of the enabled AD8107. POWER-ON RESET When powering up the AD8106/AD8107, it is usually necessary to have the outputs be in the disabled state. The RESET pin, when taken low, causes all outputs to be in the disabled state. The RESET pin has a 20 kΩ pull-up resistor to DVDD that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground holds RESET low for some time while the rest of the device stabilizes. The low condition causes all the outputs to disable. The capacitor then charges through the pullup resistor to the high state, allowing full programming capability of the device. The AD8106/AD8107 are high density building blocks that create crosspoint arrays for dimensions larger than 16 × 5. Various features such as output disable, chip enable, and gainof-one and gain-of-two options are useful for creating larger arrays. For very large arrays, they can be used with the AD8114/AD8115, 16 × 16 video crosspoint devices, or the AD8110/AD8111, 16 x 8 video crosspoint devices. When required for customizing a crosspoint array size, the parts can also be used with the AD8108 and AD8109, a pair (unity gain and gain-of-two) of 8 × 8 video crosspoint switches. The first consideration in constructing a larger crosspoint is to determine the minimum number of required devices. The 16 × 5 architecture of the AD8106/AD8107 contains 80 points. For a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. Nonblocking requires that the programming of a given input to one or more outputs does not restrict the availability of that input to be a source for any other output. Some nonblocking crosspoint architectures require more than this minimum as calculated above. In addition, there are blocking architectures that can be constructed with fewer devices than this minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system. The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to wire-OR the outputs together in a vertical direction. Rev. 0 | Page 16 of 28 AD8106/AD8107 Figure 46 illustrates this concept for a 32 × 5 crosspoint array. AD8106 16 16 OR AD8107 RTERM 5 IN 16–31 AD8106 16 16 OR Using additional crosspoint devices in the design can lower the number of outputs that must be wire-OR’ed together. Figure 47 shows a block diagram of a system using eight AD8106s and two AD8107s to create a nonblocking, gain-of-two, 128 × 5 crosspoint that restricts the wire-OR’ing at the output to only four outputs. AD8107 05774-047 RTERM 5 Figure 46. A 32 × 5 Crosspoint Array Using Two AD8106s or Two AD8107s The inputs are uniquely assigned to each of the 32 inputs of the two devices and terminated appropriately. The outputs are wireOR’ed together in pairs. The output from only one of a wire-OR’ed pair should be enabled at any given time. The device programming software must be properly written to cause this to happen. Additionally, by using the lower four outputs from each of the two Rank 2 AD8107s, a blocking 128 × 10 crosspoint array can be realized. There are, however, some drawbacks to this technique. The offset voltages of the various cascaded devices accumulate and the bandwidth limitations of the devices compound. The extra devices also consume more current and take up more board space. Once again, the overall system design specifications determine which tradeoffs should be made. At some point, the number of outputs that are wire-OR’ed becomes too great to maintain system performance. This varies according to which system specifications are most important. It also depends on whether the matrix consists of AD8106s or AD8107s. RANK 1 (8 × AD8106) 128:16 IN 00–15 16 5 AD8106 5 AD8106 5 RTERM IN 16–31 5 16 RTERM IN 32–47 RANK 2 16:8 NONBLOCKING (16:16 BLOCKING) 5 AD8106 16 5 RTERM IN 48–63 5 5 AD8106 16 5 1kΩ 5 AD8107 5 5 1kΩ OUT 00–04 NONBLOCKING RTERM IN 64–79 AD8107 5 RTERM IN 80–95 5 5 AD8106 16 5 1kΩ 5 ADDITIONAL 5 OUTPUTS (SUBJECT TO BLOCKING) 5 1kΩ 5 16 AD8106 5 AD8106 5 AD8106 5 RTERM IN 96–111 5 16 RTERM IN 112–127 05774-048 IN 00–15 The output disabled impedance of the AD8106 is much higher than that of the AD8107. As a result, its disabled parasitics have a smaller effect on the one output that is enabled. For example, a 128 × 5 crosspoint can be created with eight AD8106s/AD8107s. This design has 128 separate inputs and the corresponding outputs of each device wireOR’ed together in groups of eight. 5 16 RTERM Figure 47. A Gain-of-Two 128 × 5 Nonblocking Crosspoint Array (128 × 10 Blocking) Rev. 0 | Page 17 of 28 AD8106/AD8107 CROSSTALK Many systems, such as broadcast video, handle numerous analog signal channels that have strict requirements for keeping the various signals from influencing others in the system. Crosstalk is the term used to describe the undesired coupling between signals of other nearby channels to a given channel. In addition, crosstalk can occur among the inputs to a crosspoint as well as among the outputs. It can also occur from input to output. Refer to the Input and Output Crosstalk section for techniques to diagnose which part of a system is contributing to crosstalk. Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by When many signals are in close proximity in a system, as is undoubtedly the case in a system that uses the AD8106/ AD8107, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and its associated terms is required to specify a system that uses one or more AD8106s/AD8107s. XT = 20 log 10 (Asel ( s ) / Atest ( s )) Types of Crosstalk (1) where: Crosstalk can be propagated by means of one of three methods. These fall into the categories of electric field, magnetic field, and sharing of common impedances. This section explains these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (free space, for example), couples with the receiver, and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Currents flowing into conductors create magnetic fields that circulate around the currents. These magnetic fields then generate voltages in any other conductors whose paths they link. The undesired induced voltages in these channels are crosstalk signals. The channels that crosstalk have a mutual inductance that couples signals from one channel to another. The power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows into one of these paths, a voltage develops across the impedance and becomes an input crosstalk signal for other channels that share the common impedance. All these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions when driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. Areas of Crosstalk A practical AD8106/AD8107 circuit is required to be mounted to some sort of circuit board to connect to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that a system’s crosstalk is a combination of the device’s intrinsic crosstalk and the circuit board to which they are mounted. It is important to try to separate these two areas of crosstalk when attempting to minimize its effect. s = jw is the Laplace transform variable. Asel(s) is the amplitude of the crosstalk-induced signal in the selected channel. Atest(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the test signal’s magnitude (to first order). The crosstalk signal also has a phase relative to its associated test signal. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 16 x 5 matrix of the AD8106/AD8107, examine the number of crosstalk terms that can be considered for a single channel, such as the IN00 input. IN00 is programmed to connect to one of the AD8106/AD8107 outputs where the measurement can be made. First, measure the crosstalk terms associated with driving a test signal into each of the other 15 inputs one at a time. Then measure the crosstalk terms associated with driving a parallel test signal into all 15 other inputs taken two at a time in all possible combinations; and then three at a time, and so on, until finally, there is only one way to drive a test signal into all 15 other inputs. Each of these cases is legitimately different from the others and could yield a unique value depending on the resolution of the measurement system. However, it is impractical to measure all of these terms and then to specify them. In addition, this describes the crosstalk matrix for only one input channel. A similar crosstalk matrix can be proposed for every other input. If the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers grow rather quickly to astronomical proportions. If a larger crosspoint array of multiple AD8106/AD8107s is constructed, the numbers grow larger still. Rev. 0 | Page 18 of 28 AD8106/AD8107 Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all hostile crosstalk, which means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. In general, this yields the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one of the nearest neighbors or by two of the nearest neighbors on either side. These crosstalk measurements are generally higher than those of more distant channels, so they can serve as a worst-case measure for any other one-channel or two-channel crosstalk measurements. Input and Output Crosstalk The flexible programming capability of the AD8106/AD8107 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. For example, a given input channel, such as IN07 in the middle, can be programmed to drive OUT01. The input to IN07 is terminated to ground (via 50 Ω or 75 Ω) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier) with all other outputs disabled, except OUT01. Because grounded IN07 is programmed to drive OUT01, no signal should be present. If any signal is present, it can be attributed to the other 15 hostile input signals because no other outputs are driven; that is, they are all disabled. Thus, this method measures the all-hostile input contribution to crosstalk into IN07. This method can also be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel (IN00, for example) is driven and all outputs other than a given output are programmed to connect to IN00. OUT01 is programmed to connect to IN15, which is far away from IN00, and is terminated to ground. As a result, OUT01 should not have a signal present because it is listening for a quiet input. Any signal measured at the OUT01 can be attributed to the output crosstalk of the other seven hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies, the magnitude of the crosstalk is given by XT = 20 log 10 [(RS C M )× s ] (2) where: RS is the source resistance. CM is the mutual capacitance between the test signal circuit and the selected circuit. s is the Laplace transform variable. Equation 2 shows that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8106/AD8107 are specified with excellent differential gain and phase when driving a standard 150 Ω video load, the crosstalk is higher than the minimum obtainable because of the high output currents. These currents induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8106/AD8107. From a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drive a load resistor. For low frequencies, the magnitude of the crosstalk is given by XT = 20 log 10 (Mxy × s / R L ) (3) where: Mxy is the mutual inductance of output x to output y. RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. PCB LAYOUT Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8106/AD8107 is designed to help keep the crosstalk to a minimum. Each input is separated from other inputs by an analog ground pin. All of these AGNDs should be connected directly to the ground plane of the circuit board. These ground pins provide shielding, low impedance return paths, and physical separation for the inputs. All of these help to reduce crosstalk. Rev. 0 | Page 19 of 28 AD8106/AD8107 Each output is separated from its two neighboring outputs by an analog ground pin and an analog supply pin of one polarity or the other. Each of these analog supply pins provides power to the output stages for only the two nearest outputs. These supply pins and analog grounds provide shielding, physical separation, and a low impedance supply for the outputs. Individual bypassing of these supply pins with a 0.01 μF chip capacitor directly to the ground plane minimizes high frequency output crosstalk via the mechanism of sharing common impedances. Each output also has an on-chip compensation capacitor that is individually tied to the nearby analog ground pins AGND00 through AGND03. This technique reduces crosstalk by preventing the currents that flow in these paths from sharing a common impedance on the IC and in the package pins. These AGNDxx signals should all be connected directly to the ground plane. The input and output signals have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer. The only place the input and output signals surface is at the input termination resistors and the output series back termination resistors. These signals should also be separated, to the largest extent possible, as soon as they emerge from the IC package. Rev. 0 | Page 20 of 28 AD8106/AD8107 EVALUATION BOARD • Component Layer (see Figure 51) • Signal Routing Layer (see Figure 52) • Power Layer (see Figure 53) • Bottom Layer (see Figure 54) w = 0.008" (0.2mm) COMPONENT LAYER b = 0.024" (0.6mm) a = 0.008" (0.2mm) t = 0.00135" (0.0343mm) SIGNAL ROUTING LAYER h = 0.011325" (0.288mm) POWER PLANE LAYER BOTTOM LAYER 05774-049 A 4-layer evaluation board is available for the AD8106/ AD8107. The same board and external components are used for each device. The only difference is the device itself, which offers a selection of a gain of unity or a gain of two through the analog channels. This board has been carefully laid out and tested to demonstrate the specified high speed performance of the device. Figure 49 shows the schematic of the evaluation board. Figure 50 shows the component side silkscreen. The layout of the board’s four layers are given in: Figure 48. Cross Section of Input and Output Traces The board has 24 BNC-type connectors: 16 inputs and 8 outputs. The connectors are arranged in a crescent around the device. As shown in Figure 53, this results in all 16 input signal traces and all 8 signal output traces having the same length. This is useful in tests such as all-hostile crosstalk where the phase relationship and delay between signals needs to be maintained from input to output. The evaluation board package includes the following: • Fully populated board with BNC-type connectors. • Windows®-based software for controlling the board from a PC via the printer port. • Custom cable to connect evaluation board to PC. • Disk containing Gerber files of board layout. Optimized for video applications, all signal inputs and outputs are terminated with 75 Ω resistors. Stripline techniques are used to achieve a characteristic impedance on the signal input and output lines, also of 75 Ω. Figure 48 shows a cross section of one of the input or output tracks along with the arrangement of the PCB layers. Note that unused regions of the four layers are filled up with ground planes. As a result, the input and output traces, in addition to having controlled impedances, are well shielded. The three power supply pins, AVCC, DVCC, and AVEE, should be connected to good quality, low noise, ±5 V supplies. While the same ±5 V power supplies are used for analog and digital, separate cables should be run for the power supply to the evaluation board’s analog and digital power supply pins. As a general rule, each power supply pin (or group of adjacent power supply pins) should be locally decoupled with a 0.01 μF capacitor. If there is a space constraint, decouple analog power supply pins before digital power supply pins. A 0.1 μF capacitor located reasonably close to the pins can be used to decouple a number of power supply pins. Finally, a 10 μF capacitor should be used to decouple power supplies as they come on to the board. Rev. 0 | Page 21 of 28 AD8106/AD8107 P1-4 P1-5 NC P1-7 P1-6 + CR1 CR2 + 0.1µF 10µF DVCC 0.1µF 10µF 0.1µF 10µF 75Ω 64 IN00 65 AGND 75Ω 66 IN01 67 AGND 75Ω 68 IN02 69 AGND 75Ω 70 IN03 71 AGND 75Ω 72 IN04 73 AGND 75Ω 74 IN05 75 AGND 75Ω 76 IN06 77 AGND INPUT 00 INPUT 01 INPUT 02 INPUT 03 INPUT 04 INPUT 05 INPUT 06 78 INPUT 07 DVCC 0.01µF AVCC 0.01µF AVCC 0.01µF AVEE 0.01µF 0.01µF 79 63 43 44 45 DVCC DVCC AVCC AVCC AVEE AGND AGND OUT00 AVEE AGND OUT01 AVCC AGND OUT02 AVEE AGND OUT03 AD8106/AD8107 AVCC AGND OUT04 75Ω 1 IN08 2 AGND 75Ω 3 IN09 4 AGND 75Ω 5 IN10 6 AGND 75Ω 7 IN11 8 AGND 75Ω 9 IN12 10 AGND 75Ω 11 IN13 12 AGND 75Ω 13 IN14 14 AGND AVCC 75Ω 15 IN15 16 AGND AVEE INPUT 09 INPUT 10 INPUT 11 AVEE AGND NC AVCC AGND NC AVEE P2-4 75Ω 40 39 38 AVEE 0.01µF 75Ω 37 36 35 AVCC 0.01µF 75Ω 34 33 32 AVEE 0.01µF 75Ω 31 30 AVCC 0.01µF RESERVED 29 75Ω 28 27 AVEE 0.01µF 26 25 24 AVCC 0.01µF 23 22 21 AVEE 0.01µF 20 19 AVCC 18 AVCC 17 AVEE 0.01µF D4 D3 D2 D1 D0 A2 A1 59 RESERVED 80 DGND 62 61 60 58 56 55 54 53 52 51 50 49 48 47 A0 P2-5 RESERVED 57 41 0.01µF UPDATE INPUT 15 AVCC CLK INPUT 14 NC CE INPUT 14 AGND RESET INPUT 12 42 IN07 75Ω INPUT 08 46 P2-2 P2-3 P2-1 R25 20kΩ DVCC SERIAL MODE JUMP Figure 49. Evaluation Board Schematic Rev. 0 | Page 22 of 28 P2-4 P2-5 P2-6 P2-1 P2-2 P2-3 P2-4 P2-5 P2-6 P2-1 P2-3 P2-6 05774-050 AVEE AGND AVCC P2-3 + NC P1-3 DGND P1-2 P2-4 P1-1 P2-5 DVCC DGND AD8106/AD8107 05774-051 AD8106 AD8107 05774-052 Figure 50. Component Side Silkscreen 05774-053 Figure 51. Board Layout (Component Side) Figure 52. Board Layout (Signal Routing Layer) Rev. 0 | Page 23 of 28 05774-054 AD8106/AD8107 05774-055 Figure 53. Board Layout (Power Plane Layer) Figure 54. Board Layout (Bottom Layer) Rev. 0 | Page 24 of 28 AD8106/AD8107 CONTROLLING THE EVALUATION BOARD FROM A PC The evaluation board includes Windows-based control software and a custom cable that connects the board’s digital interface to the printer port of a PC. The wiring of this cable is shown in Figure 55. The software requires Windows 3.1 or later to operate. Before the start of the installation, terminate any other Windows applications that are running. To install the software, insert the disk labeled Disk #1 of 2 in the PC and run the setup.exe file. Additional installation instructions are given on-screen. MOLEX 0.100" CENTER CRIMP TERMINAL HOUSING RESET D-SUB 25 PIN (MALE) 14 1 1 CLK UPDATE 6 MOLEX D-SUB-25 TERMINAL HOUSING 2 3 3 1 4 4 5 5 6 2 25 6 SIGNAL CE RESET UPDATE DATA IN CLK DGND EVALUATION BOARD Figure 55. Evaluation Board PC Connection Cable 25 13 DATA-LINE OVERSHOOT ON PRINTER PORTS PC 05774-056 DGND Figure 56 shows the main screen of the control software in its initial reset state (all outputs off). Using the mouse, any input can be connected with one or more outputs by simply clicking on the appropriate radio buttons in the 16 × 8 on-screen array. Each time a button is clicked on, the software automatically sends and latches the required 40-bit data stream to the evaluation board. An output can be turned off by clicking the appropriate button in the off column. To turn all outputs on, click RESET. The software offers volatile and nonvolatile configuration storage. For volatile storage, up to two configurations can be stored and recalled using the Memory 1 Buffer and Memory 2 Buffer. These function in an identical fashion to the memory on a pocket calculator. For nonvolatile storage of a configuration, the Save Setup and Load Setup functions can be used. This stores the configuration as a data file on disk. CE DATA IN When launching the crosspoint control software, users are asked to select their desired printer port. Most modern PCs have only one printer port, usually called LPT1. However, some laptop computers use the PRN port. The data lines on some printer ports have excessive overshoot. Overshoot on the pin that is used as the serial clock (Pin 6 on the D-Sub-25 connector) can cause communication problems. This overshoot can be eliminated by connecting a capacitor from the CLK line on the evaluation board to ground. A pad has been provided on the solder side of the evaluation board to allow this capacitor to be soldered into place. Depending upon the overshoot from the printer port, this capacitor may need to be as large as 0.01 μF. Rev. 0 | Page 25 of 28 AD8106/AD8107 05774-057 AD8106/AD8107 Figure 56. Evaluation Board Control Panel Rev. 0 | Page 26 of 28 AD8106/AD8107 OUTLINE DIMENSIONS 0.75 0.60 0.45 14.00 BSC SQ 1.60 MAX 80 61 60 1 PIN 1 12.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 20 41 21 VIEW A VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 40 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BDD Figure 57. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-1) Dimensions shown in millimeters ORDERING GUIDE Model AD8106ASTZ 1 AD8107ASTZ1 AD8106-EB AD8107-EB 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Evaluation Board Z = Pb-free part. Rev. 0 | Page 27 of 28 Package Option ST-80-1 ST-80-1 AD8106/AD8107 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05774-0-3/06(0) T T Rev. 0 | Page 28 of 28