ၫᓾ೯Ⴡቖ۾ Rev 5; 7/10 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ``````````````````````````````````` ᄂቶ ET39F12.211 2135 ᆡ FFQSPN Ꭷ९ JTP0JFD! 21229.4 ڔཝྲႯज)TIB.2*ࡼᒠኯሰ።ڔཝཱྀᑺஉᏴጙă 2135 ᆡ FFQSPN ᑫॊᆐ႐Ljඛ 367 ᆡLjᄋ 75 ᆡ ࡀ᎖ᒊቲቖݷᔫăჅᎌࡀ࣒ถᒙᆐቖۣઐ ෝါLj݀భᒦጙᒙ᎖ FQSPN शᑞෝါLj૾ၫᆡ ᒑถ࠭ 2 ܤᆐ 1ăඛຢ ET39F12.211 ᎌᆎጙࡼ 75 ᆡ SPN ᓖݿ൩Ljᎅޣ૮రྜྷበຢăET39F12.211 ᄰਭ߿࢛ 2.Xjsf® ᔐሣᄰቧăᄰቧᔥክܪᓰࡼ 2.Xjsf ፇLjᏴࣶৈ ୈࡼ2.XjsfᆀᒦLjୈࡼᓖݿ൩భጲߠࡩஂ࢛ᒍă ♦ 2135ᆡFFQSPNࡀLjॊᆐ5Ljඛ367ᆡ ``````````````````````````````````` ። ࡌ፝૦ਫ਼ᒙᎧପހ ♦ ดᒙ623ᆡTIB.2༺Lj᎖ଐႯ271ᆡቧᇦཱྀᑺ൩ )NBD*݀ည߅මᏙ ♦ ቖषᆰኊገᒀࡸමᏙ݀༦ถ৫ଐႯĂࠅ႙271ᆡNBDLj ጲୂܰᑞᆗ ♦ ࡀᒦࡼ1Ă4ཝݝ႐భᎅઓᒙ ᆐቖۣઐ ♦ 2భᎅઓ߈ܠᒙᆐPUQ! FQSPNशᑞෝါ Đቖ1đ ) *ă ♦ Ꭷᓍ૦ମࡼᄰቧᄰਭവၫᔊቧږᑍ2.Xjsfፇ ቲLjᄰቧႥൈᆐ26/4lcqt236lcqt ♦ ൝࢟ຳ༤ધ࢛ᒣૄਜ਼݆ᄋ೫ఝᐅဉถೆ ጛࠅঢୂࢾᎧቅᓰ ♦ ถ৫Ᏼ3/9Wᒗ6/36WኹपᆍดቲࣗĂቖݷᔫLj ᔫᏴ.51°Dᒗ,96°Dᆨࣞपᆍ ᇹᄻᒀဤޘཚۣઐ ♦ 7୭UTPDਜ਼UEGOॖᓤ3୭TGOॖᓤ ``````````````````````````` ࢜ቯᔫ࢟വ ``````````````````````````````` ࢾ৪ቧᇦ PART VCC RPUP IO μC DS28E01-100 TEMP RANGE PIN-PACKAGE DS28E01P-100+ -40°C to +85°C 6 TSOC DS28E01P-100+T -40°C to +85°C 6 TSOC DS28E01G-100+T&R -40°C to +85°C 2 SFN DS28E01Q-100+T&R -40°C to +85°C 6 TDFN-EP* (2.5k pcs) +ܭာᇄ)Qc*0९SpITܪᓰࡼॖᓤă Uਜ਼U'S! >! ௳ࡒ۞ᓤă *FQ! >! ൡă GND ୭ᒙᏴၫᓾ೯ࡼᔢઁ߲ă ༿ࣗᑗᓖፀǖ۾ᆪဵᅲᑳၫᓾ೯ࡼჁቖ۾Ljྙኊ༿ၫᓾ೯ཝᆪLj༿षᆰdijob/nbyjn.jd/dpn0ET39F12Lj࢛ૣ ༿ၫᓾ೯ཝᆪă 2.XjsfဵNbyjn! Joufhsbufe! Qspevdut-! Jod/ࡼᓖݿܪă ________________________________________________________________ Maxim Integrated Products 1 ۾ᆪဵ፞ᆪၫᓾ೯ࡼፉᆪLjᆪᒦభถࡀᏴडፉࡼݙᓰཀྵࡇᇙăྙኊጙݛཀྵཱྀLj༿Ᏼิࡼଐᒦݬఠ፞ᆪᓾ೯ă ᎌਈଥৃĂૡૺࢿ৪ቧᇦLj༿ೊNbyjnᒴሾ၉ᒦቦǖ21911!963!235:!)۱ᒦਪཌ*Lj21911!263!235:!)ฉᒦਪཌ*Lj षᆰNbyjnࡼᒦᆪᆀᐶǖdijob/nbyjn.jd/dpnă ET39F12.211 ``````````````````````````````````` গၤ ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ABSOLUTE MAXIMUM RATINGS Lead Temperature (TSOC, TDFN only; soldering, 10s)...+300°C Soldering Temperature (reflow) TSOC, TDFN .................................................................+260°C SFN .......Refer to Application Note 4132: Attachment Methods for the Electro-Mechanical SFN Package. IO Voltage Range to GND .......................................-0.5V to +6V IO Sink Current ...................................................................20mA Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.25 V 2.2 k IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP 1-Wire Pullup Resistance (Note 2) 2.8 0.3 RPUP (Notes 2, 3) Input Capacitance CIO (Notes 4, 5) Input Load Current IL IO pin at VPUP High-to-Low Switching Threshold VTL (Notes 5, 6, 7) Input Low Voltage VIL (Notes 2, 8) Low-to-High Switching Threshold VTH (Notes 5, 6, 9) Switching Hysteresis VHY (Notes 5, 6, 10) Output Low Voltage VOL At 4mA current load (Note 11) Recovery Time (Notes 2,12) tREC Rising-Edge Hold-Off Time (Notes 5, 13) tREH Time Slot Duration (Notes 2, 14) t SLOT 1000 pF 0.05 6.7 μA 0.46 VPUP 1.8 V 0.5 V 1.0 VPUP 1.1 V 0.21 1.70 V 0.4 V Standard speed, RPUP = 2.2k 5 Overdrive speed, RPUP = 2.2k 2 Overdrive speed, directly prior to reset pulse; RPUP = 2.2k 5 Standard speed Overdrive speed 0.5 μs 5.0 Not applicable (0) Standard speed 65 Overdrive speed 8 μs μs IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Reset Low Time (Note 2) tRSTL Presence-Detect High Time t PDH Presence-Detect Low Time t PDL Presence-Detect Sample Time (Notes 2, 15) tMSP 2 Standard speed 480 640 Overdrive speed 48 80 Standard speed 15 60 Overdrive speed 2 6 Standard speed 60 240 Overdrive speed 8 24 Standard speed 60 75 Overdrive speed 6 10 _______________________________________________________________________________________ μs μs μs μs ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN (TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: 1-Wire WRITE Write-Zero Low Time (Notes 2, 16, 17) Write-One Low Time (Notes 2, 17) tW0L tW1L Standard speed 60 120 Overdrive speed, VPUP > 4.5V 5 15.5 Overdrive speed 6 15.5 Standard speed 1 15 Overdrive speed 1 2 Standard speed 5 15 - Overdrive speed 1 2- Standard speed tRL + 15 Overdrive speed tRL + 2 μs μs IO PIN: 1-Wire READ Read Low Time (Notes 2, 18) tRL Read Sample Time (Notes 2, 18) tMSR μs μs EEPROM Programming Current I PROG (Notes 5, 19) 0.8 mA Programming Time t PROG (Note 20) 10 ms Write/Erase Cycles (Endurance) (Notes 21, 22) NCY Data Retention (Notes 23, 24, 25) tDR At +25°C 200k At +85°C (worst case) 50k At +85°C (worst case) 40 Years SHA-1 ENGINE Computation Current Computation Time (Notes 5, 26) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: ILCSHA tCSHA mA Refer to the full data sheet. ms Specifications at TA = -40°C are guaranteed by design only and not production tested. System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩ pullup resistor is used, the parasite capacitance does not affect normal communications 2.5μs after VPUP has been applied. Guaranteed by design, characterization, and/or simulation only. Not production tested. VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Voltage below which, during a falling edge on IO, a logic 0 is detected. The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level. Voltage above which, during a rising edge on IO, a logic 1 is detected. After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0. The I-V characteristic is linear for voltages less than 1V. Applies to a single device attached to a 1-Wire line. The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge. Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN. Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E01-100 present. Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN. Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table. _______________________________________________________________________________________ 3 ET39F12.211 ELECTRICAL CHARACTERISTICS (continued) ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ELECTRICAL CHARACTERISTICS (continued) (TA = -40°C to +85°C.) (Note 1) Note 17: ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 18: δ in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Note 19: Current drawn from IO during the EEPROM programming interval or SHA-1 computation. Note 20: Refer to the full data sheet for this note. Write-cycle endurance is degraded as TA increases. Not 100% production tested; guaranteed by reliability monitor sampling. Data retention is degraded as TA increases. Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C. Note 26: Refer to the full data sheet for this note. Note 21: Note 22: Note 23: Note 24: ࣪ᑍܭ LEGACY VALUES PARAMETER STANDARD SPEED (μs) DS28E01-100 VALUES OVERDRIVE SPEED (μs) STANDARD SPEED (μs) OVERDRIVE SPEED (μs) MIN MAX MIN MAX MIN MAX MIN MAX 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined) tRSTL 480 (undefined) 48 80 480 640 48 80 t PDH 15 60 2 6 15 60 2 6 t PDL 60 240 8 24 60 240 8 24 tW0L 60 120 6 16 60 120 6 15.5 t SLOT (including tREC) *ᄂፀቲࡼኀখLjኀখઁࡼ2.Xjsf༄࣡ኊገৎૂࡼޠআဟମă ᓖǖ࠰ᄏၫݙ९ࠅᄻࡼ2.Xjsfޘອܪᓰă 4 _______________________________________________________________________________________ ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ୭ ߂ TSOC TDFN-EP SFN 1 3 2 GND 2 2 1 IO 3, 4, 5, 6 1, 4, 5, 6 — N.C. — EP — EP ``````````````````````````````` ሮᇼႁී ET39F12.211 Ᏼৈበຢดૹ߅೫ 2135 ᆡ FFQSPN! )ॊᆐ 5 Ljඛ 367 ᆡ*Ă75 ᆡමᏙĂጙৈࡀĂ623 ᆡ TIB. 2༺ਜ਼75ᆡSPNᓖݿ൩ăၫږᑍ2.XjsfፇࠈቲࠅၒLj ᒑኊጙᄟၫሣਜ਼ጙᄟऩૄሣăET39F12.211 ᎌጙৈ߂ ᆐࡀࡼॺᓐࡀཌLjᏴሶᓍࡀĂࡀቖၫ LjᏴᒙቤමᏙဟߠࡩદߡăၫ၅ሌቖྜྷࡀ Lj݀భ࠭ᑚಱࣗૄăၫளਭዩᑺઁLjᒑገ ET39F12. 211 ၃ࡵ೫ປࡼ 271 ᆡ NBDLjกඐ Dpqz! Tdsbudiqbe ෘ എڳၫࠅ႙ࡵᔢᒫࡼࡀᏄăNBD ଐႯૺࡀ Ᏼ ET39F12.211 ᒦࡼමᏙਜ਼এଝၫLjጲૺୈᓖݿ൩ă ᒑᎌଝᏲቤමᏙဟݣᇄኊᄋ NBDăࣗࡀጲૺଐ ႯጙৈቤමᏙ)ऎဵݙᒇଝᏲමᏙ*ဟLjጐ૮ TIB.2 ༺ଐႯ 271 ᆡ NBDăET39F12.211 ถဤܰጙৈᄂᎌࡼ Sfgsfti! Tdsbudiqbe ෘഎăୈᏴ߿ણஹဟLjྙਫᏴᒊ ቲᅲ Dpqz! Tdsbudiqbe ෘഎઁးࡩᒊቲၮቤਭ߈Ljభጲି ቃပྦྷᆡࡼᆡၫ)ݬࡒዩᑺࡼቖݷᔫݝॊ*ăၮቤਭ߈ થᄋ೫ጙᒬૂআୈᒦࠀ᎖ྦྷᓨზᆡࡼऱजă ถ ݬఠă 2.Xjsf ᔐሣాLjധఎവLjኊᅪ౯࢟ᔜă ᇄೌă ൡLjᏢᏴ࢟വۇຳෂཀྵۣᑵޟᔫLjሮᇼቧᇦ ༿ݬఠ።܊ 4384ǖFyqptfe! Qbet;! B! Csjfg! Jouspevdujpoă ୈࡼ 75 ᆡ SPN ᓖݿ൩ถ৫࣪ୈቲᆎጙࡼဤܰLj݀ Ᏼࣶ࢛ 2.Xjsf ᆀણஹ)ࣶৈୈਂᏴᄴጙ 2.Xjsf ᔐሣ Ljࣖࠥ܋ೂᔫ*ᒦ࣪ୈቲኰᒍăET39F12.211 ࡼ࢜ ቯ።۞౪ǖࡌ፝૦ਫ਼ᒙૺପހĂጛࠅঢୂܰ ᎧቅᓰĂᇹᄻᒀဤޘཚۣઐă ᔐၤ ᅄ2Ⴥာऱౖᅄႁී೫ET39F12.211ᓍ఼ᏄᎧࡀݝॊ ࡼਈᇹăET39F12.211 ۞౪ങৈᓍገၫݝୈǖ75 ᆡర SPNĂ75 ᆡࡀĂඛ 367 ᆡࡼ႐ৈ FFQSPN Ăࡀ Ă75 ᆡමᏙࡀĂ623 ᆡ TIB.2 ༺ă2.Xjsf ፇ ࡼࠨށஉ৩ྙᅄ 3 ჅာLjᔐሣᓍ૦ܘኍ၅ሌख႙ጲሆ໕ᄟ SPNถෘഎᒦࡼጙᄟǖSfbe! SPNĂNbudi! SPNĂTfbsdi SPNĂTljq! SPNĂSftvnf! DpnnvojdbujpoĂPwfsesjwf.Tljq SPNĂ Pwfsesjwf.Nbudi! SPNă ࡩ ጲ ܪᓰ Ⴅ ࣞ ᒊ ቲ ᅲ Pwfsesjwf.Tljq! SPN Pwfsesjwf.Nbudi! SPN ෘഎઁLjୈ ྜྷႥෝါLjჅᎌઁኚᄰቧጲႥෝါቲăᎧᑚ ቋ SPN ถෘഎሤਈࡼፇႁීྙᅄ 21 Ⴥာă߅ᒊቲ SPN ถෘഎઁLjభጲቲࡀਜ਼ TIB.2 ݷᔫLjᓍ૦ భख߲ : ᄟᎌถෘഎᒦࡼྀጙᄟLjਈ᎖ถෘഎፇ ࡼႁීྙᅄ9ჅာăჅᎌၫࣗቖဟ࣒ဵࢅᆡᏴ༄ă _______________________________________________________________________________________ 5 ET39F12.211 ``````````````````````````````````````````````````````````````````````````` ୭ႁී ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN PARASITE POWER 1-Wire NET 1-Wire FUNCTION CONTROL 64-BIT LASERED ROM MEMORY AND SHA-1 FUNCTION CONTROL UNIT 512-BIT SECURE HASH ALGORITHM ENGINE CRC-16 GENERATOR DS28E01-100 64-BIT SCRATCHPAD DATA MEMORY 4 PAGES OF 256 BITS EACH REGISTER PAGE SECRETS MEMORY 64 BITS ᅄ2/! ऱౖᅄ 75ᆡరSPN ඛຢ ET39F12.211 ࣒ᎌᆎጙࡼ 75 ᆡ SPN ᓖݿ൩Ljᒦ༄ 9 ᆡဵ 2.Xjsf ଜᔙ൩Ljᒦମ 59 ᆡဵᆎጙࡼኔLjᔢઁ 9 ᆡ ဵ༄ 67 ᆡࡼክણྑቅዩ)DSD*൩Ljሮᇼቧᇦྙᅄ 4 Ⴥာă 2.Xjsf! DSD ቅዩ൩ᎅጙৈ۞ጤᆡࡀਜ਼ፊඡࡼࣶሲ ါखညޘညLjྙᅄ 5 ჅာăকࣶሲါᆐǖY 9 , Y6 , Y5 , 2ăᎌਈ 2.Xjsf DSD ቅዩ൩ࡼሮᇼቧᇦ༿ݬఠ።܊ 38ǖಯஊਜ਼Ꮵ Nbyjn jCvuupo® ޘອᒦࡼክણྑቅዩ )DSD*ă ጤᆡࡀࡼ߱ᒋᆐഃă࠭ଜᔙ൩ࡼᔢࢅᎌᆡఎဪLj ඛࠨጤྜྷጙᆡăࡩଜᔙ൩ 9 ᆡጤྜྷઁLjᏳጤྜྷኔă ࡩኔ 59 ᆡጤྜྷઁLjጤᆡࡀࡼดྏဵ DSD ᒋă ጤྜྷ9ᆡDSDቅዩ൩ઁLjጤᆡࡀ።কཝݝਙഃă ````````````````````````````` ࡀषᆰ ET39F12.211 ᎌ႐ৈࡀཌǖၫࡀĂමᏙࡀĂ ᄂၐถࡀਜ਼ઓᔊஂࡼࡀĂጲૺጵပ ࡀăၫࡀৢॊ 5 Ljඛ 43 ৈᔊஂLjමᏙࡀ ਜ਼ࡀॊܰᆐ 9 ৈᔊஂăሶၫࡀቖၫĂᏲྜྷ߱ ဪමᏙሶࡀቖၫဟLjࡀᔫᆐદࡀဧă কݝॊቧᇦ༿ݬᅲᑳၫᓾ೯ă jCvuupoဵNbyjn! Joufhsbufe! Qspevdut-! Jod/ࡼᓖݿܪă 6 _______________________________________________________________________________________ ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ET39F12.211 DS28E01-100 COMMAND LEVEL: 1-Wire ROM FUNCTION COMMANDS (SEE FIGURE 10) AVAILABLE COMMANDS: DATA FIELD AFFECTED: READ ROM MATCH ROM SEARCH ROM SKIP ROM RESUME OVERDRIVE-SKIP ROM OVERDRIVE-MATCH ROM 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG RC-FLAG RC-FLAG RC-FLAG, OD-FLAG 64-BIT REG. #, RC-FLAG, OD-FLAG DEVICE-SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 8) Refer to the full data sheet. ᅄ3/! 2.Xjsfፇࠨށஉ৩ MSB LSB 8-BIT CRC CODE MSB 8-BIT FAMILY CODE 48-BIT SERIAL NUMBER LSB LSB MSB LSB MSB ᅄ4/! 75ᆡరSPN POLYNOMIAL = X8 + X5 + X4 + 1 1ST STAGE X0 2ND STAGE X1 3RD STAGE X2 4TH STAGE X3 5TH STAGE X4 6TH STAGE X5 7TH STAGE X6 8TH STAGE X7 X8 INPUT DATA ᅄ5/! 2.Xjsf! DSDखည _______________________________________________________________________________________ 7 ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ET39F12.211 ݬᅲᑳၫᓾ೯ă ᅄ7/! ࡀۣઐᑫ BIT # 7 6 5 4 3 2 1 0 TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 (0) T1 (0) T0 (0) TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8 ENDING ADDRESS WITH DATA STATUS (E/S) (READ ONLY) AA 1 PF 1 1 E2 (1) E1 (1) E0 (1) ᅄ8/! ᒍࡀ ᒍࡀਜ਼ࠅၒᓨზ ET39F12.211 ဧྯৈᒍࡀǖUB2ĂUB3 ਜ਼ F0T! )ᅄ 8*ăᑚቋࡀ໋ܩ᎖ 2.Xjsf ୈLjࡣᏴ ET39F12. 211 ᒦࡼᔫᎌݙᄴăࡀ UB2 ਜ਼ UB3 ࡀहࡼဵቖྜྷ ၫࣗནၫࡼܪᒍăࡀ F0T ဵጙৈᒑࣗࡼࠅ ၒᓨზࡀLj᎖ዩᑺቖෘഎࡼၫᅲᑳቶăፐᆐ ET39F12.211 ࡼࡀᒑ၃ 9 ᔊஂၫ్LjჅጲ UB2 ࡼ ࢅྯᆡဪᒫᆐ 1LjF0T ࡀࡼࢅྯᆡ)உၦມጤ*ဪᒫᆐ 2ăᑚፀᆜᓹࡀࡼჅᎌၫႲઁ࣒ገআᒜࡵᓍࡀ මᏙࡀăF0T ࡀࡼ 6 ᆡ߂ᆐ QG ᔊஂݙཝܪ ᒔLjকᆡྙਫᆐ൝ 2Ljᐌፀᆜᓹᓍ૦ख႙ࡼၫᆡၫݙ ဵ 9 ࡼᑳၫ۶Ljᑗࡀࡼၫᎅ᎖ࢬ࢟ऎ߅ᆐᇄၫ ăᎌࡼቖࡀݷᔫ༹߹ QG ᆡă 4Ă5Ă7 ᆡᎌ ถLj߲ࣗၫဪᒫᆐ 2ăಽ QG ܪᒔLjᓍ૦భጲᏴቖෘ _______________________________________________________________________________________ 9 ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN എᒄઁଶዩၫࡼᅲᑳቶăF0T ࡀࡼᔢᆡ߂ᆐ၈ཚ భܪ)BB*Lj᎖ᒎာࡀࡼၫጯআᒜࡵࡀܪ ᒍăሶࡀቖྜྷၫ༹߹কܪᒔă ࡒዩᑺࡼቖݷᔫ Ᏼሶ ET39F12.211 ቖၫဟLjܘኍڳࡀᔫᒦମࡀ ă၅ሌLjᓍ૦ख႙ Xsjuf! Tdsbudiqbe ෘഎLjᒎࢾܪᒍ ݀ၫቖྜྷࡀăᓖፀLjၫܘኍቖྜྷၫࡀ ࡼ 9 ᔊஂܟஏดLjጐဵႁLjܪᒍࡼྯৈᔢࢅᎌᆡ U\3;1^ܘኍࢀ᎖ 111căྙਫख႙ࡼ U\3;1^ᆐऻഃᒋLjୈ ڳᑚቋᆡᒙഃLj݀ڳኀখઁࡼᒍᔫᆐܪᒍăᓍ૦ ።ဪᒫख႙ 9 ৈᅲᑳࡼၫᔊஂLj9 ৈၫᔊஂࠅၒᅲ ઁLjᓍ૦ถ৫၃ࡵୈږᑍᓍ૦ख႙ࡼ Xsjuf! Tdsbudiqbe ෘഎĂܪᒍਜ਼ၫࢀည߅ࡼ DSD.27 ቅዩन൩ăᓍ૦ ক DSD ൩ᎧᔈଐႯ߲ࡼᒋሤ୷܈Ljభጲࣥၫ ᄰቧဵ॥߅ăቖࡀઁLjᓍ૦።ဪᒫᒊቲ Sfbe Tdsbudiqbe ෘഎLjጲዩᑺቖྜྷၫဵ॥ᑵཀྵăSfbe Tdsbudiqbe ໐ମLjET39F12.211 ્ᒮቤखૄܪᒍ UB2ĂUB3 ጲૺ F0T ࡀࡼดྏăྙਫ ET39F12.211 Ᏼ Xsjuf! TdsbudiqbeĂ Sfgsfti Tdsbudiqbeෘഎᒦ၃ࡵࡼጙৈၫᔊஂݙᅲᑳLj ᑗጙࠨቖࡀઁखညࢬ࢟৺ᑇLjᐌᔊஂݙཝܪᒔ )F0T ࡀࡼ 6 ᆡ*ᒙ 2ăᒊቲ Xsjuf! Tdsbudiqbe Sfgsfti Tdsbudiqbe ෘഎઁLj၈ཚభܪ BB! )F0T ࡀࡼ 8 ᆡ* ᄰ્༹ޟഃăჅጲLjྙਫকᆡᒙ 2Ljᐌ ීܭET39F12.211 ᎌࠀಯ Xsjuf! ) Sfgsfti*! Tdsbudiqbe ෘഎăᇄ൙ၤጙ ᒬ༽ౚLjᓍ૦࣒።ᒮቖࡀăᓍ૦၃ࡵ F0T ࡀด ྏઁLjથ્၃ࡵࡀၫăਈ᎖ Xsjuf! Tdsbudiqbe ਜ਼ Sfgsfti! Tdsbudiqbe ෘഎࡼႁී߲೫Ᏼᒬᄟୈሆࡀ ၫభถखညࡼܤછăᏴࡀၫઁෂ၃ࡵࡼဵᎅ Sfbe! Tdsbudiqbe ෘഎĂܪᒍĂF0T ࡀดྏਜ਼ࡀ ၫࢀည߅ࡼ DSD ቅዩन൩ăᎧ Xsjuf! Tdsbudiqbe ෘഎ ጙዹLjᓍ૦ڳক DSD ൩ᎧᔈଐႯ߲ࡼᒋሤ୷܈Ljጲ ࣥᄰቧဵ॥߅ăᓍ૦ዩᑺᅲၫઁLj૾భख႙ Dpqz Tdsbudiqbe ෘഎࡀၫআᒜࡵࡀăࠥᅪLjጐభ ጲख႙ Mpbe! Gjstu! Tfdsfu Dpnqvuf! Ofyu! Tfdsfu ෘഎৎখම ᏙLjሮᇼቧᇦ༿ݬఠሤਈෘഎࡼႁීă 10 কݝॊቧᇦ༿ݬᅲᑳၫᓾ೯ă ______________________________________________________________________________________ ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ET39F12.211 ````````````````` ࡀਜ਼ TIB.2ถෘഎ কݝॊႁී೫ဧୈࡼࡀਜ਼ TIB.2 ༺Ⴥኊࡼෘഎ ਜ਼ഗ߈ᅄăৎࣶቧᇦ༿ݬᅲᑳၫᓾ೯ă ______________________________________________________________________________________ 11 ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ET39F12.211 ````````````````````````````` TIB.2Ⴏज কݝॊਈ᎖ TIB.2 Ⴏजࡼႁීᔈڔཝྲܪᓰ TIB.2 ᆪ Ljࠥᆪభ࠭ਪଜܪᓰଆၣዐᏔ)OJTU*ᆀᐶሆᏲăৎ ࣶቧᇦ༿ݬᅲᑳၫᓾ೯ă ______________________________________________________________________________________ 23 ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ````````````````````````` 2.Xjsfᔐሣᇹᄻ 2.Xjsf ᔐሣᇹᄻᎅጙৈᔐሣᓍ૦ਜ਼ጙৈࣶৈ࠭ୈ ᔝ߅ăᏴჅᎌ።ᒦLjET39F12.211 ࣒ᔫᆐ࠭ୈဧă ᔐሣᓍ૦ᄰဵޟጙৈᆈ఼ᒜă࣪᎖কᔐሣᇹᄻࡼᄀ൙ ॊᆐྯݝॊǖ፮ୈᒙĂࠀಯഗ߈ਜ਼ 2.Xjsf ቧഎ)ቧಢ ቯਜ਼ဟኔ*ă2.Xjsf ፇਖࢾᔐሣࡼ၃खږᑍᄂၐဟᇺሆ ࡼᔐሣᓨზቲLjᎅᔐሣᓍ૦ख߲ࡼᄴݛ൴ߡሆଢ଼ዘ߱ ဪછă ``````````````````````````````` ፮ୈᒙ 2.Xjsf ᔐሣᒑࢾፃ೫ጙᄟၫሣLjፐࠥᔐሣࡼඛৈ۸ ถ৫Ᏼးࡩဟరདࣅᔐሣဵऻޟᒮገࡼăᆐ೫ࡉࡵᑚጙ ࡼLjᏴ 2.Xjsf ᔐሣࡼඛৈୈ࣒ܘኍᎌധఎവ ྯზၒ߲ăET39F12.211 ࡼ 2.Xjsf ࣡ాᆐധఎവLj ดࢀݝ࢟വྙᅄ:Ⴥာă ࣶ ࢛ ᔐ ሣ ᎅ ೌ ೫ ࣶ ৈ ࠭ ૦ ୈ ࡼ 2.Xjsf ᔐ ሣ ᔝ ߅ ă ET39F12.211 ᑽߒ 26/4lcqt )ᔢࡍᒋ*ࡼܪᓰᄰቧႥൈਜ਼ 236lcqt )ᔢࡍᒋ*ࡼႥᄰቧႥൈăᓖፀLjሌ༄ᅎ߲ࡼ 2.Xjsf ୈॊܰᑽߒ 27/4lcqt ࡼܪᓰᄰቧႥൈਜ਼ 253lcqt ࡼ ႥᄰቧႥൈăET39F12.211 Ⴅൈᎌଢ଼ࢅLjᏇፐဵᆐ೫ ᐐ༓ 2.Xjsf ᇕಯాࡼᐅဉጴᒜถೆऎዓޠ೫ૂআဟମă VPUP BUS MASTER DS28E01-100 1-Wire PORT RPUP DATA Rx Tx Rx = RECEIVE Tx = TRANSMIT OPEN-DRAIN PORT PIN Rx IL Tx 100Ω MOSFET ᅄ:/! ፮ୈᒙ 24 ______________________________________________________________________________________ ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN 2.Xjsf ᔐሣࡼహሔᓨზဵ࢟ຳăྙਫፐᆐ෭ᒬᏇፐኊገ ᄫᄰቧLj݀ᏴઁኊገૂআᄰቧࡼજLjᔐሣܘኍۣߒ ᏴహሔᓨზăྙਫᆚᒙᆐహሔᓨზLj݀༦ᔐሣࠀ᎖ࢅ ࢟ຳࡼဟମިਭ 27μt! )Ⴅෝါ* 231μt! )ܪᓰႥൈ*Ljᔐ ሣࡼጙৈࣶৈୈۻআᆡă ``````````````````````````````` ࠀಯഗ߈ ᄰਭ2.Xjsf࣡ాषᆰET39F12.211ࡼፇྙሆǖ • ߱ဪછ • SPNถෘഎ • ࡀ0TIB.2ถෘഎ • ࠅၒ0ၫ ````````````````````````````````` ߱ဪછ 2.Xjsf ᔐሣჅᎌࡼࠅၒݷᔫ࠭߱ဪછਭ߈ఎဪă߱ဪ છਭ߈ᎅᓍ૦ख߲ࡼআᆡ൴ߡਜ਼࠭૦ख߲ࡼᏴሣ።ࡊ൴ ߡᔝ߅ăᏴሣ።ࡊ൴ߡᄰᒀᓍ૦ ET39F12.211 ਂᏴᔐሣ Lj݀༦ጯளᓰ۸ኙăሮᇼดྏ༿ݬఠ 2.Xjsfቧഎݝॊă ```````````````````` 2.Xjsf! SPNถෘഎ ጙࡡᔐሣᓍ૦ଶࡵހᏴሣ።ࡊ൴ߡLj૾భख߲ ET39F12. 211 ᑽߒࡼ໕ৈ SPN ถෘഎᒦࡼጙৈăჅᎌ SPN ถ ෘഎࡼࣞޠᆐ 9 ᆡăጲሆ߲೫ᑚቋෘഎࡼ଼ገ )ݬᅄ21Ⴥာࡼഗ߈ᅄ*ă Sfbe! SPN! \44i^ Sfbe! SPN ෘഎᏤᔐሣᓍ૦ࣗན ET39F12.211 ࡼ 9 ᆡଜᔙ ൩Ă59 ᆡᆎጙኔਜ਼ 9 ᆡ DSD ቅዩ൩ăࠥෘഎး᎖ᔐ ሣᒑᎌጙৈ࠭ୈࡼ༽ౚăྙਫᔐሣೌ೫ࣶৈ࠭ ୈLjࡩჅᎌ࠭ୈ၂ᅄᄴဟख႙ၫဟLj્खညၫ ߡᅃ)ധఎവၒ߲ޘညጙৈሣᎧࡼஉਫ*ăࡴᒘᓍ૦ࣗ ནࡼଜᔙ൩ਜ਼59ᆡኔᎧDSDቅዩ൩ݙປă Nbudi! SPN! \66i^ Nbudi! SPN ෘഎᒄઁဵ 75 ᆡୈᓖݿ൩LjᏤᔐሣᓍ૦ षᆰࣶ࢛ᔐሣጙৈᄂࢾࡼ ET39F12.211ăᒑᎌᎧক 75 ᆡ ୈᓖݿ൩ᅲཝປࡼ ET39F12.211 ઁ્࣪ݣෂࡼࡀ TIB.2 ถෘഎᔪ߲ሰ።ăჅᎌ࠭ୈࢀࡗሆጙ ৈআᆡ൴ߡăকෘഎး᎖࢛ᔐሣਜ਼ࣶ࢛ᔐሣă Tfbsdi! SPN! \G1i^ ᇹᄻধࣅဟLjᔐሣᓍ૦భถ݀ݙᒀࡸ 2.Xjsf ᔐሣਂ ࡼୈၫૺඣࡼᓖݿ൩ăᓍ૦భಽᔐሣࡼሣᎧᄂ ቶLjݧ߹जဤܰᔐሣჅᎌ࠭ୈࡼᓖݿ൩ăᑣ࣪ ᔢࢅᎌᆡᏴ༄ࡼᓖݿ൩ࡼඛጙᆡLjᔐሣᓍ૦࣒ख႙ྯ ৈဟᇺăᏴጙৈဟᇺLjඛৈݬᎧႝჃࡼ࠭૦࣒ၒ߲ ᔈᓖݿ൩ᆡࡼᏇ൩ăᏴऔৈဟᇺLjඛৈݬᎧႝჃࡼ࠭ ૦࣒ၒ߲ᔈᓖݿ൩ᆡࡼݗ൩ᒋăᏴྯৈဟᇺLjᓍ૦ ቖྜྷჅኡᆡࡼᏇ൩ăჅᎌᎧᎅᓍ૦ቖྜྷࡼকᆡݙປࡼ ࠭૦࣒ݙᏳݬଝႝჃăྙਫᓍ૦ೝࠨࣗࡵࡼᒋဵ 1Ljᐌ ႁී࠭૦কᆡࡼೝৈᓨზ࣒ࡀᏴăᔐሣᓍ૦ᄰਭቖྜྷࡼ ᓨზᒋኡᐋႝჃၥࡼݙᄴॊᑽăளਭጙࠨᅲᑳႝჃਭ ߈Ljᔐሣᓍ૦૾భᒀࡸ෭ৈ࠭૦ࡼᓖݿ൩ăᅪࡼႝჃ ਭ߈భጲဤܰ࠭૦ࡼᓖݿ൩ăሮᇼᄀ൙༿ݬఠ። ܊298ǖ2.XjsfႝჃႯजLjᒦ۞౪ጙৈာಿă Tljq! SPN! \DDi^ Ᏼ࠭૦ᔐሣᇹᄻᒦLjᔐሣᓍ૦భဧকෘഎषᆰࡀ ऎᇄኊᄋ 75 ᆡᓖݿ൩Lj࠭ऎஂဏ೫ဟମăྙਫᔐሣ ݙᒏጙৈ࠭૦LjᏴ Tljq! SPN ෘഎઁख႙ࣗෘഎဟLj્ ፐᆐࣶৈ࠭૦ᄴဟख႙ၫऎࡴᒘၫߡᅃ)ധఎവၒ ߲ሆ౯ޘညጙৈሣᎧஉਫ*ă ______________________________________________________________________________________ 25 ET39F12.211 ౯࢟ᔜࡼᔜᒋᓍገᎅᆀਖෝਜ਼ঌᏲᄟୈࢾă ET39F12.211ᏴྀੜႥࣞሆᏥቲ࣒ኊገጙৈ3/3lΩ )ᔢࡍᒋ* ࡼ౯࢟ᔜă ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN BUS MASTER Tx RESET PULSE FROM FIGURE 10b FROM MEMORY AND SHA-1 FUNCTION FLOWCHART (FIGURE 8) OD RESET PULSE? N OD = 0 Y BUS MASTER Tx ROM FUNCTION COMMAND 33h READ ROM COMMAND? DS28E01-100 Tx PRESENCE PULSE N 55h MATCH ROM COMMAND? F0h SEARCH ROM COMMAND? N N CCh SKIP ROM COMMAND? Y Y Y Y RC = 0 RC = 0 RC = 0 RC = 0 DS28E01-100 Tx FAMILY CODE (1 BYTE) MASTER Tx BIT 0 TO FIGURE 10b DS28E01-100 Tx BIT 0 DS28E01-100 Tx BIT 0 MASTER Tx BIT 0 BIT 0 MATCH? N N BIT 0 MATCH? Y Y DS28E01-100 Tx SERIAL NUMBER (6 BYTES) N DS28E01-100 Tx BIT 1 MASTER Tx BIT 1 DS28E01-100 Tx BIT 1 MASTER Tx BIT 1 BIT 1 MATCH? N N BIT 1 MATCH? Y Y DS28E01-100 Tx BIT 63 DS28E01-100 Tx CRC BYTE MASTER Tx BIT 63 DS28E01-1001 Tx BIT 63 MASTER Tx BIT 63 BIT 63 MATCH? N N BIT 63 MATCH? Y Y RC = 1 RC = 1 TO FIGURE 10b FROM FIGURE 10b TO MEMORY AND SHA-1 FUNCTION FLOWCHART (FIGURE 8) ᅄ21b/! SPNถഗ߈ᅄ 26 ______________________________________________________________________________________ ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ET39F12.211 TO FIGURE 10a FROM FIGURE 10a A5h RESUME COMMAND? 3Ch OVERDRIVESKIP ROM? N N Y Y N Y RC = 0; OD = 1 RC = 1? 69h OVERDRIVEMATCH ROM? RC = 0; OD = 1 N Y MASTER Tx BIT 0 MASTER Tx RESET? N Y BIT 0 MATCH? N Y MASTER Tx BIT 1 MASTER Tx RESET? N Y BIT 1 MATCH? N Y MASTER Tx BIT 63 BIT 63 MATCH? N Y FROM FIGURE 10a RC = 1 TO FIGURE 10a ᅄ21c/! SPNถഗ߈ᅄ)ኚ* ______________________________________________________________________________________ 27 ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN Sftvnf! \B6i^ ᆐ೫ᔢࡍ߈ࣞᄋࣶ࢛ણஹᒦࡼၫᅔᅊൈLjᇹᄻᄋ ೫ Sftvnf ถăকถଶ އSD ᆡࡼᓨზLjྙਫᒙᆡLj ᐌᒇ఼ڳᒜཚୣࡀਜ਼ TIB.2 ถෘഎLjᎧ Tljq SPN ෘഎಢ႒ăSD ᒙᆡᒑถᄰਭ߅ᒊቲ Nbudi! SPNĂ Tfbsdi! SPN Pwfsesjwf.Nbudi! SPN ෘഎဣሚăጙࡡ SD ᒙ ᆡLj૾భಽ Sftvnf ෘഎᒮআषᆰকୈăषᆰᔐሣ ࡼୈ્༹߹ SD ᆡLjጲऴᒏೝৈৎࣶࡼ࠭૦ᄴဟ ሰ።Sftvnfෘഎă Pwfsesjwf.Tljq! SPN! \4Di^ Ᏼৈ࠭૦ᔐሣဧকෘഎဟLjᓍ૦ݙኊገᄋ 75 ᆡ ᓖݿ൩૾భषᆰࡀถLj࠭ऎஂဏ೫ဟମăᎧᄰࡼޟ Tljq! SPN ෘഎݙᄴLjPwfsesjwf.Tljq! SPN ෘഎ ET39F12. 211 ᒙᆐႥෝါ)PE! >! 2*ăকෘഎઁࡼჅᎌᄰቧᆐ ႥෝါLjᒇࡵᎌጙৈߒኚဟମᒗᆐ 591μt ࡼআᆡ൴ߡ ᔐሣࡼჅᎌୈআᆡ߅ܪᓰႥൈ)PE! >! 1*ă ྙਫᏴࣶ࢛ᔐሣख႙কෘഎLjᐌᔐሣჅᎌᑽߒႥ ෝါࡼୈ࣒ۻᒙ߅ႥෝါăႲઁLjᆐ೫ኰᒍᄂࢾ ࡼႥෝါୈLjܘኍᏴႥෝါሆख߲ጙৈআᆡ൴ߡLj ઁဧ Nbudi! SPN Tfbsdi! SPN ෘഎLjᑚዹถ৫ଝႥ ႝჃਭ߈ăྙਫᔐሣᎌࣶৈᑽߒႥෝါࡼ࠭૦Ljऎ ༦ Pwfsesjwf.Tljq! SPN ෘഎઁৌᓹጙৈࣗෘഎLj્ፐࣶৈ ࠭૦ᄴဟख႙ၫऎޘညၫߡᅃ)ധఎവၒ߲ሆ౯ ޘညጙৈሣᎧஉਫ*ă Pwfsesjwf.Nbudi! SPN! \7:i^ ᄰਭ Pwfsesjwf.Nbudi! SPN ෘഎਜ਼ႲઁጲႥෝါख႙ࡼ 75 ᆡᓖݿ൩Ljถ৫ဧᔐሣᓍ૦Ᏼࣶ࢛ᔐሣषᆰጙৈᄂ ࢾࡼ ET39F12.211LjᄴဟᒙᆐႥෝါăᒑᎌᎧক 75 ᆡᓖݿ൩ᅲཝປࡼ ET39F12.211 ્ݣሰ።ઁኚࡼࡀ TIB.2 ถෘഎăጯளۻᒄ༄ࡼ Pwfsesjwf.Tljq! SPN Pwfsesjwf.Nbudi! SPN ෘഎ߅ᒙᆐႥෝါࡼ࠭૦ ଖኚۣߒႥෝါăჅᎌᑽߒႥෝါࡼ࠭૦Ᏼሆጙ ৈߒኚဟମᒗᆐ 591μt ࡼআᆡ൴ߡઁૂআࡵܪᓰႥൈă Pwfsesjwf.Nbudi! SPN ෘഎး᎖ᔐሣਂጙৈࣶৈ ୈࡼ༽ౚă 28 ````````````````````````````` 2.Xjsfቧഎ ET39F12.211 ኊገዏৃࡼፇۣᑺၫᅲᑳቶăকፇ Ᏼጙᄟሣࢾፃ೫႐ᒬಢቯࡼቧǖ۞౪আᆡ൴ߡਜ਼Ᏼ ሣ።ࡊ൴ߡࡼআᆡኔĂቖ 1Ăቖ 2 ਜ਼ࣗၫă߹Ᏼሣ። ࡊ൴ߡᅪLjჅᎌቧሆଢ଼ዘᎅᔐሣᓍ૦ख߲ă ET39F12.211 ถ৫ጲೝᒬݙᄴࡼႥൈᄰቧǖܪᓰႥൈਜ਼ ႥෝါăྙਫᎌීཀྵࢾᆐႥෝါLjET39F12.211 ጲܪᓰႥൈᄰቧăႥෝါሆLjჅᎌ݆ተݧႥ ࢾဟă ࠭హሔᓨზታဟLj2.Xjsf ᔐሣ࢟ኹኊገ࠭ WQVQ ଢ଼ᒗ WUM ඡሢ࢟ኹጲሆă࠭ᔫᓨზऩૄహሔᓨზဟLj࢟ኹ።࠭ W JMNBY ဍࡵ WUI ඡሢ࢟ኹጲă࢟ኹဍဟମᏴᅄ 22 ᒦ ε ܭာLjߒኚဟମན᎖Ⴥဧࡼ౯࢟ᔜ)SQVQ*ਜ਼ 2.Xjsf ᆀࡼএଝ࢟ྏă࢟ኹ WJMNBY ፬ሰ ET39F12.211 ࣪ ൝࢟ຳࡼࣥLj߿્ݙखྀੜူୈă ᅄ 22 ჅာဵఎጙࠨᎧ ET39F12.211 ᄰቧჅኊࡼ߱ဪછਭ ߈ăআᆡ൴ߡઁࡼ።ࡊ൴ߡීܭET39F12.211ጯᓰ۸ኙLj ᒑገ၃ࡵᑵཀྵࡼ SPNĂࡀਜ਼ TIB.2 ถෘഎLj૾భ ၃ၫăྙਫᔐሣᓍ૦Ᏼሆଢ଼ዘݧڼൈ఼ᒜLjܘኍ ᔐሣ࢟ຳ౯ࢅۣ݀ߒ uSTUM ,! uG ဟମLjጲܟޡݗዘă ႥෝါሆLjྦ uSTUM ߒኚ 591μt ৎޠLjభ࠭૦ૂআࡵܪ ᓰႥࣞăྙਫ ET39F12.211 ࠀ᎖Ⴅෝါ݀༦ uSTUM ࡍݙ᎖ 91μtLjᐌۣ྆ߒႥෝါăྙਫୈࠀ᎖ႥෝါLj u STUM ᎖ 91μt ਜ਼ 591μt ᒄମLjୈআᆡLjᄰቧႥൈݙ ཀྵࢾă ᔐሣᓍ૦ျहᔐሣઁྜྷ၃ෝါăࠥဟ 2.Xjsf ᔐሣ࢟ຳ ۻ౯࢟ᔜ ET3593.y11 ET3591C དࣅࢀᎌᏎ࢟വ ౯ᒗ W QVQ ăࡩ࢟ຳ᎖ඡሢ W UI ဟLjET39F12.211 ࢀࡗ uQEI ဟମLjઁᄰਭᔐሣ࢟ຳ౯ࢅۣ݀ߒ uQEM ဟମख ႙ጙৈ።ࡊ൴ߡăᆐ೫ଶހ።ࡊ൴ߡLjᓍ૦ܘኍᏴuNTQ ဟ ମଶހ2.Xjsfᔐሣࡼ൝ᓨზă uSTUI ࠊాဟମܘኍᒗࢀ᎖ uQEINBYĂuQEMNBY Ꭷ uSFDNJO ࡼᔐਜ਼ăጙࡡuSTUI உၦLjET39F12.211૾భఎဪၫᄰቧă Ᏼጙৈ۸ᔝ߅ࡼᆀᒦLjᆐ೫ରྏ2.Xjsf۸Lj uSTUI ᏴܪᓰႥࣞሆ።ᒗᆐ 591μtLjᏴႥෝါሆᒗᆐ 59μtă ______________________________________________________________________________________ ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ET39F12.211 MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE" ε tMSP VPUP VIHMASTER VTH VTL VILMAX 0V tPDH tRSTL tF tPDL tREC tRSTH RESISTOR MASTER DS28E01-100 ᅄ22/! ߱ဪછਭ߈ǖআᆡਜ਼Ᏼሣ።ࡊ൴ߡ ࣗ0ቖဟᇺ Ꭷ ET39F12.211 ࡼၫᄰቧږᑍဟᇺቲLjඛৈဟᇺࠅၒ ጙᆡăቖဟᇺLjၫ࠭ᔐሣᓍ૦ࠅၒࡵ࠭૦ǗࣗဟᇺLj ၫᎅ࠭૦ࠅၒࡵᓍ૦Ljᅄ 23 ႁී೫ቖဟᇺਜ਼ࣗဟᇺࡼ ࢾፃă Ⴥᎌᄰቧጲᓍ૦౯ࢅၫሣఎဪLjࡩ 2.Xjsf ᔐሣ࢟ኹଢ଼ ᒗඡሢ࢟ኹ WUM ጲሆဟLjET39F12.211 ࣅดࢾݝဟखည LjᏴቖဟᇺཀྵࢾੜဟ࣪ၫሣݧዹLjᏴࣗဟᇺཀྵࢾၫ ᎌࡼဟମă ᓍ૦ࡵ࠭૦ ࣪᎖ቖ2ဟᇺLjၫሣࡼ࢟ኹܘኍᏴቖ2ࢅ࢟ຳဟମuX2MNBY உၦ༄ިਭඡሢ࢟ኹ WUIă࣪᎖ቖ 1 ဟᇺLjၫሣࡼ࢟ኹ Ᏼቖ 1 ࢅ࢟ຳဟମ u X1MNJO உၦ༄ܘኍۣߒࢅ᎖ඡሢ࢟ኹ WUIăᆐ೫ဣሚᔢభణࡼᄰቧLjၫሣ࢟ኹᏴᑳৈ uX1M u X2M ဟମࠊాด࣒ݙ።ިਭ W JMNBYăၫሣࡼ࢟ኹިਭ WUI ઁLjET39F12.211 Ᏼሆጙৈဟᇺ༄ኊገጙৈૂআဟମ uSFDă ࠭૦ࡵᓍ૦ ࣗၫဟᇺᏴఎဪဟᎧቖ 2 ဟᇺಢ႒ăၫሣ࢟ኹᏴࣗࢅ ࢟ຳဟମ uSM உၦ༄ܘኍۣߒࢅ᎖ WUMăᏴ uSM ࠊాLj።ࡊ 1 ဟLjET39F12.211 ఎဪ౯ࢅၫሣLjดࢾݝဟࢾੜ ဟஉၦሆ౯Lj݀༦࢟ຳᒮቤఎဪဍă።ࡊ2ဟLjET39F12. 211 ݀ߒۣݙၫሣࡼࢅ࢟ຳLju SM உၦઁLj࢟ຳ૾ఎဪ ဍă ᓍ૦ݧዹࠊా)uNTSNJO ࡵ uNTSNBY*ན᎖ uSM ,! δ )ဍဟ ମ*ਜ਼ ET39F12.211 ࡼดࢾݝဟLjᓍ૦ܘኍᏴݧዹࠊాด ᒊቲጙࠨၫሣࣗݷᔫăᆐဣሚᔢభణࡼᄰቧLjuSM ᏴᏤ पᆍด።Ljᓍ૦።কᏴதĂࡣݙᅵ᎖ uNTSNBY ဟࣗནၫă࠭ၫሣࣗནၫઁLjᓍ૦ܘኍࢀࡗᒇᒗ uTMPU உၦLjጲཀྵۣ ET39F12.211 Ᏼሆጙৈဟᇺᓰ۸ኙ༄ ᎌᔗ৫ࡼૂআဟମ uSFDăᒋࡻᓖፀࡼဵLjᑚಱᒎࢾࡼ uSFD ஞး᎖ 2.Xjsf ᔐሣᒑਂጙৈ ET39F12.211 ࡼ༽ౚă Ᏼࣶ࢛ᔐሣLjᆐ೫း። 2.Xjsf ୈࡼၒྜྷ࢟ྏLj። ዓޠuSFDăᅪLjથభဧET3593.y11ET3591Cࢀ2.Xjsf ᔐሣདࣅాୈLjᏴ2.XjsfૂআဟମดቲᎌᏎ౯ă ______________________________________________________________________________________ 29 ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN WRITE-ONE TIME SLOT tW1L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF tSLOT RESISTOR MASTER WRITE-ZERO TIME SLOT tW0L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF tREC tSLOT RESISTOR MASTER READ-DATA TIME SLOT tMSR tRL VPUP VIHMASTER VTH MASTER SAMPLING WINDOW VTL VILMAX 0V δ tF tREC tSLOT RESISTOR MASTER DS28E01-100 ᅄ23/! ࣗ0ቖဟኔᅄ 30 ______________________________________________________________________________________ ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ````````````````````````````` ည߅DSD൩ Ᏼ 2.Xjsf ᇹᄻᒦLjᒑᎌᏴᔐሣᓍ૦)2.Xjsf དࣅ*఼ᒜޘ ညࡼቧၾܤ໐ମᄋሣവ࣡ປLjፐࠥLj2.Xjsf ᆀ ੪ྏጵ၊ࡵᒬᐅဉᏎࡼ፬ሰăোᆀࡼᇕಯਖෝਜ਼ᅠ ແஉ৩Lj࢛࠭࣡ࡵॊᑽ࢛ࡼनభถ્Ᏼጙࢾ߈ࣞሤઑ ࢶଝࢎሿăᑚቋनቧᏴ 2.Xjsf ᄰቧሣവܭሚᆐඇ ࠦᑩഅă࠭ᅪݝছཷᏎẮࡵ 2.Xjsf ሣവࡼᐅဉጐถޘ ညቧඇࠦăဟᇺဍዘ߲ሚࡼඇࠦభถ્࠭ୈᎧ ᓍ૦ݙᄴݛLjஉਫᐆ߅ Tfbsdi! SPN ෘഎᇄLjࡴᒘ ୈᄂࢾࡼถෘഎᒦᒏăᆐᄋᆀቶถLjET39F12.211 ݧ೫ጙᒬቤቯ2.Xjsf༄࣡Ljଢ଼ࢅ೫࣪ᐅဉࡼැঢࣞă ET39F12.211 ᎌೝᒬݙᄴಢቯࡼDSD ൩Ljጙᒬᆐ9 ᆡLjᏴ ޣଐႯည߅݀ࡀᏴ 75 ᆡᓖݿ൩ࡼᔢᎌᔊஂăᔐሣᓍ ૦ถ৫ো 75 ᆡᓖݿ൩ࡼ༄ 67 ᆡଐႯ߲ক DSD ൩Lj݀Ꭷ ࠭ ET39F12.211 ࣗૄࡼၫᒋቲ୷܈Ljࣥᓖݿ൩ဵ॥ ၃ᇄᇙăଐႯক DSD ቅዩ൩ࡼࢀࣶሲါᆐǖY 9 ,! Y6 , Y5 ,! 2ă၃ࡵࡼ9ᆡDSDᆐᏇ൩)ݙནन*ተါă ጙᒬ DSD ൩ᆐ 27 ᆡLj࣪ࡀਜ਼TIB.2 ෘഎቲᇙ ൩ଶހăሮᇼቧᇦ༿ݬᅲᑳၫᓾ೯ă ET39F12.211 ࡼ 2.Xjsf ༄࣡Ꭷࠅᄻࡼ࠭૦ୈሤ܈ᎌྯৈ ݙᄴᄂቶă 2* Ᏼ࢟വᒦএଝ೫ጙৈࢅᄰ݆Ljଶހဟᇺఎဪဟࡼ ሆଢ଼ዘăᑚଢ଼ࢅ೫࣪ຫᐅဉࡼැঢࣞăႥෝါሆ ݙဧᑚጙএଝ݆ă 3* Ᏼࢅ࢟ຳࡵ࢟ຳࡼఎਈඡሢWUI ࠀᎌጙৈᒣૄLjྙ ਫᎌጙৈঌඇࠦࢅ᎖ WUI ࡣથᎌࢅ᎖ WUI .! WIZLj ۻ્ݙ၊)ᅄ 24 ᒦࡼာಿ B*LjᒣૄᏴྀੜ 2.Xjsf Ⴅࣞ ෝါሆᎌă 4* ᎅဍዘۣߒਈܕဟମ u SFI ࢾፃ೫ጙৈဟମࠊాLjᏴ ᑚৈࠊాด૾ဧඇࠦ࢟ኹࢅ᎖ඡሢ WUI .! WIZLj્྆ ۻ)ᅄ 24 ᒦࡼာಿ CLjuHM =! uSFI*ăࡍࡼኹଢ଼ࠃਭ WUI ඡሢઁ߲ሚࡼ݀༦ዓኚဟମި߲ uSFI ࠊాࡼඇࠦᐌ ᇄज߹Ljۻᓍ૦ᇙཱྀᆐቤဟᇺࡼఎဪ)ᅄ 24 ᒦࡼ ာಿDLjuHM ≥ uSFI*ă ᒑᎌᏴ࢟ᄂቶᒦ࣪ݬၫ WIZ ૺ uSFI ᄋࢾፃࡼ࠭ୈဧ ೫ᑚᒬখࡼ2.Xjsf༄࣡ă tREH tREH VPUP VTH VHY CASE A CASE B CASE C 0V tGL tGL ᅄ24/! ᐅဉጴᒜာፀᅄ ______________________________________________________________________________________ 31 ET39F12.211 ```````````````` খ࿖ᆀቶถ)༤ધ࢛ᒣૄ* ၫᓾ೯Ⴡቖ۾ ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN TOP VIEW TOP VIEW BOTTOM VIEW SIDE VIEW 1 2 IO GND + DS28E01-100 1 IO 2 N.C. 3 6 N.C. DS28E01-100 TSOC 5 N.C. 4 N.C. + N.C. 1 IO 2 GND 3 2801 ymrrF GND EP TDFN (3mm × 3mm) 6 N.C. 5 N.C. 4 N.C. SFN (6mm × 6mm × 0.9mm) NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE. ```````````````````````````````````````````````````````` TGOॖᓤᏴ௳ࡒ۞ᓤࡼऱሶ USER DIRECTION OF FEED LEADS FACE UP IN ORIENTATION SHOWN ABOVE. ```````````````````````````````````````````````````````````````````````````` ॖᓤቧᇦ ྙኊᔢதࡼॖᓤᅪተቧᇦਜ਼ݚLj༿އኯ china.maxim-ic.com/packagesă༿ᓖፀLjॖᓤܠ൩ᒦࡼĐ,đĂ Đ$đĐ.đஞܭာ SpITᓨზă ॖᓤᅄᒦభถ۞ݙᄴࡼᆘᓮᔊ९LjࡣॖᓤᅄᒑᎧॖᓤᎌਈLjᎧ SpIT ᓨზᇄਈă ॖᓤಢቯ ॖᓤܠ൩ ᅪተܠ ݚܠ 6 TSOC D6+1 21-0382 90-0321 2 SFN G266N+1 21-0390 — 6 TDFN-EP T633+2 21-0137 90-0058 ______________________________________________________________________________________ 35 ET39F12.211 ```````````````````````````````````````````````````````````````````````````` ୭ᒙ ၫᓾ೯Ⴡቖ۾ ET39F12.211 ࡒTIB.2༺ۣઐࡼ 2Lᆡ2.Xjsf! FFQSPN ```````````````````````````````````````````````````````````````````````````` ኀࢿ಼ဥ ኀࢿ ኀࢿ྇໐ ႁී ኀখ 0 4/07 ᔢ߱۾ۈă — 1 7/07 ᏴTGO ୭ᒙᒦLjᐐଝॖᓤᅄቧᇦ0ᆀೌLj݀ᐐଝྙሆᓖျǖTGO ॖᓤஞቲ೫࢟ .૦߿።ዩᑺLjᆚቲዩᑺăᐐଝ TGOॖᓤᏴ௳ࡒ۞ᓤࡼऱሶݝॊăᏴࢾ ৪ቧᇦᒦᐐଝᓖျǖVDTQॖᓤࡼૡᓨౚ༿ೊᇹޣă 16 2 3/08 ࿎߹VDTQॖᓤࡼሤਈดྏă 3 4 5 6/08 2/09 7/10 1, 16 ᏴTGO ୭ᒙᒦLjᐐଝݬఠ።܊ 5243ă 16 Ᏼࢾ৪ቧᇦᒦ࿎߹UTPDॖᓤࡼሤਈቧᇦLjᐐଝ UEGO ॖᓤă 1 ৎቤ୭ႁීᆐ۞Ⴥᎌॖᓤಢቯă 4 Ᏼ୭ᒙਜ਼ॖᓤቧᇦܭᒦᐐଝ UEGO ॖᓤă 16 ည߅ቤෝৃۇါࡼၫᓾ೯ă Ⴥᎌ ৎᑵ೫UTPD௳ࡒ۞ᓤࡼࢾ৪ୈቯ)࿎߹೫Đ'Sđ*ă 1 ৎቤ೫ᆨࣞă 2 ᐐଝ೫ॖᓤܠ൩ਜ਼ݚቧᇦă 35 Nbyjn ۱யࠀူێ ۱ய 9439ቧረ ᎆᑶܠ൩ 211194 ॅ࢟જǖ911!921!1421 ࢟જǖ121.7322 62:: ࠅᑞǖ121.7322 63:: Nbyjn࣪ݙNbyjnޘອጲᅪࡼྀੜ࢟വဧঌᐊLjጐݙᄋᓜಽభăNbyjnۣഔᏴྀੜဟମĂᎌྀੜᄰۨࡼ༄ᄋሆኀখޘອᓾ೯ਜ਼ਖৃࡼཚಽă 36 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Nbyjn ဵ Nbyjn!Joufhsbufe!Qspevdut-!Jod/ ࡼᓖݿܪă ABRIDGED DATA SHEET Rev 6; 2/12 1Kb Protected 1-Wire EEPROM with SHA-1 Engine The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations. All memory pages can be write protected, and one page can be put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. Each DS28E01-100 has its own guaranteed unique 64-bit ROM registration number that is factory lasered into the chip. The DS28E01100 communicates over the single-contact 1-Wire® bus. The communication follows the standard 1-Wire protocol with the registration number acting as the node address in the case of a multidevice 1-Wire network. Applications Printer Cartridge Configuration and Monitoring Medical Sensor Authentication and Calibration System Intellectual Property Protection Typical Operating Circuit Features ♦ 1024 Bits of EEPROM Memory Partitioned Into Four Pages of 256 Bits ♦ On-Chip 512-Bit SHA-1 Engine to Compute 160Bit Message Authentication Codes (MACs) and to Generate Secrets ♦ Write Access Requires Knowledge of the Secret and the Capability of Computing and Transmitting a 160-Bit MAC as Authorization ♦ User-Programmable Page Write Protection for Page 0, Page 3, or All Four Pages Together ♦ User-Programmable OTP EPROM Emulation Mode for Page 1 (“Write to 0”) ♦ Communicates to Host with a Single Digital Signal at 15.3kbps or 125kbps Using 1-Wire Protocol ♦ Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise ♦ Reads and Writes Over 2.8V to 5.25V Voltage Range from -40°C to +85°C ♦ 6-Lead TSOC and TDFN or 2-Lead TO-92 and SFN Packages VCC Ordering Information RPUP PART IO μC DS28E01-100 GND TEMP RANGE PIN-PACKAGE DS28E01-100+ -40°C to +85°C 2 TO-92 DS28E01P-100+ -40°C to +85°C 6 TSOC DS28E01P-100+T -40°C to +85°C 6 TSOC DS28E01G-100+T&R -40°C to +85°C 2 SFN DS28E01Q-100+T&R -40°C to +85°C 6 TDFN-EP* (2.5k pcs) +Denotes a lead(Pb)-free/RoHS-compliant package. T and T&R = Tape and reel. *EP = Exposed pad. Pin Configurations appear at end of data sheet. Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to www.maxim-ic.com/DS28E01 and click on Request Full Data Sheet. 1-Wire is a registered trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS28E01-100 General Description ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine ABSOLUTE MAXIMUM RATINGS Lead Temperature (TSOC, TO-92, TDFN only; soldering, 10s) ..............................................................+300°C Soldering Temperature (reflow) TSOC, TDFN .................................................................+260°C TO-92 ............................................................................+250°C SFN .......Refer to Application Note 4132: Attachment Methods for the Electro-Mechanical SFN Package. IO Voltage Range to GND .......................................-0.5V to +6V IO Sink Current ...................................................................20mA Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 2) 2.8 5.25 V 1-Wire Pullup Resistance RPUP (Notes 2, 3) 0.3 2.2 k Input Capacitance CIO 1000 pF Input Load Current IL IO pin at VPUP 0.05 6.7 μA High-to-Low Switching Threshold VTL (Notes 5, 6, 7) 0.46 VPUP 1.8 V Input Low Voltage VIL (Notes 2, 8) 0.5 V Low-to-High Switching Threshold VTH (Notes 5, 6, 9) 1.0 VPUP 1.1 V Switching Hysteresis VHY (Notes 5, 6, 10) 0.21 1.70 V Output Low Voltage VOL At 4mA current load (Note 11) 0.4 V Recovery Time (Notes 2,12) tREC Rising-Edge Hold-Off Time (Notes 5, 13) tREH Time Slot Duration (Notes 2, 14) t SLOT (Notes 4, 5) Standard speed, RPUP = 2.2k 5 Overdrive speed, RPUP = 2.2k 2 Overdrive speed, directly prior to reset pulse; RPUP = 2.2k 5 Standard speed Overdrive speed 0.5 μs 5.0 Not applicable (0) Standard speed 65 Overdrive speed 8 μs μs IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Reset Low Time (Note 2) tRSTL Presence-Detect High Time t PDH Presence-Detect Low Time t PDL Presence-Detect Sample Time (Notes 2, 15) tMSP 2 Standard speed 480 640 Overdrive speed 48 80 Standard speed 15 60 Overdrive speed 2 6 Standard speed 60 240 Overdrive speed 8 24 Standard speed 60 75 Overdrive speed 6 10 _______________________________________________________________________________________ μs μs μs μs ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine (TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: 1-Wire WRITE Write-Zero Low Time (Notes 2, 16, 17) Write-One Low Time (Notes 2, 17) tW0L tW1L Standard speed 60 120 Overdrive speed, VPUP > 4.5V 5 15.5 Overdrive speed 6 15.5 Standard speed 1 15 Overdrive speed 1 2 Standard speed 5 15 - Overdrive speed 1 2- Standard speed tRL + 15 Overdrive speed tRL + 2 μs μs IO PIN: 1-Wire READ Read Low Time (Notes 2, 18) tRL Read Sample Time (Notes 2, 18) tMSR μs μs EEPROM Programming Current I PROG (Notes 5, 19) 0.8 mA Programming Time t PROG (Note 20) 10 ms Write/Erase Cycles (Endurance) (Notes 21, 22) NCY Data Retention (Notes 23, 24, 25) tDR At +25°C 200k At +85°C (worst case) 50k At +85°C (worst case) 40 Years SHA-1 ENGINE Computation Current Computation Time (Notes 5, 26) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: ILCSHA tCSHA mA Refer to the full data sheet. ms Specifications at TA = -40°C are guaranteed by design only and not production tested. System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩ pullup resistor is used, the parasite capacitance does not affect normal communications 2.5µs after VPUP has been applied. Guaranteed by design, characterization, and/or simulation only. Not production tested. VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Voltage below which, during a falling edge on IO, a logic 0 is detected. The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level. Voltage above which, during a rising edge on IO, a logic 1 is detected. After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0. The I-V characteristic is linear for voltages less than 1V. Applies to a single device attached to a 1-Wire line. The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge. Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN. Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E01-100 present. Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN. Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table. _______________________________________________________________________________________ 3 DS28E01-100 ELECTRICAL CHARACTERISTICS (continued) ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine ELECTRICAL CHARACTERISTICS (continued) (TA = -40°C to +85°C.) (Note 1) Note 17: ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 18: δ in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Note 19: Current drawn from IO during the EEPROM programming interval or SHA-1 computation. Note 20: Refer to the full data sheet for this note. Write-cycle endurance is degraded as TA increases. Not 100% production tested; guaranteed by reliability monitor sampling. Data retention is degraded as TA increases. Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C. Note 26: Refer to the full data sheet for this note. Note 21: Note 22: Note 23: Note 24: COMPARISON TABLE LEGACY VALUES PARAMETER t SLOT (including tREC) tRSTL STANDARD SPEED (μs) DS28E01-100 VALUES OVERDRIVE SPEED (μs) STANDARD SPEED (μs) OVERDRIVE SPEED (μs) MIN MAX MIN MAX MIN MAX MIN MAX 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined) 480 (undefined) 48 80 480 640 48 80 t PDH 15 60 2 6 15 60 2 6 t PDL 60 240 8 24 60 240 8 24 tW0L 60 120 6 16 60 120 6 15.5 *Intentional change; longer recovery time requirement due to modified 1-Wire front-end. Note: Numbers in bold are not in compliance with legacy 1-Wire product standards. 4 _______________________________________________________________________________________ ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine PIN NAME TSOC TDFN-EP SFN TO-92 1 3 2 1 GND 2 2 1 3 IO 3, 4, 5, 6 1, 4, 5, 6 — 2 N.C. — — — — EP Detailed Description The DS28E01-100 combines 1024 bits of EEPROM organized as four 256-bit pages, a 64-bit secret, a register page, a 512-bit SHA-1 engine, and a 64-bit ROM registration number in a single chip. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return. The DS28E01100 has an additional memory area called the scratchpad that acts as a buffer when writing to the memory, the register page, or when installing a new secret. Data is first written to the scratchpad from where it can be read back. After the data has been verified, a Copy Scratchpad command transfers the data to its final memory location, provided that the DS28E01-100 receives a matching 160-bit MAC. The computation of the MAC involves the secret and additional data stored in the DS28E01-100 including the device’s registration number. Only a new secret can be loaded without providing a MAC. The SHA-1 engine is also activated to compute 160-bit MACs when performing an authenticated read of a memory page and when computing a new secret, instead of loading it. The DS28E01-100 understands a unique command “Refresh Scratchpad.” Proper use of a refresh sequence after a Copy Scratchpad operation reduces the number of weak bit failures if the device is used in a touch environment (see the Writing with Verification section). The refresh sequence also provides a means to restore functionality in a device with bits in a weak state. FUNCTION Ground Reference 1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor. Not Connected Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information. The device’s 64-bit ROM registration number guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each other. Applications of the DS28E01-100 include printer cartridge configuration and monitoring, medical sensor authentication and calibration, and system intellectual property protection. Overview The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS28E01-100. The DS28E01-100 has six main data components: 64-bit lasered ROM, 64-bit scratchpad, four 256-bit pages of EEPROM, register page, 64-bit secrets memory, and a 512-bit SHA-1 engine. Figure 2 shows the hierarchic structure of the 1-Wire protocol. The bus master must first provide one of the seven ROM function commands: Read ROM, Match ROM, Search ROM, Skip ROM, Resume Communication, OverdriveSkip ROM, or Overdrive-Match ROM. Upon completion of an Overdrive-Skip ROM or Overdrive-Match ROM command executed at standard speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the memory and SHA-1 functions become accessible and the master can provide any one of the 9 available function commands. The function protocols are described in Figure 8. All data is read and written least significant bit first. _______________________________________________________________________________________ 5 DS28E01-100 Pin Description ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine PARASITE POWER 1-Wire NET DS28E01-100 1-Wire FUNCTION CONTROL 64-BIT LASERED ROM MEMORY AND SHA-1 FUNCTION CONTROL UNIT 512-BIT SECURE HASH ALGORITHM ENGINE CRC-16 GENERATOR 64-BIT SCRATCHPAD DATA MEMORY 4 PAGES OF 256 BITS EACH REGISTER PAGE SECRETS MEMORY 64 BITS Figure 1. Block Diagram 64-Bit Lasered ROM Each DS28E01-100 contains a unique ROM registration number that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits. See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton® Products. The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the CRC returns the shift register to all 0s. Memory Access The DS28E01-100 has four memory areas: data memory, secrets memory, register page with special function registers and user bytes, and a volatile scratchpad. The data memory is organized as four pages of 32 bytes. Secret and scratchpad are 8 bytes each. The scratchpad acts as a buffer when writing to the data memory, loading the initial secret, or when writing to the register page. Refer to the full data sheet for this information. iButton is a registered trademark of Maxim Integrated Products, Inc. 6 _______________________________________________________________________________________ ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine DS28E01-100 DS28E01-100 COMMAND LEVEL: 1-Wire ROM FUNCTION COMMANDS (SEE FIGURE 10) AVAILABLE COMMANDS: DATA FIELD AFFECTED: READ ROM MATCH ROM SEARCH ROM SKIP ROM RESUME OVERDRIVE-SKIP ROM OVERDRIVE-MATCH ROM 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG 64-BIT REG. #, RC-FLAG RC-FLAG RC-FLAG RC-FLAG, OD-FLAG 64-BIT REG. #, RC-FLAG, OD-FLAG DEVICE-SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 8) Refer to the full data sheet. Figure 2. Hierarchic Structure for 1-Wire Protocol MSB LSB 8-BIT CRC CODE MSB 8-BIT FAMILY CODE 48-BIT SERIAL NUMBER LSB MSB LSB MSB LSB Figure 3. 64-Bit Lasered ROM POLYNOMIAL = X8 + X5 + X4 + 1 1ST STAGE X0 2ND STAGE X1 3RD STAGE X2 4TH STAGE X3 5TH STAGE X4 6TH STAGE X5 7TH STAGE X6 8TH STAGE X7 X8 INPUT DATA Figure 4. 1-Wire CRC Generator _______________________________________________________________________________________ 7 ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine DS28E01-100 Refer to the full data sheet. Figure 6. Memory Protection Matrix BIT # 7 6 5 4 3 2 1 0 TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 (0) T1 (0) T0 (0) TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8 ENDING ADDRESS WITH DATA STATUS (E/S) (READ ONLY) AA 1 PF 1 1 E2 (1) E1 (1) E0 (1) Figure 7. Address Registers Address Registers and Transfer Status The DS28E01-100 employs three address registers: TA1, TA2, and E/S (Figure 7). These registers are common to many other 1-Wire devices, but operate slightly differently with the DS28E01-100. Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only transfer-status register used to verify data integrity with write commands. Since the scratchpad of the DS28E01-100 is designed to accept data in blocks of 8 bytes only, the lower 3 bits of TA1 are forced to 0 and the lower 3 bits of the E/S register (ending offset) always read 1. This indicates that all the data in the scratchpad is used for a subsequent copying into main memory or secret. Bit 5 of the E/S register, called PF or partial byte flag, is a logic 1 if the number of data bits sent by the master is not an integer multiple of eight or if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad clears the PF bit. Bits 3, 4, and 6 have no function; they always read 1. The partial flag supports the master checking the data integrity after a write command. The highest _______________________________________________________________________________________ 9 ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine valued bit of the E/S register, called authorization accepted (AA), acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag. data, it can send the Copy Scratchpad to copy the scratchpad to memory. Alternatively, the Load First Secret or Compute Next Secret command can be issued to change the secret. See the descriptions of these commands for more information. Writing with Verification To write data to the DS28E01-100, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command, which specifies the desired target address and the data to be written to the scratchpad. Note that writes to data memory must be performed on 8-byte boundaries with the three LSBs of the target address T[2:0] equal to 000b. Therefore, if T[2:0] are sent with nonzero values, the device sets these bits to 0 and uses the modified address as the target address. The master should always send eight complete data bytes. After the 8 bytes of data have been transmitted, the master can elect to receive an inverted CRC-16 of the Write Scratchpad command, the address as sent by the master, and the data as sent by the master. The master can compare the CRC to the value it has calculated itself to determine if the communication was successful. After the scratchpad has been written, the master should always perform a Read Scratchpad to verify that the intended data was in fact written. During a Read Scratchpad, the DS28E01-100 repeats the target address TA1 and TA2 and sends the contents of the E/S register. The partial flag (bit 5 of the E/S register) is set to 1 if the last data byte the DS28E01-100 received during a Write Scratchpad or Refresh Scratchpad command was incomplete, or if there was a loss of power since data was last written to the scratchpad. The authorization-accepted (AA) flag (bit 7 of the E/S register) is normally cleared by a Write Scratchpad or Refresh Scratchpad; therefore, if it is set to 1, it indicates that the DS28E01-100 did not understand the proceeding Write (or Refresh) Scratchpad command. In either of these cases, the master should rewrite the scratchpad. After the master receives the E/S register, the scratchpad data is received. The descriptions of Write Scratchpad and Refresh Scratchpad provide clarification of what changes can occur to the scratchpad data under certain conditions. An inverted CRC of the Read Scratchpad command, target address, E/S register, and scratchpad data follows the scratchpad data. As with the Write Scratchpad command, this CRC can be compared to the value the master has calculated to determine if the communication was successful. After the master has verified the 10 Refer to the full data sheet for this information. ______________________________________________________________________________________ ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine DS28E01-100 Memory and SHA-1 Function Commands This section describes the commands and flowcharts needed to use the memory and SHA-1 engine of the device. Refer to the full data sheet for more information. ______________________________________________________________________________________ 11 ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine DS28E01-100 SHA-1 Computation Algorithm This description of the SHA-1 computation is adapted from the Secure Hash Standard SHA-1 document from the National Institute of Standards and Technology (NIST). Refer to the full data sheet for more information. bit ______________________________________________________________________________________ 23 ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine 1-Wire Bus System The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28E01100 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. Hardware Configuration The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or three-state outputs. The 1-Wire port of the DS28E01100 is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS28E01-100 supports both a standard and overdrive communication speed of 15.3kbps (max) and 125kbps (max), respectively. Note VPUP BUS MASTER DS28E01-100 1-Wire PORT RPUP DATA Rx Tx Rx = RECEIVE Tx = TRANSMIT OPEN-DRAIN PORT PIN Rx IL Tx 100Ω MOSFET Figure 9. Hardware Configuration 24 ______________________________________________________________________________________ ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine Transaction Sequence The protocol for accessing the DS28E01-100 through the 1-Wire port is as follows: • Initialization • ROM Function Command • Memory/SHA-1 Function Command • Transaction/Data Initialization All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS28E01-100 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function Commands Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the DS28E01-100 supports. All ROM function commands are 8 bits long. A list of these commands follows (see the flowchart in Figure 10). Read ROM [33h] The Read ROM command allows the bus master to read the DS28E01-100’s 8-bit family code, unique 48bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data colli- sion occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. Match ROM [55h] The Match ROM command, followed by a 64-bit device registration number, allows the bus master to address a specific DS28E01-100 on a multidrop bus. Only the DS28E01-100 that exactly matches the 64-bit registration number responds to the subsequent memory or SHA-1 function command. All other slaves wait for a reset pulse. This command can be used with a single device or multiple devices on the bus. Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the search tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit registration number. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). ______________________________________________________________________________________ 25 DS28E01-100 that legacy 1-Wire products support a standard communication speed of 16.3kbps and overdrive of 142kbps. The slightly reduced rates for the DS28E01100 are a result of additional recovery times, which in turn were driven by a 1-Wire physical interface enhancement to improve noise immunity. The value of the pullup resistor primarily depends on the network size and load conditions. The DS28E01-100 requires a pullup resistor of 2.2kΩ (max) at any speed. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs (overdrive speed) or more than 120µs (standard speed), one or more devices on the bus could be reset. ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine BUS MASTER Tx RESET PULSE FROM FIGURE 10b FROM MEMORY AND SHA-1 FUNCTION FLOWCHART (FIGURE 8) OD RESET PULSE? N OD = 0 Y BUS MASTER Tx ROM FUNCTION COMMAND 33h READ ROM COMMAND? DS28E01-100 Tx PRESENCE PULSE N 55h MATCH ROM COMMAND? F0h SEARCH ROM COMMAND? N N CCh SKIP ROM COMMAND? Y Y Y Y RC = 0 RC = 0 RC = 0 RC = 0 DS28E01-100 Tx FAMILY CODE (1 BYTE) MASTER Tx BIT 0 TO FIGURE 10b DS28E01-100 Tx BIT 0 DS28E01-100 Tx BIT 0 MASTER Tx BIT 0 BIT 0 MATCH? N N BIT 0 MATCH? Y Y DS28E01-100 Tx SERIAL NUMBER (6 BYTES) N DS28E01-100 Tx BIT 1 MASTER Tx BIT 1 DS28E01-100 Tx BIT 1 MASTER Tx BIT 1 BIT 1 MATCH? N N BIT 1 MATCH? Y Y DS28E01-100 Tx BIT 63 DS28E01-100 Tx CRC BYTE MASTER Tx BIT 63 DS28E01-1001 Tx BIT 63 MASTER Tx BIT 63 BIT 63 MATCH? N N BIT 63 MATCH? Y Y RC = 1 RC = 1 TO FIGURE 10b FROM FIGURE 10b TO MEMORY AND SHA-1 FUNCTION FLOWCHART (FIGURE 8) Figure 10a. ROM Functions Flowchart 26 ______________________________________________________________________________________ ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine DS28E01-100 TO FIGURE 10a FROM FIGURE 10a A5h RESUME COMMAND? 3Ch OVERDRIVESKIP ROM? N N Y Y N Y RC = 0; OD = 1 RC = 1? 69h OVERDRIVEMATCH ROM? RC = 0; OD = 1 N Y MASTER Tx BIT 0 MASTER Tx RESET? N Y BIT 0 MATCH? N Y MASTER Tx BIT 1 MASTER Tx RESET? N Y BIT 1 MATCH? N Y MASTER Tx BIT 63 BIT 63 MATCH? N Y FROM FIGURE 10a RC = 1 TO FIGURE 10a Figure 10b. ROM Functions Flowchart (continued) ______________________________________________________________________________________ 27 ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine Resume [A5h] To maximize the data throughput in a multidrop environment, the Resume command is available. This command checks the status of the RC bit and, if it is set, directly transfers control to the memory and SHA-1 function commands, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive-Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume command. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume command. Overdrive-Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit registration number. Unlike the normal Skip ROM command, the OverdriveSkip ROM command sets the DS28E01-100 into the overdrive mode (OD = 1). All communication following this command must occur at overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting overdrive is present on the bus and the Overdrive-Skip ROM command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wiredAND result). Overdrive-Match ROM [69h] The Overdrive-Match ROM command followed by a 64bit registration number transmitted at overdrive speed allows the bus master to address a specific DS28E01100 on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS28E01-100 that exactly matches the 64-bit number responds to the subsequent memory or SHA-1 function command. Slaves already in overdrive mode from a previous Overdrive-Skip ROM or successful Overdrive-Match ROM command remain in overdrive mode. All overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480µs duration. The Overdrive-Match ROM command can be used with a single device or multiple devices on the bus. 28 1-Wire Signaling The DS28E01-100 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and readdata. Except for the presence pulse, the bus master initiates all falling edges. The DS28E01-100 can communicate at two different speeds: standard speed and overdrive speed. If not explicitly set into the overdrive mode, the DS28E01-100 communicates at standard speed. While in overdrive mode, the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes for the voltage to make this rise is seen in Figure 11 as ε, and its duration depends on the pullup resistor (RPUP) used and the capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the DS28E01-100 when determining a logical level, not triggering any events. Figure 11 shows the initialization sequence required to begin any communication with the DS28E01-100. A reset pulse followed by a presence pulse indicates that the DS28E01-100 is ready to receive data, given the correct ROM and memory and SHA-1 function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. A tRSTL duration of 480µs or longer exits the overdrive mode, returning the device to standard speed. If the DS28E01-100 is in overdrive mode and t RSTL is no longer than 80µs, the device remains in overdrive mode. If the device is in overdrive mode and tRSTL is between 80µs and 480µs, the device resets, but the communication speed is undetermined. After the bus master has released the line it goes into receive mode. Now the 1-Wire bus is pulled to VPUP through the pullup resistor or, in the case of a DS2482x00 or DS2480B driver, through active circuitry. When the threshold VTH is crossed, the DS28E01-100 waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP. The tRSTH window must be at least the sum of tPDHMAX, t PDLMAX , and t RECMIN . Immediately after t RSTH is expired, the DS28E01-100 is ready for data communication. In a mixed population network, tRSTH should be extended to minimum 480µs at standard speed and ______________________________________________________________________________________ ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine DS28E01-100 MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE" ε tMSP VPUP VIHMASTER VTH VTL VILMAX 0V tRSTL tPDH tF tPDL tREC tRSTH RESISTOR MASTER DS28E01-100 Figure 11. Initialization Procedure: Reset and Presence Pulse 48µs at overdrive speed to accommodate other 1-Wire devices. Read/Write Time Slots Data communication with the DS28E01-100 takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. Figure 12 illustrates the definitions of the write and read time slots. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold VTL, the DS28E01-100 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the VTH threshold before the writeone low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH threshold has been crossed, the DS28E01-100 needs a recovery time tREC before it is ready for the next time slot. Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the DS28E01-100 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS28E01-100 does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS28E01-100 on the other side define the master sampling window (tMSRMIN to tMSRMAX), in which the master must perform a read from the data line. For the most reliable communication, tRL should be as short as permissible, and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS28E01-100 to get ready for the next time slot. Note that tREC specified herein applies only to a single DS28E01-100 attached to a 1-Wire line. For multidevice configurations, tREC must be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire drivers can be used. ______________________________________________________________________________________ 29 ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine WRITE-ONE TIME SLOT tW1L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF tSLOT RESISTOR MASTER WRITE-ZERO TIME SLOT tW0L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF tREC tSLOT RESISTOR MASTER READ-DATA TIME SLOT tMSR tRL VPUP VIHMASTER VTH MASTER SAMPLING WINDOW VTL VILMAX 0V δ tF tREC tSLOT RESISTOR MASTER DS28E01-100 Figure 12. Read/Write Timing Diagrams 30 ______________________________________________________________________________________ ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a Search ROM command coming to a dead end or cause a device-specific function command to abort. For better performance in network applications, the DS28E01-100 uses a new 1-Wire frontend, which makes it less sensitive to noise. The DS28E01-100’s 1-Wire front-end differs from traditional slave devices in three characteristics. 1) There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at overdrive speed. 2) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but does not go below VTH - VHY, it is not recognized (Figure 13, Case A). The hysteresis is effective at any 1-Wire speed. 3) There is a time window specified by the rising edge hold-off time tREH during which glitches are ignored, even if they extend below the VTH - VHY threshold tREH (Figure 13, Case B, tGL < tREH). Deep voltage droops or glitches that appear late after crossing the VTH threshold and extend beyond the tREH window cannot be filtered out and are taken as the beginning of a new time slot (Figure 13, Case C, tGL ≥ tREH). Devices that have the parameters VHY and tREH specified in their electrical characteristics use the improved 1-Wire front-end. CRC Generation The DS28E01-100 uses two different types of CRCs. One CRC is an 8-bit type that is computed at the factory and is stored in the most significant byte of the 64-bit registration number. The bus master can compute a CRC value from the first 56 bits of the 64-bit registration number and compare it to the value read from the DS28E01-100 to determine if the registration number has been received error-free. The equivalent polynomial function of this CRC is X8 + X5 + X4 + 1. This 8-bit CRC is received in the true (noninverted) form. The other CRC is a 16-bit type, which is used for error detection with memory and SHA-1 commands. For details, refer to the full data sheet. tREH VPUP VTH VHY CASE A CASE B CASE C 0V tGL tGL Figure 13. Noise Suppression Scheme ______________________________________________________________________________________ 31 DS28E01-100 Improved Network Behavior (Switchpoint Hysteresis) ABRIDGED DATA SHEET 1Kb Protected 1-Wire EEPROM with SHA-1 Engine TOP VIEW TOP VIEW BOTTOM VIEW SIDE VIEW 1 2 IO GND + GND 2 N.C. 3 DS28E01-100 5 N.C. 4 N.C. + TSOC N.C. 1 IO 2 GND 3 2801 ymrrF IO DS28E01-100 6 N.C. 1 EP TDFN (3mm x 3mm) SIDE VIEW 6 N.C. 5 N.C. 4 N.C. SFN (6mm x 6mm x 0.9mm) NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE. FRONT VIEW GND 1 N.C. 2 IO 3 1 2 3 TO-92 SFN Package Orientation on Tape and Reel USER DIRECTION OF FEED LEADS FACE UP IN ORIENTATION SHOWN ABOVE. Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 6 TSOC D6+1 21-0382 90-0321 2 SFN G266N+1 21-0390 — 6 TDFN-EP T633+2 21-0137 90-0058 2 TO-92 Q2+1 21-0249 — ______________________________________________________________________________________ 35 DS28E01-100 Pin Configurations ABRIDGED DATA SHEET DS28E01-100 1Kb Protected 1-Wire EEPROM with SHA-1 Engine Revision History REVISION NUMBER REVISION DATE 0 4/07 Initial release — 1 7/07 In the SFN Pin Configuration, added the package drawing information/weblink and a note that the SFN package is qualified for electro-mechanical contact applications only, not for soldering. Added the SFN Package Orientation on Tape-and-Reel section. In the Ordering Information, added note to contact factory for availability of the UCSP package 16 2 3/08 DESCRIPTION Removed references to the UCSP package 3 4 5 6 6/08 2/09 7/10 2/12 PAGES CHANGED 1, 16 In the SFN Pin Configuration, added reference to Application Note 4132 16 In the Ordering Information, removed the leaded TSOC packages and added the TDFN package 1 Updated the Pin Description to include all package variants 4 Added the TDFN package to Pin Configurations and Package Information table 16 Created newer template-style data sheet All Corrected TSOC tape-and-reel ordering part number (deleted “&R”) 1 Updated soldering temperatures 2 Added package codes and land pattern information 35 Added the 2-pin TO-92 package to the Features, Ordering Information, Absolute Maximum Ratings, Pin Description, Pin Configurations, and Package Information. 1, 2, 5, 35 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.