MITSUBISHI<Dig.Ana.INTERFACE> M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M62370GP is a CMOS semiconductor IC,containing 36 channels of 8-bit D-A converters.It is operable with a low supply voltage between 2.7~3.6V,and is easy to use due to serial data input,and 3-pin(DI,CLK,LD)connection with microcomputer.The IC also contains Do pin terminal,enabling cascade connection,and therefore is suitable for automatic control in combination with a microcomputer. Ao35 Ao34 Ao33 Ao32 Vss2 VDD2 C1 Vcc Ao31 Ao30 Ao29 Ao28 DI CLK LD Do GND C0 Vss1 VDD1 Ao12 Ao13 Ao14 Ao15 FEATURES •Operable with a low voltage between 2.7~3.6V •16-bit serial data input(connected via 3 pins:DI,CLK,LD) •36 channels built-in of 8-bit D-A converter •6 channels of D-A converters capable of selecting and outputting 4 data stored in each converter,through 2 control terminals APPLICATION Digital-analog conversion in industrial or home-use electronic equipment. Automatic control in combination with EEPROM and microcomputer(Substitute for conventional semi-fixed resistor) Outline 48P6D-A BLOCK DIAGRAM CLK 2 DI 1 VCC GND 29 5 16-BIT SHIFT REGISTER 8 DECODER 8-BIT LATCH X 4 8-BIT LATCH X 4 8-BIT LATCH X 4 DATA CONTROL VDD1 8 Vss1 Do 3 LD 6 Co D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 8-BIT LATCH 4 D-A D-A D-A D-A - - - - 30 C1 7 38 21 36 37 Ao1 Ao24 Ao35 Ao36 MITSUBISHI ELECTRIC 31 32 VDD2 Vss2 ( 1 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS Pin No. 1 4 2 Function Serial data input terminal to input 16-bit long ssrial data Terminal to output MSB data of 16-bit shift register Symbol DI Do Shift clock input terminal.Input signal at DI pin is input to 16-bit shift register at rise of shift clock pulse CLK When H-level signal is input to this terminal,the value stored in 16-bit shift register is loaded in decoder and D-A converter output register 3 LD 38 Ao1 48 9 Ao11 Ao12 28 33 Ao31 Ao32 37 Ao36 29 VCC GND Power supply terminal C0 C1 Data sslect signal input terminal 1 for channel No.31 through 36 8 7 VDD1 Upper reference voltage input terminal and power supply to operational amplifier for channel No.1 through 24 VSS1 Lower reference voltage input terminal for channel No.1 through 24 31 VDD2 VSS2 Upper reference voltage input terminal and power supply to operational amplifier for channel No.25 through 36 5 6 30 32 8-bit D-A converter output terminal GND terminal Data select signal input terminal 2 for channel No.31 through 36 Lower reference voltage input terminal for channel No.25 through 36 BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS Vcc GND 29 5 CLK 2 16-BIT SHIFT REGISTER DI 1 D15 D14 D13 D12 D11 D10 D9 D8 D6 D7 Do 3 LD 6 C0 D5 D4 D3 D2 D1 D0 ADDRESS DECODER (8) 4 1 2 3 4 (4) 1 ............ ............ 8-BIT LATCH 8-BIT LATCH 30 (4) ............ (4) 8-BIT LATCH X 4 SEL ............ 8-BIT LATCH X 4 SEL DATA CONTROL 36 31 VDD1 8 8-BIT D-A CONVERTER DAC DAC 8-BIT D-A CONVERTER Vss1 7 - - - - 30 C1 38 27 28 37 31 32 Ao1 Ao30 Ao31 Ao36 VDD2 Vss2 MITSUBISHI ELECTRIC ( 2 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS DIGITAL DATA FORMAT FIRST LSB LAST MSB DAC DATA DAC SELECT DATA D8 0 D9 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 D5 D4 0 D3 0 0 0 0 0 0 0 D10 D11 D12 D14 D13 (VrefU-VrefL) / 256 X 1 +VrefL (VrefU-VrefL) / 256 X 2 +VrefL 0 0 0 0 0 0 0 0 0 0 0 (VrefU-VrefL) / 256 X 3 +VrefL 0 0 (VrefU-VrefL) / 256 X 4 +VrefL 1 1 1 (VrefU-VrefL) / 256 X 255 +VrefL 1 1 1 1 D2 D1 D0 0 0 0 Don‘t care 0 0 0 1 0 0 1 0 VrefU DAC selection Ao31 through Ao36 data selected C0 C1 Ao1 selection 0 0 Ao2 selection 0 1 Address 1 selected 1 0 Address 2 selected 1 1 Address 3 selected 1 1 0 1 1 1 0 Ao30 selection 1 0 1 0 1 0 1 0 Ao31(0) selection Ao32(0) selection 1 1 0 0 1 0 0 Ao36(0) selection 0 0 1 0 1 Ao31(1) selection 1 0 1 0 1 0 Ao36(1) selection 1 0 1 0 1 1 Ao31(2) selection 1 1 1 1 0 0 0 0 Ao36(2) selection 0 0 0 1 Ao31(3) selection 1 1 1 0 1 1 0 Ao36(3) selection 1 0 1 1 1 Don‘t care 1 1 1 1 1 1 Don‘t care 0 1 D-A output D15 0 Address 0 selected * VrefU=VDD1,VDD2 VrefL=Vss1,Vss2 TIMING CHART (MODEL) LSB DI D0 MSB D1 D2 D3 D13 D14 D15 CLK LD D-A OUTPUT MITSUBISHI ELECTRIC ( 3 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXIMUM RATINGS(Ta=25°C,unless otherwise noted) Symbol Vcc Vo Conditions Parameter Supply voltage Pd Output voltage Power dissipation K Topr Tstg Terminal derating Operating temperature Storage temperature Ratings Unit -0.3~+7.0 -0.3~Vcc+0.3 V V mW mW/°C °C 400 4 -20~+85 -40~+125 Ta≤25°C °C ELECTRICAL CHARACTERISTICS Digital part(VCC=+3V±10%, VCC=VDD,Ta=-20 ~ +85°C,unless otherwise noted) Symbol VCC Supply voltage Icc Circuit current Input leak current IILK VIL Test conditions Parameter Min. 2.7 CLK=1MHz operation,Vcc=3V,IAO=0µA Limits Typ. Max. 3.0 5.5 VIH VOL Output low voltage IOL=2.5mA VOH Output high voltage IOH=-400µA V mA 1.0 -10 Input low voltage Input high voltage Unit 10 µA 0.6 V 2.4 V 0.4 V V VCC-0.4 Note.Standard value is at Ta=25°C Analog part(VCC=+3V±10%, VCC=VDD,Ta=-20 ~ +85°C,unless otherwise noted) Symbol IDD VDD Vss VAO IAO SDL SL SZERO SFULL Co Ro Parameter Test conditions Min. Current dissipation Limits Typ. Max. mA 5.0 D-A converter upper reference voltage range D-A converter lower reference voltage range 2.7 IAO=±100µA Buffer amplifier output voltage range IAO=+300µA -200µA Upper saturation voltage=0.4V Buffer amplifier output driving Lower saturation voltage=0.3V range Differential nonlinearity error Vcc=2.700V Nonlinearity error VDD=2.700V Zero code error Vss=0.050V No load(IAO=±0) Full scale error 3.0 Unit 5.5 V GND VDD-2 V 0.1 VDD-0.1 0.2 VDD-0.2 -300 500 µA -1.0 -1.5 -2 -2 1.0 1.5 2 2 LSB LSB LSB LSB 0.1 µF Output capacitative load V Ω 50 Buffer amplifier output impedance MITSUBISHI ELECTRIC ( 4 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62370GP 3V TYPE 8-BIT 36CH SELECTOR SW BUILT-IN D-A CONVERTER WITH BUFFER AMPLIFIERS AC CHARACTERISTICS(VCC=VDD,Ta=-20 ~ +85°C,unless otherwise noted) Parameter Symbol tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDo tLDD Test conditions Min 200 200 Clock "L"pulse width Clock "H"pulse width Clock rise time Clock fall time Data set up time Data hold time Limits Typ Max Unit 200 ns ns ns ns ns ns ns 100 100 ns ns 200 200 30 60 LD set up time LD hold time LD "H" pulse duration Data output delay time CL=100pF 70 CL≤100pF,VAO:0.3 2.7V The time until the output becomes the final value of ±2 LSB D-A converter output setting time 350 ns 100 µs TIMING CHART tCKH tCR tCF CLK tCKL DI tDCH tLDC tCHD tLDH tCHL LD tLDD D-A OUTPUT tDo Do OUTPUT MITSUBISHI ELECTRIC ( 5 / 5 )