MITSUBISHI<Dig.Ana.INTERFACE> M62399P,FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M62399P,FP is an integrated circuit semiconductor of high voltage type CMOS structure with 8 channels of built-in DA converters with output buffer operational amplifiers. The input is 2-wires serial method is used for the transfer formal of digital data to allow connection with a microcomputer with minimum wiring. The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of 2.5mA or more,and it operates in the whole voltage range from VrefU to ground. And because of connects maximum 8 pieces,it is possible to 64 channels control. FEATURES •Digital data transfer format I 2C-bus serial data method •Output buffer operational amplifier it operates in the whole voltage range from VrefU(0~12V)to ground. •High output current drive capacity ±2.5mA over •Preparation two high level reference voltage terminal because there are two high level reference voltage terminal,it can set up two kinds differ voltage range. R 1 20 CS0 SCL 2 19 CS1 SDA 3 18 CS2 Ao5 4 17 VDD Ao6 5 16 Vcc Ao7 6 15 Ao4 Ao8 7 14 Ao3 VrefL 8 13 Ao2 VrefU1 9 12 Ao1 GND 10 11 VrefU2 Outline 20P4(P) 20P2N-A(FP) APPLICATION Conversion from digital control data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of DISPLAYMONITOR or CTV. BLOCK DIAGRAM CS0 CS1 CS2 VDD 20 19 18 17 Ao4 15 Ao3 Ao2 Ao1 14 13 12 Vcc VrefU2 16 R2 R2 R2 R2 R1 R1 R1 R1 CHIP SELECT 8bit upper segment R-2R 8bit Latch 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit Latch 8bit Latch 8bit Latch R2 =2.4 R1 8 1 2 3 8 R SCL SDA VrefL 11 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R 8bit upper segment R-2R R1 R1 R1 R1 R2 R2 R2 R2 4 5 6 7 Ao5 Ao6 Ao7 Ao8 MITSUBISHI ELECTRIC 10 9 GND VrefU1 ( 1 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62399P,FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS Pin No. 3 1 2 12 Symbol SDA 13 Ao2 14 Ao3 15 Ao4 4 5 6 7 16 17 10 Ao5 Ao6 8 9 11 VrefU1 VrefU2 18 19 CS2 CS1 20 CS0 R SCL Ao1 Function Serial data input terminal Reset signal input terminal Serial clock input terminal 8-bit D-A converter output terminal Ao7 Ao8 VCC Analog power supply terminal VDD Digital power supply terminal GND Analog and digital common GND VrefL D-A converter low level reference voltage input terminal D-A converter high level reference voltage input terminal 1 D-A converter high level reference voltage input terminal 2 Chip select data input terminal 2 Chip select data input terminal 1 Chip select data input terminal 0 MITSUBISHI ELECTRIC ( 2 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62399P,FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXIMUM RATINGS Symbol VCC VDD VrefU1,2 VIND Conditions Parameter Supply voltage Supply voltage D-A converter upper reference voltage Digital input voltage Ratings -0.3~+13.5 Unit V -0.3~+7.0 VDD -0.3~VDD+0.3 V V V Topr Operating temperature -20~+85 °C Tstg Storage temperature -40~+125 °C ELECTRICAL CHARACTERISTICS Digital part(Vcc=13V,VDD=VrefU1,2=+5V±10%,GND=VrefL=0V,Ta=-20 ~ +85°C,unless otherwise noted) Symbol VDD Test conditions Parameter Supply voltage 4.5 IDD Supply current CLK=1MHz operation IAO=0µA IILK Input leak current VIN=0~VDD VIL Input low voltage Input high voltage VIH Min. Limits Typ. Max. 5.0 5.5 V 1 mA 10 µA 0.2VCC V -10 Unit V 0.8VCC Analog part(Vcc=13V,VDD=VrefU1,2=+5V±10%,GND=VrefL=0V,Ta=-20 ~ +85°C,unless otherwise noted) Symbol Test conditions Parameter Min. Limits Typ. Max. Vcc Supply voltage Icc Circuit current CLK=1MHz operation IAO=0µA 2.0 13 4.0 IrefU D-A converter upper reference voltage input current VrefU=5V VrefL=0V Data condition:at maximum current 1.2 2.5 VrefU D-A converter upper reference voltage range VrefL D-A converter lower reference voltage range VAO IAO SDL SL SZERO SFULL Eo SR VDD Unit V mA mA The output does not necessarily be the values within the reference voltage setting range. 3.5 VDD V GND 1.5 V Buffer amplifier output voltage range IAO=±500µA IAO=±1.0mA 0.1 0.2 Vcc-0.1 Vcc-0.2 V Buffer amplifier output drive range Upper side saturation voltage=0.3V Lower side saturation voltage=0.2V -2.5 2.5 mA Differential nonlinearity error Nonlinearity error Zero code error Full scale error Gain error Output slew rate VrefU=4.79V VrefL=0.95V Vcc=5.5V(15mV/LSB) without load(IAO=0) -1.0 -1.5 -2.0 -2.0 -3.0 1.0 1.5 2.0 2.0 3.0 LSB LSB LSB LSB % V/µs 0.2 MITSUBISHI ELECTRIC ( 3 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62399P,FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS I 2 C-BUS LINE CHARACTERISTICS Parameter Symbol SCL clock frequency fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT Time the bus must be free before a new transmission can start Hold time start condition.After this period.The first clock pulse is generated The low period of the clock The high period of the clock Set up time for start condition(only relevant for a repeated start condition) Hold time data Normal mode Min Max 0 100 4.7 4.0 High speed mode 4.7 4.0 4.7 0 tSU:DAT tR tF Set up time data Rise time of both SDA and SCL lines tSU:STO Set up time for stop condition 250 1000 Fall time of both SDA and SCL lines 300 4.0 Min 0 1.3 0.6 1.3 0.6 4.7 Max 400 0 100 20 20 0.6 0.9 Unit KHz µs µs µs µs µs µs ns ns ns 300 300 µs *Note that transmitter must internally at reset a hold time to bridge the undefined region(max.300ns)of the falling edge of SCL. TIMING CHART tR, tF tBUF VIL SDA VIH tHD:STA tSU:DAT tHD:DAT tSU:STA tSU:STO VIL SCL VIH tLOW S tHIGH S MITSUBISHI ELECTRIC P S ( 4 / 5 ) MITSUBISHI<Dig.Ana.INTERFACE> M62399P,FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS I2C BUS FORMAT STA SLAVE ADDRESS W A SUB ADDRESS A DAC DATA A STP DIGITAL DATA FORMAT •SLAVE ADDRESS FIRST 0 1 0 1 (SLAVE ADDRESS) A2 A1 D6 X A0 D5 D4 D3 D2 X S3 S2 S1 S0 CHANNEL SELECT DATA D1 D0 (2)CHANNEL SELECT DATA MSB LSB A2 A1 A0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 X LAST LSB (1)CHIP SELECT DATA MSB LSB 1 X LAST Don't care CHIP SELECT DATA •DAC DATA FIRST MSB D7 •SUB ADDRESS FIRST LAST 1 CS2 1 CS1 1 CS0 1 S3 S2 S1 S0 Channel selection 0 0 0 0 Don't care. 0 0 0 1 ch1 selection 0 0 1 0 ch2 selection 0 1 1 1 ch7 selection 1 0 0 0 ch8 selection 1 0 0 1 Don't care. 1 1 1 1 Don't care. (3)DAC DATA LAST LSB FIRST MSB D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 (VrefU-VrefL)/256 x 1 x 2.4 + VrefL 0 0 0 0 0 0 0 1 (VrefU-VrefL)/256 x 2 x 2.4 +VrefL 0 0 0 0 0 0 1 0 (VrefU-VrefL)/256 x 3 x 2.4 +VrefL 0 0 0 0 0 0 1 1 (VrefU-VrefL)/256 x 4 x 2.4 +VrefL 1 1 1 1 1 1 1 0 (VrefU-VrefL)/256 x 255 x 2.4 +VrefL 1 1 1 1 1 1 1 1 VrefU x 2.4 + VrefL DAC output MITSUBISHI ELECTRIC ( 5 / 5 )