MOTOROLA DSP56F802

DSP56F802/D
Rev. 0, 1/2002
DSP56F802
Preliminary Technical Data
DSP56F802 16-bit Digital Signal Processor
•
Up to 40 MIPS operation at 80 MHz core
frequency
•
Hardware DO and REP loops
•
6-channel PWM Module with fault input
•
DSP and MCU functionality in a unified,
C-efficient architecture
•
Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
•
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
•
Serial Communications Interface (SCI)
•
Two General Purpose Quad Timers with 2
external outputs
•
8K × 16-bit words Program Flash
•
JTAG/OnCETM port for debugging
•
1K × 16-bit words Program RAM
•
4 shared GPIO
•
2K × 16-bit words Data Flash
•
On-chip relaxation oscillator
•
1K × 16-bit words Data RAM
•
32-pin LQFP Package
•
2K × 16-bit words Boot Flash
6
PWM Outputs
PWMA
Fault A0
RESET
VCAPC VDD
5
2
2
JTAG/
OnCE
Port
2
3
A/D1
A/D2
VREF
Quad Timer C
2
Quad Timer D
or GPIO
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
SCI0
or
GPIO
Program Controller
and
Hardware Looping Unit
•
ApplicationSpecific
Memory &
Peripherals
Analog Reg
Low Voltage
Supervisor
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
•
PLL
XDB2
•
CGDB
XAB1
XAB2
•
•
•
•
IPBB
CONTROLS
16
Relaxation
Oscillator
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
.
16-Bit
DSP56800
Core
IPBus Bridge
(IPBB)
DATA BUS [15:0]
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. DSP56F802 Block Diagram
© Motorola, Inc., 2002. All rights reserved.
Bit
Manipulation
Unit
•
INTERRUPT
CONTROLS
16
COP/
Watchdog
VSSA
PAB
PDB
Boot Flash
2048x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
2
Digital Reg
ADC
Interrupt
Controller
VSS* VDDA
3
Part 1 Overview
1.1 DSP56F802 Features
1.1.1
Digital Signal Processing Core
•
Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture
•
As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency
•
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
•
Two 36-bit accumulators including extension bits
•
16-bit bidirectional barrel shifter
•
Parallel instruction set with unique DSP addressing modes
•
Hardware DO and REP loops
•
Three internal address buses and one external address bus
•
Four internal data buses and one external data bus
•
Instruction set supports both DSP and controller functions
•
Controller style addressing modes and instructions for compact code
•
Efficient C compiler and local variable support
•
Software subroutine and interrupt stack with depth limited only by memory
•
JTAG/OnCE debug programming interface
1.1.2
Memory
•
Harvard architecture permits as many as three simultaneous accesses to program and data memory
•
On-chip memory including a low-cost, high-volume flash solution
— 8K × 16 bit words of Program Flash
— 1K × 16-bit words of Program RAM
— 2K × 16-bit words of Data Flash
— 1K × 16-bit words of Data RAM
— 2K × 16-bit words of Boot Flash
•
1.1.3
2
Programmable Boot Flash supports customized boot code and field upgrades of stored code through
a variety of interfaces (JTAG)
Peripheral Circuits for DSP56F802
•
Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion and fault protection;
supports both center- and edge-aligned modes
•
Two 12-bit, Analog-to-Digital Converters (ADCs), 1 x 2 channel and 1 x 3 channel, which support
two simultaneous conversions; ADC and PWM modules can be synchronized
•
Two General Purpose Quad Timers with two external pins (or two GPIO)
•
Serial Communication Interface (SCI) with two pins (or two GPIO)
•
Four multiplexed General Purpose I/O (GPIO) pins
DSP56F802 Preliminary Technical Data
MOTOROLA
DSP56F802 Description
•
Computer-Operating Properly (COP) watchdog timer
•
External interrupts via GPIO
•
Trimmable on-chip relaxation oscillator
•
External reset pin for hardware reset
•
JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
•
Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
1.1.4
Energy Information
•
Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs
•
Uses a single 3.3V power supply
•
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
•
Wait and Stop modes available
•
Integrated power supervisor
1.2 DSP56F802 Description
The DSP56F802 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the DSP56F802 is well-suited for many applications.
The DSP56F802 includes many peripherals that are especially useful for applications such as motion
control, home appliances, encoders, tachometers, limit switches, power supply and control, engine
management, and industrial control for power, lighting, automation and HVAC.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The DSP56F802 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip data RAM per instruction cycle. The DSP56F802 also provides and up to
4 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The DSP56F802 DSP controller includes 8K words (16-bit) of program Flash and 2K words of Data Flash
(each programmable through the JTAG port) with 1K words of both program and data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main program and data flash memory areas. Both program and data flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the DSP56F802 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs to
enhance motor control functionality. Complementary operation permits programmable dead-time insertion,
and separate top and bottom output polarity control. The up-counter value is programmable to support a
continuously variable PWM frequency. Both edge and center aligned synchronous pulse width control (0%
to 100% modulation) are supported. The device is capable of controlling most motor types: ACIM (AC
MOTOROLA
DSP56F802 Preliminary Technical Data
3
Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and
Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection with sufficient
output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”, write-once protection
feature for key parameters is also included. The PWM is double-buffered and includes interrupt control to
permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output
to synchronize the Analog-to-Digital Converters.
The DSP56F802 incorporates two 12-bit Analog-to-Digital Converters (ADCs) with a total of five channels.
A full set of standard programmable peripherals is provided that include a Serial Communications Interface
(SCI), and two Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO)
if that function is not required. An on-chip relaxation oscillator eliminates the need for an external crystal.
1.3 “Best in Class” Development Environment
The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces
that allow programmers to create their unique C application code independent of component architecture.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the
DSP56F802. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/dsp.
Table 1. DSP56F802 Chip Documentation
Topic
4
Description
Order Number
DSP56800
Family Manual
Detailed description of the DSP56800 family architecture, and
16-bit DSP core processor and the instruction set
DSP56800FM/D
DSP56F801/803/805/807
User’s Manual
Detailed description of memory, peripherals, and interfaces of
the DSP56F801, DSP56F802, DSP56F803, DSP56F805, and
DSP56F807
DSP56F801-7UM/D
DSP56F802
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
DSP56F802/D
DSP56F802
Product Brief
Summary description and block diagram of the DSP56F802
core, memory, peripherals and interfaces
DSP56F802PB/D
DSP56F802 Preliminary Technical Data
MOTOROLA
Data Sheet Conventions
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted”
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
1.
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
MOTOROLA
DSP56F802 Preliminary Technical Data
5
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56F802 are organized into functional groups, as shown in Table 2
and as illustrated in Figure 2. In Table 3 through Table 11, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
Number of
Pins
Detailed
Description
Power (VDD or VDDA)
3
Table 3
Ground (VSS, VSSA, TCS)
4
Table 4
Supply Capacitors
2
Table 5
Program Control
1
Table 6
Pulse Width Modulator (PWM) Port and Fault Input
7
Table 7
Serial Communications Interface (SCI) Port1
2
Table 8
Analog-to-Digital Converter (ADC) Port (including VREF)
6
Table 9
Quad Timer Module Port
2
Table 10
JTAG/On-Chip Emulation (OnCE)
5
Table 11
Functional Group
1.
6
Alternately, GPIO pins
DSP56F802 Preliminary Technical Data
MOTOROLA
Introduction
Power Port
Ground Port
Power Port
Ground Port
Other
Supply Port
VDD
VSS
VDDA
VSSA
VCAPC
2
3*
1
1
6
PWMA0-5
2
1
Fault A0
DSP56F802
1
1
5
1
TCK
JTAG/
OnCE Port
TMS
TDI
TDO
TRST
TXD0 (GPIOB0)
RXD0 (GPIOB1)
ANA2-4, ANA6-7
SCI0 Port or
GPIO
ADCA Port
VREF
1
1
2
TD1-2 (GPIOA1-2)
1
Quad
Timer D or
GPIO
1
1
1
RESET
Program
Control
Figure 2. DSP56F802 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parenthesis.
MOTOROLA
*includes TCS pin which is reserved for factory use and is tied to VSS
DSP56F802 Preliminary Technical Data
7
2.2 Power and Ground Signals
Table 3. Power Inputs
No. of Pins
Signal Name
Signal Description
2
VDD
Power—These pins provide power to the internal structures of the chip, and
should all be attached to VDD.
1
VDDA
Analog Power—This pin supplies an analog power source.
Table 4. Grounds
No. of Pins
Signal Name
Signal Description
2
VSS
GND—These pins provide grounding for the internal structures of the chip, and
should all be attached to VSS.
1
VSSA
Analog Ground—This pin supplies an analog ground.
1
TCS
TCS—This pin is reserved for factory use and must be tied to VSS for normal
use. In block diagrams, this pin is considered an additional V SS.
Table 5. Supply Capacitors and VPP
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
2
VCAPC
Supply
Supply
Signal Description
VCAPC - Connect each pin to a 2.2 µF bypass capacitor in order
to bypass the core logic voltage regulator (required for proper chip
operation). For more information, refer to Section 5.2
2.3 Interrupt and Program Control Signals
Table 6. Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
RESET
Input
Input
Signal Description
Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the DSP is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip operating
mode is latched from the EXTBOOT pin. The internal reset signal
will be deasserted synchronous with the internal clocks, after a
fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware DSP reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET, but do not assert TRST.
8
DSP56F802 Preliminary Technical Data
MOTOROLA
Pulse Width Modulator (PWM) Signals
2.4 Pulse Width Modulator (PWM) Signals
Table 7. Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
6
PWMA0-5
Output
Tri-stated
1
FAULTA0
Input
Input
Signal Description
PWMA0-5— These are six PWMA output pins.
FAULTA0 —This fault input is used for disabling selected
PWMA outputs in cases where fault conditions originate off
chip.
2.5 Serial Communications Interface (SCI) Signals
Table 8. Serial Communications Interface (SCI0) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
1
TXD0
Output
Input
Transmit Data (TXD0)—transmit data output
GPIOB0
Input/
Output
Input
Port B GPIO—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
Signal Description
After reset, the default state is SCI output.
1
RXD0
Input
Input
Receive Data (RXD0)—receive data input
GPIOB1
Input/
Output
Input
Port B GPIO—This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
After reset, the default state is SCI input.
2.6 Analog-to-Digital Converter (ADC) Signals
Table 9. Analog to Digital Converter Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
3
ANA2-4
Input
Input
ANA2-4—Analog inputs to ADC channel 1
2
ANA6-7
Input
Input
ANA6-7—Analog inputs to ADC channel 2
1
VREF
Input
Input
VREF—Analog reference voltage. Must be set to VDDA - 0.3V
= 3.0V for optimal performance.
MOTOROLA
Signal Description
DSP56F802 Preliminary Technical Data
9
2.7 Quad Timer Module Signals
Table 10. Quad Timer Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
2
TD1-2
Input/
Output
Input
TD1-2—Timer D Channel 1-2
GPIOA1-2
Input/
Output
Input
Port A GPIO—These pins are General Purpose I/O (GPIO)
pins that can individually be programmed as input or output
pins.
Signal Description
After reset, the default state is the quad timer input.
2.8 JTAG/OnCE
Table 11. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
1
TCK
Input
Input, pulled Test Clock Input—This input pin provides a gated clock to
low internally synchronize the test logic and shift serial data to the JTAG/OnCE port.
The pin is connected internally to a pull-down resistor.
1
TMS
Input
Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG
high internally TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
1
TDI
Input
Input, pulled Test Data Input—This input pin provides a serial input data stream to
high internally the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
1
TDO
Output
1
TRST
Input
10
State During
Reset
Tri-stated
Signal Description
Test Data Output—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
Input, pulled Test Reset—As an input, a low signal on this pin provides a reset
high internally signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment, since the OnCE/JTAG
module is under the control of the debugger. In this case it is not
necessary to assert TRST when asserting RESET. Outside of a
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the OnCE/JTAG module on the
DSP.
DSP56F802 Preliminary Technical Data
MOTOROLA
General Characteristics
Part 3 Specifications
3.1 General Characteristics
The DSP56F802 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5Vcompatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10%
during normal operation without causing damage). This 5V tolerant capability therefore offers the power
savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 12 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The DSP56F802 DC and AC electrical specifications are preliminary and are from design simulations.
These specifications may not be fully tested or guaranteed at this early stage of the product life cycle.
Finalized specifications will be published after complete characterization and device qualifications have
been completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Table 12. Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
Supply voltage
VDD
VSS – 0.3
VSS + 4.0
V
All other input voltages, excluding Analog inputs
VIN
VSS – 0.3
VSS + 5.5V
V
Analog Inputs ANAx, VREF
VIN
VSS – 0.3
VDDA + 0.3V
V
Current drain per pin excluding VDD, VSS, & PWM ouputs
I
—
10
mA
Current drain per pin for PWM outputs
I
—
20
mA
TJ
—
150
°C
TSTG
-55
150
°C
Junction temperature
Storage temperature range
MOTOROLA
DSP56F802 Preliminary Technical Data
11
Table 13. Recommended Operating Conditions
Characteristic
Symbol
Min
Max
Unit
VDD
3.0
3.6
V
TA
-40
85
°C
Supply voltage
Ambient operating temperature
Table 14. Thermal Characteristics 1
32-pin LQFP
Characteristic
Symbol
Value
Unit
Junction-to-ambient (estimated)
RθJA
53.2
°C/W
I/O pin power dissipation
PI/O
User Determined
W
Power dissipation
PD
PD = (IDD x VDD) + PI/O
W
PDMAX
(TJ - TA) / θJA
°C
Maximum allowed PD
1.
See Section 5.1 for more detail.
3.2 DC Electrical Characteristics
Table 15. DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input high voltage
VIH
2.0
—
5.5
V
Input low voltage
VIL
-0.3
—
0.8
V
Input current low (pullups/pulldowns disabled)
IIL
-1
—
1
µA
Input current high (pullups/pulldowns disabled)
IIH
-1
—
1
µA
RPU, RPD
—
30
—
KΩ
Input/output tri-state current low
IOZL
-10
—
10
µA
Input/output tri-state current low
IOZH
-10
—
10
µA
Output High Voltage (at IOH)
VOH
VDD – 0.7
—
—
V
Output Low Voltage (at IOL)
VOL
—
—
0.4
V
Output High Current
IOH
—
—
-4
mA
Output Low Current
IOL
—
—
4
mA
Input capacitance
CIN
—
8
—
pF
COUT
—
12
—
pF
Typical pullup or pulldown resistance
Output capacitance
12
DSP56F802 Preliminary Technical Data
MOTOROLA
DC Electrical Characteristics
Table 15. DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fop = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
PWM pin output source current1
IOHP
—
—
-10
mA
PWM pin output sink current2
IOLP
—
—
16
mA
VDD supply current
IDDT3
Run4
—
103
138
mA
Wait5
—
72
98
mA
Stop
—
60
84
mA
VEI
2.4
—
2.7
2.2
2.9
—
V
POR
—
1.7
2.0
V
Low Voltage Interrupt6
Core Voltage Interrupt
Power on Reset7
1. PWM pin output source current measured with 50% duty cycle.
2. PWM pin output sink current measured with 50% duty cycle.
3. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
4. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.
5. Wait IDD measured using internal relaxation oscillator set to 8 MHz; all inputs 0.2V from rail; no DC loads; less
than 50 pF on all outputs. CL = 20 pF on EXTAL; all ports configured as inputs; measured with PLL enabled.
6. Low voltage interrupt monitors the VDD supply. When VDD drops below VEI value, an interrupt is generated.
Functionality of the device is guaranteed under transient conditions when VDDA>VEI.
7. Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below VPOR. While power is
ramping up, this signal remains active for as long as the internal 2.5V supply is below 1.5V no matter how long the ramp
up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at
which time it self regulates.
Digital (VDD=3.6V)
Total
Analog (VDDA=3.6V)
180
150
120
Idd (mA)
90
60
30
0
0
20
40
60
80
Freq. (MHz)
Figure 3. Maximum Run Idd vs. Frequency (see Note 4 above)
MOTOROLA
DSP56F802 Preliminary Technical Data
13
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for
all pins except XTAL, which is tested using the input levels in Section 3.2 In Figure 4 the levels of VIH and
VIL for an input signal are shown.
Low
VIH
Input Signal
High
90%
50%
10%
Midpoint1
VIL
Fall Time
Rise Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 4. Input Signal Measurement References
Figure 5 shows the definitions of the following signal states:
•
Active state, when a bus or signal is driven, and enters a low impedance state.
•
Tri-stated, when a bus or signal is placed in a high impedance state.
•
Data Valid state, when a signal level has reached V OL or VOH.
•
Data Invalid state, when a signal level is in transition between VOL and VOH.
Data2 Valid
Data1 Valid
Data1
Data3 Valid
Data2
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 5. Signal States
14
DSP56F802 Preliminary Technical Data
MOTOROLA
Flash Memory Characteristics
3.4 Flash Memory Characteristics
Table 16. Flash Memory Truth Table
Mode
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Standby
L
L
L
L
L
L
L
L
Read
H
H
H
H
L
L
L
L
Word Program
H
H
L
L
H
L
L
H
Page Erase
H
L
L
L
L
H
L
H
Mass Erase
H
L
L
L
L
H
H
H
1.
2.
3.
4.
5.
6.
7.
8.
X address enable, all rows are disabled when XE = 0
Y address enable, YMUX is disabled when YE = 0
Sense amplifier enable
Output enable, tri-state flash data out bus when OE = 0
Defines program cycle
Defines erase cycle
Defines mass erase cycle, erase whole block
Defines non-volatile store cycle
Table 17. IFREN Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Read main memory block
Word program
Program information block
Program main memory block
Page erase
Erase information block
Erase main memory block
Mass erase
Erase both blocks
Erase main memory block
MOTOROLA
DSP56F802 Preliminary Technical Data
15
Table 18. Timing Symbols
Characteristic
Symbol
See Figure(s)
PROG/ERASE to NVSTR set up time
Tnvs
Figure 6, Figure 7, Figure 8
NVSTR hold time
Tnvh
Figure 6, Figure 7
NVSTR hold time(mass erase)
Tnvh1
Figure 8
NVSTR to program set up time
Tpgs
Figure 6
Program hold time
Tpgh
Figure 6
Address/data set up time
Tads
Figure 6
Address/data hold time
Tadh
Figure 6
Recovery time
Trcv
Figure 6, Figure 7, Figure 8
Cumulative program HV period
Thv
Figure 6
Program time
Tprog
Figure 6
Erase time
Terase
Figure 7
Mass erase time
Tme
Figure 8
Table 19. Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF
Characteristic
Symbol
Min
Typ
Max
Unit
Program time
Tprog
20
—
—
us
Erase time
Terase
20
—
—
ms
Mass erase time
Tme
100
—
—
ms
Endurance1
ECYC
10,000
20,000
—
cycles
Data Retention @ 5,000 Cycles1
DRET
10
30
—
years
The following parameters should only be used in the Manual Word Programming mode.
PROG/ERASE to NVSTR set up time
Tnvs
—
5
—
us
NVSTR hold time
Tnvh
—
5
—
us
NVSTR hold time(mass erase)
Tnvh1
—
100
—
us
NVSTR to program set up time
Tpgs
—
10
—
us
Recovery time
Trcv
—
1
—
us
1.
16
One cycle is equal to an erase, program, and read.
DSP56F802 Preliminary Technical Data
MOTOROLA
Flash Memory Characteristics
IFREN
XADR
XE
Tadh
YADR
YE
DIN
Tads
PROG
Tnvs
Tprog
Tpgh
NVSTR
Tpgs
Tnvh
Trcv
Thv
Figure 6. Flash Program Cycle
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE
Tnvs
NVSTR
Tnvh
Terase
Trcv
Figure 7. Flash Erase Cycle
MOTOROLA
DSP56F802 Preliminary Technical Data
17
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE
Tnvs
NVSTR
Tnvh1
Tme
Trcv
Figure 8. Flash Mass Erase Cycle
3.5 Clock Operation
The DSP56F802 device clock is derived from an on-chip relaxation oscillator. The internal PLL generates
a master reference frequency that determines the speed at which chip operations occur.
The PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2) must be set to 0 for internal
oscillator use.
3.5.1
Use of On-Chip Relaxation Oscillator
The DSP56F802 internal relaxation oscillator provides the chip clock without the need for an external
crystal or ceramic resonator. The frequency output of this internal oscillator can be corrected by adjusting
the 8-bit IOSCTL (internal oscillator control) register. Each bit added or deleted changes the output
frequency of the oscillator allowing incremental adjustment until the desired frequency is achieved. Figures
9 and 10 show the typical characteristics of the DSP56F802 relaxation oscillator with respect to temperature
and trim value.
During factory production test, an oscillator calibration procedure is executed which determines an
optimum trim value for a given device (8 MHz at 25 oC). This optimum trim value is then stored at address
$103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence (executed
after power-up and RESET). This trim routine automatically sets the oscillator frequency by programming
the IOSCTL register with the optimum trim value.
Due to the inherent frequency tolerances required for SCI communication, changing the factory-trimmed
oscillator frequency is not recommended. If modification of the Boot Flash contents are required, code must
be included which retrieves the optimum trim value (from address $103F in the Data Flash Information
Block) and writes it to the IOSCTL register. Note that the IFREN bit in the Data Flash control register must
be set in order to read the Data Flash Information Block.
18
DSP56F802 Preliminary Technical Data
MOTOROLA
Clock Operation
Table 20. Relaxation Oscillator Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
∆f
—
+2
+5
%
Frequency Drift over Temp
∆f/∆t
—
+0.1
—
%/oC
Frequency Drift over Supply
∆f/∆V
—
0.1
—
%/V
Frequency Accuracy1
1.
Over full temperature range.
8.4
Output Frequency
8.3
8.2
8.1
8.0
7.9
7.8
-40
-25
-5
15
35
55
75
85
Temperature (oC)
Figure 9. Typical Relaxation Oscillator Frequency vs. Temperature
(Trimmed to 8 MHz @ 25oC)
MOTOROLA
DSP56F802 Preliminary Technical Data
19
11
10
9
8
7
6
5
0
10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
Figure 10. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 21. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF
Symbol
Typical
Min
Typical
Max
Unit
RESET Assertion to Address, Data and Control Signals High
Impedance
tRAZ
—
21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
128T
—
—
ns
ns
RESET De-assertion to First External Address Output
tRDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
Characteristic
1.
2.
20
In the formulas, T = clock cycle. For an operating frequency of 80 MHz, T = 12.5 ns.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
DSP56F802 Preliminary Technical Data
MOTOROLA
Quad Timer Timing
Figure 11. External Level-Sensitive Interrupt Timing
General
Purpose
I/O Pin
tIG
IRQA
b) General Purpose I/O
3.7 Quad Timer Timing
Table 22. Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
Characteristic
Symbol
Typical Min
Typical Max
Unit
PIN
4T+6
—
ns
Timer input high/low period
PINHL
2T+3
—
ns
Timer output period
POUT
2T
—
ns
POUTHL
1T
—
ns
Timer input period
Timer output high/low period
1.
2.
In the formulas listed, T = clock cycle. For 80 MHz operation, T = 12.5 ns.
Parameters listed are guaranteed by design.
Timer Inputs
PIN
PINHL
PINHL
POUTHL
POUTHL
Timer Outputs
POUT
Figure 12. Timer Timing
MOTOROLA
DSP56F802 Preliminary Technical Data
21
3.8 Serial Communication Interface (SCI) Timing
Table 23. SCI Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
Characteristic
Symbol
Min
Max
Unit
BR
—
(fMAX*2.5)/(80)
Mbps
RXD2 Pulse Width
RXDPW
0.965/BR
1.04/BR
ns
TXD3 Pulse Width
TXDPW
0.965/BR
1.04/BR
ns
Baud Rate1
1.
2.
3.
4.
fMAX is the frequency of operation of the system clock in MHz.
The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
Parameters listed are guaranteed by design.
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 13. RXD Pulse Width
TXD
SCI receive
data pin
(Input)
TXDPW
Figure 14. TXD Pulse Width
3.9 Analog-to-Digital Converter (ADC) Characteristics
Table 24. ADC Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14,
ADC clock = 4MHz, 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
VADIN
0
—
VDDA1
V
Resolution
RES
12
—
12
Bits
Integral Non-Linearity2
INL
—
+/- 4
+/- 5
LSB3
Differential Non-Linearity
DNL
—
+/- 0.9
+/- 1
LSB3
Input voltages
Monotonicity
22
GUARANTEED
ADC internal clock
fADIC
0.5
—
5
MHz
Conversion range
RAD
VSSA
—
VDDA
V
DSP56F802 Preliminary Technical Data
MOTOROLA
Analog-to-Digital Converter (ADC) Characteristics
Table 24. ADC Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14,
ADC clock = 4MHz, 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Power-up time
tADPU
—
2.5
—
msec
Conversion time
tADC
—
6
—
tAIC cycles4
Sample time
tADS
—
1
—
tAIC cycles4
Input capacitance
CADI
—
5
—
pF4
Gain Error (transfer gain)
EGAIN
1.00
1.10
1.15
—
VOFFSET
+10
+230
+325
mV
THD
55
60
—
dB
Signal-to-Noise plus Distortion
SINAD
54
56
—
—
Effective Number of Bits
ENOB
8.5
9.5
—
bit
Spurious Free Dynamic Range
SFDR
60
65
—
dB
Spurious Free Dynamic Range
SFDR
65
70
—
dB
ADC Quiescent Current (both ADCs)
IADC
—
39.3
—
mA
VREF Quiescent Current (both ADCs)
IVREF
—
11.85
14.5
mA
Offset Voltage
Total Harmonic Distortion
1. VDDA should be tied to the same potential as VDD via separate traces. VREF must be equal to or less than VDD
and must be greater than or equal to 2.7V.
2.
Measured in 10-90% range.
3.
LSB = Least Significant Bit.
4.
tAIC = 1/fADIC
ADC analog input
1
3
2
4
Figure 15. Equivalent Analog Input Circuit
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing.
2.04pf
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. 500 ohms
Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the
input and is only connected to it at sampling time. 1pf
MOTOROLA
DSP56F802 Preliminary Technical Data
23
3.10 JTAG Timing
Table 25. JTAG Timing 1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50 pF, fOP = 80 MHz
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation2
fOP
DC
10
MHz
TCK cycle time
tCY
100
—
ns
TCK clock pulse width
tPW
50
—
ns
TMS, TDI data setup time
tDS
0.4
—
ns
TMS, TDI data hold time
tDH
1.2
—
ns
TCK low to TDO data valid
tDV
—
26.6
ns
TCK low to TDO tri-state
tTS
—
23.5
ns
tTRST
50
—
ns
TRST assertion time
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80 MHz
operation, T = 12.5 ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
tCY
tPW
tPW
VIH
VM
TCK
(Input)
VM = VIL + (VIH – VIL)/2
VM
VIL
Figure 16. Test Clock Input Timing Diagram
24
DSP56F802 Preliminary Technical Data
MOTOROLA
JTAG Timing
TCK
(Input)
TDI
TMS
(Input)
tDS
tDH
Input Data Valid
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 17. Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 18. TRST Timing Diagram
MOTOROLA
DSP56F802 Preliminary Technical Data
25
Part 4 Packaging
4.1 Package and Pin-Out Information DSP56F802
ANA4
ANA6
ANA7
PWMA0
VCAPC1
PWMA1
PWMA2
PWMA3
This section contains package and pin-out information for the 32-pin LQFP configuration of the
DSP56F802.
ORIENTATION
MARK
PWMA4
ANA3
25
PWMA5
VREF
PIN 1
TD1
ANA2
Motorola
TD2
FAULTA0
TXDO
DSP56F802
VSS
VSS
VDD
VDD
VSSA
17
9
RXD0
RESET
TRST
TDO
VCAPC2
TDI
TMS
TCK
TCS
VDDA
Figure 19. Top View, DSP56F802 32-pin LQFP Package
26
DSP56F802 Preliminary Technical Data
MOTOROLA
Package and Pin-Out Information DSP56F802
Table 26. DSP56F802 Pin Identification by Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
PWMA4
9
TCS
17
VDDA
25
ANA4
2
PWMA5
10
TCK
18
VSSA
26
ANA6
3
TD1
11
TMS
19
VDD
27
ANA7
4
TD2
12
TDI
20
VSS
28
PWMA0
5
TXDO
13
VCAPC2
21
FAULTA0
29
VCAPC1
6
VSS
14
TDO
22
ANA2
30
PWMA1
7
VDD
15
TRST
23
VREF
31
PWMA2
8
RXD0
16
RESET
24
ANA3
32
PWMA3
MOTOROLA
DSP56F802 Preliminary Technical Data
27
1.
2.
3.
4.
5.
6.
7.
NOTES:
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
CONTROLLING DIMENSION: MILLIMETER.
DATUM PLANE A, B AND D TO BE DETERMINED
AT DATUM PLANE H.
DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
DIMENSIONS b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b DIMENSION
BY MORE THEN 0.08 MM. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTURSION: 0.07 MM.
DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
MM PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC
BODY SIZE DIMENSIONS INCLUDING MOLD
MISMATCH.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE
FLAT SECTION OF THE LEAD
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
O
O1
R1
R2
S
MILLIMETERS
MIN
MAX
1.40
1.60
0.15
0.05
1.45
1.35
0.45
0.30
0.30
0.40
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.50
0.70
1.00 REF
°
0
7°
12° REF
0.08
0.20
0.08
-0.20 REF
Figure 20. 32-pin LQFP Mechanical Information (Case 873A)
28
DSP56F802 Preliminary Technical Data
MOTOROLA
Thermal Design Considerations
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1: TJ = T A + ( PD × R θJA )
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2: R θJA = R θJC + R θCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the
thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
•
Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.
•
Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.
•
Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package
case determined by a thermocouple.
MOTOROLA
DSP56F802 Preliminary Technical Data
29
The junction-to-case thermal resistances quoted in this data sheet are determined using the first definition
on page 45. From a practical standpoint, that value is also suitable for determining the junction temperature
from a case thermocouple reading in forced convection environments. In natural convection, using the
junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the
case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal
metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD. This value gives
a better estimate of the junction temperature in natural convection when using the surface temperature of
the package. Remember that surface temperature readings of packages are subject to significant errors
caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor.
The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the
package with thermally conductive epoxy.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Use the following list of considerations to assure correct DSP operation:
30
•
Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from
the board ground to each VSS (GND) pin.
•
The minimum bypass requirement is to place six 0.01–0.1 µF capacitors positioned as close as
possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA. The VCAP capacitors must be
150 milliohm or less ESR capacitors.
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and
VSS (GND) pins are less than 0.5 inch per capacitor lead.
•
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS.
•
Bypass the VDD and VSS layers of the PCB with approximately 100 µF, preferably with a highgrade capacitor such as a tantalum capacitor.
•
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
•
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the VDD and GND circuits.
•
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
DSP56F802 Preliminary Technical Data
MOTOROLA
Electrical Design Considerations
•
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together. TRST must be
asserted at power up for proper operation.
•
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.
Part 6 Ordering Information
Table 27 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Table 27. DSP56F802 Ordering Information
Part
Supply
Voltage
DSP56F802
3.0–3.6 V
MOTOROLA
Package Type
Low Profile Plastic Quad Flat Pack
(LQFP)
Pin
Count
Frequency
(MHz)
Order Number
32
80
DSP56F802TA80
DSP56F802 Preliminary Technical Data
31
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DSP56F802/D