ICS93738 Integrated Circuit Systems, Inc. DDR and SDRAM Buffer • • • • • • • • Low skew, fanout buffer 1 to 12 differential clock distribution I2C for functional and output control Feedback pin for input to output synchronization Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2 DDR DIMMs Frequency supports up to 200MHz (DDR400) Supports Power Down Mode for power mananagement CMOS level control signal input Switching Characteristics: • OUTPUT - OUTPUT skew: <100ps SDRAM OUTPUT - OUTPUT skew: <150ps DDR • Output Rise and Fall Time for DDR outputs: 600ps 950ps • DUTY CYCLE: 47% - 53% DDR DUTY CYCLE: 45%- 55% SDRAM Pin Configuration FB_OUT VDD3.3_2.5 GND DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3 VDD3.3_2.5 GND DDRT2_SDRAM4 DDRC2_SDRAM5 VDD3.3_2.5 BUF_IN GND DDRT3_SDRAM6 DDRC3_SDRAM7 VDD3.3_2.5 GND DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM10 DDRC5_SDRAM11 VDD3.3_2.5 SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS93738 Recommended Application: DDR & SDRAM fanout buffer, for VIA P4X/KT266/333 chipsets. Product Description/Features: 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEL_DDR* VDD2.5 GND DDRT11 DDRC11 DDRT10 DDRC10 VDD2.5 GND DDRT9 DDRC9 VDD2.5 PD#* GND DDRT8 DDRC8 VDD2.5 GND DDRT7 DDRC7 DDRT6 DDRC6 GND SCLK 48-Pin SSOP *Internal Pull-up Resistor of 120K to VDD Block Diagram Functionality FB_OUT DDRT0_SDRAM0 DDRC0_SDRAM1 BUF_IN DDRT1_SDRAM2 DDRC1_SDRAM3 SCLK SDATA SEL_DDR* PD# Control Logic DDRT2_SDRAM4 DDRC2_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM10 DDRC5_SDRAM11 DDRT(11:6) DDRC (11:6) 0689A—01/09/03 PIN 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21, 22 MODE PIN 48 VDD 3.3_2.5 DDR Mode SEL_DDR=1 2.5V These outputs will be DDR outputs DDR/SD Mode SEL_DDR=0 3.3V These outputs will be standard SDRAM outputs ICS93738 Pin Descriptions PIN NUMBER 1 PIN NAME TYPE DESCRIPTION FB_OUT OUT Feedback output, dedicated for external feedback 2, 8, 12, 17, 23, VDD3.3_2.5 PWR 2.5V or 3.3V voltage supply to pins 4, 5, 6, 7, 10, 11, 15 , 16, 19 , 20, 21, 22 3, 9, 14, 18, 26, 31, 35, 40, 46 GND PWR Ground 45, 43, 39, 34, 30, 28, DDRT (11:6) OUT "Tr ue" Clock of differential pair outputs. 44, 42, 38, 33, 29, 27, DDRC (11:6) OUT "Complementory" clocks of differential pair outputs. DDRT (5:0) SDRAM (10, 8, 6, 4, 2, 0) OUT "Tr ue" Clock of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input OUT "Complementory" clocks of differential pair outputs, or 3.3V SDRAM clock outputs depending on SEL_DDR input 21, 19, 15, 10, 6, 4 DDRC (5:0) 22, 20, 16, 11, 7, 5 SDRAM (11, 9, 7, 5, 3, 1,) 13 BUF_IN IN Single ended buffer input 24 SDATA I/O Data pin for I2C circuitry 5V tolerant 25 SCLK IN Clock input of I2C input, 5V tolerant input 32, 37, 41, 47 VDD2.5 PWR 2.5V voltage supply 36 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled. The latency of the power down will not be greater t h a n 3 m s. 48 SEL_DDR IN Select input for DDR mode or DDR/SD mode 0=DDR/SD mode 1=DDR mode 0689A—01/09/03 2 ICS93738 Byte 6: Output Control (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 48 45, 44 43, 42 39, 38 34, 33 PWD 1 1 1 1 1 1 1 1 Byte 7: Output Control (1= enable, 0 = disable) DESCRIPTION SEL_DDR (Read back only) (Reserved) (Reserved) (Reserved) DDRT11, DDRC11 DDRT10, DDRC10 DDRT9, DDRC9 DDRT8, DDRC8 0689A—01/09/03 3 BIT Bit 7 Bit 6 PIN# 30, 29 28, 27 Bit 5 21, 22 Bit 4 19, 20 Bit 3 15, 16 Bit 2 10, 11 Bit 1 6, 7 Bit 0 4, 5 PWD DESCRIPTION 1 DDRT7, DDRC7 1 DDRT6, DDRC6 DDRT5, SDRAM10 1 DDRC5_SDRAM11 DDRT4_SDRAM8 1 DDRC4_SDRAM9 DDRT3_SDRAM6 1 DDRC3_SDRAM7 DDRT2_SDRAM4 1 DDRC2_SDRAM5 DDRT1_SDRAM2 1 DDRC1_SDRAM3 DDRT0_SDRAM1 1 DDRC0_SDRAM0 ICS93738 Absolute Maximum Ratings Supply Voltage (VDD & VDD2.5) . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND –0.5 V to VDD +0.5 V 0°C to +85°C 115°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input / Supply / Common Output Parameters - SDRAM o SEL_DDR=0, SDRAM Outputs, VDD3.3_2.5 = 3.3V, TA = 0 - 85 C (unless otherwise stated) PARAMETER SYMBOL Input High Current IIH VIN = VDD or GND Input Low Current IIL VIN = VDD or GND Operating Supply Current CONDITIONS MIN TYP MAX UNITS 10 µA µA -100 IDD3.3_2.5 CL = 0 pF at 133 MHz 170 250 mA IDD2.5 CL = 0 pF at 133 MHz 90 200 mA IDDPD CL = 0 pF 0 10 µA -18 mA Output High Current IOH VDD = 3.3V, VOUT = 1V Output Low Current IOL VDD = 3.3V, VOUT = 1.2V 26 mA High-level Output Voltage VOH VDD = 3.3V, IOH = -12mA 2 V Low-level Output Voltage VOL VDD = 3.3V, IOL = 12mA CIN VIN = VDD or GND 1 Input Capacitance 0.4 V pF 1. Guaranteed by design, not 100% tested in production. Recommended Operating Conditions - SDRAM SEL_DDR=0, SDRAM Outputs, VDD3.3_2.5 = 3.3V, TA = 0 - 85oC (unless otherwise stated) PARAMETER Power Supply Voltage SYMBOL CONDITIONS MIN TYP MAX VDD3.3_2.5 3 3.3 3.6 VDD2.5 2.5 2.5 2.7 Input High Voltage VIH SEL_DDR, PD# inputs Input Low Voltage VIL SEL_DDR, PD# inputs Input Voltage Level VIN 2 UNITS V V 0.8 V V 0689A—01/09/03 4 ICS93738 Electrical Characteristics - Input / Supply / Common Output Parameters - DDR SEL_DDR=1, DDR/DDR_SDRAM Outputs, VDD3.3_2.5 = 2.5V, TA = 0 - 85oC (unless otherwise stated) PARAMETER SYMBOL Input High Current IIH VIN = VDD or GND Input Low Current IIL VIN = VDD or GND Operating Supply Current CONDITIONS MIN TYP MAX UNITS 10 µA µA -100 IDD3.3_2.5 CL = 0 pF at 133 MHz 125 200 mA IDD2.5 CL = 0 pF at 133 MHz 90 200 mA IDDPD CL = 0 pF 0 10 µA -18 mA Output High Current IOH VDD = 2.5V, VOUT = 1V Output High Current IOL VDD = 2.5V, VOUT = 1.2V 26 mA High-level Output Voltage VOH VDD = 2.5V, IOH = -12mA 1.7 V Low-level Output Voltage VOL VDD = 2.5V, IOL = 12mA Output differential-pair 1 crossing voltage CIN Input Capacitance1 CIN VDD/2 0.1 1.2 0.46 V VDD/2 + 0.1 V VIN = VDD or GND pF 1. Guaranteed by design, not 100% tested in production. Recommended Operating Conditions - DDR SEL_DDR=1, DDR/DDR_SDRAM Outputs, VDD3.3_2.5 = 2.5V, TA = 0 - 85oC (unless otherwise stated) PARAMETER Power Supply Voltage SYMBOL CONDITIONS MIN TYP MAX VDD3.3_2.5 2.3 2.5 2.7 VDD2.5 2.5 2.5 2.7 Input High Voltage VIH SEL_DDR, PD# inputs Input Low Voltage VIL SEL_DDR, PD# inputs Input Voltage Level VIN 2 UNITS V V 0.8 V V 0689A—01/09/03 5 ICS93738 Switching Characteristics o TA = 0 - 85 C PARAMETER SYMBOL CONDITIONS Operating Frequency dtin Input clock duty cycle MIN TYP MAX UNITS 66 133 200 MHz 40 50 60 % 1 Output to output Skew (DDR outputs) Output to output Skew1 (SDRAM outputs) Duty Cycle1,3 VT = 50%, Not including FB_OUT to outputs 80 150 ps TskewSD VT = 1.5V 70 100 ps DCDDR (DDR outputs) Duty Cycle1,3 VT = 50%, 66 MHz to 100 MHz , w/loads 48 49 52 VT = 50%, 101 MHz to 167 MHz, w/loads 47 50 53 VT = 1.5V, w/loads 45 50 55 % 600 800 950 ps 0.5 1.5 1.7 ns DCSD (SDRAM outputs) Rise Time, Fall Time1 (DDR outputs) Rise Time, Fall Time (SDRAM outputs) TskewDDR Single-ended 20 - 80 % trd, tfd 133 MHz, Load = 120Ω / 12 pF Single-ended VOL = 0.4V, VOH = 2.4V 1 trs, tfs 133 MHz, Load = 12 pF % SDRAM Buffer LH Propagation Delay1,2 tPLH Input edge greater than 1V/ns 2 2.5 ns SDRAM Buffer HL Propagation Delay1,2 tPHL Input edge greater than 1V/ns 1.9 2.5 ns 1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting output. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t2 / t1, where the cycle time (t1) decreases as the frequency increases. Switching Waveforms Duty Cycle Timing t1 t2 1.5V 1.5V 1.5V SDRAM Buffer LH and HL Propagation Delay 1.5V 1.5V INPUT 1.5V 1.5V OUTPUT t6 t7 0689A—01/09/03 6 ICS93738 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Read: How to Write: Controller (Host) Start Bit Address D4(H) Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver) ACK ICS (Slave/Receiver) ACK Byte Count Dummy Command Code ACK ACK Dummy Byte Count Byte 0 ACK ACK Byte 0 Byte 1 ACK ACK Byte 1 Byte 2 ACK ACK Byte 2 Byte 3 ACK ACK Byte 3 ACK Byte 4 Byte 4 ACK ACK Byte 5 Byte 5 ACK ACK Byte 6 Byte 6 ACK ACK Byte 7 Byte 7 Stop Bit ACK Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0689A—01/09/03 7 ICS93738 c N 300 mil SSOP L E1 INDEX AREA E 1 2 α h x 45° D A A1 -Ce SEATING PLANE b SYMBOL A A1 b c D E E1 e h L N α In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS N 48 D mm. MIN 15.75 D (inch) MAX 16.00 MIN .620 .10 (.004) C Reference Doc.: JEDEC Publication 95, MO-118 300 mil SSOP 10-0034 Ordering Information ICS93738yFT Example: ICS XXXX y F - T Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 0689A—01/09/03 8 MAX .630