MC54/74F646 MC54/74F648 Product Preview OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS These devices consist of bus transceiver circuits with 3-state D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Output Enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable OE is Active LOW. In the isolation mode (OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. • • • • OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS FAST SCHOTTKY TTL Independent Registers for A and B Multiplexed Real-Time and Stored Data Choice of True (F646) and Inverting (F648) Data Paths 3-State Outputs PIN ASSIGNMENTS 24 VCC CPBA SBA OE B0 B1 B2 B3 B4 B5 B6 B7 24 20 19 18 17 16 15 14 13 23 22 21 1 4 A0 5 A1 6 A2 7 A3 8 A4 9 A5 10 A6 11 12 A7 GND VCC CPBA SBA OE B0 B1 B2 B3 B4 B5 B6 B7 24 20 19 18 17 16 15 14 13 23 22 21 N SUFFIX PLASTIC CASE 724-03 24 F646 1 2 3 CPAB SAB DIR J SUFFIX CERAMIC CASE 758-01 1 DW SUFFIX SOIC CASE 751E-03 24 1 ORDERING INFORMATION F648 MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 CPAB SAB DIR 4 1 2 3 23 22 21 4 A0 5 A1 6 A2 5 6 7 A A1 A2 CPAB 0 SAB DIR CPBA SBA OE B0 B1 B2 20 19 18 8 A4 7 A3 8 A3 A4 9 9 A5 10 11 A5 A6 A7 10 A6 11 12 A7 GND LOGIC SYMBOLS 1 2 3 23 22 21 F646 B3 B4 17 16 B5 B6 B7 15 14 13 4 5 6 A A1 A2 CPAB 0 SAB DIR CPBA SBA OE B0 B1 B2 20 19 18 7 8 A3 A4 9 10 11 A5 A6 A7 F648 B3 B4 17 16 B5 B6 B7 15 14 13 This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. FAST AND LS TTL DATA 4-241 MC54/74F646 • MC54/74F648 FUNCTION TABLE Inputs Data I/O* Operation/Function OE bar DIR CPAB CPBA SAB SBA A0–A7 B0–B7 H H H H X X X X H or L ↑ X ↑ H or L X ↑ ↑ X X X X X X X X Input Input Input Input Input Input Input Input L L L L H H H H X ↑ H or L ↑ X X X X L L H H X X X X Input Input Input Input Output Output Output Output An to Bn — Real Time (Transparent Mode) Store An Data in A Register A Register to Bn (Stored Mode) Clock An Data to Bn and into A Register L L L L L L L L X X X X X ↑ H or L ↑ X X X X L L H H Output Output Output Output Input Input Input Input Bn to An — Real Time (Transparent Mode) Store Bn Data in B Register B Register to An (Stored Mode) Clock An Data to Bn and into B Register Isolation Store An Data in A Register Store Bn Data in B Register Store An/Bn Data in A/B Register *The data output function may be enabled or disabled by various signals at the OE bar and DIR inputs. Data input functions are always enabled; i.e., data at the *bus pins will be stored on every low-to-high transition of the appropriate clock inputs. H = HIGH voltage level L = LOW voltage level X = Don’t Care ↑ = Low-to-High transition GUARANTEED OPERATING RANGES Symbol VCC Parameter DC Supply Voltage Min Typ Max Unit 54, 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 54 74 –55 0 25 25 125 70 °C IOH Output Current High 54 74 — — — — –12 –15 mA IOL Output Current Low 54 74 — — — — 48 64 mA FAST AND LS TTL DATA 4-242 MC54/74F646 • MC54/74F648 LOGIC DIAGRAM F646 OE DIR CPBA SBA SAB CPAB 1 OF 8 CHANNELS C0 D0 A0 D0 C0 TO 7 OTHER CHANNELS FAST AND LS TTL DATA 4-243 B0 MC54/74F646 • MC54/74F648 LOGIC DIAGRAM F648 OE DIR CPBA SBA SAB CPAB 1 OF 8 CHANNELS C0 D0 A0 D0 C0 TO 7 OTHER CHANNELS FAST AND LS TTL DATA 4-244 B0 MC54/74F646 • MC54/74F648 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions (Note 1) VIH Input HIGH Voltage 2.0 — — V Guaranteed as a HIGH Signal VIL Input LOW Voltage — — 0.8 V Guaranteed as a LOW Signal VIK Input Clamp Diode Voltage — — –1.2 V VCC = MIN, IIN = –18 mA 54/74 2.4 — — V IOH = –3.0 mA VCC = 4.5 V 74 2.7 — — V IOH = –3.0 mA VCC = 4.75 V 54 2.0 — — V IOH = –12.0 mA VCC = 4.5 V 74 2.0 — — V IOH = –15.0 mA VCC = 4.5 V 54 — — 0.55 V IOL = 48 mA VCC = MIN 74 — — 0.55 V IOL = 64 mA VCC = MIN Non I/O Pins — — 20 µA VCC = MAX, VIN = 2.7 V Non I/O Pins — — 100 µA VCC = MAX, VIN = 7.0 V I/O (Aa, Bn) — — 1.0 mA VCC = MAX, VIN = 5.5 V VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current An, Bn An, Bn IIL Input LOW Current Non I/O Pins — — –600 µA VCC = MAX, VIN = 0.5 V IIH + IOZH Output Leakage Current I/O (An, Bn) — — 70 µA VCC = MAX IIL + IOZL Output Leakage Current I/O (An, Bn) — — –650 µA VCC = MAX, VOUT = 0.5 V IOS Output Short Circuit Current (Note 2) mA VCC = MAX, VOUT = GND ICC Power Supply Current –100 — –225 ICCH — — 135 ICCL — — 150 ICCZ — — 150 VOUT = 2.7 V Vout = HIGH mA Vout = LOW VCC = MAX Vout = HIGH Z NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-245 MC54/74F646 • MC54/74F648 AC ELECTRICAL CHARACTERISTICS Symbol Parameter 54/74F 54F 74F TA = +25°C VCC = +5.0 V CL = 50 pF RL = 500 Ω TA = –55°C to +125°C VCC = +5.0 V ±10% CL = 50 pF RL = 500 Ω TA = 0°C to +70°C VCC = +5.0 V ±10% CL = 50 pF RL = 500 Ω Min Max Min Max Min Max Unit fMAX Maximum Clock Frequency 100 — 75 — 90 — MHz tPLH tPHL Propagation Delay Clock to Bus 2.0 2.0 7.0 8.0 2.0 2.0 8.5 9.5 2.0 2.0 8.0 9.0 ns tPLH tPHL Propagation Delay Bus to Bus (F646) 1.0 1.0 7.0 6.5 1.0 1.0 8.0 8.0 1.0 1.0 7.5 7.0 ns tPLH tPHL Propagation Delay Bus to Bus (F648) 1.0 1.0 7.0 6.5 1.0 1.0 10.0 9.0 1.0 1.0 7.5 7.0 ns tPLH tPHL Propagation Delay SBA or SAB to An or Bn 2.0 2.0 7.5 7.5 2.0 2.0 10.0 10.0 2.0 2.0 9.0 9.0 ns tPZH tPZL Output Enable Time OE to An or Bn 2.0 2.0 7.0 7.0 2.0 2.0 9.5 9.5 2.0 2.0 8.5 8.5 ns tPHZ tPLZ Output Disable Time OE to An or Bn 1.0 2.0 7.0 7.0 1.0 2.0 9.5 9.5 1.0 2.0 8.5 8.5 ns tPZH tPZL Output Enable Time DIR to An or Bn 2.0 2.0 7.0 7.0 2.0 2.0 9.5 9.5 2.0 2.0 8.5 8.5 ns tPHZ tPLZ Output Disable Time DIR to An or Bn 1.0 2.0 7.0 7.0 1.0 2.0 9.5 9.5 1.0 2.0 8.5 8.5 ns AC OPERATING REQUIREMENTS Symbol Parameter 54/74F 54F 74F TA = +25°C VCC = +5.0 V CL = 50 pF RL = 500 Ω TA = –55°C to +125°C VCC = +5.0 V ±10% CL = 50 pF RL = 500 Ω TA = 0°C to +70°C VCC = +5.0 V ±10% CL = 50 pF RL = 500 Ω Min Max Min Max Min Max Unit ts(H) ts(L) Setup Time, HIGH or LOW Bus to Clock 4.0 4.0 — — 5.0 5.0 — — 5.0 5.0 — — ns th(H) th(L) Hold Time, HIGH or LOW Bus to Clock 0.0 0.0 — — 0.0 0.0 — — 0.0 0.0 — — ns tw(H) tw(L) Clock Pulse Width HIGH or LOW 4.0 5.0 — — 4.0 5.0 — — 4.0 5.0 — — ns FAST AND LS TTL DATA 4-246