Revised January 2004 74F646 Octal Transceiver/Register with 3-STATE Outputs General Description Features These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control G is Active LOW. In the isolation mode (control G HIGH), A data may be stored in the B register and/or B data may be stored in the A register. ■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ 74F646 has non-inverting data paths ■ 3-STATE outputs ■ 300 mil slim DIP Ordering Code: Order Number 74F646SC Package Number M24B 74F646MSA MSA24 74F646SPC N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2004 Fairchild Semiconductor Corporation DS009580 www.fairchildsemi.com 74F646 Octal Transceiver/Register with 3-STATE Outputs March 1988 74F646 Unit Loading/Fan Out Pin Names Description A0–A7 U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 3.5/1.083 70 µA/−650 µA 600/106.6 (80) −12 mA/64 mA (48 mA) Data Register A Inputs/ 3-STATE Outputs B0–B7 3.5/1.083 70 µA/−650 µA 600/106.6 (80) −12 mA/64 mA (48 mA) Data Register B Inputs/ 3-STATE Outputs CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20 µA/−0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 µA/−0.6 mA G Output Enable Input 1.0/1.0 20 µA/−0.6 mA DIR Direction Control Input 1.0/1.0 20 µA/−0.6 mA Function Table Inputs G DIR H X H X H X L H L H L H L H L L Data I/O (Note 1) CPAB CPBA SAB H or L H or L X X H or L X L L X L L X L L X H = HIGH Voltage Level SBA A0–A7 B0–B7 Input Input Function X X X X X X X L X X L X X H X X H X Clock An Data into A Register and Output to Bn X L Bn to An—Real Time (Transparent Mode) X X H or L X L X H X H Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn—Real Time (Transparent Mode) Input Output Clock An Data into A Register A Register to Bn (Stored Mode) Output L = LOW Voltage Level Input Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An X = Irrelevant = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 3: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA (Non I/O Pins) VOH Output HIGH V Min IOH = −15 mA (An, Bn) 0.55 V Min IOL = 64 mA (An, B n) 5.0 µA Max VIN = 2.7V (Non I/O Pins) 7.0 µA Max VIN = 7.0V (Non I/O Pins) 0.5 mA Max VIN = 5.5V (An, Bn) 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V (Non I/O Pins) 70 µA Max VOUT = 2.7V (An, Bn) −650 µA Max VOUT = 0.5V (An, Bn) −225 mA Max VOUT = 0V 10% VCC Voltage VOL Output LOW V Conditions VIH 2.0 10% VCC Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown (I/O) ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage Circuit Current Recognized as a HIGH Signal Recognized as a LOW Signal IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded IIL Input LOW Current IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test 500 µA 0.0V VOUT = 5.25V ICCH Power Supply Current 135 mA Max VO = HIGH ICCL Power Supply Current 150 mA Max VO = LOW ICCZ Power Supply Current 150 mA Max VO = HIGH Z −100 3 www.fairchildsemi.com 74F646 Absolute Maximum Ratings(Note 2) 74F646 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Max Min Max 75 Min Max fMAX Maximum Clock Frequency 90 tPLH Propagation Delay 2.0 tPHL Clock to Bus 2.0 8.0 2.0 9.5 2.0 9.0 tPLH Propagation Delay 1.0 7.0 1.0 8.0 1.0 7.5 tPHL Bus to Bus 1.0 6.5 1.0 8.0 1.0 7.0 tPLH Propagation Delay 2.0 8.5 2.0 11.0 2.0 9.5 tPHL SBA or SAB to A or B 2.0 8.0 2.0 10.0 2.0 9.0 tPZH Enable Time 2.0 8.5 2.0 10.0 2.0 9.0 tPZL OE to A or B 2.0 12.0 2.0 13.5 2.0 12.5 tPHZ Disable Time 1.0 7.5 1.0 9.0 1.0 8.5 tPLZ OE to A or B 2.0 9.0 2.0 11.0 2.0 9.5 tPZH Enable Time 2.0 14.0 2.0 16.0 2.0 15.0 tPZL DIR to A or B 2.0 13.0 2.0 15.0 2.0 14.0 tPHZ Disable Time 1.0 9.0 1.0 10.0 1.0 9.5 tPLZ DIR to A or B 2.0 11.0 2.0 12.0 2.0 11.5 7.0 90 2.0 8.5 Units MHz 2.0 8.0 ns ns ns ns ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 5.0 5.0 5.0 tS(L) Bus to Clock 5.0 5.0 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.5 2.0 tH(L) Bus to Clock 2.0 2.5 2.0 tW(H) Clock Pulse Width 5.0 5.0 5.0 tW(L) HIGH or LOW 5.0 5.0 5.0 www.fairchildsemi.com 4 Units Max ns ns ns 74F646 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA24 5 www.fairchildsemi.com 74F646 Octal Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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