DS21610 3.3V/5V Clock Rate Adapter www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21610 is a multirate, low-jitter clock adapter that converts E-carrier and T-carrier clocks to multiple PDH carrier clock rates. Two clock outputs are available that are frequency-locked to the input clock. The clock outputs along with an 8kHz framesync output can be phase-aligned to a frame-sync input. The device is backward compatible with the LXP610 and operates from either a 3.3V or 5V supply. All modes of operation include a standard 8kHz output. Direct Replacement for LXP610SE PIN CONFIGURATION 8kHz Frequency-Locked Output for all Operation Modes Converts E-Carrier Clock Rates to T-Carrier Clock Rates Converts T-Carrier Clock Rates to E-Carrier Clock Rates 3.3V or 5V Supply Low Jitter Output Multiple Output Clocks Synchronized to Input Clock No External Components Required TOP VIEW 16-Pin SO and 28-Pin PLCC Industrial Temperature Range: -40°C to +85°C Dallas Semiconductor DS21610 ORDERING INFORMATION PART DS21610SN DS21610SN+ DS21610QN DS21610QN+ SO TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 16 SO 16 SO 28 PLCC 28 PLCC + Denotes a lead-free/RoHS-compliant device. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 15 REV: 011606 DS21610 3.3V/5V Clock Rate Adapter TABLE OF CONTENTS 1. PIN DESCRIPTION ........................................................................................................................ 3 1.1 COMPATIBILITY WITH LXP610 .........................................................................................................................3 2. FUNCTIONAL DESCRIPTION ....................................................................................................... 5 3. OUTPUT JITTER............................................................................................................................ 6 3.1 JITTER TRANSFER...........................................................................................................................................6 4. OPERATING PARAMETERS......................................................................................................... 8 5. PACKAGE INFORMATION.......................................................................................................... 13 5.1 5.2 6. 16-PIN SO (300 MILS) (56-G4009-001) .......................................................................................................13 28-PIN PLCC (56-G4001-001)....................................................................................................................14 REVISION HISTORY.................................................................................................................... 15 LIST OF FIGURES Figure 1-1. Block Diagram ...................................................................................................................... 4 Figure 3-1. Nominal Jitter Transfer (1.544MHz CLKIN to 2.048MHz CLKOUT1)................................... 6 Figure 3-2. Nominal Jitter Transfer (2.048MHz CLKIN to 1.544MHz CLKOUT1)................................... 7 Figure 4-1. SYNCIN/CLKIN to CLKOUT1/SYNCOUT and CLKOUT2.................................................. 10 Figure 4-2. Output Frame-Sync Alignment When CLKOIT2 = 2 x CLKOUT1 ...................................... 11 Figure 4-3. Output Frame-Sync Alignment When CLKOUT2 = 3 x CLKOUT1..................................... 11 Figure 4-4. Output Frame-Sync Alignment When CLKOIT2 = 4 x CLKOUT1 ...................................... 12 Figure 4-5. Output Frame-Sync Alignment When CLKOUT2 = 5 x CLKOUT1..................................... 12 LIST OF TABLES Table 1-A. Pin Description ...................................................................................................................... 3 Table 1-B. Pin Name Cross-Reference to LXP610 ................................................................................ 3 Table 2-A. Program Pin Functions (SEL = 0) ......................................................................................... 5 Table 2-B. Program Pin Functions (SEL = 1) ......................................................................................... 5 Table 3-A. Output Jitter Specifications, CLKOUT1 = 1.544MHz ............................................................ 6 Table 3-B. Output Jitter Specifications, CLKOUT1 = 2.048MHz ............................................................ 6 2 of 15 DS21610 3.3V/5V Clock Rate Adapter 1. PIN DESCRIPTION Table 1-A. Pin Description PIN NAME TYPE 1 P3 Input 2 2 SYNCOUT Output 3–5, 7–9, 11, 12, 17– 19, 21, 23, 25, 26 3, 6, 11 N.C. — 6 4 CLKOUT2 Output 10 5 CLKIN Input 13 7 CLKOUT1 Output 14 8 P1 Input 15 9 VSS Supply 1.1 PLCC SO 1 FUNCTION Program Pin 3. Used to select the various combinations of clock and sync outputs. Synchronization Pulse Output. An 8kHz output that can be synchronized to the clock outputs and SYNCIN (if present). No Connection Clock Output 2. T1 or E1 carrier clock output referenced to CLKIN. Clock Input. Reference Clock Input. CLKOUT1 and CLKOUT2 will be referenced to this clock. Clock Output 1. T1 or E1 carrier clock output referenced to CLKIN. Program Pin 3. Used to select the various combinations of clock and sync outputs. Ground 16 10 P2 Input Program Pin 2. Used to select the various combinations of clock and sync outputs. 20 12 SEL Input Clock Mode Select. T-carrier/E-carrier mode select. 22 13 FSP Input 24 14 SYNCIN Input 27 15 P4 Input 28 16 VDD Supply Frame Synchronization Pulse Polarity. Used to change the polarity of the SYNCOUT output. Synchronization Pulse Input. Used to synchronize the clock outputs and SYNCOUT to CLKIN and SYNCIN. SYNCIN should be tied high or low when not in use. Program Pin 4. Used to select the various combinations of clock and sync outputs. Positive Supply, 3.3V or 5V ±5% Compatibility with LXP610 The DS21610 is pin compatible with the LXP610. Table 1-B. Pin Name Cross-Reference to LXP610 DS21610 P3 SYNCOUT CLKOUT2 CLKIN CLKOUT1 P1 VSS P2 N.C. LXP610 P3 FSO HFO CLKI CLKO P1 GND P2 N.C. FUNCTION Program Pin 3 Synchronization Pulse Output Clock 2 Output Clock Input Clock 1 Output Program pin 1 Ground Program Pin 2 No Connection 3 of 15 DS21610 3.3V/5V Clock Rate Adapter Figure 1-1. Block Diagram CLKOUT2 CLKIN ANALOG PLL FEEDBACK CIRCUIT OUTPUT DIVIDER CLKOUT1 DS21610 SEL FRAME SYNC GENERATOR SYNCIN P1 P2 P3 P4 FREQUENCY PLL SELECT LOGIC 4 of 15 SYNCOUT FSP DS21610 3.3V/5V Clock Rate Adapter 2. FUNCTIONAL DESCRIPTION A clock input at CLKIN is converted to various clocks available on CLKOUT1 and CLKOUT2. Additionally, an 8kHz clock locked to CLKIN and SYNCIN (if present) is always available at the SYNCOUT pin. The pulse width of the SYNCOUT is selectable. It can be one or one-half the clock period of CLKIN, centered on the rising edge of CLKIN. Pins P1 to P4 are used to select the various clock rates and operational modes. Table 2-A and Table 2-B list the various operational modes of the DS21610. CLKIN, CLKOUT1, and CLCKOUT2 are always frequency-locked. They can all be phase-locked to a system frame-sync pulse. A frame-sync pulse applied to SYNCIN will cause CLKIN and CLKOUT1 and CLKOUT2 to be phased-locked to that sync pulse. This causes the clocks to have a fixed alignment at the frame-sync boundaries. The signal applied to SYNCIN can be 8kHz or some integer subrate such as 1kHz, 2kHz, or 4kHz. Phase synchronization occurs within a maximum of 50ms when SYNCIN is 8kHz. Table 2-A. Program Pin Functions (SEL = 0) P4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 P2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLKIN 1.544 3.088 1.544 1.544 1.544 6.176 1.544 6.176 3.088 3.088 3.088 1.544 6.176 6.176 6.176 6.176 CLKOUT1 2.048 2.048 2.048 2.048 2.560 4.096 2.560 2.048 2.048 4.096 2.048 4.096 2.560 4.096 2.560 4.096 CLKOUT2 6.144 8.192 6.144 8.192 7.680 8.192 7.680 8.192 6.144 8.192 6.144 8.192 7.680 8.192 7.680 8.192 SYNCOUT Long Short Long Short Long Long Long Short Long Long Long Long Long Long Long Long CLKOUT2 6.176 6.176 6.176 6.176 7.720 6.176 7.720 6.176 6.176 6.176 6.176 6.176 7.720 6.176 7.720 6.176 SYNCOUT Long Long Long Long Long Long Long Long Long Long Long Long Long Long Long Long Table 2-B. Program Pin Functions (SEL = 1) P4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 P2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLKIN 2.048 2.048 2.048 2.048 2.560 8.192 2.560 8.192 2.048 4.096 2.048 4.096 2.560 8.192 2.560 8.192 CLKOUT1 3.088 3.088 1.544 1.544 1.544 3.088 1.544 1.544 3.088 3.088 3.088 1.544 1.544 3.088 1.544 1.544 5 of 15 DS21610 3.3V/5V Clock Rate Adapter 3. OUTPUT JITTER Table 3-A shows the output jitter specifications for 2.048MHz (or 4.096MHz) to 1.544MHz conversions (SEL = 1) and 1.544MHz to 2.048MHz (or 4.096MHz) conversions (SEL = 0). Table 3-A. Output Jitter Specifications, CLKOUT1 = 1.544MHz FREQUENCY BAND No bandlimiting 10Hz–40kHz 8kHz–40kHz TR62411 SPECIFICATION TR62411 TR62411 TR62411 TYP MAX UNITS 0.010 0.005 0.006 0.020 0.010 0.012 UIP-P UIP-P UIP-P Table 3-B. Output Jitter Specifications, CLKOUT1 = 2.048MHz FREQUENCY BAND 20Hz–100kHz 18kHz–100kHz 3.1 G.823 SPECIFICATION 1.5 0.2 TYP MAX UNITS 0.018 0.012 0.035 0.025 UIP-P UIP-P Jitter Transfer Figure 3-1 and Figure 3-2 show jitter transfer for 2.048MHz-to-1.544MHz conversions and vice versa. Figure 3-1. Nominal Jitter Transfer (1.544MHz CLKIN to 2.048MHz CLKOUT1) 2.00 JITTER GAIN (ns/ns) 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 0 5 10 15 20 25 30 35 40 JITTER FREQUENCY (kHz) NOTE: THE TYPICAL PEAK JITTER GAIN OF THE DS21610 IS ABOUT 1.6 FOR CONVERSION FROM T1 TO E1. THE TYPICAL PEAK-JITTER GAIN OF THE LEVEL ONE DEVICE IS ABOUT 1.1. HOWEVER, THE JITTER GAIN FOR THE DS21610 PEAKS IN THE 4kHz TO 8kHz RANGE, WHEREAS THE PEAK JITTER GAIN FOR THE LXP610 SPANS A GREATER FREQUENCY RANGE (20kHz TO 40kHz). 6 of 15 DS21610 3.3V/5V Clock Rate Adapter Figure 3-2. Nominal Jitter Transfer (2.048MHz CLKIN to 1.544MHz CLKOUT1) 2 JITTER GAIN (ns/ns) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 JITTER FREQUENCY (kHz) NOTE: THE TYPICAL PEAK JITTER GAIN OF THE DS2161 IS ABOUT 1.4 FOR CONVERSION FROM T1 TO E1. THE TYPICAL PEAK-JITTER GAIN OF THE LEVEL ONE DEVICE IS ABOUT 1.1. HOWEVER, THE JITTER GAIN FOR THE DS21610 PEAKS IN THE 4kHz TO 8kHz RANGE, WHEREAS THE PEAK JITTER GAIN FOR THE LXP610 SPANS A GREATER FREQUENCY RANGE (20kHz TO 40kHz). 7 of 15 DS21610 3.3V/5V Clock Rate Adapter 4. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground…………………………………………………………..-1.0V to +6.0V Operating Temperature Range for DS21610SN………………………………………………………...-40°C to +85°C Storage Temperature Range……………………………………………………………………………..-55°C to +125°C Soldering Temperature………………………………………………………See IPC/JEDEC J-STD-020 Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER Logic 1 Logic 0 Supply Voltage SYMBOL VIH VIL VDD CONDITIONS (Note 1) (Note 1) 3.3V 5V MIN 2.0 -0.3 3.135 4.75 TYP CONDITIONS (Note 2) (Note 3) MIN TYP 3.3 5.0 MAX 5.5 +0.8 3.465 5.25 UNITS V V MAX 14 +10.0 UNITS mA µA µA mA mA V DC CHARACTERISTICS (VDD = 3.3V/5V ± 5%, TA = -40°C to +85°C.) PARAMETER SYMBOL Supply Current IDD Input Leakage IIL Output Leakage ILO Output Current (2.4V) IOH Output Current (0.4V) IOL -10.0 -1.0 +4.0 8 of 15 DS21610 3.3V/5V Clock Rate Adapter AC TIMING (Figure 4-1, Figure 4-2, Figure 4-3, Figure 4-4, and Figure 4-5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Capture Range on CLKIN (Note 1) ±10,000 ppm Lock Range on CLKIN (Note 1) ±10,000 ppm CLKIN Duty Cycle SYNCIN Setup to CLKIN Rising SYNCIN Hold After CLKIN Rising tSU tHI (Note 1) (Note 1) (Note 1) 35 46 30 SYNCIN Pulse Width tPW (Note 1) 76 CLKOUT1 Delay from CLKIN Rising tD -15 -15 CLKOUT1 Duty Cycle SYNCOUT Delay from CLKOUT2 CD tDF 3.3V (Note 1) 5V (Note 1) (Note 1) 3.3V (Note 1) SYNCOUT Pulse Width tSPW (Note 1) CLKOUT1 Delay from CLKOUT2 Rising tDH 3.3V (Note 1) Rise/Fall Time on CLKIN, SYNCIN tRF Rise/Fall Time on CLKOUT1, SYNCOUT, CLKOUT2 (Note 4) tRF Note 1: Guaranteed by design. Note 2: 100pF load on all outputs. Note 3: 0V < VIN < VDD. Note 4: 100pF load on CLKOUT1, SYNCOUT, CLKOUT2. 3.3V (Note 1) 5V (Note 1) 3.3V (Note 1) 5V (Note 1) 9 of 15 65 0 0 50 -5 CLKIN period +41 +22 +30 CLKOUT1 period -15 0 % ns ns ns ns % ns ns +15 60 40 75 40 ns ns ns DS21610 3.3V/5V Clock Rate Adapter Figure 4-1. SYNCIN/CLKIN to CLKOUT1/SYNCOUT and CLKOUT2 CLKIN SINCIN tSU tHI tPW CLKOUT1 tD CLKOUT1 SYNCOUT tDF tDF tWO CLKOUT2 CLKOUT1 tDH tDH 10 of 15 DS21610 3.3V/5V Clock Rate Adapter Figure 4-2. Output Frame-Sync Alignment When CLKOIT2 = 2 x CLKOUT1 CLKOUT1 (4.096MHz) CLKOUT2 (8.192MHz) SYNCOUT CLKOUT1 (3.088MHz) CLKOUT2 (6.176MHz) SYNCOUT Figure 4-3. Output Frame-Sync Alignment When CLKOUT2 = 3 x CLKOUT1 CLKOUT1 (2.56MHz or 2.048MHz) CLKOUT2 (7.680MHz or 6.144MHz) SYNCOUT 11 of 15 DS21610 3.3V/5V Clock Rate Adapter Figure 4-4. Output Frame-Sync Alignment When CLKOIT2 = 4 x CLKOUT1 CLKOUT1 (1.544MHz or 2.048MHz) CLKOUT2 (6.176MHz or 8.192MHz) SYNCOUT (short) SYNCOUT (long) Figure 4-5. Output Frame-Sync Alignment When CLKOUT2 = 5 x CLKOUT1 CLKOUT1 (1.544MHz) CLKOUT2 (7.720MHz) SYNCOUT 12 of 15 DS21610 3.3V/5V Clock Rate Adapter 5. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 5.1 16-Pin SO (300 mils) (56-G4009-001) 13 of 15 DS21610 3.3V/5V Clock Rate Adapter 5.2 28-Pin PLCC (56-G4001-001) 14 of 15 DS21610 3.3V/5V Clock Rate Adapter 6. REVISION HISTORY REVISION 090100 112700 120600 021501 060601 082001 032002 032803 113004 112105 011606 DESCRIPTION Preliminary release. Remove references to 3V operation. Add FSP pin to block diagram. Add mechanical drawings for PLCC package. Added jitter specifications and pinout for all packages. Added timing diagrams. Updated jitter specifications. Added 3.3V operation specifications. Added soldering temperature to Absolute Maximum Ratings section. Changed timing specs in DC Characteristics and AC Timing tables to guaranteed by design. Added lead-free packages to Ordering Information on page 1. 15 of 15 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products • Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.