19-5323; Rev 3; 10/11 KIT ATION EVALU E L B A IL AVA 12-Bit, 300ksps ADCs with FIFO and Internal Reference Features The MAX11626–MAX11629/MAX11632/MAX11633 are serial 12-bit analog-to-digital converters (ADCs) with an internal reference. These devices feature on-chip FIFO, scan mode, internal clock mode, internal averaging, and AutoShutdown™. The maximum sampling rate is 300ksps using an external clock. The MAX11632/ MAX11633 have 16 input channels; the MAX11628/ MAX11629 have 8 input channels; and the MAX11626/ MAX11627 have 4 input channels. These six devices operate from either a +3V supply or a +5V supply, and contain a 10MHz SPI™-/QSPI™-/MICROWIRE™-compatible serial port. The MAX11626–MAX11629 are available in 16-pin QSOP packages. The MAX11632/MAX11633 are available in 24-pin QSOP packages. All six devices are specified over the extended -40°C to +85°C temperature range. o Analog Multiplexer with Track/Hold 16 Channels (MAX11632/MAX11633) 8 Channels (MAX11628/MAX11629) 4 Channels (MAX11626/MAX11627) o Single Supply 2.7V to 3.6V (MAX11627/MAX11629/MAX11633) 4.75V to 5.25V (MAX11626/MAX11628/MAX11632) o Internal Reference 2.5V (MAX11627/MAX11629/MAX11633) 4.096V (MAX11626/MAX11628/MAX11632) o External Reference: 1V to VDD o 16-Entry First-In/First-Out (FIFO) o Scan Mode, Internal Averaging, and Internal Clock o Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing Codes Over Temperature o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible Interface o Small Packages 16-Pin QSOP (MAX11626–MAX11629) 24-Pin QSOP (MAX11632/MAX11633) ________________________Applications System Supervision Data-Acquisition Systems Industrial Control Systems Patient Monitoring Ordering Information Data Logging Instrumentation PART AutoShutdown is a trademark of Maxim Integrated Products, Inc. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Pin Configurations TOP VIEW AIN0 1 + 16 EOC AIN1 2 15 DOUT AIN2 3 14 DIN AIN3 4 AIN4 (N.C.) 5 MAX11626– MAX11629 13 SCLK SUPPLY VOLTAGE RANGE (V) PIN PACKAGE MAX11626EEE+ 4 4.75 to 5.25 16 QSOP MAX11627EEE+ 4 2.7 to 3.6 16 QSOP MAX11628EEE+ 8 4.75 to 5.25 16 QSOP MAX11628EEE/V+ 8 4.75 to 5.25 16 QSOP MAX11629EEE+ 8 2.7 to 3.6 16 QSOP MAX11632EEG+ 16 4.75 to 5.25 24 QSOP MAX11633EEG+ 16 2.7 to 3.6 24 QSOP Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. 12 CS AIN5 (N.C.) 6 11 VDD AIN6 (N.C.) 7 10 GND AIN7/(CNVST) 8 NUMBER OF INPUTS 9 REF QSOP () MAX11626/MAX11627 ONLY Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX11626–MAX11629/MAX11632/MAX11633 General Description MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (VDD + 0.3V) AIN0–AIN13, AIN_, CNVST/AIN_, REF to GND ...........................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW 24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V (MAX11626/MAX11628/ MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1.0 LSB ±1.0 LSB ±0.5 ±4.0 LSB ±0.5 ±4.0 LSB DC ACCURACY (Note 1) Resolution RES Integral Nonlinearity INL Differential Nonlinearity DNL 12 No missing codes over temperature Offset Error Gain Error Bits (Note 2) ±2 ppm/°C FSR Gain Temperature Coefficient ±0.8 ppm/°C Channel-to-Channel Offset Matching ±0.1 LSB Offset Error Temperature Coefficient DYNAMIC SPECIFICATIONS (30kHz sine-wave input, 2.5VP-P, 300ksps, fSCLK = 4.8MHz) Signal-to-Noise Plus Distortion Total Harmonic Distortion SINAD THD MAX11627/MAX11629/MAX11633 71 MAX11626/MAX11628/MAX11632 73 Up to the 5th harmonic MAX11627/MAX11629/ MAX11633 -80 MAX11626/MAX11628/ MAX11632 -88 dB dBc MAX11627/MAX11629/MAX11633 81 MAX11626/MAX11628/MAX11632 89 76 dBc Full-Power Bandwidth fIN1 = 29.9kHz, fIN2 = 30.2kHz -3dB point 1 MHz Full-Linear Bandwidth S/(N + D) > 68dB 100 kHz Spurious-Free Dynamic Range Intermodulation Distortion 2 SFDR IMD _______________________________________________________________________________________ dBc 12-Bit, 300ksps ADCs with FIFO and Internal Reference (VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V (MAX11626/MAX11628/ MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE Power-Up Time t PU Acquisition Time External reference 0.8 Internal reference (Note 3) 65 Internally clocked 3.5 µs tACQ Conversion Time tCONV External Clock Frequency f SCLK 0.6 Externally clocked (Note 4) 2.7 Externally clocked conversion 0.1 µs µs 4.8 Data I/O 10 MHz Aperture Delay 30 ns Aperture Jitter < 50 ps ANALOG INPUT Input Voltage Range Unipolar Input Leakage Current VIN = VDD Input Capacitance During acquisition time (Note 5) 0 ±0.01 VREF V ±1 µA 24 pF INTERNAL REFERENCE REF Output Voltage REF Temperature Coefficient TCREF MAX11626/MAX11628/MAX11632 4.024 4.096 4.168 MAX11627/MAX11629/MAX11633 2.48 2.50 2.52 MAX11626/MAX11628/MAX11632 ±20 MAX11627/MAX11629/MAX11633 ±30 Output Resistance REF Output Noise REF Power-Supply Rejection PSRR V ppm/°C 6.5 k 200 µVRMS -70 dB EXTERNAL REFERENCE INPUT REF Input Voltage Range REF Input Current VREF IREF 1.0 VDD + 50mV VREF = 2.5V (MAX11627/MAX11629/ MAX11633); VREF = 4.096V (MAX11626/MAX11628/MAX11632), f SAMPLE = 300ksps 40 VREF = 2.5V (MAX11627/MAX11629/ MAX11633); VREF = 4.096V (MAX11626/MAX11628/MAX11632), f SAMPLE = 0 ±0.1 V 100 µA ±5 _______________________________________________________________________________________ 3 MAX11626–MAX11629/MAX11632/MAX11633 ELECTRICAL CHARACTERISTICS (continued) MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE = 300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V (MAX11626/MAX11628/ MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, CNVST) Input Voltage Low VIL Input Voltage High VIH Input Hysteresis MAX11626/MAX11628/MAX11632 0.8 MAX11627/MAX11629/MAX11633 VDD x 0.3 MAX11626/MAX11628/MAX11632 2.0 MAX11627/MAX11629/MAX11633 VDD x 0.7 VHYST Input Leakage Current I IN Input Capacitance CIN V 200 VIN = 0V or VDD V ±0.01 mV ±1.0 15 µA pF DIGITAL OUTPUTS (DOUT, EOC) Output Voltage Low VOL Output Voltage High VOH Three-State Leakage Current Three-State Output Capacitance I SINK = 2mA 0.4 I SINK = 4mA 0.8 I SOURCE = 1.5mA VDD - 0.5 V V IL CS = VDD ±0.05 C OUT CS = VDD 15 ±1 µA pF POWER REQUIREMENTS Supply Voltage MAX11627/MAX11629/MAX11633 Supply Current (Note 6) MAX11626/MAX11628/MAX11632 Supply Current (Note 6) VDD MAX11626/MAX11628/MAX11632 4.75 5.25 MAX11627/MAX11629/MAX11633 2.7 3.6 Internal reference IDD External reference Internal reference IDD PSR 1750 2000 f SAMPLE = 0, REF on 1000 1200 Shutdown f SAMPLE = 300ksps Shutdown 0.2 5 1050 1200 0.2 5 f SAMPLE = 300ksps 2300 2550 f SAMPLE = 0, REF on 1050 1350 Shutdown External reference Power-Supply Rejection f SAMPLE = 300ksps f SAMPLE = 300ksps Shutdown 0.2 5 1550 1700 0.2 5 VDD = 2.7V to 3.6V; full-scale input ±0.2 ±1 VDD = 4.75V to 5.25V; full-scale input ±0.2 ±1.2 MAX11627/MAX11629/MAX11633 tested at VDD = +3V. MAX11626/MAX11628/MAX11632 tested at VDD = +5V. Offset nulled. Time for reference to power up and settle to within 1 LSB. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating Characteristics section. Note 6: Supply current is specified depending on whether an internal or external reference is used for voltage conversions. Note 1: Note 2: Note 3: Note 4: Note 5: 4 _______________________________________________________________________________________ V µA µA mV 12-Bit, 300ksps ADCs with FIFO and Internal Reference (VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE = 300kHz, f SCLK = 4.8MHz (50% duty cycle), V REF = 2.5V (MAX11627//MAX11629/MAX11633); V REF = 4.096V (MAX11626/ MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL SCLK Clock Period tCP SCLK Pulse Width High tCH SCLK Pulse Width Low CONDITIONS MIN Externally clocked conversion 208 Data I/O 100 TYP MAX UNITS ns 40 tCL ns 40 ns SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 40 ns CS Rise to DOUT Disable tDOD CLOAD = 30pF 40 ns CS Fall to DOUT Enable tDOE CLOAD = 30pF 40 ns DIN to SCLK Rise Setup tDS 40 ns SCLK Rise to DIN Hold tDH 0 ns CS Low to SCLK Setup tCSS0 40 ns CS High to SCLK Setup tCSS1 40 ns CS High After SCLK Hold tCSH1 0 ns CS Low After SCLK Hold tCSH0 0 tCSPW CNVST Pulse Width Low CS or CNVST Rise to EOC Low (Note 7) 4 µs CKSEL = 00 40 ns CKSEL = 01 1.4 µs Voltage conversion 7 Reference power-up 65 µs Note 7: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal reference needs to be powered up, the total time is additive. Typical Operating Characteristics (VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) 0.6 0.8 0.6 0.8 0.6 0.2 0.2 0 0 -0.2 -0.4 -0.4 -0.6 -0.6 MAX11626/MAX11628/MAX11632 fSAMPLE = 300ksps -0.8 DNL (LSB) 0.4 0.2 INL (LSB) 0.4 0.4 -0.2 0 1024 2048 3072 OUTPUT CODE (DECIMAL) 4096 0 -0.2 -0.4 MAX11627/MAX11629/MAX11633 fSAMPLE = 300ksps -0.8 -0.6 MAX11626/MAX11628/MAX11632 fSAMPLE = 300ksps -0.8 -1.0 -1.0 -1.0 MAX11626 toc03 0.8 1.0 MAX11626 toc02 1.0 MAX11626 toc01 1.0 INL (LSB) DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE INTEGRAL NONLINEARITY vs. OUTPUT CODE INTEGRAL NONLINEARITY vs. OUTPUT CODE 0 1024 2048 3072 OUTPUT CODE (DECIMAL) 4096 0 1024 2048 3072 4096 OUTPUT CODE (DECIMAL) _______________________________________________________________________________________ 5 MAX11626–MAX11629/MAX11632/MAX11633 TIMING CHARACTERISTICS (Figure 1) Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) SINAD vs. FREQUENCY MAX11626/MAX11628/MAX11632 75 SINAD (dB) 0.4 0.2 0 -0.2 MAX11626/MAX11628/ MAX11632 90 70 SFDR (dB) 0.6 100 MAX11626 toc05 0.8 SFDR vs. FREQUENCY 80 MAX11626 toc04 1.0 MAX11627/MAX11629/MAX11633 65 80 MAX11627/MAX11629/MAX11633 70 60 -0.6 MAX11627/MAX11629/MAX11633 fSAMPLE = 300ksps -0.8 60 55 50 -1.0 0 1024 2048 3072 1 4096 10 1 10 FREQUENCY (kHz) OUTPUT CODE (DECIMAL) 100 FREQUENCY (kHz) SUPPLY CURRENT vs. SAMPLING RATE THD vs. FREQUENCY 3000 MAX11626 toc07 -50 -60 MAX11626/MAX11628/MAX11632 VDD = 5V 2500 MAX11627/MAX11629/MAX11633 2000 -70 IVDD (µA) THD (dB) 50 1000 100 MAX11626 toc08 -0.4 INTERNAL REFERENCE 1500 -80 1000 EXTERNAL REFERENCE -90 500 MAX11626/MAX11628/MAX11632 0 -100 10 100 1 1000 10 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SAMPLING RATE MAX11627/MAX11629/MAX11633 VDD = 3V 1600 1400 INTERNAL REFERENCE 2400 2200 INTERNAL REFERENCE IDD (µA) 1200 IVDD (µA) 2600 MAX11626 toc09 1800 1000 100 SAMPLING RATE (ksps) FREQUENCY (kHz) MAX11626 toc10 1 1000 800 600 2000 1800 EXTERNAL REFERENCE 1600 EXTERNAL REFERENCE 1400 400 MAX11626/MAX11628/MAX11632 fSAMPLE = 300ksps 1200 200 1000 0 1 10 100 SAMPLING RATE (ksps) 6 MAX11626 toc06 DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE DNL (LSB) MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference 1000 4.75 4.85 4.95 5.05 5.15 VDD (V) _______________________________________________________________________________________ 5.25 1000 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL REFERENCE 0.8 1600 MAX11626 toc12 1800 MAX11626 toc11 2000 0.7 0.6 1400 IDD (µA) IDD (µA) 1200 EXTERNAL REFERENCE 1000 800 0.5 0.4 0.3 600 0.2 400 MAX11627/MAX11629/MAX11633 fSAMPLE = 300ksps 200 MAX11626/MAX11628/MAX11632 VDD = 5V 0.1 0 0 4.75 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 4.85 4.95 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 5.15 5.25 SUPPLY CURRENT vs. TEMPERATURE 0.4 INTERNAL REFERENCE 2200 IDD (µA) 0.3 MAX11626 toc14 2500 MAX11626 toc13 0.5 IDD (µA) 5.05 VDD (V) VDD (V) 1900 1600 0.2 EXTERNAL REFERENCE 1300 0.1 MAX11626/MAX11628/MAX11632 VDD = 5V fSAMPLE = 300ksps MAX11627/MAX11629/MAX11633 VDD = 3V 1000 0 -40 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 -15 10 35 60 TEMPERATURE (°C) SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 2.5 MAX11626 toc15 1800 INTERNAL REFERENCE 1600 85 MAX11626 toc16 VDD (V) MAX11626/MAX11628/MAX11632 VDD = 5V 2.0 MAX11627/MAX11629/MAX11633 VDD = 3V fSAMPLE = 300ksps 1200 IDD (µA) IDD (µA) 1400 1.5 1.0 1000 800 0.5 EXTERNAL REFERENCE 600 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX11626–MAX11629/MAX11632/MAX11633 Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 4.096 0.2 4.095 2.501 VREF (V) 4.097 0.4 2.502 MAX11626 toc19 4.098 VREF (V) 2.500 2.499 2.498 MAX11627/MAX11629/MAX11633 VDD = 3V MAX11626/MAX11628/MAX11632 VDD = 5V 4.094 35 60 85 2.497 4.75 4.85 4.95 5.05 5.15 TEMPERATURE (°C) VDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 4.11 2.51 VREF (V) 4.10 4.09 2.50 2.48 MAX11626/MAX11628/MAX11632 VDD = 5V 4.07 -15 10 35 60 85 0.4 -15 10 35 60 85 1.02 4.95 1.00 5.25 1.1 0.9 0.7 MAX11626/MAX11628/MAX11632 fSAMPLE = 300ksps MAX11627/MAX11629/MAX11633 fSAMPLE = 300ksps 0.5 -1.0 3.6 5.15 1.3 OFFSET ERROR (LSB) -0.2 -0.6 5.05 OFFSET ERROR vs. TEMPERATURE 0.2 MAX11627/MAX11629/MAX11633 fSAMPLE = 300ksps VDD (V) 4.85 1.5 MAX11626 toc24 0.6 OFFSET ERROR (LSB) 1.03 3.3 4.75 VDD (V) 1.0 MAX11626 toc23 1.04 3.0 MAX11626/MAX11628/MAX11632 fSAMPLE = 300ksps OFFSET ERROR vs. TEMPERATURE 1.05 2.7 -0.2 TEMPARATURE (°C) 1.06 1.01 0 -0.6 -40 OFFSET ERROR vs. SUPPLY VOLTAGE 1.07 0.2 -0.4 MAX11627/MAX11629/MAX11633 VDD = 3V TEMPARATURE (°C) 1.08 3.6 3.3 0.6 2.47 -40 3.0 OFFSET ERROR vs. SUPPLY VOLTAGE 2.49 4.08 2.7 VDD (V) 2.52 MAX11626 toc20 4.12 5.25 MAX11626 toc22 10 MAX11626 toc25 -15 OFFSET ERROR (LSB) -40 MAX11626 toc21 IDD (µA) 0.6 0 VREF (V) 4.099 MAX11626 toc18 MAX11627/MAX11629/MAX11633 VDD = 3V 0.8 8 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX11626 toc17 1.0 OFFSET ERROR (LSB) MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 12-Bit, 300ksps ADCs with FIFO and Internal Reference GAIN ERROR vs. SUPPLY VOLTAGE GAIN ERROR vs. SUPPLY VOLTAGE MAX11626 toc27 0.6 -0.1 0.5 GAIN ERROR (LSB) GAIN ERROR (LSB) 0 MAX11626 toc26 0.7 0.4 0.3 -0.2 -0.3 0.2 -0.4 MAX11626/MAX11628/MAX11632 fSAMPLE = 300ksps 0.1 0 MAX11627/MAX11629/MAX11633 -0.5 4.85 4.95 5.05 5.25 5.15 2.7 3.0 VDD (V) GAIN ERROR vs. TEMPERATURE 0.3 -0.2 -0.6 0.1 -0.1 -0.3 MAX11626/MAX11628/MAX11632 fSAMPLE = 300ksps -1.0 -15 10 35 TEMPERATURE (°C) 60 85 0 -2 -4 -6 -8 -10 -0.5 -40 2 SAMPLING ERROR (LSB) 0.2 MAX11627/MAX11629/MAX11633 fSAMPLE = 300ksps MAX11626 toc29 0.5 GAIN ERROR (LSB) GAIN ERROR (LSB) 0.6 SAMPLING ERROR vs. SOURCE IMPEDANCE GAIN ERROR vs. TEMPERATURE MAX11626 toc28 1.0 3.6 3.3 VDD (V) MAX11626 toc30 4.75 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 2 4 6 8 10 SOURCE IMPEDANCE (kΩ) _______________________________________________________________________________________ 9 MAX11626–MAX11629/MAX11632/MAX11633 Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.) MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Pin Description MAX11626 MAX11627 (4 CHANNELS) MAX11628 MAX11629 (8 CHANNELS) 5, 6, 7 — — N.C. — — 1–15 AIN0–AIN14 Analog Inputs — 1–7 — AIN0–AIN6 Analog Inputs 1–4 — — AIN0–AIN3 Analog Inputs — — 16 CNVST/AIN15 Active-Low Conversion Start Input/Analog Input 15. See Table 3 for details on programming the setup register. — 8 — CNVST/AIN7 Active-Low Conversion Start Input/Analog Input 7. See Table 3 for details on programming the setup register. 8 — — CNVST Active-Low Conversion Start Input. See Table 3 for details on programming the setup register. 9 9 17 REF Reference Input. Bypass to GND with a 0.1µF capacitor. 10 10 18 GND Ground 11 11 19 VDD Power Input. Bypass to GND with a 0.1µF capacitor. 12 12 20 CS Active-Low Chip-Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high impedance. 13 13 21 SCLK Serial Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40% to 60%.) See Table 3 for details on programming the clock mode. 14 14 22 DIN Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK. 15 15 23 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is connected to VDD. 16 16 24 EOC End of Conversion Output. Data is valid after EOC pulls low. 10 MAX11632 MAX11633 (16 CHANNELS) NAME FUNCTION No Connection. Not internally connected. ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with FIFO and Internal Reference MAX11626–MAX11629/MAX11632/MAX11633 CS tCP tCH tCSS0 tCSH1 tCL tCSH0 tCSS1 SCLK tDH tDS DIN tDOT tDOD tDOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK SERIAL INTERFACE OSCILLATOR CONTROL DOUT EOC CNVST AIN1 AIN2 T/H AIN15 12-BIT SAR ADC FIFO AND ACCUMULATOR INTERNAL REFERENCE REF MAX11626–MAX11629/MAX11632/MAX11633 Figure 2. Functional Diagram Detailed Description The MAX11626–MAX11629/MAX11632/MAX11633 are low-power, serial-output, multichannel ADCs with FIFO capability for system monitoring, process-control, and instrumentation applications. These 12-bit ADCs have internal track and hold (T/H) circuitry supporting singleended inputs. Data is converted from analog voltage sources in a variety of channel and data-acquisition configurations. Microprocessor (µP) control is made easy through a 3-wire SPI-/QSPI-/MICROWIRE-compatible serial interface. Figure 2 shows a simplified functional diagram of the MAX11626–MAX11629/MAX11632/MAX11633 internal architecture. The MAX11632/MAX11633 have 16 single-ended analog input channels. The MAX11628/ MAX11629 have 8 single-ended analog input channels. The MAX11626/MAX11627 have 4 single-ended analog input channels. ______________________________________________________________________________________ 11 MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Converter Operation The MAX11626–MAX11629/MAX11632/MAX11633 ADCs use a successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert voltage signals into a 12-bit digital result. This single-ended configuration supports unipolar signal ranges. Input Bandwidth The ADC’s input-tracking circuitry has a 1MHz smallsignal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. Analog Input Protection Internal ESD protection diodes clamp all pins to VDD and GND, allowing the inputs to swing from (GND 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than GND by 50mV. If an off-channel analog input voltage exceeds the supplies, limit the input current to 2mA. 3-Wire Serial Interface The MAX11626–MAX11629/MAX11632/MAX11633 feature a serial interface compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, ensure the CPU serial interface runs in master mode so it generates the serial clock signal. Select the SCLK frequency of 10MHz or less, and set clock polarity (CPOL) and phase (CPHA) in the µP control registers to the same value. The MAX11626–MAX11629/MAX11632/MAX11633 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch input data at DIN on the rising edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK. Results are output in binary format. Serial communication always begins with an 8-bit input data byte (MSB first) loaded from DIN. A high-to-low transition on CS initiates the data input operation. The input data byte and the subsequent data bytes are clocked from DIN into the serial interface on the rising edge of SCLK. Tables 1–5 detail the register descriptions. Bits 5 and 4, CKSEL1 and CKSEL0, respectively, control the clock modes in the setup register (see Table 3). Choose between four different clock modes for various ways to start a conversion and determine whether the acquisitions are internally or externally timed. Select clock mode 00 to configure CNVST/AIN_ to act as a conversion start and use it to request the programmed, internally timed conversions without tying up the serial 12 bus. In clock mode 01, use CNVST to request conversions one channel at a time, controlling the sampling speed without tying up the serial bus. Request and start internally timed conversions through the serial interface by writing to the conversion register in the default clock mode 10. Use clock mode 11 with SCLK up to 4.8MHz for externally timed acquisitions to achieve sampling rates up to 300ksps. Clock mode 11 disables scanning and averaging. See Figures 4–7 for timing specifications and how to begin a conversion. These devices feature an active-low, end-of-conversion output. EOC goes low when the ADC completes the last requested operation and is waiting for the next input data byte (for clock modes 00 and 10). In clock mode 01, EOC goes low after the ADC completes each requested operation. EOC goes high when CS or CNVST goes low. EOC is always high in clock mode 11. Single-Ended Inputs The single-ended analog input conversion modes can be configured by writing to the setup register (see Table 3). Single-ended conversions are internally referenced to GND (see Figure 3). AIN0–AIN3 are available on the MAX11626–MAX11629/ MAX11632/MAX11633. AIN4–AIN7 are only available on the MAX11628–MAX11633. AIN8–AIN15 are only available on the MAX11632/MAX11633. See Tables 2–5 for more details on configuring the inputs. For the inputs that can be configured as CNVST or an analog input, only one can be used at a time. Unipolar The MAX11626–MAX11629/MAX11632/MAX11633 always operate in unipolar mode. The analog inputs are internally referenced to GND with a full-scale input range from 0 to VREF. REF GND DAC AIN0-AIN15 CIN+ COMPARATOR + HOLD CINGND HOLD VDD/2 Figure 3. Equivalent Input Circuit ______________________________________________________________________________________ HOLD 12-Bit, 300ksps ADCs with FIFO and Internal Reference tACQ = 9 x (RS + RIN) x 24pF + tPWR where RIN = 1.5kΩ, RS is the source impedance of the input signal, and tPWR = 1µs, the power-up time of the device. The varying power-up times are detailed in the explanation of the clock mode conversions. tACQ is never less than 1.4µs, and any source impedance below 300Ω does not significantly affect the ADC’s AC performance. A high-impedance source can be accommodated either by lengthening t ACQ or by placing a 1µF capacitor between the positive and negative analog inputs. Internal FIFO The MAX11626–MAX11629/MAX11632/MAX11633 contain a FIFO buffer that can hold up to 16 ADC results. This allows the ADC to handle multiple internally clocked conversions, without tying up the serial bus. If the FIFO is filled and further conversions are requested without reading from the FIFO, the oldest ADC results are overwritten by the new ADC results. Each result contains 2 bytes, with the MSB preceded by four leading zeros. After each falling edge of CS, the oldest available byte of data is available at DOUT, MSB first. When the FIFO is empty, DOUT is zero. Internal Clock The MAX11626–MAX11629/MAX11632/MAX11633 operate from an internal oscillator, which is accurate within 10% of the 4.4MHz nominal clock rate. The internal oscillator is active in clock modes 00, 01, and 10. Read out the data at clock speeds up to 10MHz. See Figures 4–7 for details on timing specifications and starting a conversion. Applications Information Register Descriptions The MAX11626–MAX11629/MAX11632/MAX11633 communicate between the internal registers and the external circuitry through the SPI-/QSPI-compatible serial interface. Table 1 details the registers and the bit names. Tables 2–5 show the various functions within the conversion register, setup register, averaging register, and reset register. Conversion Time Calculations The conversion time for each scan is based on a number of different factors: conversion time per sample, samples per result, results per scan, and if the external reference is in use. Use the following formula to calculate the total conversion time for an internally timed conversion in clock modes 00 and 10 (see the Electrical Characteristics section as applicable): Total Conversion Time = tCNV x nAVG x nRESULT + tRP where tCNV = tACQ (max) + tCONV (max). nAVG = samples per result (amount of averaging). nRESULT = number of FIFO results requested; determined by the number of channels being scanned or by NSCAN1, NSCAN0. tRP = internal reference wake-up; set to zero if internal reference is already powered up or external reference is being used . In clock mode 01, the total conversion time depends on how long CNVST is held low or high, including any time required to turn on the internal reference. Conversion time in externally clocked mode (CKSEL1, CKSEL0 = 11) depends on the SCLK period and how long CS is held high between each set of eight SCLK cycles. In clock mode 01, the total conversion time does not include the time required to turn on the internal reference. Table 1. Input Data Byte (MSB First) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Conversion REGISTER NAME 1 CHSEL3 CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 X Setup 0 1 CKSEL1 CKSEL0 REFSEL1 REFSEL0 X X Averaging 0 0 1 AVGON NAVG1 NAVG0 NSCAN1 NSCAN0 Reset 0 0 0 1 RESET X X X X = Don’t care. ______________________________________________________________________________________ 13 MAX11626–MAX11629/MAX11632/MAX11633 True Differential Analog Input T/H The equivalent circuit of Figure 3 shows the MAX11626–MAX11629/MAX11632/MAX11633’s input architecture. In track mode, a positive input capacitor is connected to AIN0–AIN15. A negative input capacitor is connected to GND. For external T/H timing, use clock mode 01. After the T/H enters hold mode, the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal’s source impedance is high, the required acquisition time lengthens. The acquisition time, tACQ, is the maximum time needed for a signal to be acquired, plus the power-up time. It is calculated by the following equation: MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Conversion Register Select active analog input channels per scan and scan modes by writing to the conversion register. Table 2 details channel selection and the four scan modes. Request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01. A conversion is not performed if it is requested on a channel that has been configured as CNVST. Do not request conversions on channels 8–15 on the MAX11626–MAX11629. Set CHSEL3:CHSEL0 to the lower channel’s binary values. Select scan mode 00 or 01 to return one result per single-ended channel within the requested range. Select scan mode 10 to scan a single input channel numerous times, depending on NSCAN1 and NSCAN0 in the averaging register (Table 4). Select scan mode 11 to return only one result from a single channel. Table 2. Conversion Register* BIT NAME — 7 (MSB) Set to 1 to select conversion register. 6 Analog input channel select. CHSEL2 5 Analog input channel select. CHSEL1 4 Analog input channel select. CHSEL0 3 Analog input channel select. SCAN1 2 Scan mode select. 1 Scan mode select. SCAN0 — 0 (LSB) Don’t care. *See below for bit details. CHSEL3 CHSEL2 CHSEL1 CHSEL0 SELECTED CHANNEL (N) 0 0 0 0 AIN0 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AIN8 1 0 0 1 AIN9 1 0 1 0 AIN10 1 0 1 1 AIN11 1 1 0 0 AIN12 1 1 0 1 AIN13 1 1 1 0 AIN14 1 1 1 1 AIN15 Averaging Register Write to the averaging register to configure the ADC to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans. Table 2 details the four scan modes available in the conversion register. All four scan modes allow averaging as long as the AVGON bit, bit 4 in the averaging register, is set to 1. Select scan mode 10 to scan the same channel multiple times. Clock mode 11 disables averaging. 14 FUNCTION CHSEL3 Setup Register Write a byte to the setup register to configure the clock, reference, and power-down modes. Table 3 details the bits in the setup register. Bits 5 and 4 (CKSEL1 and CKSEL0) control the clock mode, acquisition and sampling, and the conversion start. Bits 3 and 2 (REFSEL1 and REFSEL0) control internal or external reference use. Reset Register Write to the reset register (as shown in Table 5) to clear the FIFO or to reset all registers to their default states. Set the RESET bit to 1 to reset the FIFO. Set the reset bit to zero to return the MAX11626–MAX11629/ MAX11632/MAX11633 to the default power-up state. BIT SCAN1 SCAN0 SCAN MODE (CHANNEL N IS SELECTED BY BITS CHSEL3–CHSEL0) 0 0 Scans channels 0 through N. 0 1 Scans channels N through the highest numbered channel. 1 0 Scans channel N repeatedly. The averaging register sets the number of results. 1 1 No scan. Converts channel N once only. ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with FIFO and Internal Reference BIT NAME BIT — 7 (MSB) Set to 0 to select setup register. — 6 Set to 1 to select setup register. CKSEL1 5 Clock mode and CNVST configuration. Resets to 1 at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference mode configuration. MAX11626–MAX11629/MAX11632/MAX11633 Table 3. Setup Register* FUNCTION REFSEL0 2 Reference mode configuration. — 1 Don’t care. — 0 (LSB) Don’t care. *See below for bit details. CKSEL1 CKSEL0 CONVERSION CLOCK ACQUISITION/SAMPLING CNVST CONFIGURATION 0 0 Internal Internally timed CNVST 0 1 Internal Externally timed through CNVST CNVST 1 0 Internal Internally timed AIN15/AIN11/AIN7* 1 1 External (4.8MHz max) Externally timed through SCLK AIN15/AIN11/AIN7* *For the MAX11626/MAX11627, CNVST has its own dedicated pin. REFSEL1 REFSEL0 VOLTAGE REFERENCE AutoShutdown 0 0 Internal Reference off after scan; need wake-up delay. 0 1 External Reference off; no wake-up delay. 1 0 Internal Reference always on; no wake-up delay. 1 1 Reserved Reserved. Do not use. ______________________________________________________________________________________ 15 MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Table 4. Averaging Register* BIT NAME BIT — 7 (MSB) Set to 0 to select averaging register. FUNCTION — 6 Set to 0 to select averaging register. Set to 1 to select averaging register. — 5 AVGON 4 Set to 1 to turn averaging on. Set to 0 to turn averaging off. NAVG1 3 Configures the number of conversions for single-channel scans. NAVG0 2 Configures the number of conversions for single-channel scans. NSCAN1 1 Single-channel scan count. (Scan mode 10 only.) NSCAN0 0 (LSB) Single-channel scan count. (Scan mode 10 only.) *See below for bit details. AVGON NAVG1 NAVG0 FUNCTION 0 x x Performs one conversion for each requested result. 1 0 0 Performs four conversions and returns the average for each requested result. 1 0 1 Performs eight conversions and returns the average for each requested result. 1 1 0 Performs 16 conversions and returns the average for each requested result. 1 1 1 Performs 32 conversions and returns the average for each requested result. NSCAN1 NSCAN0 0 0 Scans channel N and returns four results. 0 1 Scans channel N and returns eight results. 1 0 Scans channel N and returns 12 results. 1 1 Scans channel N and returns 16 results. FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED) Table 5. Reset Register BIT NAME BIT — 7 (MSB) Set to 0 to select reset register. — 6 Set to 0 to select reset register. — 5 Set to 0 to select reset register. — 4 Set to 1 to select reset register. RESET 3 Set to 0 to reset all registers. Set to 1 to clear the FIFO only. x 2 Reserved. Don’t care. x 1 Reserved. Don’t care. x 0 (LSB) Reserved. Don’t care. 16 FUNCTION ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with FIFO and Internal Reference Output Data Format Figures 4–7 illustrate the conversion timing for the MAX11626–MAX11629/MAX11632/MAX11633. The 12-bit conversion result is output in MSB-first format with four leading zeros. DIN data is latched into the serial interface on the rising edge of SCLK. Data on DOUT transitions on the falling edge of SCLK. Conversions in clock modes 00 and 01 are initiated by CNVST. Conversions in clock modes 10 and 11 are initiated by writing an input data byte to the conversion register. Data output is binary. Internally Timed Acquisitions and Conversions Using CNVST Performing Conversions in Clock Mode 00 In clock mode 00, the wake-up, acquisition, conversion, and shutdown sequences are initiated through CNVST and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read out later. See Figure 4 for clock mode 00 timing. Initiate a scan by setting CNVST low for at least 40ns before pulling it high again. The MAX11626–MAX11629/ MAX11632/MAX11633 then wake up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. Wait until EOC goes low before pulling CS low to communicate with the serial interface. EOC stays low until CS or CNVST is pulled low again. Do not initiate a second CNVST before EOC goes low; otherwise, the FIFO can become corrupted. Externally Timed Acquisitions and Internally Timed Conversions with CNVST Performing Conversions in Clock Mode 01 In clock mode 01, conversions are requested one at a time using CNVST and performed automatically using the internal oscillator. See Figure 5 for clock mode 01 timing. Setting CNVST low begins an acquisition, wakes up the ADC, and places it in track mode. Hold CNVST low for at least 1.4µs to complete the acquisition. If the internal reference needs to wake up, an additional 65µs is required for the internal reference to power up. Set CNVST high to begin a conversion. After the conversion is complete, the ADC shuts down and pulls EOC low. EOC stays low until CS or CNVST is pulled low again. Wait until EOC goes low before pulling CS or CNVST low. If averaging is turned on, multiple CNVST pulses need to be performed before a result is written to the FIFO. Once the proper number of conversions has been performed to generate an averaged FIFO result, as specified by the averaging register, the scan logic automatically switches the analog input multiplexer to the next-requested channel. The result is available on DOUT once EOC has been pulled low. CNVST (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION. Figure 4. Clock Mode 00 Timing ______________________________________________________________________________________ 17 MAX11626–MAX11629/MAX11632/MAX11633 Power-Up Default State The MAX11626–MAX11629/MAX11632/MAX11633 power up with all blocks in shutdown, including the reference. All registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (CKSEL1 = 1) MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference CNVST (CONVERSION2) (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT LSB1 MSB1 MSB2 EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 Timing (CONVERSION BYTE) DIN (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. Figure 6. Clock Mode 10 Timing Internally Timed Acquisitions and Conversions Using the Serial Interface Performing Conversions in Clock Mode 10 In clock mode 10, the wake-up, acquisition, conversion, and shutdown sequences are initiated by writing an input data byte to the conversion register, and are performed automatically using the internal oscillator. This is the default clock mode upon power-up. See Figure 6 for clock mode 10 timing. Initiate a scan by writing a byte to the conversion register. The MAX11626–MAX11629/MAX11632/MAX11633 then power up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is 18 complete, EOC is pulled low and the results are available in the FIFO. EOC stays low until CS is pulled low again. Externally Clocked Acquisitions and Conversions Using the Serial Interface Performing Conversions in Clock Mode 11 In clock mode 11, acquisitions and conversions are initiated by writing to the conversion register and are performed one at a time using the SCLK as the conversion clock. Scanning and averaging are disabled, and the conversion result is available at DOUT during the conversion. See Figure 7 for clock mode 11 timing. ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with FIFO and Internal Reference (ACQUISITION1) (ACQUISITION2) (CONVERSION1) CS SCLK DOUT MSB1 LSB1 MSB2 EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Timing Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles. If CS is pulsed high between the eight and ninth cycles, the pulse width must be less than 100µs. To continuously convert at 16 cycles per conversion, alternate 1 byte of zeros between each conversion byte. If reference mode 00 is requested, wait 65µs with CS high after writing the conversion byte to extend the acquisition and allow the internal reference to power up. OUTPUT CODE FULL-SCALE TRANSITION 11 . . . 111 11 . . . 110 11 . . . 101 FS = VREF + VCOM ZS = VCOM Partial Reads and Partial Writes If the first byte of an entry in the FIFO is partially read (CS is pulled high after fewer than eight SCLK cycles), the second byte of data that is read out contains the next 8 bits (not b7–b0). The remaining bits are lost for that entry. If the first byte of an entry in the FIFO is read out fully, but the second byte is read out partially, the rest of the entry is lost. The remaining data in the FIFO is uncorrupted and can be read out normally after taking CS low again, as long as the 4 leading bits (normally zeros) are ignored. Internal registers that are written partially through the SPI contain new values, starting at the MSB up to the point that the partial write is stopped. The part of the register that is not written contains previously written values. If CS is pulled low before EOC goes low, a conversion cannot be completed and the FIFO is corrupted. Transfer Function Figure 8 shows the unipolar transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = VREF/2.5V (MAX11627/MAX11629/MAX11633) and 1 LSB = VREF/ 4.096V (MAX11626/MAX11628/MAX11632). V 1 LSB = REF 4096 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 (COM) 2 3 INPUT VOLTAGE (LSB) FS FS - 3/2 LSB Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF Layout, Grounding, and Bypassing For best performance, use PCBs. Do not use wire wrap boards. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) signals parallel to one another or run digital lines underneath the MAX11626–MAX11629/MAX11632/MAX11633 package. High-frequency noise in the V DD power supply can affect performance. Bypass the VDD supply with a 0.1µF capacitor to GND, close to the VDD pin. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, connect a 10Ω resistor in series with the supply to improve power-supply filtering. ______________________________________________________________________________________ 19 MAX11626–MAX11629/MAX11632/MAX11633 (CONVERSION BYTE) DIN MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX11626–MAX11629/MAX11632/MAX11633 is measured using the end-point method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Delay Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD (dB) = 20 x log (SignalRMS/NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76)/6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: ⎛ ⎞ THD = 20 x log ⎜ ⎛⎝ V22 + V32 + V4 2 + V52 ⎞⎠ /V1⎟ ⎝ ⎠ where V1 is the fundamental amplitude, and V2–V5 are the amplitudes of the first five harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. 20 ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with FIFO and Internal Reference Chip Information PROCESS: BiCMOS TOP VIEW Package Information + AIN0 1 24 EOC AIN1 2 23 DOUT AIN2 3 22 DIN AIN3 4 21 SCLK AIN4 5 MAX11632 MAX11633 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 20 CS AIN5 6 19 VDD AIN6 7 18 GND AIN7 8 17 REF AIN8 9 16 CNVST/AIN15 AIN9 10 15 AIN14 AIN10 11 14 AIN13 AIN11 12 13 AIN12 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 QSOP E16+5 21-0055 90-0167 24 QSOP E24+1 21-0055 90-0172 QSOP ______________________________________________________________________________________ 21 MAX11626–MAX11629/MAX11632/MAX11633 Pin Configurations (continued) MAX11626–MAX11629/MAX11632/MAX11633 12-Bit, 300ksps ADCs with FIFO and Internal Reference Revision History REVISION NUMBER REVISION DATE 0 6/10 Initial release — 1 8/10 Initial release of MAX11628/MAX11629 and changed internal reference voltage 1 2 3/11 Added MAX11628 automotive qualified part to data sheet 1 3 10/11 Initial release of MAX11626/MAX11627 1 DESCRIPTION PAGES CHANGED Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.