Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9272 LOSW-C LO-C LI-C LG-C LOSW-D LO-D LI-D LG-D LOSW-E LO-E LI-E LG-E LOSW-F LO-F LI-F LG-F LOSW-G LO-G LI-G LG-G LNA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LOSW-H LO-H LI-H LG-H PDWN STBY VGA LNA VGA AAF 12-BIT ADC SERIAL LVDS DOUTA+ DOUTA– 12-BIT ADC SERIAL LVDS DOUTB+ DOUTB– 12-BIT ADC SERIAL LVDS DOUTC+ DOUTC– 12-BIT ADC SERIAL LVDS DOUTD+ DOUTD– 12-BIT ADC SERIAL LVDS DOUTE+ DOUTE– 12-BIT ADC SERIAL LVDS DOUTF+ DOUTF– 12-BIT ADC SERIAL LVDS DOUTG+ DOUTG– 12-BIT ADC SERIAL LVDS DOUTH+ DOUTH– REFERENCE SWITCH ARRAY DATA RATE MULTIPLIER LOSW-B LO-B LI-B LG-B AD9272 SERIAL PORT INTERFACE LOSW-A LO-A LI-A LG-A DRVDD FUNCTIONAL BLOCK DIAGRAM AVDD2 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise voltage = 0.75 nV/√Hz (gain = 21.3 dB) @ 5 MHz typical SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB Single-ended input; VIN maximum = 733 mV p-p/ 550 mV p-p/367 mV p-p Dual-mode active input impedance matching Bandwidth (BW) > 100 MHz Full-scale (FS) output = 4.4 V p-p differential Variable gain amplifier (VGA) Attenuator range = −42 dB to 0 dB SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB Linear-in-dB gain control Antialiasing filter (AAF) Programmable 2nd-order low-pass filter (LPF) from 8 MHz to 18 MHz Programmable high-pass filter (HPF) Analog-to-digital converter (ADC) 12 bits at 10 MSPS to 80 MSPS SNR = 70 dB SFDR = 75 dB Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data and frame clock outputs Includes an 8 × 8 differential crosspoint switch to support continuous wave (CW) Doppler Low power, 195 mW per channel at 12 bits/40 MSPS (TGC) 120 mW per channel in CW Doppler Flexible power-down modes Overload recovery in <10 ns Fast recovery from low power standby mode, <2 μs 100-lead TQFP AVDD1 FEATURES FCO+ FCO– DCO+ DCO– The AD9272 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a low noise preamplifier (LNA) with a variable gain amplifier (VGA), an antialiasing filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-todigital converter (ADC). Each channel features a variable gain range of 42 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 80 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical. SDIO CLK+ CLK– CSB SCLK VREF RBIAS GAIN– 07029-001 GENERAL DESCRIPTION GAIN+ Medical imaging/ultrasound Automotive radar CWD[7:0]+ AND CWD[7:0]– APPLICATIONS Figure 1. The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input-referred noise voltage is typically 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise voltage of the entire channel is 0.85 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is about 92 dB. In CW Doppler mode, the LNA output drives a transconductance amp that is switched through an 8 × 8 differential crosspoint switch. The switch is programmable through the SPI. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD9272 TABLE OF CONTENTS Features .............................................................................................. 1 Ultrasound .................................................................................. 21 Applications ....................................................................................... 1 Channel Overview ..................................................................... 22 General Description ......................................................................... 1 Input Overdrive .......................................................................... 25 Functional Block Diagram .............................................................. 1 CW Doppler Operation............................................................. 25 Revision History ............................................................................... 2 TGC Operation ........................................................................... 27 Product Highlights ........................................................................... 3 ADC ............................................................................................. 31 Specifications..................................................................................... 4 Clock Input Considerations ...................................................... 31 AC Specifications.......................................................................... 4 Serial Port Interface (SPI) .............................................................. 38 Digital Specifications ................................................................... 8 Hardware Interface..................................................................... 38 Switching Specifications .............................................................. 9 Memory Map .................................................................................. 40 Absolute Maximum Ratings.......................................................... 11 Reading the Memory Map Table .............................................. 40 Thermal Impedance ................................................................... 11 Reserved Locations .................................................................... 40 ESD Caution ................................................................................ 11 Default Values ............................................................................. 40 Pin Configuration and Function Descriptions ........................... 12 Logic Levels ................................................................................. 40 Typical Performance Characteristics ........................................... 15 Outline Dimensions ....................................................................... 44 Equivalent Circuits ......................................................................... 19 Ordering Guide .......................................................................... 44 Theory of Operation ...................................................................... 21 REVISION HISTORY 7/09—Rev. B to Rev. C Changes to Input Overload Protection Section and Figure 43 ....... 25 Changes to Digital Outputs and Timing Section and Changes to Figure 63 ...................................................................................... 33 Changes to Hardware Interface Section ...................................... 39 6/09—Rev. A to Rev. B Changes to Product Highlights Section......................................... 3 Changes to Table 1 ............................................................................ 4 Changes to Absolute Maximum Ratings Table ........................... 11 Changes to Figure 22 ...................................................................... 17 Changes to Figure 33 and Figure 34 ............................................. 20 Changes to Low Noise Amplifier (LNA) Section ....................... 22 Changes to Active Impedance Matching Section ....................... 23 Changes to Figure 39 ...................................................................... 23 Changes to LNA Noise Section ..................................................... 24 Changes to Figure 47 ...................................................................... 28 Changes to Figure 48 and Figure 49 ............................................. 29 Changes to CSB Pin Section.......................................................... 36 Changes to Reading the Memory Map Table Section................ 40 4/09—Revision A: Initial Version Rev. C | Page 2 of 44 AD9272 The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. Fabricated in an advanced CMOS process, the AD9272 is available in a 16 mm × 16 mm, RoHS-compliant, 100-lead TQFP. It is specified over the industrial temperature range of −40°C to +85°C. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided. PRODUCT HIGHLIGHTS Powering down individual channels is supported to increase battery life for portable applications. There is also a standby mode option that allows quick power-up for power cycling. In CW Doppler operation, the VGA, antialiasing filter (AAF), and ADC are powered down. The power of the time gain control (TGC) path scales with selectable speed grades. 1. 2. 3. 4. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the serial port interface. 5. 6. Rev. C | Page 3 of 44 Small Footprint. Eight channels are contained in a small, space-saving package. A full TGC path, ADC, and crosspoint switch are contained within a 100-lead, 16 mm × 16 mm TQFP. Low Power of 195 mW Per Channel at 40 MSPS. Integrated Crosspoint Switch. This switch allows numerous multichannel configuration options to enable the CW Doppler mode. Ease of Use. A data clock output (DCO±) operates up to 480 MHz and supports double data rate (DDR) operation. User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Integrated Second-Order Antialiasing Filter. This filter is placed between the VGA and the ADC and is programmable from 8 MHz to 18 MHz. AD9272 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, GAIN− = 0.8 V, AAF LPF cutoff = fSAMPLE/4.5, HPF = LPF cutoff/20.7 (default), full temperature, ANSI-644 LVDS mode, unless otherwise noted. Table 1. Parameter 1 LNA CHARACTERISTICS Gain Input Voltage Range Input Common Mode Input Resistance Input Capacitance −3 dB Bandwidth Input-Referred Noise Voltage Input Noise Current 1 dB Input Compression Point Noise Figure Active Termination Matched Unterminated FULL-CHANNEL (TGC) CHARACTERISTICS AAF Low-Pass Filter Cutoff -In Range AAF Low-Pass Filter Cutoff - Out of Range 3 AAF Bandwidth Tolerance -In Range Conditions Single-ended input to differential output Single-ended input to single-ended output LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB, LNA output limited to 4.4 V p-p differential output RFB = 250 Ω RFB = 500 Ω RFB = ∞ LI-x LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞ RFB = ∞ LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB, GAIN+ = 0 V LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB RS = 50 Ω, RFB = 200 Ω/ 250 Ω/350 Ω RFB = ∞ −3 dB, programmable −3 dB, programmable, AAF Bandwidth Tolerance Min AD9272-40 Typ Max Min AD9272-65 Typ Max Min AD9272-80 Typ Max Unit 15.6/17.9/21.3 15.6/17.9/21.3 15.6/17.9/21.3 dB 9.6/11.9/15.3 9.6/11.9/15.3 9.6/11.9/15.3 dB 733/550/367 733/550/367 733/550/367 mV p-p SE 2 0.9 0.9 0.9 V 50 100 15 22 100 0.98/0.86/0.75 50 100 15 22 100 0.98/0.86/0.75 50 100 15 22 100 0.98/0.86/0.75 Ω Ω kΩ pF MHz nV/√Hz 1 1.0/0.8/0.5 1 1.0/0.8/0.5 1 1.0/0.8/0.5 pA/√Hz mV p-p 4.8/4.1/3.2 4.8/4.1/3.2 4.8/4.0/3.2 dB 3.4/2.8/2.3 3.4/2.8/2.3 3.4/2.8/2.3 dB 8 to 18 8 to 18 8 to 18 MHz 5 to 8 and 18 to 35 5 to 8 and 18 to 35 5 to 8 and 18 to 35 MHz ±10 ±10 ±10 % Rev. C | Page 4 of 44 AD9272 Parameter 1 Group Delay Variation Input-Referred Noise Voltage Noise Figure Active Termination Matched Unterminated Correlated Noise Ratio Output Offset Signal-to-Noise Ratio (SNR) Harmonic Distortion Second Harmonic Third Harmonic Two-Tone IMD3 (2 × F1 − F2) Distortion Channel-to-Channel Crosstalk Channel-to-Channel Delay Variation PGA GAIN Conditions f = 1 MHz to 18 MHz, GAIN+ = 0 V to 1.6 V LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB, RFB = ∞ LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB Min RS = 50 Ω, RFB = 200 Ω/ 250 Ω/350 Ω RFB = ∞ No signal, correlated/ uncorrelated AD9272-40 Typ ±2 fIN = 5 MHz at −10 dBFS, GAIN+ =0V fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V fIN = 5 MHz at −10 dBFS, GAIN+ =0V fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V fIN1 = 5.0 MHz at −1 dBFS, fIN2 = 5.01 MHz at −21 dBFS, GAIN+ = 1.6 V, LNA gain = 21.3 dB fIN1 = 5.0 MHz at −1 dBFS Overrange condition 4 Full TGC path, fIN = 5 MHz, GAIN+ = 0 V to 1.6 V Differential input to differential output Min AD9272-65 Typ ±2 Max Min AD9272-80 Typ ±2 Max Unit ns 1.26/1.04/0.85 1.26/1.04/0.85 1.26/1.04/0.85 nV/√Hz 8.0/6.6/4.7 7.7/6.2/4.5 7.6/6.1/4.4 dB 4.7/3.7/2.8 −30 4.6/3.6/2.8 −30 4.5/3.6/2.7 −30 dB dB −35 fIN = 5 MHz at −10 dBFS, GAIN+ =0V fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V Max 65 +35 −35 64 63 LSB dBFS 57 56 54.5 dBFS −62 −58 −55 dBc −60 −61 −58 dBc −71 −60 −60 dBc −57 −55 −56 dBc −75 −75 −75 dBc −70 −70 −70 dB −65 −65 −65 dB 0.3 0.3 0.3 Degrees 21/24/27/30 21/24/27/30 21/24/27/30 dB Rev. C | Page 5 of 44 +35 −35 +35 AD9272 Parameter 1 GAIN ACCURACY Gain Law Conformance Error Linear Gain Error Channel-to-Channel Matching GAIN CONTROL INTERFACE Normal Operating Range Gain Range Scale Factor Response Time Gain+ Impedance Gain− Impedance CW DOPPLER MODE Transconductance (differential) Output Level Range (differential) Input-Referred Noise Voltage Input-Referred Dynamic Range Two-Tone IMD3 (2 × F1 − F2) Distortion Output DC Bias (single-ended) Maximum Output Swing (singleended) POWER SUPPLY AVDD1 AVDD2 DRVDD Conditions 25°C 0 V < GAIN+ < 0.16 V 0.16 V < GAIN+ < 1.44 V 1.44 V < GAIN+ < 1.6 V GAIN+ = 0.8 V, normalized for ideal AAF loss 0.16 V < GAIN+ < 1.44 V Min AD9272-40 Typ Min 1.5 −1.5 −1.5 −2.5 −1.5 42 dB change Single-ended Single-ended +1.5 1.7 2.7 1.7 Min +1.5 −1.5 Max −1.6 +1.6 −1.6 +1.6 0 dB dB 0.1 1.6 Unit dB −2.5 +1.5 0 AD9272-80 Typ 1.5 0.1 1.6 dB dB 1.6 V 42 42 42 dB 28.5 750 10 70 28.5 750 10 70 28.5 750 10 70 dB/V ns MΩ kΩ 5.4/7.3/10.9 5.4/7.3/10.9 5.4/7.3/10.9 mA/V 1.5 Per channel Max −2.5 0.1 GAIN+ = 0 V to 1.6 V AD9272-65 Typ 1.5 +1.5 0 LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB CW Doppler output pins LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞, RL = 675 Ω LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB, RS = 0 Ω, RFB = ∞ fIN1 = 5.0 MHz at −1 dBFS (FS at LNA input), fIN2 = 5.01 MHz at −21 dBFS (FS at LNA input), LNA gain = 21.3 dB Per channel Max 3.6 1.5 3.6 1.5 3.6 V 2.35/1.82/1.31 2.35/1.82/1.31 2.35/1.82/1.31 nV/√Hz 161/161/160 161/161/160 161/161/160 dBFS/√Hz −70 −70 −70 dBc 2.4 2.4 2.4 mA ±2 ±2 ±2 mA p-p 1.8 3.0 1.8 1.9 3.6 1.9 1.7 2.7 1.7 Rev. C | Page 6 of 44 1.8 3.0 1.8 1.9 3.6 1.9 1.7 2.7 1.7 1.8 3.0 1.8 1.9 3.6 1.9 V V V AD9272 Parameter 1 IAVDD1 IAVDD2 IDRVDD Total Power Dissipation Power-Down Dissipation Standby Power Dissipation Power Supply Rejection Ratio (PSRR) ADC RESOLUTION ADC REFERENCE Output Voltage Error Load Regulation Input Resistance Conditions Full-channel mode CW Doppler mode with four channels enabled Full-channel mode CW Doppler mode with four channels enabled Includes output drivers, fullchannel mode, no signal CW Doppler mode with four channels enabled VREF = 1 V At 1.0 mA, VREF = 1 V Min AD9272-40 Typ 210 Max Min AD9272-65 Typ 280 Max Min AD9272-80 Typ 335 Max Unit mA 32 32 32 mA 365 140 365 140 365 140 mA mA 49 1560 1713 475 51 1690 1860 475 52 1780 1975 475 mA mW mW 5 5 5 mW 175 200 210 mW 1.6 1.6 1.6 mV/V 12 12 12 Bits 2 ±20 2 2 mV mV 6 6 6 kΩ 1 ±20 ±20 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. SE = single-ended. 3 AAF settings < 5 MHz are out of range and not supported. 4 The overrange condition is specified as being 6 dB more than the full-scale input range. 2 Rev. C | Page 7 of 44 AD9272 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 2. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, STBY, SCLK) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO) 3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (DOUTx+, DOUTx−), IN ANSI-644 MODE1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (DOUTx+, DOUTx−), WITH LOW POWER, REDUCED SIGNAL OPTION1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) Temperature Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 0 Typ Max Unit CMOS/LVDS/LVPECL mV p-p V kΩ pF 1.2 20 1.5 3.6 0.3 V V kΩ pF 3.6 0.3 V V kΩ pF DRVDD + 0.3 0.3 V V kΩ pF 30 0.5 70 0.5 30 2 Full Full 1.79 0.05 V V 454 1.375 mV V 250 1.30 mV V LVDS Full Full 247 1.125 Offset binary LVDS Full Full 150 1.10 Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection. Rev. C | Page 8 of 44 AD9272 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 3. Parameter 1 CLOCK 2 Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO± Propagation Delay (tFCO) DCO± Propagation Delay (tCPD) 4 DCO± to Data Delay (tDATA)4 DCO± to FCO± Delay (tFRAME)4 Data-to-Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby), GAIN+ = 0.8 V Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Uncertainty (Jitter) Temp Min Full Full Full 10 Full Full Full Full Full Full Full Full (tSAMPLE/2) + 1.5 Typ Max Unit 80 MSPS ns ns (tSAMPLE/2) + 3.1 ns ps ps ns ns ps ps ps 6.25 6.25 (tSAMPLE/2) + 1.5 (tSAMPLE/24) − 300 (tSAMPLE/24) − 300 (tSAMPLE/2) + 2.3 300 300 (tSAMPLE/2) + 2.3 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) ±100 (tSAMPLE/2) + 3.1 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 ±350 25°C 25°C Full 2 1 8 μs ms Clock cycles 25°C <1 ps rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 Can be adjusted via the SPI. 3 Measurements were made using a part soldered to FR-4 material. 4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. Rev. C | Page 9 of 44 AD9272 ADC Timing Diagrams N–1 AIN N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD MSB N–8 D10 N–8 D9 N–8 D8 N–8 D7 N–8 D6 N–8 D5 N–8 D4 N–8 D3 N–8 D2 N–8 D1 N–8 D0 N–8 MSB N–7 D10 N–7 DOUTx+ 07029-002 tDATA DOUTx– Figure 2. 12-Bit Data Serial Stream (Default) N–1 AIN N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA DOUTx– D0 N–8 D1 N–8 D2 N–8 D3 N–8 D4 N–8 D5 N–8 D6 N–8 D7 N–8 D8 N–8 D9 N–8 D10 N–8 LSB N–7 D0 N–7 07029-004 LSB N–8 DOUTx+ Figure 3. 12-Bit Data Serial Stream, LSB First Rev. C | Page 10 of 44 AD9272 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Electrical AVDD1 AVDD2 DRVDD GND AVDD2 AVDD1 AVDD2 Digital Outputs (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) CLK+, CLK−, GAIN+,GAIN− LI-x, LO-x, LOSW-x CWDx−, CWDx+ PDWN, STBY, SCLK, CSB RBIAS, VREF, SDIO Environmental Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) With Respect To Rating GND GND GND GND AVDD1 DRVDD DRVDD GND −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +3.9 V −2.0 V to +2.0 V −2.0 V to +3.9 V −0.3 V to +2.0 V GND −0.3 V to +3.9 V LG-x GND GND GND GND −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL IMPEDANCE Table 5. Air Flow Velocity (m/sec) 0.0 1.0 2.5 1 θJA1 20.3 14.4 12.9 θJB N/A 7.6 N/A θJC N/A 4.7 N/A Unit °C/W °C/W °C/W θJA is for a 4-layer PCB with a solid ground plane (simulated). The exposed pad is soldered to the PCB. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 300°C Rev. C | Page 11 of 44 AD9272 76 LOSW-D 77 LO-D 78 CWD0– 79 CWD0+ 80 CWD1– 81 CWD1+ 82 CWD2– 83 CWD2+ 84 CWD3– 85 CWD3+ 86 AVDD2 87 GAIN– 88 GAIN+ 89 RBIAS 90 VREF 91 CWD4– 92 CWD4+ 93 CWD5– 94 CWD5+ 95 CWD6– 96 CWD6+ 97 CWD7– 98 CWD7+ 99 LO-E 100 LOSW-E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR LI-E 1 LI-D 74 LG-D AVDD2 3 73 AVDD2 AVDD1 4 72 AVDD1 71 LO-C 70 LOSW-C 69 LI-C 68 LG-C 67 AVDD2 AVDD1 10 66 AVDD1 LO-G 11 65 LO-B LOSW-G 12 64 LOSW-B LI-G 13 63 LI-B LG-G 14 62 LG-B AVDD2 15 61 AVDD2 AVDD1 16 60 AVDD1 LO-H 17 59 LO-A LOSW-H 18 58 LOSW-A LI-H 19 57 LI-A LG-H 20 56 LG-A AVDD2 21 55 AVDD2 AVDD1 22 54 AVDD1 CLK– 23 53 CSB CLK+ 24 52 SDIO AVDD1 25 51 SCLK EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) LO-F 5 LOSW-F 6 LI-F 7 AD9272 LG-F 8 AVDD1 50 PDWN 49 STBY 48 DRVDD 47 DOUTA+ 46 DOUTA– 45 DOUTB+ 44 DOUTB– 43 DOUTC+ 42 DOUTC– 41 DOUTD+ 40 DOUTD– 39 FCO+ 38 FCO– 37 DCO– 35 DOUTE+ 34 DOUTE– 33 DOUTF+ 32 DOUTF– 31 DOUTG+ 30 DOUTG– 29 DOUTH+ 28 DRVDD 26 DOUTH– 27 DCO+ 36 TOP VIEW (Not to Scale) AVDD2 9 NOTES 1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND. Figure 4. TQFP Pin Configuration Table 6. Pin Function Descriptions Pin No. 0 4, 10, 16, 22, 25, 50, 54, 60, 66, 72 3, 9, 15, 21, 55, 61, 67, 73, 86 26, 47 1 2 5 6 7 8 11 12 13 14 17 18 19 Name GND AVDD1 Description Ground (exposed paddle should be tied to a quiet analog ground) 1.8 V Analog Supply AVDD2 3.0 V Analog Supply DRVDD LI-E LG-E LO-F LOSW-F LI-F LG-F LO-G LOSW-G LI-G LG-G LO-H LOSW-H LI-H 1.8 V Digital Output Driver Supply LNA Analog Input for Channel E LNA Ground for Channel E LNA Analog Inverted Output for Channel F LNA Analog Switched Output for Channel F LNA Analog Input for Channel F LNA Ground for Channel F LNA Analog Inverted Output for Channel G LNA Analog Switched Output for Channel G LNA Analog Input for Channel G LNA Ground for Channel G LNA Analog Inverted Output for Channel H LNA Analog Switched Output for Channel H LNA Analog Input for Channel H Rev. C | Page 12 of 44 07029-005 75 LG-E 2 AD9272 Pin No. 20 23 24 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 48 49 51 52 53 56 57 58 59 62 63 64 65 68 69 70 71 74 75 76 77 78 79 80 81 82 83 84 85 87 Name LG-H CLK− CLK+ DOUTH− DOUTH+ DOUTG− DOUTG+ DOUTF− DOUTF+ DOUTE− DOUTE+ DCO− DCO+ FCO− FCO+ DOUTD− DOUTD+ DOUTC− DOUTC+ DOUTB− DOUTB+ DOUTA− DOUTA+ STBY PDWN SCLK SDIO CSB LG-A LI-A LOSW-A LO-A LG-B LI-B LOSW-B LO-B LG-C LI-C LOSW-C LO-C LG-D LI-D LOSW-D LO-D CWD0− CWD0+ CWD1− CWD1+ CWD2− CWD2+ CWD3− CWD3+ GAIN− Description LNA Ground for Channel H Clock Input Complement Clock Input True ADC H Digital Output Complement ADC H Digital Output True ADC G Digital Output Complement ADC G Digital Output True ADC F Digital Output Complement ADC F Digital Output True ADC E Digital Output Complement ADC E Digital Output True Digital Clock Output Complement Digital Clock Output True Frame Clock Digital Output Complement Frame Clock Digital Output True ADC D Digital Output Complement ADC D Digital Output True ADC C Digital Output Complement ADC C Digital Output True ADC B Digital Output Complement ADC B Digital Output True ADC A Digital Output Complement ADC A Digital Output True Standby Power-Down Full Power-Down Serial Clock Serial Data Input/Output Chip Select Bar LNA Ground for Channel A LNA Analog Input for Channel A LNA Analog Switched Output for Channel A LNA Analog Inverted Output for Channel A LNA Ground for Channel B LNA Analog Input for Channel B LNA Analog Switched Output for Channel B LNA Analog Inverted Output for Channel B LNA Ground for Channel C LNA Analog Input for Channel C LNA Analog Switched Output for Channel C LNA Analog Inverted Output for Channel C LNA Ground for Channel D LNA Analog Input for Channel D LNA Analog Switched Output for Channel D LNA Analog Inverted Output for Channel D CW Doppler Output Complement for Channel 0 CW Doppler Output True for Channel 0 CW Doppler Output Complement for Channel 1 CW Doppler Output True for Channel 1 CW Doppler Output Complement for Channel 2 CW Doppler Output True for Channel 2 CW Doppler Output Complement for Channel 3 CW Doppler Output True for Channel 3 Gain Control Voltage Input Complement Rev. C | Page 13 of 44 AD9272 Pin No. 88 89 90 91 92 93 94 95 96 97 98 99 100 Name GAIN+ RBIAS VREF CWD4− CWD4+ CWD5− CWD5+ CWD6− CWD6+ CWD7− CWD7+ LO-E LOSW-E Description Gain Control Voltage Input True External Resistor to Set the Internal ADC Core Bias Current Voltage Reference Input/Output CW Doppler Output Complement for Channel 4 CW Doppler Output True for Channel 4 CW Doppler Output Complement for Channel 5 CW Doppler Output True for Channel 5 CW Doppler Output Complement for Channel 6 CW Doppler Output True for Channel 6 CW Doppler Output Complement for Channel 7 CW Doppler Output True for Channel 7 LNA Analog Inverted Output for Channel E LNA Analog Switched Output for Channel E Rev. C | Page 14 of 44 AD9272 TYPICAL PERFORMANCE CHARACTERISTICS fSAMPLE = 40 MSPS, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, AAF LPF cutoff = fSAMPLE/4.5, HPF = LPF cutoff/20.7 (default), unless otherwise noted. 25 2.0 GAIN ERROR (dB) 1.0 –40°C 0.5 +25°C 0 +85°C –0.5 –1.0 0 0.2 0.4 0.6 0.8 1.0 GAIN+ (V) 1.2 1.4 15 10 5 0 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 –2.0 07029-114 –1.5 20 07029-186 PERCENTAGE OF UNITS (%) 1.5 1.6 GAIN ERROR (dB) Figure 5. Gain Error vs. GAIN+ at Three Temperatures Figure 8. Gain Error Histogram, GAIN+ = 1.44 V 25 15 10 5 15 10 5 0 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 20 07029-180 PERCENTAGE OF UNITS (%) 20 07029-184 PERCENTAGE OF UNITS (%) 25 –1.25 –1.00 –0.75 –0.50 –0.25 GAIN ERROR (dB) 0 0.25 0.50 0.75 1.00 1.25 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) Figure 6. Gain Error Histogram, GAIN+ = 0.16 V Figure 9. Gain Match Histogram, GAIN+ = 0.3 V 25 14 8 6 4 07029-185 2 0 20 15 10 5 07029-181 PERCENTAGE OF UNITS (%) 10 0 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 PERCENTAGE OF UNITS (%) 12 –1.25 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) GAIN ERROR (dB) Figure 10. Gain Match Histogram, GAIN+ = 1.3 V Figure 7. Gain Error Histogram, GAIN+ = 0.8 V Rev. C | Page 15 of 44 AD9272 –126 OUTPUT-REFERRED NOISE (dBFS/Hz) 450k NUMBER OF HITS 400k 350k 300k 250k 200k 150k 07029-115 100k 50k 0 –7 –6 –5 –4 –3 –2 –1 0 1 CODES 2 3 4 5 6 –128 LNA GAIN = 12× –130 –132 LNA GAIN = 8× –134 –136 LNA GAIN = 6× –138 –140 7 07029-117 500k 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) Figure 14. Short-Circuit, Output-Referred Noise vs. GAIN+ Figure 11. Output-Referred Noise Histogram, GAIN+ = 0 V 180k 64 160k SNR 62 60 120k SNR/SINAD (dBFS) NUMBER OF HITS 140k 100k 80k 60k 58 SINAD 56 54 40k –4 –3 –2 –1 0 1 CODES 2 3 4 5 6 50 0.4 7 07029-118 0 –7 –6 –5 52 07029-116 20k 0.5 0.6 0.7 0.8 0.9 1.0 1.1 GAIN+ (V) 1.4 1.5 1.6 0 1.8 1.6 AD9272-65 –5 AMPLITUDE (dBFS) 1.4 LNA GAIN = 15.6dB 1.2 1.0 LNA GAIN = 17.9dB 0.8 LNA GAIN = 21.3dB 0.6 0.4 AD9272-80 –10 AD9272-40 –15 0.2 1 2 3 4 5 6 7 FREQUENCY (MHz) 8 9 –25 10 07029-120 –20 07029-187 INPUT-REFERRED NOISE (nV/√Hz) 1.3 Figure 15. SNR/SINAD vs. GAIN+, AIN = −1 dBFS Figure 12. Output-Referred Noise Histogram, GAIN+ = 1.6 V 0 1.2 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 Figure 16. Antialiasing Filter (AAF) Pass-Band Response, LPF Cutoff = 1 × (1/4.5) × fSAMPLE Figure 13. Short-Circuit, Input-Referred Noise vs. Frequency, PGA Gain = 30 dB, GAIN+ = 1.6 V Rev. C | Page 16 of 44 40 AD9272 100 GAIN+ = 1.6V GAIN+ = 0.8V GAIN+ = 0V 75 50 07029-121 25 0 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 0 GAIN+ = 0.8V –60 GAIN+ = 0V –80 GAIN+ = 1.6V –100 –120 –50 –30 –20 ADC OUTPUT LEVEL (dBFS) –10 0 –20 –30 –40 GAIN+ = 0.4V –50 –60 GAIN+ = 1.6V –70 GAIN+ = 1.0V –80 –90 2 4 6 8 10 12 INPUT FREQUENCY (MHz) 14 –20 –40 –80 GAIN+ = 0.8V –100 –120 –40 16 Figure 18. Second-Order Harmonic Distortion vs. Frequency, AIN = −1 dBFS GAIN+ = 1.6V GAIN+ = 0V –60 07029-125 THIRD-ORDER HARMONIC DISTORTION (dBFS) –10 –35 –30 –25 –20 –15 –10 ADC OUTPUT LEVEL (dBFS) –5 0 Figure 21. Third-Order Harmonic Distortion vs. ADC Output Level 0 0 –10 –10 fIN2 = fIN1 + 0.01MHz AIN1 = –1dBFS, AIN2 = –21dBFS –20 –20 –30 IMD3 (dBFS) –30 GAIN+ = 0.4V –40 GAIN+ = 1.6V –50 –40 –50 –60 –60 2.3MHz 5MHz 8MHz –70 GAIN+ = 1.0V 0 2 4 6 8 10 12 INPUT FREQUENCY (MHz) –80 07029-123 –70 –80 –40 0 0 THIRD-ORDER HARMONIC DISTORTION (dBFS) –40 Figure 20. Second-Order Harmonic Distortion vs. ADC Output 07029-122 SECOND-ORDER HARMONIC DISTORTION (dBFS) Figure 17. Antialiasing Filter (AAF) Group Delay Response –20 14 –90 16 Figure 19. Third-Order Harmonic Distortion vs. Frequency, AIN = −1 dBFS Rev. C | Page 17 of 44 07029-126 GROUP DELAY (ns) 125 0 07029-124 SECOND-ORDER HARMONIC DISTORTION (dBFS) 150 0.4 0.6 0.8 1.0 GAIN+ (V) 1.2 Figure 22. IMD3 vs. GAIN+ 1.4 1.6 AD9272 0 fIN1 = 5.00MHz, fIN2 = 5.01MHz FUND2 LEVEL = FUND1 LEVEL – 20dB –20 –60 GAIN+ = 0V GAIN+ = 1.6V –80 –100 GAIN+ = 0.8V –120 –40 –35 –30 –25 –20 –15 FUND1 LEVEL (dBFS) –10 07029-127 IMD3 (dBFS) –40 –5 0 Figure 23. IMD3 vs. Fundamental 1 Amplitude Level Rev. C | Page 18 of 44 AD9272 EQUIVALENT CIRCUITS AVDDx VCM 15kΩ LI-x, LG-x 350Ω SDIO 07029-008 AVDDx 07029-073 30kΩ Figure 27. Equivalent SDIO Input Circuit Figure 24. Equivalent LNA Input Circuit DRVDD AVDDx V V DOUTx– DOUTx+ 07029-075 V V 07029-009 10Ω LO-x, LOSW-x DRGND Figure 28. Equivalent Digital Output Circuit Figure 25. Equivalent LNA Output Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ SCLK, PDWN, OR STBY 10Ω 30kΩ 07029-010 07029-007 CLK– 1kΩ Figure 26. Equivalent Clock Input Circuit Figure 29. Equivalent SCLK, PDWN, or STBY Input Circuit Rev. C | Page 19 of 44 AD9272 AVDDx 100Ω RBIAS AVDD2 50Ω 07029-074 07029-011 GAIN+ Figure 30. Equivalent RBIAS Circuit Figure 33. Equivalent GAIN+ Input Circuit AVDDx 70kΩ CSB 1kΩ 40Ω Figure 31. Equivalent CSB Input Circuit Figure 34. Equivalent GAIN− Input Circuit CWDx+, CWDx– 10Ω +0.5V 07029-076 07029-014 VREF 6kΩ +0.5V 07029-176 07029-012 GAIN– Figure 32. Equivalent VREF Circuit Figure 35. Equivalent CWDx± Output Circuit Rev. C | Page 20 of 44 AD9272 THEORY OF OPERATION following the TGC amplifier, and then beam forming is accomplished digitally. ULTRASOUND The primary application for the AD9272 is medical ultrasound. Figure 36 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution. The ADC resolution of 12 bits with up to 80 MSPS sampling satisfies the requirements of both general-purpose and highend systems. Power conservation and low cost are two of the most important factors in low-end and portable ultrasound machines, and the AD9272 is designed to meet these criteria. Key requirements in an ultrasound signal chain are very low noise, active input termination, fast overload recovery, low power, and differential drive to an ADC. Because ultrasound machines use beam-forming techniques requiring large binaryweighted numbers (for example, 32 to 512) of channels, using the lowest power at the lowest possible noise is of chief importance. For additional information regarding ultrasound systems, refer to “How Ultrasound System Considerations Influence Front-End Component Choice,” Analog Dialogue, Volume 36, Number 1, May–July 2002, and “The AD9271—A Revolutionary Solution for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 3, July 2007. Most modern machines use digital beam forming. In this technique, the signal is converted to digital format immediately Tx HV AMPs BEAM-FORMER CENTRAL CONTROL Tx BEAM FORMER MULTICHANNELS AD9272 HV MUX/ DEMUX T/R SWITCHES LNA ADC VGA AAF Rx BEAM FORMER (B AND F MODES) CW BIDIRECTIONAL CABLE CW (ANALOG) BEAM FORMER SPECTRAL DOPPLER PROCESSING MODE AUDIO OUTPUT Figure 36. Simplified Ultrasound System Block Diagram Rev. C | Page 21 of 44 IMAGE AND MOTION PROCESSING (B MODE) COLOR DOPPLER (PW) PROCESSING (F MODE) DISPLAY 07029-077 TRANSDUCER ARRAY 128, 256, ... ELEMENTS AD9272 RFB1 LO-x CFB R FB2 LOSW-x CWD[7:0]– LI-x ATTENUATOR –42dB TO 0dB LNA CLG POSTAMP FILTER PIPELINE ADC SERIAL LVDS LG-x 15.6dB, 17.9dB, 21.3dB GAIN+ GAIN INTERPOLATOR 21dB 24dB, 27dB, 30dB DOUTx+ DOUTx– AD9272 07029-071 CSH GAIN– TRANSDUCER T/R SWITCH C S CWD[7:0]+ SWITCH ARRAY gm Figure 37. Simplified Block Diagram of a Single Channel CHANNEL OVERVIEW Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides useradjustable input impedance termination. The CW Doppler path includes a transconductance amplifier and a crosspoint switch. The TGC path includes a differential X-AMP® VGA, an antialiasing filter, and an ADC. Figure 37 shows a simplified block diagram with external components. The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNA is designed to be driven from a single-ended signal source. Low Noise Amplifier (LNA) Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input impedance matching. A simplified schematic of the LNA is shown in Figure 38. LI-x is capacitively coupled to the source. An on-chip bias generator establishes dc input bias voltages of around 0.9 V and centers the output common-mode levels at 1.5 V (AVDD2 divided by 2). A capacitor, CLG, of the same value as the input coupling capacitor, CS, is connected from the LG-x pin to ground. CFB VO+ RFB1 RFB2 V O– LOSW-x LO-x VCM LI-x CSH Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low input-referred noise voltage of 0.75 nV/√Hz (at a gain of 21.3 dB). This is achieved with a current consumption of only 27 mA per channel (80 mW). On-chip resistor matching results in precise singleended gains, which are critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low second-order harmonic distortion is particularly important in second harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third-order distortion. Recommendation It is highly recommended that the LG-x pins form a Kelvin type connection to the input or probe connection ground. Simply connecting the LG pin to ground near the device can allow differences in potential to be amplified through the LNA. This generally shows up as a dc offset voltage that can vary from channel to channel and part to part given the application and layout of the PCB (see Figure 38). LG-x CLG 07029-101 TRANSDUCER T/R SWITCH CS VCM The LNA supports differential output voltages as high as 4.4 V p-p with positive and negative excursions of ±1.1 V from a commonmode voltage of 1.5 V. The LNA differential gain sets the maximum input signal before saturation. One of three gains is set through the SPI. The corresponding full-scale input for the gain settings of 6, 8, and 12 is 733 mV p-p, 550 mV p-p, and 367 mV p-p, respectively. Overload protection ensures quick recovery time from large input voltages. Because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection. Figure 38. Simplified LNA Schematic Rev. C | Page 22 of 44 AD9272 1k Active Impedance Matching R FB A (1 + ) 2 RS = 200Ω, RFB = 800Ω 100 RS = 50Ω, RFB = 200Ω, CSH = 70pF (1) 10 100k Because the amplifier has a gain of 8× from its input to its differential output, it is important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the gain of the amplifier or 12.1 dB (4×). The input resistance is reduced by an internal bias resistor of 15 kΩ in parallel with the source resistance connected to Pin LI-x, with Pin LG-x ac grounded. Equation 2 can be used to calculate the needed RFB for a desired RIN, even for higher values of RIN. R FB || 15 k Ω (1 + 3) (2) For example, to set RIN to 200 Ω, the value of RFB must be 1000 Ω. If the simplified equation (Equation 2) is used to calculate RIN, the value is 188 Ω, resulting in a gain error less than 0.6 dB. Some factors, such as the presence of a dynamic source resistance, might influence the absolute gain accuracy more significantly. At higher frequencies, the input capacitance of the LNA must be considered. The user must determine the level of matching accuracy and adjust RFB accordingly. The bandwidth (BW) of the LNA is greater than 100 MHz. Ultimately, the BW of the LNA limits the accuracy of the synthesized RIN. For RIN = RS up to about 200 Ω, the best match is between 100 kHz and 10 MHz, where the lower frequency limit is determined by the size of the ac-coupling capacitors, and the upper limit is determined by the LNA BW. Furthermore, the input capacitance and RS limit the BW at higher frequencies. Figure 39 shows RIN vs. frequency for various values of RFB. 1M 10M 100M FREQUENCY (Hz) where A/2 is the single-ended gain or the gain from the LI-x inputs to the LO-x outputs, and RFB is the resulting impedance of the RFB1 and RFB2 combination (see Figure 38). R IN = RS = 100Ω, RFB = 400Ω, CSH = 20pF 07029-188 R IN = RS = 500Ω, RFB = 2kΩ INPUT RESISTANCE (Ω) The LNA consists of a single-ended voltage gain amplifier with differential outputs, and the negative output is externally available. For example, with a fixed gain of 8× (17.9 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, LO-x, and the positive input pin, LI-x. This is a well known technique used for interfacing multiple probe impedances to a single system. The input resistance is shown in Equation 1. Figure 39. RIN vs. Frequency for Various Values of RFB (Effects of RS and CSH Are Also Shown) Note that at the lowest value (50 Ω), RIN peaks at frequencies greater than 10 MHz. This is due to the BW roll-off of the LNA, as mentioned previously. However, as can be seen for larger RIN values, parasitic capacitance starts rolling off the signal BW before the LNA can produce peaking. CSH further degrades the match; therefore, CSH should not be used for values of RIN that are greater than 100 Ω. Table 7 lists the recommended values for RFB and CSH in terms of RIN. CFB is needed in series with RFB because the dc levels at Pin LO-x and Pin LI-x are unequal. Table 7. Active Termination External Component Values LNA Gain (dB) 15.6 17.9 21.3 15.6 17.9 21.3 15.6 17.9 21.3 Rev. C | Page 23 of 44 RIN (Ω) 50 50 50 100 100 100 200 200 200 RFB (Ω) 200 250 350 400 500 700 800 1000 1400 Minimum CSH (pF) 90 70 50 30 20 10 N/A N/A N/A BW (MHz) 57 69 88 57 69 88 72 72 72 AD9272 LNA Noise The short-circuit noise voltage (input-referred noise) is an important limit on system performance. The short-circuit input-referred noise voltage for the LNA is 0.85 nV/√Hz at a gain of 21.3 dB, including the VGA noise at a VGA postamp gain of 27 dB. These measurements, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance of the configurations shown in Figure 40. RS LI-x UNTERMINATED RIN + Figure 41 shows the relative noise figure performance. In this graph, the input impedance was swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 Ω are 7.3 dB, 4.2 dB, and 2.8 dB for the resistive termination, active termination, and unterminated configurations, respectively. The noise figures for 200 Ω are 4.5 dB, 1.7 dB, and 1 dB, respectively. Figure 42 shows the noise figure as it relates to RS for various values of RIN, which is helpful for design purposes. 12.0 10.5 VOUT – NOISE FIGURE (dB) 9.0 RESISTIVE TERMINATION RS LI-x RIN + RS VOUT – RESISTIVE TERMINATION 7.5 6.0 4.5 3.0 LI-x 0 + VOUT 07029-182 1.5 IN RS ACTIVE TERMINATION UNTERMINATED ACTIVE IMPEDANCE MATCH RFB R 10 – 8 Figure 40. Input Configurations RIN = 50Ω RIN = 75Ω RIN = 100Ω RIN = 200Ω UNTERMINATED 7 The main purpose of input impedance matching is to improve the transient response of the system. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the input voltage noise generator of the LNA. With active impedance matching, however, the contributions of both are smaller (by a factor of 1/(1 + LNA Gain)) than they would be for resistive termination. Rev. C | Page 24 of 44 6 NOISE FIGURE (dB) Figure 41 and Figure 42 are simulations of noise figure vs. RS results using these configurations and an input-referred noise voltage of 3.8 nV/√Hz for the VGA. Unterminated (RFB = ∞) operation exhibits the lowest equivalent input noise and noise figure. Figure 42 shows the noise figure vs. source resistance rising at low RS—where the LNA voltage noise is large compared with the source noise—and at high RS due to the noise contribution from RFB. The lowest NF is achieved when RS matches RIN. 5 4 3 2 1 0 07029-183 1 + A/2 1k Figure 41. Noise Figure vs. RS for Resistive Termination, Active Termination Matched, and Unterminated Inputs, VGAIN = 0.8 V 07029-104 RIN = RFB 100 RS (Ω) 10 100 RS (Ω) Figure 42. Noise Figure vs. RS for Various Fixed Values of RIN, Active Termination Matched Inputs, VGAIN = 0.8 V 1k AD9272 INPUT OVERDRIVE CW DOPPLER OPERATION Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event. Modern ultrasound machines used for medical applications employ a 2N binary array of receivers for beam forming, with typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When used in multiples, the desired signals from each channel can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), and the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beam-former design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole. Input Overload Protection As with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages. In Figure 43, a simplified ultrasound transducer interface is shown. A common transducer element serves the dual functions of transmitting and receiving ultrasound energy. During the transmitting phase, high voltage pulses are applied to the ceramic elements. A typical transmit/receive (T/R) switch can consist of four high voltage diodes in a bridge configuration. Although the diodes ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and the resulting leakage transients imposed on the LI-x inputs can be problematic. Because ultrasound is a pulse system and time-of-flight is used to determine depth, quick recovery from input overloads is essential. Overload can occur in the preamp and the VGA. Immediately following a transmit pulse, the typical VGA gains are low, and the LNA is subject to overload from T/R switch leakage. With increasing gain, the VGA can become overloaded due to strong echoes that occur near field echoes and acoustically dense materials, such as bone. Figure 43 illustrates an external overload protection scheme. A pair of back-to-back signal diodes is installed prior to installing the ac-coupling capacitors. Keep in mind that all diodes shown in this example are prone to exhibiting some amount of shot noise. Many types of diodes are available for achieving the desired noise performance. The configuration shown in Figure 43 tends to add 2 nV/√Hz of input-referred noise. Decreasing the 5 kΩ resistor and increasing the 2 kΩ resistor may improve noise contribution, depending on the application. With the diodes shown in Figure 43, clamping levels of ±0.5 V or less significantly enhance the overload performance of the system. +5V Tx DRIVER 5kΩ HV 10nF AD9272 LNA 10nF TRANSDUCER –5V 07029-100 5kΩ 2kΩ Beam forming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals that are generated from a common source but received at different times by a multi-element ultrasound transducer. Beam forming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. The AD9272 includes the front-end components needed to implement analog beam forming for CW Doppler operation. These components allow CW channels with similar phases to be coherently combined before phase alignment and down mixing, thus reducing the number of delay lines or adjustable phase shifters/ down mixers (AD8333 or AD8339) required. Next, if delay lines are used, the phase alignment is performed, and then the channels are coherently summed and down converted by a dynamic range I/Q demodulator. Alternatively, if phase shifters/down mixers, such as the AD8333 and AD8339, are used, phase alignment and down conversion are done before coherently summing all channels into I/Q signals. In either case, the resultant I and Q signals are filtered and sampled by two high resolution ADCs, and the sampled signals are processed to extract the relevant Doppler information. Alternately, the LNA of the AD9272 can directly drive the AD8333 or AD8339 without the crosspoint switch. The LO-x pin presents the inverting LNA output, and the LOSW-x pin can be configured via Register 0x2C (see Table 17) to connect to the noninverting output to provide a differential output of the LNA. The LNA output full-scale voltage of the AD9272 is 4.4 V p-p, and the input fullscale voltage is 2.7 V p-p. If no attenuation is provided between the LNA output and the demodulator, the LNA input full-scale voltage must be limited. Figure 43. Input Overload Protection Rev. C | Page 25 of 44 AD9272 AD9272 LNA gm LNA gm SWITCH ARRAY 8 × CHANNEL gm LNA gm AD8333 2.5V LNA gm 2.5V LNA gm LNA gm 700Ω 600µH 600µH 700Ω 600µH 600µH 2.5V SWITCH ARRAY 8 × CHANNEL 600µH AD8333 AD9272 gm 700Ω 600µH 2.5V LNA 600µH 700Ω 600µH I 16-BIT ADC Q 16-BIT ADC Figure 44. Typical Connection Interface with the AD8333 or AD8339 Using the CWDx± Outputs 2.5V AD9272 LO-A 500Ω LOSW-A 500Ω LOS-B 500Ω LOSW-B 500Ω 1nF 5kΩ 5kΩ AD8339 LNA 1nF 1nF 2.5V 5kΩ 5kΩ LNA 1nF 2.5V LO-H 500Ω LOSW-H 500Ω 1nF 5kΩ 5kΩ AD8339 LNA Q 16-BIT ADC 16-BIT ADC 07029-111 I 1nF Figure 45. Typical Connection Interface with the AD8333 or AD8339 Using the LO-x and LOSW-x Outputs Rev. C | Page 26 of 44 07029-096 LNA AD9272 Crosspoint Switch The maximum gain required is determined by Each LNA is followed by a transconductance amp for voltageto-current conversion. Currents can be routed to one of eight pairs of differential outputs or to 16 single-ended outputs for summing. Each CWD output pin sinks 2.4 mA dc current, and the signal has a full-scale current of ±2 mA for each channel selected by the crosspoint switch. For example, if four channels are summed on one CWD output, the output sinks 9.6 mA dc and has a full-scale current output of ±8 mA. (ADC Noise Floor/VGA Input Noise Floor) + Margin = 20 log(224/3.9) + 11 dB = 46 dB The minimum gain required is determined by (ADC Input FS/VGA Input FS) + Margin = 20 log(2/0.55) − 10 dB = 3 dB The maximum number of channels combined must be considered when setting the load impedance for current-to-voltage conversion to ensure that the full-scale swing and common-mode voltage are within the operating limits of the AD9272. When interfacing to the AD8339, a common-mode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are desired. This can be accomplished by connecting an inductor between each CWD output and a 2.5 V supply and then connecting either a single-ended or differential load resistance to the CWDx± outputs. The value of resistance should be calculated based on the maximum number of channels that can be combined. CWDx± outputs are required under full-scale swing to be greater than 1.5 V and less than AVDD2 (3.0 V supply). TGC OPERATION The TGC signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNAs are designed to be driven from a singleended signal source. Gain values are referenced from the singleended LNA input to the differential ADC input. A simple exercise in understanding the maximum and minimum gain requirements is shown in Figure 46. ADC FS (2V p-p) ~10dB MARGIN MINIMUM GAIN LNA FS (0.55V p-p SE) 70dB ADC 94dB LNA >11dB MARGIN ADC NOISE FLOOR (224µV rms) VGA GAIN RANGE > 42dB MAX CHANNEL GAIN > 48dB Figure 46. Gain Requirements of TGC Operation for a 12-Bit, 40 MSPS ADC 07029-097 MAXIMUM GAIN LNA INPUT-REFERRED NOISE FLOOR (3.9µV rms) @ AAF BW = 15MHz LNA + VGA NOISE = 1.0nV/ Hz Therefore, 42 dB of gain range for a 12-bit, 40 MSPS ADC with 15 MHz of bandwidth should suffice in achieving the dynamic range required for most ultrasound systems today. The system gain is distributed as listed in Table 8. Table 8. Channel Gain Distribution Section LNA Attenuator VGA Amp Filter ADC Nominal Gain (dB) 15.6/17.9/21.3 0 to −42 21/24/27/30 0 0 The linear-in-dB gain (law conformance) range of the TGC path is 42 dB. The slope of the gain control interface is 28 dB/V, and the gain control range is −0.8 V to +0.8 V. Equation 3 is the expression for the differential voltage VGAIN, and Equation 4 is the expression for the channel gain. VGAIN (V ) = GAIN (+) − GAIN (−) Gain (dB) = 28.5 dB VGAIN + ICPT V (3) (4) where ICPT is the intercept point of the TGC gain. In its default condition, the LNA has a gain of 21.3 dB (12×), and the VGA postamp gain is 24 dB if the voltage on the GAIN+ pin is 0 V and GAIN− is 0.8 V (42 dB attenuation). This gives rise to a total gain (or ICPT) of 3.6 dB through the TGC path if the LNA input is unmatched or of −2.4 dB if the LNA is matched to 50 Ω (RFB = 350 Ω). If the voltage on the GAIN+ pin is 1.6 V and the GAIN− pin is 0.8 V (0 dB attenuation), however, the VGA gain is 24 dB. This results in a total gain of 45 dB through the TGC path if the LNA input is unmatched or in a total gain of 39 dB if the LNA input is matched. Each LNA output is dc-coupled to a VGA input. The VGA consists of an attenuator with a range of −42 dB to 0 dB followed by an amplifier with 21 dB, 24 dB, 27 dB, or 30 dB of gain. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. Rev. C | Page 27 of 44 AD9272 Table 9. Sensitivity and Dynamic Range of Trade-Offs 1, 2, 3 LNA Gain (V/V) 6 (dB) 15.6 Full-Scale Input (V p-p) 0.733 Input-Referred Noise Voltage (nV/√Hz) 0.98 8 17.9 0.550 0.86 12 21.3 0.367 0.75 VGA Channel Typical Output Dynamic Range Postamp Gain (dB) 21 24 27 30 21 24 27 30 21 24 27 30 GAIN+ = 0 V 5 67.5 66.4 64.6 62.5 67.5 66.4 64.5 62.5 67.5 66.4 64.6 62.5 Input-Referred Noise 4 @ GAIN+ = 1.6 V (nV/√Hz) 1.395 1.286 1.227 1.197 1.149 1.071 1.030 1.009 0.910 0.865 0.842 0.830 GAIN+ = 1.6 V 6 65.1 63.0 60.6 57.9 64.5 62.3 59.8 57.1 63.3 60.9 58.2 55.4 1 LNA: output full scale = 4.4 V p-p differential. Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V. ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input. 4 Channel noise at maximum VGA gain. 5 Output dynamic range at minimum VGA gain (VGA dominated). 6 Output dynamic range at maximum VGA gain (LNA dominated). 2 3 For example, when the VGA is set for the minimum gain voltage, the TGC path is dominated by VGA noise and achieves the maximum output SNR. However, as the postamp gain options are increased, the input-referred noise is reduced, and the SNR is degraded. GAIN± pins. The LNA has three limitations, or full-scale settings, that can be applied through the SPI. Similarly, the VGA has four postamp gain settings that can be applied through the SPI. The voltage applied to the GAIN± pins determines which amplifier (the LNA or VGA) saturates first. The maximum signal input level that can be applied as a function of voltage on the GAIN± pins for the selectable gain options of the SPI is shown in Figure 47 to Figure 49. 0.9 If the VGA is set for the maximum gain voltage, the TGC path is dominated by LNA noise and achieves the lowest inputreferred noise but with degraded output SNR. The higher the TGC (LNA + VGC) gain, the lower the output SNR. As the postamp gain is increased, the input-referred noise is reduced. INPUT FULL SCALE (V p-p) 0.8 At low gains, the VGA should limit the system noise performance (SNR); at high gains, the noise is defined by the source and the LNA. The maximum voltage swing is bound by the fullscale peak-to-peak ADC input voltage (2 V p-p). 0.7 0.6 PGA GAIN = 21dB 0.5 0.4 PGA GAIN = 24dB 0.3 PGA GAIN = 27dB 0.2 PGA GAIN = 30dB Both the LNA and VGA have full-scale limitations within each section of the TGC path. These limitations are dependent on the gain setting of each function block and on the voltage applied to the 0.1 0 0 07029-177 Table 9 demonstrates the sensitivity and dynamic range of trade-offs that can be achieved relative to various LNA and VGA gain settings. 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) Figure 47. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations Rev. C | Page 28 of 44 AD9272 0.6 per side is 180 Ω nominally for a total differential resistance of 360 Ω. The ladder is driven by a fully differential input signal from the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors. The common-mode voltage of the attenuator and the VGA is controlled by an amplifier that uses the same midsupply voltage derived in the LNA, permitting dc coupling of the LNA to the VGA without introducing large offsets due to commonmode differences. However, any offset from the LNA becomes amplified as the gain increases, producing an exponentially increasing VGA output offset. 0.4 PGA GAIN = 21dB 0.3 PGA GAIN = 24dB PGA GAIN = 27dB 0.2 PGA GAIN = 30dB 0.1 07029-178 0 0 The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from −42 dB to 0 dB. This circuit technique results in linear-in-dB gain law conformance and low distortion levels—only deviating ±0.5 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) Figure 48. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations 0.9 0.7 PGA GAIN = 21dB 0.6 The X-AMP inputs are part of a programmable gain feedback amplifier that completes the VGA. Its bandwidth is approximately 100 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting. 0.5 PGA GAIN = 24dB 0.4 0.3 PGA GAIN = 27dB 0.2 0.1 0 0 PGA GAIN = 30dB 0.2 0.4 Gain Control 07029-179 INPUT FULL SCALE (V p-p) 0.8 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) Figure 49. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations Variable Gain Amplifier The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 3.8 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 50. GAIN± Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. GAIN INTERPOLATOR + POSTAMP There are two ways in which the GAIN+ and GAIN− pins can be interfaced. Using a single-ended method, a Kelvin type of connection to ground can be used as shown in Figure 51. For driving multiple devices, it is preferable to use a differential method, as shown in Figure 52. In either method, the GAIN+ and GAIN− pins should be dc-coupled and driven to accommodate a 1.6 V full-scale input. gm VIP The gain control interface, GAIN±, is a differential input. VGAIN varies the gain of all VGAs through the interpolator by selecting the appropriate input stages connected to the input attenuator. For GAIN− at 0.8 V, the nominal GAIN+ range for 28.5 dB/V is 0 V to 1.6 V, with the best gain linearity from about 0.16 V to 1.44 V, where the error is typically less than ±0.5 dB. For GAIN+ voltages greater than 1.44 V and less than 0.16 V, the error increases. The value of GAIN+ can exceed the supply voltage by 1 V without gain foldover. 3dB VIN POSTAMP 07029-078 AD9272 – Figure 50. Simplified VGA Schematic 100Ω GAIN+ GAIN– The input of the VGA is a 14-stage differential resistor ladder with 3.5 dB per tap. The resulting total gain range is 42 dB, which allows for range loss at the endpoints. The effective input resistance Rev. C | Page 29 of 44 0.01µF 0V TO 1.6V DC 50Ω 0.01µF KELVIN CONNECTION Figure 51. Single-Ended GAIN± Pins Configuration 07029-109 INPUT FULL SCALE (V p-p) 0.5 AD9272 GAIN+ 100Ω 0.01µF GAIN– ±0.4DC AT 0.8V CM 499Ω AD8138 ±0.4DC AT 0.01µF 0.8V CM ±0.8V DC 0.8V CM 523Ω 100Ω 31.3kΩ 50Ω 10kΩ 07029-098 AD9272 The antialaising filter is a combination of a single-pole highpass filter and a second-order low-pass filter. The high-pass filter can be configured at a ratio of the low-pass filter cutoff. This is selectable through the SPI. AVDD2 499Ω Figure 52. Differential GAIN± Pins Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This latter limit is set in accordance with the total noise floor of the ADC. The filter uses on-chip tuning to trim the capacitors and in turn set the desired cutoff frequency and reduce variations. The default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. The cutoff tolerance is maintained from 8 MHz to 18 MHz. 4kΩ C 30C 2kΩ 10kΩ/n 4C 2kΩ 4kΩ 30C Output-referred noise as a function of GAIN+ is shown in Figure 14 for the short-circuit input conditions. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. 4kΩ C = 0.8pF TO 5.1pF n = 0 TO 7 C 4kΩ 07029-110 499Ω Figure 53. Simplified Filter Schematic The output-referred noise is a flat 60 nV/√Hz (postamp gain = 24 dB) over most of the gain range because it is dominated by the fixed output-referred noise of the VGA. At the high end of the gain control range, the noise of the LNA and of the source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the inputreferred contribution of the VGA is miniscule. Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled and disabled through the SPI. Initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift. At lower gains, the input-referred noise, and therefore, the noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. The contribution of the ADC noise floor has the same dependence. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. There is a total of eight SPI-programmable settings that allow the user to vary the high-pass filter cutoff frequency as a function of the low-pass cutoff frequency. Two examples are shown in Table 10: one is for an 8 MHz low-pass cutoff frequency and the other is for an 18 MHz low-pass cutoff frequency. In both cases, as the ratio decreases, the amount of rejection on the low-end frequencies increases. Therefore, making the entire AAF frequency pass band narrow can reduce low frequency noise or maximize dynamic range for harmonic processing. Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and is usually evident only when a large signal is present. The gain interface includes an on-chip noise filter, which significantly reduces this effect at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN± inputs. An external RC filter can be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth. Antialiasing Filter The filter that the signal reaches prior to the ADC is used to reject dc signals and to band limit the signal for antialiasing. Figure 53 shows the architecture of the filter. Table 10. SPI-Selectable High-Pass Filter Cutoff Options SPI Setting 0 1 2 3 4 5 6 7 1 Ratio1 20.65 11.45 7.92 6.04 4.88 4.10 3.52 3.09 High-Pass Cutoff Low-Pass Cutoff Low-Pass Cutoff = 8 MHz = 18 MHz 387 kHz 872 kHz 698 kHz 1.571 MHz 1.010 MHz 2.273 MHz 1.323 MHz 2.978 MHz 1.638 MHz 3.685 MHz 1.953 MHz 4.394 MHz 2.270 MHz 5.107 MHz 2.587 MHz 5.822 MHz Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency. Rev. C | Page 30 of 44 AD9272 ADC 3.3V 50Ω* VFAC3 OUT The AD9272 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9272 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 54 shows the preferred method for clocking the AD9272. A low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50 MHz, is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9272 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9272, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1µF CLK+ LVDS DRIVER 0.1µF CLK– 07029-052 *50Ω ADC AD9272 100Ω CLK RESISTOR IS OPTIONAL. Figure 56. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 57). Although the CLK+ input circuit supply is AVDDx (1.8 V), this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible. 3.3V VFAC3 OUT AD951x FAMILY 0.1µF CLK 50Ω* CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK+ ADC AD9272 CLK 0.1µF CLK– 0.1µF 39kΩ *50Ω RESISTOR IS OPTIONAL. Figure 57. Single-Ended 1.8 V CMOS Sample Clock 3.3V 0.1µF OUT MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1µF XFMR 50Ω 100Ω VFAC3 OUT ADC AD9272 0.1µF VFAC3 CLK 50Ω* CLK+ 07029-050 SCHOTTKY DIODES: HSM2812 0.1µF Figure 54. Transformer-Coupled Differential Clock 3.3V AD951x FAMILY 0.1µF 0.1µF CLK+ CLK 100Ω PECL DRIVER 0.1µF CLK 240Ω ADC AD9272 CLK– 240Ω RESISTOR IS OPTIONAL. Figure 55. Differential PECL Sample Clock 07029-051 0.1µF OPTIONAL 0.1µF 100Ω 0.1µF CLK+ ADC AD9272 CLK– *50Ω RESISTOR IS OPTIONAL. If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 55. The AD951x family of clock drivers offers excellent jitter performance. 50Ω* VFAC3 OUT CMOS DRIVER CLK CLK– 0.1µF AD951x FAMILY 0.1µF 07029-054 3.3V *50Ω 0.1µF CLK 07029-053 The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clocks. AD951x FAMILY 0.1µF Figure 58. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9272 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9272. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See Table 17 for more details on using this feature. Rev. C | Page 31 of 44 AD9272 400 The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. 350 CURRENT (mA) 300 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by 250 IAVDD1 , 65MSPS SPEED GRADE 200 IAVDD1 , 40MSPS SPEED GRADE 150 100 IDRVDD 50 In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 59). 0 0 10 20 70 80 215 POWER/CHANNEL (mW) 210 80MSPS SPEED GRADE 205 200 195 65MSPS SPEED GRADE 190 185 180 07029-031 40MSPS SPEED GRADE 175 170 RMS CLOCK JITTER REQUIREMENT 0 10 20 30 40 50 60 70 80 SAMPLING FREQUENCY (MSPS) Figure 61. Power per Channel vs. fSAMPLE for fIN = 5 MHz 110 100 16 BITS 90 14 BITS 12 BITS 70 10 BITS 40 1 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) HIGH 1000 Figure 59. Ideal SNR vs. Analog Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 61, the power dissipated by the AD9272 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. LNA BIAS SETTING 8 BITS MID-HIGH MID-LOW LOW 07029-119 80 The AD9272 features scalable LNA bias currents (see Register 0x12 in Table 17). The default LNA bias current settings are high. Figure 62 shows the typical reduction of AVDD2 current with each bias setting. It is also recommended to adjust the LNA offset using Register 0x10 in Table 17 when the LNA bias setting is low. 07029-038 SNR (dB) 60 Figure 60. Supply Current vs. fSAMPLE for fIN = 5 MHz 120 30 50 220 Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about how jitter performance relates to ADCs (visit www.analog.com). 50 40 SAMPLING FREQUENCY (MSPS) The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9272. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step. 60 30 07029-032 SNR Degradation = 20 × log 10[1/2 × π × fA × tJ] 130 IAVDD1 , 80MSPS SPEED GRADE 0 50 100 150 200 250 300 TOTAL AVDD2 CURRENT (mA) 350 Figure 62. AVDD2 Current at Different LNA Bias Settings, AD9272-40 Rev. C | Page 32 of 44 400 AD9272 By asserting the STBY pin high, the AD9272 is placed into a standby mode. In this state, the device typically dissipates 150 mW. During standby, the entire part is powered down except the internal references. The LVDS output drivers are placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power this device back up is also greatly reduced. The AD9272 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference buffer, PLL, and biasing networks. The decoupling capacitors on VREF are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. To restore the device to full operation, approximately 0.5 ms is required when using the recommended 1 μF and 0.1 μF decoupling capacitors on the VREF pin and 0.01 μF on the GAIN± pins. Most of this time is dependent on the gain decoupling: higher value decoupling capacitors on the GAIN± pins result in longer wake-up times. There are a number of other power-down options available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered up when fast wake-up times are required. The wake-up time is slightly dependent on gain. To achieve a 1 μs wake-up time when the device is in standby mode, 0.8 V must be applied to the GAIN± pins. See Table 17 for more details on using these features. Digital Outputs and Timing The AD9272 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard by using Register 14, Bit 6 or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9272 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. An example of the FCO, DCO, and data stream with proper trace length and position can be found in Figure 63. 07029-034 By asserting the PDWN pin high, the AD9272 is placed into power-down mode. In this state, the device typically dissipates 2 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9272 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. CH1 500mV/DIV = DCO CH2 500mV/DIV = DATA CH3 500mV/DIV = FCO 5.0ns/DIV Figure 63. LVDS Output Timing Example in ANSI-644 Mode (Default) An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 64. Figure 65 shows an example of the trace lengths exceeding 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (and therefore increase the current) of all eight outputs in order to drive longer trace lengths (see Figure 66). Even though this produces sharper rise and fall times on the data edges, is less prone to bit errors, and improves frequency distribution (see Figure 66), the power dissipation of the DRVDD supply increases when this option is used. In cases that require increased driver strength to the DCO± and FCO± outputs because of load mismatch, Register 0x15 allows the user to double the drive strength. To do this, set the appropriate bit in Register 0x05. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 0x15 because these bits take precedence over this feature. See Table 17 for more details. Rev. C | Page 33 of 44 AD9272 600 400 EYE: ALL BITS 200 100 0 –100 –200 –400 ULS: 2399/2399 200 100 0 –100 –200 –300 –1.0ns –0.5ns 0ns 0.5ns 1.0ns –400 1.5ns 25 20 20 TIE JITTER HISTOGRAM (Hits) 25 15 10 5 0 –200ps –100ps 0ps 100ps –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 15 10 5 0 –200ps 200ps Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches On Standard FR-4 –1.5ns 07029-036 –1.5ns 07029-035 TIE JITTER HISTOGRAM (Hits) –600 EYE: ALL BITS 300 EYE DIAGRAM VOLTAGE (V) EYE DIAGRAM VOLTAGE (V) 400 ULS: 2398/2398 –100ps 0ps 100ps 200ps Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater Than 24 Inches On Standard FR-4 Rev. C | Page 34 of 44 AD9272 600 EYE: ALL BITS ULS: 2396/2396 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 11. To change the output data format to twos complement, see the Memory Map section. EYE DIAGRAM VOLTAGE (V) 400 200 0 Table 11. Digital Output Coding –200 Code 4095 2048 2047 0 –400 –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 20 15 10 5 07029-037 TIE JITTER HISTOGRAM (Hits) Digital Output Offset Binary (D11...D0) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 960 Mbps (12 bits × 80 MSPS = 960 Mbps). The lowest typical conversion rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for a specific application. See Table 17 for details on enabling this feature. 25 0 –200ps (VIN+) − (VIN−), Input Span = 2 V p-p (V) +1.00 0.00 −0.000488 −1.00 –100ps 0ps 100ps 200ps Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4 Two output clocks are provided to assist in capturing data from the AD9272. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9272 and must be captured on the rising and falling edges of the DCO± that supports double data rate (DDR) capturing. The frame clock output (FCO±) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. Table 12. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard output PN sequence long PN sequence short One-/zero-word toggle User input 1-/0-bit toggle 1× sync One bit high Mixed bit frequency Digital Output Word 1 N/A 1000 0000 0000 1111 1111 1111 0000 0000 0000 1010 1010 1010 N/A N/A 1111 1111 1111 Register 0x19 to Register 0x1A 1010 1010 1010 0000 0011 1111 1000 0000 0000 1010 0011 0011 Rev. C | Page 35 of 44 Digital Output Word 2 N/A 1000 0000 0000 1111 1111 1111 0000 0000 0000 0101 0101 0101 N/A N/A 0000 0000 0000 Register 0x1B to Register 0x1C N/A N/A N/A N/A Subject to Data Format Select N/A Yes Yes Yes No Yes Yes No No No No No No AD9272 When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in Figure 2, is 90° relative to the output data edge. An 8-, 10-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial streams and test the compatibility of the device, with lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. When using the 14-bit option, the data stream stuffs two 0s at the end of the normal 14-bit serial data. When using the SPI, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this can be inverted so that the LSB is represented first in the data output serial stream (see Figure 3). There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 12 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns may not adhere to the data format select option. In addition, user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 bits or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value is a specific value instead of all 1s (see Table 13 for the initial values). The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 bits or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value is a specific value instead of all 1s, and the AD9272 inverts the bit stream with relation to the ITU standard (see Table 13 for the initial values). Sequence PN Sequence Short PN Sequence Long This pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. SCLK Pin This pin is required to operate the SPI port interface. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. CSB Pin This pin is required to operate the SPI port interface. It has an internal 70 kΩ pull-up resistor that pulls this pin high and is both 1.8 V and 3.3 V tolerant. RBIAS Pin To set the internal core bias current of the ADC, place a resistor nominally equal to 10 kΩ to ground at the RBIAS pin. Using other than the recommended 10 kΩ resistor for RBIAS degrades the performance of the device. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Voltage Reference A stable and accurate 0.5 V voltage reference is built into the AD9272. This is gained up internally by a factor of 2, setting VREF to 1 V, which results in a full-scale differential input span of 2 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, this device does not support ADC full-scale ranges below 2 V p-p. When applying the decoupling capacitors to the VREF pin, use ceramic low-ESR capacitors. These capacitors should be close to the reference pin and on the same layer of the PCB as the AD9272. The VREF pin should have both a 0.1 μF capacitor and a 1 μF capacitor connected in parallel to the analog ground. These capacitor values are recommended for the ADC to properly settle and acquire the next valid sample. The reference settings can be selected using the SPI. The settings allow two options: using the internal reference or using an external reference. The internal reference option is the default setting and has a resulting differential span of 2 V p-p. Table 14. SPI-Selectable Reference Settings Table 13. PN Sequence Initial Value 0x0DF 0x29B80A SDIO Pin First Three Output Samples (MSB First) 0xDF9, 0x353, 0x301 0x591, 0xFD7, 0x0A3 SPI-Selected Mode External Reference Internal Reference (Default) Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. Rev. C | Page 36 of 44 Resulting VREF (V) N/A 1 Resulting Differential Span (V p-p) 2 × external reference 2 AD9272 Power and Ground Recommendations When connecting power to the AD9272, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one 1.8 V supply is available, it should be routed to the AVDD1 first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace lengths. A single PC board ground plane should be sufficient when using the AD9272. With proper decoupling and smart partitioning of the analog, digital, and clock sections of the PC board, optimum performance can be easily achieved. the AD9272 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the device and PCB, partition the continuous copper pad by overlaying a silkscreen or solder mask to divide it into several uniform sections. This ensures several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the AD9272 and PCB. See Figure 67 for a PCB layout example. For more detailed information on packaging and for more PCB layout examples, see the AN-772 Application Note. SILKSCREEN PARTITION PIN 1 INDICATOR It is required that the exposed paddle on the underside of the device be connected to a quiet analog ground to achieve the best electrical and thermal performance of the AD9272. An exposed continuous copper plane on the PCB should mate to Rev. C | Page 37 of 44 07029-069 Exposed Paddle Thermal Heat Slug Recommendations Figure 67. Typical PCB Layout AD9272 SERIAL PORT INTERFACE (SPI) The AD9272 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., AN-877 Application Note, Interfacing to High Speed ADCs via SPI. There are three pins that define the serial port interface or SPI. They are the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the device. The SDIO (serial data input/output) is a dualpurpose pin that allows data to be sent to and read from the internal memory map registers of the device. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 15). Table 15. Serial Port Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. Chip select bar (active low). This control gates the read and write cycles. The falling edge of the CSB pin in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 69 and Table 16. In normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructtions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset, and the device waits for a new instruction. In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode as defined in the SDIO Pin and SCLK Pin sections. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 15 constitute the physical interface between the programming device of the user and the serial port of the AD9272. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. In cases where multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Figure 68 shows the number of SDIO pins that can be connected together, assuming the same load as the AD9272 and the resulting VOH level. Rev. C | Page 38 of 44 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers. This provides the user with an alternative method, other than a full SPI controller, for programming the device (see the AN-812 Application Note). 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER 07029-113 VOH (V) AD9272 Figure 68. SDIO Pin Loading tDS tS tHI tCLK tDH tH tLO CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 07029-068 SDIO DON’T CARE DON’T CARE Figure 69. Serial Timing Details Table 16. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO Minimum Timing (ns) 5 2 40 5 2 16 16 10 tDIS_SDIO 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 69) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 69) Rev. C | Page 39 of 44 AD9272 MEMORY MAP READING THE MEMORY MAP TABLE Caution Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04 to Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x2D). All registers except Register 0x00, Register 0x02, Register 0x04, Register 0x05, and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. When a 0 is written to Bit 0 of this address followed by an 0x01 to the SW transfer bit in Register 0xFF, the duty cycle stabilizer turns off. It is important to follow each writing sequence with a write to the SW transfer bit to update the SPI registers. Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. RESERVED LOCATIONS DEFAULT VALUES After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 17, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Rev. C | Page 40 of 44 AD9272 Table 17. AD9272 Memory Map Register Addr. Bit 7 (Hex) Register Name (MSB) Chip Configuration Registers 00 Chip_port_config 0 01 Chip_id 02 Chip_grade Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 Soft reset 1 = on 0 = off (default) LSB first 1 = on 0 = off (default) Bit 0 (LSB) Default Value Default Notes/ Comments 0 0x18 The nibbles should be mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a read-only register. Child ID used to differentiate graded devices. Chip ID Bits[7:0] (AD9272 = 0x2E, default) Read only X Child ID[5:4] (identify device variants of Chip ID) 00 = 40 MSPS (default) 01 = 65 MSPS 10 = 80 MSPS X X X X 0x00 Device Index and Transfer Registers 04 Device_index_2 X X X X X X Bits are set to determine which on-chip device receives the next write command. device_update X X Clock Channel FCO± 1 = on 0 = off (default) X Data Channel E 1 = on (default) 0 = off Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) 0x0F FF Clock Channel DCO± 1 = on 0 = off (default) X Data Channel F 1 = on (default) 0 = off Data Channel B 1 = on (default) 0 = off X Bits are set to determine which on-chip device receives the next write command. Device_index_1 Data Channel G 1 = on (default) 0 = off Data Channel C 1 = on (default) 0 = off X 0x0F 05 Data Channel H 1 = on (default) 0 = off Data Channel D 1 = on (default) 0 = off X 0x00 Synchronously transfers data from the master shift register to the slave. ADC Functions 08 Modes X X X X 0 0x00 Determines various generic modes of chip operation (global). 09 Clock X X X X 0x01 Turns the internal duty cycle stabilizer on and off (global). 0D Test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset 100 = CW mode (TGC PDWN) X X X Duty cycle stabilizer 1 = on (default) 0 = off Output test mode—see Table 12 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the output_mode register) 0x00 When this register is set, the test data is placed on the output pins in place of normal data. (Local, expect for PN sequence.) X Rev. C | Page 41 of 44 AD9272 Addr. (Hex) 0F Register Name Flex_channel_input Bit 7 Bit 0 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) X X X X Filter cutoff frequency control 0000 = 1.3 × 1/3 × fSAMPLE 0001 = 1.2 × 1/3 × fSAMPLE 0010 = 1.1 × 1/3 × fSAMPLE 0011 = 1.0 × 1/3 × fSAMPLE (default) 0100 = 0.9 × 1/3 × fSAMPLE 0101 = 0.8 × 1/3 × fSAMPLE 0110 = 0.7 × 1/3 × fSAMPLE 1000 = 1.3 × 1/4.5 × fSAMPLE 1001 = 1.2 × 1/4.5 × fSAMPLE 1010 = 1.1 × 1/4.5 × fSAMPLE 1011 = 1.0 × 1/4.5 × fSAMPLE 1100 = 0.9 × 1/4.5 × fSAMPLE 1101 = 0.8 × 1/4.5 × fSAMPLE 1110 = 0.7 × 1/4.5 × fSAMPLE X X 6-bit LNA offset adjustment 10 0000 for LNA bias high, mid-high, mid-low (default) 10 0001 for LNA bias low LNA gain X X X X PGA gain 00 = 15.6 dB 00 = 21 dB 01 = 17.9 dB 01 = 24 dB (default) 10 = 21.3 dB 10 = 27 dB (default) 11 = 30 dB X X X X 1 X LNA bias 00 = high (default) 01 = mid-high 10 = mid-low 11 = low 00 = offset binary X X X Output X 0 = LVDS (default) invert ANSI-644 01 = twos 1 = on (default) complement 0 = off 1 = LVDS (default) low power, (IEEE 1596.3 similar) X X X DCO± X X Output driver and termination FCO± 00 = none (default) 2× drive 01 = 200 Ω strength 10 = 100 Ω 1 = on 11 = 100 Ω 0 = off (default) Default Value 0x30 Default Notes/ Comments Antialiasing filter cutoff (global). 10 Flex_offset 0x20 LNA force offset correction (local). LNA and PGA gain adjustment (global). 11 Flex_gain 12 Bias_current 14 Output_mode 15 Output_adjust 16 Output_phase X X X X 0x03 18 Flex_vref X 0= internal reference 1= external reference X X 0011 = output clock phase adjust (0000 through 1010) (Default: 180° relative to data edge) 0000 = 0° relative to data edge 0001 = 60° relative to data edge 0010 = 120° relative to data edge 0011 = 180° relative to data edge 0100 = 240° relative to data edge 0101 = 300° relative to data edge 0110 = 360° relative to data edge 0111 = 420° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge X X X X Rev. C | Page 42 of 44 0x06 0x08 LNA bias current adjustment (global). 0x00 Configures the outputs and the format of the data (Bits[7:3] and Bits[1:0] are global; Bit 2 is local). 0x00 Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor (Bits[7:1] are global; Bit 0 is local). On devices that use global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. 0x00 Select internal reference (recommended default) or external reference (global). AD9272 Addr. (Hex) 19 Register Name User_patt1_lsb Bit 7 (MSB) B7 Bit 6 B6 Bit 5 B5 Bit 4 B4 Bit 3 B3 Bit 2 B2 Bit 1 B1 Bit 0 (LSB) B0 Default Value 0x00 1A User_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 1B User_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 1C User_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 21 Serial_control LSB first 1 = on 0 = off (default) X X X 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 22 Serial_ch_stat X X X X <10 MSPS, low encode rate mode 1 = on 0 = off (default) X 2B Flex_filter X Enable automatic low-pass tuning 1 = on (selfclearing) X X 2C Analog_input X X 2D Cross_point_switch X X X Channel output reset 1 = on 0 = off (default) Channel powerdown 1 = on 0 = off (default) High-pass filter cutoff 0000 = fLP/20.7 0001 = fLP/11.5 0010 = fLP/7.9 0011 = fLP/6.0 0100 = fLP/4.9 0101 = fLP/4.1 0110 = fLP/3.5 0111 = fLP/3.1 X X X X LOSW-x connect 00 = high Z 01 = (−)LNA output 10 = (+)LNA output 11 = high Z Crosspoint switch enable 10 0000 = CWD0± (differential) 10 0001 = CWD1± (differential) 10 0010 = CWD2± (differential) 10 0011 = CWD3± (differential) 10 0100 = CWD4± (differential) 10 0101 = CWD5± (differential) 10 0110 = CWD6± (differential) 10 0111 = CWD7± (differential) 11 0000 = CWD0+ (single-ended) 11 0001 = CWD1+ (single-ended) 11 0010 = CWD2+ (single-ended) 11 0011 = CWD3+ (single-ended) 11 0100 = CWD4+ (single-ended) 11 0101 = CWD5+ (single-ended) 11 0110 = CWD6+ (single-ended) 11 0111 = CWD7+ (single-ended) 11 1000 = CWD0− (single-ended) 11 1001 = CWD1− (single-ended) 11 1010 = CWD2− (single-ended) 11 1011 = CWD3− (single-ended) 11 1100 = CWD4− (single-ended) 11 1101 = CWD5− (single-ended) 11 1110 = CWD6− (single-ended) 11 1111 = CWD7− (single-ended) 0x xxxx = power down CW channel (default) Rev. C | Page 43 of 44 0x00 Default Notes/ Comments User-defined pattern, 1 LSB (global). User-defined pattern, 1 MSB (global). User-defined pattern, 2 LSB (global). User-defined pattern, 2 MSB (global). Serial stream control. Default causes MSB first and the native bit stream (global). 0x00 Used to power down individual sections of a converter (local). 0x00 Filter cutoff (global). (fLP = low-pass filter cutoff frequency.) 0x00 LNA active termination/input impedance (global). 0x00 Crosspoint switch enable (local). AD9272 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 76 75 100 1 76 75 100 1 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 51 25 26 50 BOTTOM VIEW (PINS UP) 51 26 0.50 BSC LEAD PITCH VIEW A 25 50 VIEW A 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD 100908-A 0° MIN 1.05 1.00 0.95 9.50 SQ Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters ORDERING GUIDE Model AD9272BSVZ-80 1 AD9272BSVZRL-801 AD9272BSVZ-651 AD9272BSVZRL-651 AD9272BSVZ-401 AD9272BSVZRL-401 AD9272-65EBZ1 AD9272-80KITZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel Evaluation Board Evaluation Board and High Speed FPGA-Based Data Capture Board Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07029-0-7/09(C) Rev. C | Page 44 of 44 Package Option SV-100-3 SV-100-3 SV-100-3 SV-100-3 SV-100-3 SV-100-3