AD AD9239

Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS
Serial Output 1.8 V ADC
AD9239
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
DRGND
AD9239
VIN + A
VIN – A
BUF
SHA
PIPELINE
ADC
12
BUF
SHA
PIPELINE
ADC
12
BUF
SHA
PIPELINE
ADC
12
BUF
SHA
PIPELINE
ADC
12
VCM A
VIN + B
VIN – B
VCM B
VIN + C
VIN – C
VCM C
VIN + D
VIN – D
DATA SERIALIZER, ENCODER, AND
CML DRIVERS
CHANNEL A
CHANNEL B
CHANNEL C
CHANNEL D
DOUT + A
DOUT – A
DOUT + B
DOUT – B
DOUT + C
DOUT – C
DOUT + D
DOUT – D
VCM D
PGM3
REFERENCE
RBIAS
DATA RATE
MULTIPLIER
SERIAL
PORT
TEMPOUT
PGM2
PGM1
PGM0
RESET
SCLK
APPLICATIONS
SDI/
SDIO
SDO
CSB
CLK+ CLK–
06980-001
4 ADCs in 1 package
Coded serial digital outputs with ECC per channel
On-chip temperature sensor
−95 dB channel-to-channel crosstalk
SNR = 65 dBFS with AIN = 85 MHz at 250 MSPS
SFDR = 77 dBc with AIN = 85 MHz at 250 MSPS
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.7 LSB (typical)
780 MHz full power analog bandwidth
Power dissipation = 380 mW per channel at 250 MSPS
1.25 V p-p input voltage range, adjustable up to 1.5 V p-p
1.8 V supply operation
Clock duty cycle stabilizer
Serial port interface features
Power-down modes
Digital test pattern enable
Programmable header
Programmable pin functions (PGMx, PDWN)
Figure 1.
Communication receivers
Cable head end equipment/M-CMTS
Broadband radios
Wireless infrastructure transceivers
Radar/military-aerospace subsystems
Test equipment
GENERAL DESCRIPTION
The AD9239 is a quad, 12-bit, 250 MSPS analog-to-digital
converter (ADC) with an on-chip temperature sensor and a
high speed serial interface. It is designed to support digitizing
high frequency, wide dynamic range signals with an input
bandwidth up to 780 MHz. The output data are serialized and
presented in packet format, consisting of channel-specific
information, coded samples, and error correction code.
The ADC requires a single 1.8 V power supply and the input
clock may be driven differentially with a sine wave, LVPECL,
TTL, or LVDS. A clock duty cycle stabilizer allows high
performance at full speed with a wide range of clock duty
cycles. The on-chip reference eliminates the need for external
decoupling and can be adjusted by means of SPI control.
Various power-down and standby modes are supported. The
ADC typically consumes 145 mW per channel with the digital
link still in operation when standby operation is enabled.
Fabricated on an advanced CMOS process, the AD9239 is available in a Pb-free/RoHS-compliant, 72-lead LFCSP package. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Four ADCs are contained in a small, space-saving package.
An on-chip PLL allows users to provide a single ADC
sampling clock, and the PLL distributes and multiplies up
to produce the corresponding data rate clock.
Coded data rate supports up to 4.0 Gbps per channel.
Coding includes scrambling to ensure proper dc common
mode, embedded clock, and error correction.
The AD9239 operates from a single 1.8 V power supply.
Flexible synchronization schemes and programmable
mode pins.
On-chip temperature sensor.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD9239
TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications ....................................................................................... 1 Equivalent Circuits ......................................................................... 17 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 19 General Description ......................................................................... 1 Analog Input Considerations ................................................... 19 Product Highlights ........................................................................... 1 Clock Input Considerations ...................................................... 21 Revision History ............................................................................... 2 Serial Port Interface (SPI) .............................................................. 31 Specifications..................................................................................... 3 Hardware Interface..................................................................... 31 AC Specifications.......................................................................... 4 Memory Map .................................................................................. 33 Digital Specifications ................................................................... 5 Reading the Memory Map Table .............................................. 33 Switching Specifications .............................................................. 6 Reserved Locations .................................................................... 33 Timing Diagram ........................................................................... 7 Default Values ............................................................................. 33 Absolute Maximum Ratings............................................................ 8 Logic Levels ................................................................................. 33 Thermal Resistance ...................................................................... 8 Outline Dimensions ....................................................................... 38 ESD Caution .................................................................................. 8 Ordering Guide .......................................................................... 38 Pin Configuration and Function Description .............................. 9 REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9239
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 1.
Parameter 1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
ANALOG INPUTS
Differential Input Voltage Range 2
Common-Mode Voltage
Input Capacitance
Input Resistance
Analog Bandwidth, Full Power
Voltage Common Mode (VCMx)
Voltage Output
Current Drive
Temperature Sensor Output
Voltage Output
Current Drive
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation
(Including Output Drivers)
Power-Down Dissipation
Standby Dissipation2
CROSSTALK
Overrange Condition 3
Temp
AD9239BCPZ-170
Min Typ
Max
12
Full
25°C
25°C
25°C
25°C
Full
Full
Guaranteed
−2
±12
4
12
−2.8 +1
+4.7
0.9
2.7
±0.28 ±0.6
±0.45 ±0.9
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
−2.8
1.25
1.4
2
4.3
780
AD9239BCPZ-210
Typ
Max
Guaranteed
−2
4
+1
0.9
±0.28
±0.7
±12
12
+4.7
2.7
±0.6
±1.3
Min
−2.8
1.25
1.4
2
4.3
780
AD9239BCPZ-250
Typ
Max
Guaranteed
−2
4
+1
0.9
±0.3
±0.7
±12
12
+4.7
2.7
±0.6
±1.3
1.25
1.4
2
4.3
780
Unit
Bits
mV
mV
% FS
% FS
LSB
LSB
V p-p
V
pF
kΩ
MHz
1.4
1.44
1
−1.12
739
10
1.5
1.4
1.44
1
−1.12
737
10
1.5
1.4
1.44
1
−1.12
734
10
1.5
V
mA
mV/°C
mV
μA
1.7
1.7
1.8
1.8
535
98
1.139
1.9
1.9
570
105
1.215
1.7
1.7
1.8
1.8
610
111
1.298
1.9
1.9
650
120
1.386
1.7
1.7
1.8
1.8
725
123
1.526
1.9
1.9
775
133
1.634
V
V
mA
mA
W
Full
Full
Full
Full
Full
Full
Full
Min
12
3
152
−95
−90
3
173
−95
−90
1
3
195
−95
−90
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
AVDD/DRVDD, with link established.
3
Overrange condition is specified with 6 dB above the full-scale input range.
2
Rev. 0 | Page 3 of 40
mW
mW
dB
dB
AD9239
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 84.3 MHz
fIN = 170.3 MHz
fIN = 240.3 MHz
SIGNAL-TO-NOISE RATIO (SINAD)
fIN = 9.7 MHz
fIN = 84.3 MHz
fIN = 170.3 MHz
fIN = 240.3 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 84.3 MHz
fIN = 170.3 MHz
fIN = 240.3 MHz
WORST HARMONIC (SECOND)
fIN = 9.7 MHz
fIN = 84.3 MHz
fIN = 170.3 MHz
fIN = 240.3 MHz
WORST HARMONIC (THIRD)
fIN = 9.7 MHz
fIN = 84.3 MHz
fIN = 170.3 MHz
fIN = 240.3 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 84.3 MHz
fIN = 170.3 MHz
fIN = 240.3 MHz
TWO-TONE INTERMOD DISTORTION (IMD)
fIN1 = 140.2 MHz, fIN2 = 141.3 MHz,
AIN1 and AIN2 = −7.0 dBFS
fIN1 = 170.2 MHz, fIN2 = 171.3 MHz,
AIN1 and AIN2 = −7.0 dBFS 2
1
2
Temp
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
AD9239BCPZ-170
Min
Typ
Max
AD9239BCPZ-210
Min
Typ
Max
AD9239BCPZ-250
Min
Typ
Max
63.5
63.2
63.1
64.5
64.1
63.3
63.2
64.4
62.8
63.9
10.2
10.1
10.3
62.8
10.3
10.1
4
10.2
78.6
82
79
63.9
63
10.4
87.5
64.2
86
77
80
74
84
76
72.6
77
Unit
64.5
64.1
63.9
63.3
dB
dB
dB
dB
64.2
63.8
63.1
63.1
dB
dB
dB
dB
10.4
10.3
Bits
Bits
10.2
10.2
Bits
Bits
90
86
76
82
78
76
74
80
74.5
72.5
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
Full
25°C
25°C
88
88
85
94
85
85
25°C
78
77
76
dBc
77
76
dBc
96
25°C
86
90
83.7
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
Tested at 210 MSPS and 250 MSPS only.
Rev. 0 | Page 4 of 40
83.6
dBc
dBc
dBc
dBc
AD9239
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 3.
Parameter 1
CLOCK INPUTS (CLK+, CLK–)
Logic Compliance
Differential Input Voltage
Input Voltage Range
Internal Common-Mode Bias
Input Common-Mode Voltage
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Differential Input Resistance
Input Capacitance
LOGIC INPUTS (PDWN, CSB, SDI/
SDIO, SCLK, RESET, PGMx) 2
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (CSB)
Logic 0 Input Current (CSB)
Logic 1 Input Current
(SCLK, PDWN, SDI/SDIO,
RESET, PGMx)
Logic 0 Input Current
(SCLK, PDWN, SDI/SDIO,
RESET, PGMx)
Input Resistance
Input Capacitance
LOGIC OUTPUTS (SDO)
Logic 1 Voltage
Logic 0 Voltage
DIGITAL OUTPUTS
(DOUT + x, DOUT − x)
Logic Compliance
Differential Output Voltage
Common-Mode Level
1
2
AD9239BCPZ-170
Typ
Max
Full
Full
Full
LVPECL/LVDS/CMOS
0.2
6
AVDD −
AVDD +
0.3
1.6
1.2
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
16
20
24
4
LVPECL/LVDS/CMOS
0.2
6
AVDD −
AVDD +
0.3
1.6
1.2
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
16
20
24
4
LVPECL/LVDS/CMOS
0.2
6
AVDD −
AVDD +
0.3
1.6
1.2
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
16
20
24
4
0.8 ×
AVDD
0.8 ×
AVDD
0.8 ×
AVDD
Full
Full
0.2 ×
AVDD
Min
AD9239BCPZ-250
Typ
Max
Min
Full
Full
Full
Full
Full
Full
25°C
25°C
Min
AD9239BCPZ-210
Typ
Max
Temp
Unit
V p-p
V
V
V
V
V
μA
μA
kΩ
pF
V
0.2 ×
AVDD
0.2 ×
AVDD
V
Full
Full
Full
0
−60
55
0
−60
55
0
−60
55
μA
μA
μA
Full
0
0
0
μA
25°C
25°C
30
4
30
4
30
4
kΩ
pF
Full
1.2
Full
0
Full
Full
AVDD +
0.3
0.3
1.2
AVDD +
0.3
0.3
0
Current
mode
logic
0.8
DRVDD/2
Current
mode
logic
0.8
DRVDD/2
1.2
AVDD +
0.3
0.3
0
Current
mode
logic
0.8
DRVDD/2
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
Specified for 13 SDI/SDIO pins sharing the same connection.
Rev. 0 | Page 5 of 40
V
V
V
V
AD9239
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = –1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 4.
Parameter 1
CLOCK
Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
DATA OUTPUT PARAMETERS
Data Output Period or UI
(DOUT + x, DOUT − x)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (tLOCK)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down) 2
Pipeline Latency
Data Rate per Channel (NRZ)
Deterministic Jitter
Random Jitter
Channel-to-Channel Bit Skew
Channel-to-Channel Packet Skew 3
Output Rise/Fall Time
TERMINATION CHARACTERISTICS
Differential Termination Resistance
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
OUT-OF-RANGE RECOVERY TIME
Temp
Min
Full
Full
Full
170
2.65
2.65
AD9239BCPZ-170
Typ
Max
100
2.9
2.9
Min
AD9239BCPZ-210
Typ
Max
210
2.15
2.15
100
2.4
2.4
Min
250
1.8
1.8
AD9239BCPZ-250
Typ
Max
100
Unit
2.0
2.0
MSPS
ns
ns
Full
1/(16 × fCLK)
1/(16 × fCLK)
1/(16 × fCLK)
sec
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
50
0.8
4
250
50
50
0.8
4
250
50
50
0.8
4
250
50
2.72
10
6
0
+1
50
3.36
10
6
0
+1
50
4.0
10
6
0
+1
50
%
UI
μs
ns
μs
CLK cycles
Gbps
ps max
ps rms
sec
CLK cycles
ps
25°C
100
100
100
Ω
25°C
25°C
25°C
1.2
0.2
1
1.2
0.2
1
1.2
0.2
1
ns
ps rms
CLK cycles
40
1
40
40
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
Receiver dependent.
3
See the Digital Start-Up Sequence section.
2
Rev. 0 | Page 6 of 40
AD9239
TIMING DIAGRAM
SAMPLE
N+1
N
N – 40
ANALOG
INPUT SIGNAL
N – 39
N – 38
N – 37
SAMPLE
RATE CLOCK
...
SAMPLE
RATE CLOCK
...
SERIAL CODED SAMPLES: N – 40, N – 39, N – 38, N – 37 ...
SERIAL
DATA OUT
...
...
...
...
...
...
8-BIT HEADER
CHANNEL ID
48-BIT ADC
DATA-WORD
8-BIT ERROR
CORRECTION
06980-002
DATA PACKET 1
(64 BITS)
Figure 2. Timing Diagram
Table 1. Packet Protocol
Bits[64:57]
Header
(8 bits MSB first)
Bits[56:45]
Data 1
(12 bits MSB first)
Bits[44:33]
Data 2
(12 bits MSB first)
Bits[32:21]
Data 3
(12 bits MSB first)
Rev. 0 | Page 7 of 40
Bits[20:9]
Data 4
(12 bits MSB first)
Bits[8:1]
ECC
(8 bits MSB first)
AD9239
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Electrical
AVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
DOUT ± x to DRGND
SDO, SDI/SDIO, CLK± , VIN ± x,
VCMx, TEMPOUT, RBIAS to AGND
SCLK, CSB, PGMx, RESET,
PDWN to AGND
Environmental
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 10 sec)
Junction Temperature
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−2.0 V to +2.0 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints, maximizing
the thermal capability of the package.
Table 6. Thermal Resistance
Package Type
72-Lead LFCSP (CP-72-3)
θJA
16.2
θJB
7.9
θJC
0.6
Unit
°C/W
Typical θJA, θJB, and θJC values are specified for a 4-layer board in
still air. Airflow increases heat dissipation, effectively reducing
θJA. In addition, metal in direct contact with the package leads
from metal traces and through holes, ground, and power planes
reduces the θJA.
−0.3 V to AVDD + 0.3 V
−65°C to +125°C
−40°C to +85°C
300°C
ESD CAUTION
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 8 of 40
AD9239
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
NC
AVDD
VCM C
AVDD
VIN – C
VIN + C
AVDD
AVDD
AVDD
NC
AVDD
AVDD
AVDD
VIN + B
VIN – B
AVDD
VCM B
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN 1
INDICATOR
PIN 0 = EPAD = AGND
AD9239
TOP VIEW
(Not to Scale)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
NC
PGM0
PGM1
PGM2
PGM3
NC
AVDD
VCM A
AVDD
VIN – A
VIN + A
AVDD
AVDD
AVDD
CSB
SCLK
SDI/SDIO
SDO
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE GROUND PLANE
FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO
THE CUSTOMER BOARD INCREASES THE RELIABILITY OF THE SOLDER
JOINTS, MAXIMIZING THE THERMAL CAPABILITY OF THE PACKAGE.
06980-004
NC
AVDD
AVDD
RESET
DRGND
DRVDD
DOUT + D
DOUT – D
DOUT + C
DOUT – C
DOUT + B
DOUT – B
DOUT + A
DOUT – A
DRVDD
DRGND
PDWN
NC
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
TEMPOUT
RBIAS
AVDD
NC
NC
AVDD
VCM D
AVDD
VIN – D
VIN + D
AVDD
AVDD
AVDD
AVDD
CLK–
CLK+
AVDD
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
0
23, 34
4, 7, 9, 12, 13, 14,
15, 18, 20, 21, 41, 42,
43, 46, 48, 55, 57,
60, 61, 62, 64, 65,
66, 69, 71
24, 33
2
3
8
10
11
16
17
22
25
26
27
28
29
30
31
32
35
Mnemonic
AGND
DRGND
AVDD
Description
Analog Ground (Exposed Paddle).
Digital Output Driver Ground.
1.8 V Analog Supply.
DRVDD
TEMPOUT
RBIAS
VCM D
VIN − D
VIN + D
CLK−
CLK+
RESET
DOUT + D
DOUT − D
DOUT + C
DOUT − C
DOUT + B
DOUT − B
DOUT + A
DOUT − A
PDWN
1.8 V Digital Output Driver Supply.
Output Voltage to Monitor Temperature.
External Resistor to Set the Internal ADC Core Bias Current.
Common-Mode Output Voltage Reference (0.5 × AVDD).
ADC D Analog Complement.
ADC D Analog True.
Input Clock Complement.
Input Clock True.
Digital Output Timing Reset.
ADC D True Digital Output.
ADC D Complement Digital Output.
ADC C True Digital Output.
ADC C Complement Digital Output.
ADC B True Digital Output.
ADC B Complement Digital Output.
ADC A True Digital Output.
ADC A Complement Digital Output.
Power-Down.
Rev. 0 | Page 9 of 40
AD9239
Pin No.
37
38
39
40
44
45
47
50
51
52
53
56
58
59
67
68
70
1, 5, 6, 19, 36,
49, 54, 63, 72
Mnemonic
SDO
SDI/SDIO
SCLK
CSB
VIN + A
VIN − A
VCM A
PGM3
PGM2
PGM1
PGM0
VCM B
VIN − B
VIN + B
VIN + C
VIN − C
VCM C
NC
Description
Serial Data Output. Used for 4-wire SPI interface.
Serial Data Input/Serial Data IO for 3-Wire SPI Interface.
Serial Clock.
Chip Select Bar.
ADC A Analog Input True.
ADC A Analog Input Complement.
Common-Mode Output Voltage Reference (0.5 × AVDD).
Optional Pin to be Programmed by Customer.
Optional Pin to be Programmed by Customer.
Optional Pin to be Programmed by Customer.
Optional Pin to be Programmed by Customer.
Common-Mode Output Voltage Reference (0.5 × AVDD).
ADC B Analog Input Complement.
ADC B Analog Input True.
ADC C Analog Input True.
ADC C Analog Input Complement.
Common-Mode Output Voltage Reference (0.5 × AVDD).
No Connection.
Rev. 0 | Page 10 of 40
AD9239
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
AIN = –1.0dBFS
SNR = 64.88dB
ENOB = 10.49 BITS
SFDR = 77.57dBc
–20
AMPLITUDE (dBFS)
–40
–60
–80
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
80
–120
Figure 4. Single-Tone 32k FFT with fIN = 84.3 MHz, fSAMPLE = 170 MSPS
–40
AMPLITUDE (dBFS)
80
100
AIN = –1.0dBFS
SNR = 64.62dB
ENOB = 10.44 BITS
SFDR = 75.48dBc
–60
–80
–40
–60
–80
–100
10
20
30
40
50
FREQUENCY (MHz)
60
70
80
–120
06980-060
0
Figure 5. Single-Tone 32k FFT with fIN = 240.3 MHz, fSAMPLE = 170 MSPS
0
20
40
60
80
FREQUENCY (MHz)
100
120
06980-063
AMPLITUDE (dBFS)
40
60
FREQUENCY (MHz)
–20
–100
Figure 8. Single-Tone 32k FFT with fIN = 10.3 MHz, fSAMPLE = 250 MSPS
0
0
AIN = –1.0dBFS
SNR = 64.65dB
ENOB = 10.44 BITS
SFDR = 77.54dBc
–20
AIN = –1.0dBFS
SNR = 64.50dB
ENOB = 10.42 BITS
SFDR = 77.97dBc
–20
–40
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
20
0
AIN = –1.0dBFS
SNR = 63.95dB
ENOB = 10.33 BITS
SFDR = 78.90dBc
–20
–60
–80
–100
–40
–60
–80
–100
0
20
40
60
FREQUENCY (MHz)
80
100
–120
06980-061
–120
0
Figure 7. Single-Tone 32k FFT with fIN = 240.3 MHz, fSAMPLE = 210 MSPS
0
–120
–80
–100
06980-059
–120
–60
06980-062
–100
–40
Figure 6. Single-Tone 32k FFT with fIN = 84.3 MHz, fSAMPLE = 210 MSPS
0
20
40
60
80
FREQUENCY (MHz)
100
120
06980-064
AMPLITUDE (dBFS)
–20
AIN = –1.0dBFS
SNR = 63.13dB
ENOB = 10.19 BITS
SFDR = 76.07dBc
Figure 9. Single-Tone 32k FFT with fIN = 84.3 MHz, fSAMPLE = 250 MSPS
Rev. 0 | Page 11 of 40
AD9239
90
0
AIN = –1.0dBFS
SNR = 63.90dB
ENOB = 10.32 BITS
SFDR = 73.10dBc
88
86
84
–40
SFDR (dBFS)
AMPLITUDE (dBFS)
–20
–60
–80
82
170MSPS
250MSPS
80
78
76
74
–100
210MSPS
20
40
60
80
FREQUENCY (MHz)
100
120
70
50
06980-065
0
Figure 10. Single-Tone 32k FFT with fIN = 171.3 MHz, fSAMPLE = 250 MSPS
90
110
130 150 170
ENCODE (MSPS)
190
210
230
250
–10
0
Figure 13. SFDR vs. Encode, fIN = 84.3 MHz
0
100
AIN = –1.0dBFS
SNR = 63.41dB
ENOB = 10.24 BITS
SFDR = 77.49dBc
–20
90
SFDR (dBFS)
80
SNR (dBFS)
70
–40
SNR/SFDR (dB)
AMPLITUDE (dBFS)
70
06980-068
72
–120
–60
–80
60
50
SFDR (dB)
40
30
SNR (dB)
20
–100
0
20
40
60
80
FREQUENCY (MHz)
100
120
0
–90
06980-066
Figure 11. Single-Tone 32k FFT with fIN = 240.3 MHz, fSAMPLE = 250 MSPS
100
69
90
68
80
250MSPS
SNR/SFDR (dB)
210MSPS
50
SFDR (dB)
40
30
62
20
61
10
60
50
SNR (dBFS)
60
63
SNR (dB)
70
90
110
130 150 170
ENCODE (MSPS)
190
210
Figure 12. SNR vs. Encode, fIN = 84.3 MHz
230
250
0
–90
06980-067
SNR (dBFS)
65
170MSPS
–60
–50
–40
–30
–20
ANALOG INPUT LEVEL (dBFS)
SFDR (dBFS)
70
66
64
–70
Figure 14. SNR/SFDR vs. Analog Input Level, fIN = 84.3 MHz, fSAMPLE = 170 MSPS
70
67
–80
–80
–70
–60
–50
–40
–30
–20
ANALOG INPUT LEVEL (dBFS)
–10
0
06980-070
–120
06980-069
10
Figure 15. SNR/SFDR vs. Analog Input Level, fIN = 84.3 MHz, fSAMPLE = 210 MSPS
Rev. 0 | Page 12 of 40
AD9239
0
100
90
SFDR (dBFS)
80
SNR/SFDR (dB)
AMPLITUDE (dBFS)
SNR (dBFS)
70
60
50
SFDR (dB)
40
AIN1 AND AIN2 = –7.0dBFS
SFDR = 76.88dBc
IMD2 = –78.75dBc
IMD3 = –78.68dBc
–20
30
–40
–60
–80
SNR (dB)
20
–100
–80
–70
–60
–50
–40
–30
–20
ANALOG INPUT LEVEL (dBFS)
–10
0
–120
06980-071
0
–90
Figure 16. SNR/SFDR vs. Analog Input Level, fIN = 84.3 MHz, fSAMPLE = 250 MSPS
AMPLITUDE (dBFS)
100
–40
–60
–80
–40
–60
–80
10
20
30
40
50
FREQUENCY (MHz)
60
70
80
–120
06980-072
0
Figure 17. Two-Tone 32k FFT with fIN1 = 140.2 MHz and fIN2 = 141.3 MHz,
fSAMPLE = 170 MSPS
20
40
60
80
FREQUENCY (MHz)
100
120
Figure 20. Two-Tone 32k FFT with fIN1 = 140.2 MHz and fIN2 = 141.3 MHz,
fSAMPLE = 250 MSPS
0
0
AIN1 AND AIN2 = –7.0dBFS
SFDR = 75.44dBc
IMD2 = –78.34dBc
IMD3 = –75.44dBc
–20
0
06980-075
–100
AIN1 AND AIN2 = –7.0dBFS
SFDR = 74.29dBc
IMD2 = –76.51dBc
IMD3 = –74.30dBc
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–40
–60
–80
–100
20
40
60
FREQUENCY (MHz)
80
100
–120
06980-073
0
Figure 18. Two-Tone 32k FFT with fIN1 = 140.2 MHz and fIN2 = 141.3 MHz,
fSAMPLE = 210 MSPS
0
20
40
60
80
FREQUENCY (MHz)
100
120
06980-076
AMPLITUDE (dBFS)
80
AIN1 AND AIN2 = –7.0dBFS
SFDR = 74.48dBc
IMD2 = –76.10dBc
IMD3 = –74.48dBc
–20
–100
AMPLITUDE (dBFS)
40
60
FREQUENCY (MHz)
0
AIN1 AND AIN2 = –7.0dBFS
SFDR = 77.26dBc
IMD2 = –86.55dBc
IMD3 = –77.26dBc
–20
–120
20
Figure 19. Two-Tone 32k FFT with fIN1 = 170.2 MHz and fIN2 = 171.3 MHz,
fSAMPLE = 2 10 MSPS
0
–120
0
06980-074
10
Figure 21. Two-Tone 32k FFT with fIN1 = 170.2 MHz and fIN2 = 171.3 MHz,
fSAMPLE = 250 MSPS
Rev. 0 | Page 13 of 40
95
70
90
69
85
68
67
SNR, 170MSPS
SFDR (dB)
SNR (dB)
75
70
65
65
64
SNR (dB)
60
63
55
62
50
61
45
SNR, 210MSPS
66
0
50
100
150 200 250 300 350
AIN FREQUENCY (MHz)
400
450
500
SNR, 250MSPS
60
–40
Figure 22. SNR/SFDR Amplitude vs. AIN Frequency, fSAMPLE = 170 MSPS
–20
0
20
40
TEMPERATURE (°C)
60
80
06980-080
80
06980-077
AMPLITUDE (dBFS)
AD9239
Figure 25. SNR vs. Temperature, fIN = 84.3 MHz
90
95
90
85
SFDR, 210MSPS
80
70
65
SNR (dB)
60
SFDR, 250MSPS
80
SFDR (dB)
75
SFDR (dB)
AMPLITUDE (dBFS)
85
75
SFDR, 170MSPS
70
55
65
0
50
100
150 200 250 300 350
AIN FREQUENCY (MHz)
400
450
500
60
–40
06980-078
45
90
0.8
85
0.6
80
0.4
INL (LSB)
1.0
75
SFDR (dB)
70
65
0
20
40
TEMPERATURE (°C)
60
80
Figure 26. SFDR vs. Temperature, fIN = 84.3 MHz
95
0.2
0
–0.2
60
–0.4
55
–0.6
50
–0.8
45
0
50
100
150 200 250 300 350
AIN FREQUENCY (MHz)
400
450
500
–1.0
Figure 24. SNR/SFDR Amplitude vs. AIN Frequency, fSAMPLE = 250 MSPS
Rev. 0 | Page 14 of 40
0
500
1000
1500
2000 2500
CODE
3000
3500
Figure 27. INL, fIN = 9.7 MHz, fSAMPLE = 250 MSPS
4000
06980-082
SNR (dB)
06980-079
AMPLITUDE (dBFS)
Figure 23. SNR/SFDR Amplitude vs. AIN Frequency, fSAMPLE = 210 MSPS
–20
06980-081
50
AD9239
0.5
40000
INPUT REFERRED NOISE: 0.71 LSB
0.4
35000
0.3
30000
NUMBER OF HITS
DNL (LSB)
0.2
0.1
0
–0.1
–0.2
25000
20000
15000
10000
–0.3
500
1000
1500
2000 2500
CODE
3000
3500
4000
0
N–3
N–2
N–1
N
N+1
Figure 28. DNL, fIN = 9.7 MHz, fSAMPLE = 250 MSPS
35000
NPR = 52dB
NOTCH = 18.9MHz
NOTCH WIDTH = 1MHz
–20
30000
–40
AMPLITUDE (dBFS)
25000
20000
15000
10000
–60
–80
–100
–120
5000
N–2
N–1
N
N+1
N+2
N+3
MORE
BIN
–140
06980-106
N–3
0
20
40
60
80
FREQUENCY (Hz)
100
120
Figure 32. Noise Power Ratio (NPR), fSAMPLE = 250 MSPS
Figure 29. Input-Referred Noise Histogram, fSAMPLE = 170 MSPS
40000
90
INPUT REFERRED NOISE: 0.70 LSB
85
35000
80
30000
SFDR (dBc)
75
SNR/SFDR (dB)
25000
20000
15000
70
65
SNR (dB)
60
55
10000
50
5000
45
N–3
N–2
N–1
N
N+1
N+2
N+3
MORE
BIN
06980-107
0
Figure 30. Input-Referred Noise Histogram, fSAMPLE = 210 MSPS
40
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
ANALOG INPUT COMMON-MODE VOLTAGE (V)
1.8
Figure 33. SNR/SFDR vs. Analog Input Common-Mode Voltage,
fIN = 84.3 MHz, fSAMPLE = 250 MSPS
Rev. 0 | Page 15 of 40
06980-087
NUMBER OF HITS
MORE
0
INPUT REFERRED NOISE: 0.72 LSB
NUMBER OF HITS
N+3
Figure 31. Input-Referred Noise Histogram, fSAMPLE = 250 MSPS
40000
0
N+2
BIN
06980-109
0
06980-083
–0.5
06980-108
5000
–0.4
AD9239
0
–1
–3dB CUTOFF =
780MHz
AMPLITUDE (dBFS)
–2
–3
–4
–5
–6
–7
–8
10M
100M
AIN FREQUENCY (Hz)
1G
10G
06980-088
–9
–10
1M
Figure 34. Full-Power Bandwidth Amplitude vs. AIN Frequency, fSAMPLE = 250 MSPS
Rev. 0 | Page 16 of 40
AD9239
EQUIVALENT CIRCUITS
AVDD
AVDD
AVDD
1.2V
10kΩ
CLK+
10kΩ
CLK–
250Ω
SDI/SDIO
06980-009
06980-005
30kΩ
Figure 35. CLK± Inputs
Figure 39. Equivalent SDI/SDIO Input Circuit
AVDD
VIN + x
AVDD
BUF
2kΩ
AVDD
AVDD
BUF
~1.4V
2kΩ
TEMPOUT
VIN – x
06980-006
06980-010
BUF
Figure 40. Equivalent TEMPOUT Output Circuit
Figure 36. Analog Inputs
100Ω
175Ω
RBIAS
175Ω
30kΩ
06980-011
06980-007
SCLK,
PDWN,
PGMx,
RESET
Figure 37. Equivalent SCLK, PDWN, PGMx, RESET Input Circuit
Figure 41. Equivalent RBIAS Input/Output Circuit
AVDD
VCMx
26kΩ
06980-012
1kΩ
06980-008
CSB
175Ω
Figure 42. Equivalent VCMx Output Circuit
Figure 38. Equivalent CSB Input Circuit
Rev. 0 | Page 17 of 40
AD9239
AVDD
SDO
DRVDD
RTERM
VCM
DOUT + x
DOUT – x
345Ω
4mA
06980-089
4mA
AVDD
4mA
06980-030
4mA
Figure 44. Equivalent SDO Output Circuit
Figure 43. Equivalent Digital Output Circuit
Rev. 0 | Page 18 of 40
AD9239
THEORY OF OPERATION
series with each input can help reduce the peak transient current
injected from the output stage of the driving source.
The AD9239 architecture consists of a differential input buffer,
front-end sample-and-hold amplifier (SHA) followed by a
pipelined switched capacitor ADC. The quantized outputs from
each stage are combined into a final 12-bit result in the digital
correction logic. The pipelined architecture permits the first
stage to operate on a new input sample, while the remaining
stages operate on preceding samples. Sampling occurs on the
rising edge of the clock.
In addition, low-Q inductors or ferrite beads can be placed on
each leg of the input to reduce high differential capacitance at
the analog inputs and therefore achieve the maximum bandwidth
of the ADC. Such use of low-Q inductors or ferrite beads is
required when driving the converter front end at high intermediate
frequency (IF). Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive
network. This ultimately creates a low-pass filter at the input to
limit unwanted broadband noise. See the AN-827 Application Note
and the Analog Dialogue article “Transformer-Coupled Front-End
for Wideband A/D Converters” (Volume 39, April 2005) for
more information on this subject. In general, the precise values
depend on the application.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9239, the default input span is 1.25 V p-p. To configure the
ADC for a different input span, see Register 18. For the best
performance, an input span of 1.25 V p-p or greater should be
used (see Table 14 for details).
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output of
the pipeline ADC is put into its final serial format by the data
serializer, encoder, and CML drivers block. The data rate multiplier
creates the clock used to output the high speed serial data at the
CML outputs.
Differential Input Configurations
There are several ways to drive the AD9239 either actively or
passively; in either case, optimum performance is achieved by
driving the analog input differentially. For example, using the
ADA4937 differential amplifier to drive the AD9239 provides
excellent performance and a flexible interface to the ADC (see
Figure 45 and Figure 46) for baseband and second Nyquist
(~100 MHz IF) applications. In either application, 1% resistors
should be used for good gain matching. It should also be noted
that the dc-coupled configuration will show some degradation
in spurious performance. For further reference, consult the
ADA4937 data sheet.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9239 is a differential buffer. This
input is optimized to provide superior wideband performance
and requires that the analog inputs be driven differentially. SNR
and SINAD performance degrades if the analog input is driven
with a single-ended signal.
For best dynamic performance, the source impedances driving
VIN + x and VIN − x should be matched such that commonmode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. A small resistor in
3.3V
1.8V
1.8V
AVDD
DRVDD
205Ω
200Ω
62Ω
SIGNAL
GENERATOR
10kΩ
0.1µF
10kΩ
1.65V
VOCM
0.1µF
24Ω
ADA4937
VIN + x
OPTIONAL C
G = UNITY
200Ω
33Ω
+VS
C
R
–VS
24Ω
27Ω
0.1µF
33Ω
AD9239
ADC INPUT
IMPEDANCE
VIN – x
06980-090
1.25V p-p
205Ω
Figure 45. Differential Amplifier Configuration for AC-Coupled Baseband Applications
1.25V p-p
SIGNAL
GENERATOR
24Ω
200Ω
62Ω
0.1µF
33Ω
VIN + x
+VS
VOCM
ADA4937
G = UNITY
200Ω
OPTIONAL C
R
–VS
24Ω
27Ω
33Ω
VIN – x
1.8V
1.8V
AVDD
DRVDD
C
AD9239
ADC INPUT
IMPEDANCE
VCMx
205Ω
1.4V
Figure 46. Differential Amplifier Configuration for DC-Coupled Baseband Applications
Rev. 0 | Page 19 of 40
06980-091
3.3V
205Ω
AD9239
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 47 to Figure 49), to achieve the true performance of
the AD9239.
1.25V p-p
BALUN
1:1 Z
50Ω
0.1µF
06980-017
VIN – x
C
Single-Ended Input Configuration
06980-013
AGND
Figure 47. Differential Transformer-Coupled Configuration
for Baseband Applications
0.1μF
ADT1-1WT
1:1 Z RATIO
L
33Ω
VIN + x
65Ω
2.2pF
33Ω
ADC
AD9239
VIN – x
06980-014
250Ω
L
0.1μF
0.1μF
ADT1-1WT
1:1 Z RATIO
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance can degrade due to input common-mode
swing mismatch. If the application requires a single-ended input
configuration, ensure that the source impedances on each input
are well matched in order to achieve the best possible performance.
A full-scale input of 1.25 V p-p can be applied to the ADC’s
VIN + x pin while the VIN − x pin is terminated. Figure 51
details a typical single-ended input configuration.
C
33Ω
Figure 48. Differential Transformer-Coupled Configuration
for Wideband IF Applications
1.25V p-p
VIN – x
Figure 50. Differential Balun-Coupled Configuration
for Wideband IF Applications
ADC
AD9239
*CDIFF IS OPTIONAL
L
33Ω
ADC
AD9239
BALUN
1:1 Z
VIN + x
33Ω
1.25V p-p
4.7pF
66Ω
C
*CDIFF
0.1μF
VIN + x
1.25V p-p
49.9Ω
*CDIFF
33Ω
VIN + x
L
33Ω
25Ω
ADC
AD9239
0.1µF
33Ω
ADC
AD9239
VIN – x
C
VIN – x
0.1μF
06980-015
250Ω
VIN + x
0.1µF
Figure 49. Differential Transformer-Coupled Configuration
for Narrow-Band IF Applications
Rev. 0 | Page 20 of 40
*CDIFF IS OPTIONAL
Figure 51. Single-Ended Input Configuration
06980-016
1.25V p-p
0.1µF
33Ω
33Ω
0.1µF
Regardless of the configuration, the value of the shunt capacitor, C,
is dependent on the input frequency and may need to be reduced
or removed.
ADT1-1WT
1:1 Z RATIO
0.1µF
AD9239
0.1µF
CLK+
Figure 52 shows a preferred method for clocking the AD9239. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-toback Schottky diodes across the secondary transformer limit
clock excursions into the AD9239 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9239,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
CLK+
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
0.1µF
XFMR
50Ω
0.1µF
Figure 55. Single-Ended 1.8 V CMOS Sample Clock
CLK
06980-018
0.1µF
CLK–
0.1µF
240Ω
50Ω*
240Ω
06980-019
50Ω*
ADC
AD9239
CLK–
CLK
*50Ω RESISTORS ARE OPTIONAL.
Figure 53. Differential PECL Sample Clock
0.1µF
CLK+
CLK
0.1µF
CLK–
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
LVDS DRIVER
0.1µF
CLK+
100Ω
0.1µF
CLK
ADC
AD9239
CLK–
50Ω*
*50Ω RESISTORS ARE OPTIONAL.
06980-020
50Ω*
0.1µF
CLK+
ADC
AD9239
CLK–
Figure 56. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
100Ω
OPTIONAL
100Ω
*50Ω RESISTOR IS OPTIONAL.
CLK+
PECL DRIVER
CMOS DRIVER
0.1µF
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 53. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9518
family of clock drivers offers excellent jitter performance.
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
CLK
50Ω*
ADC
AD9239
CLK
39kΩ
*50Ω RESISTOR IS OPTIONAL.
Figure 52. Transformer-Coupled Differential Clock
0.1µF
ADC
AD9239
CLK–
0.1µF
CLK+
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
CLK+
CLK
0.1µF
SCHOTTKY
DIODES:
HSM2812
OPTIONAL
100Ω
0.1µF
CLK–
CLK+
CMOS DRIVER
CLK+
0.1µF
0.1µF
CLK
50Ω*
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
06980-021
For optimum performance, the AD9239 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
to 1.2 V and require no additional biasing.
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V and
therefore offers several selections for the drive logic voltage.
06980-022
CLOCK INPUT CONSIDERATIONS
Figure 54. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 55). Although the
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
is required on the clock duty cycle to maintain dynamic performance characteristics.
The AD9239 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling edge, providing an internal clock signal with a
nominal 50% duty cycle. This allows a wide range of clock input
duty cycles without affecting the performance of the AD9239.
When the DCS is on (default), noise and distortion performance
are nearly flat for a wide range of duty cycles. However, some
applications may require the DCS function to be off. If so, keep
in mind that the dynamic range performance may be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
Jitter in the rising edge of the input is an important concern,
and it is not reduced by the internal stabilization circuit. The
duty cycle control loop does not function for clock rates of less
than 50 MHz nominal. It is not recommended that this ADC
clock be dynamic in nature. Moving the clock around dynamically
requires long wait times for the back end serial capture to retime
and resynchronize to the receiving logic. This long time constant
far exceeds the time it takes for the DSC and PLL to lock and
stabilize. Only in rare applications would it be necessary to disable
the DCS circuitry of Register 9 (see Table 14). Keeping the DCS
circuit enabled is recommended to maximize ac performance.
Rev. 0 | Page 21 of 40
AD9239
Clock Jitter Considerations
2.0
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
1.8
Refer to the AN-501 Application Note, the AN-756 Application
Note, and the Analog Dialogue article “Analog-to-Digital Converter
Clock Optimization: A Test Engineering Perspective” (Volume 42,
Number 2, February 2008) for more in-depth information about
jitter performance as it relates to ADCs (visit www.analog.com).
0.5
POWER
1.0
0.4
0.8
0.3
CURRENT (mA)
1.2
0.6
0.2
0.4
IDRVDD
0
50
70
90
0.1
110
130
ENCODE (MSPS)
0
170
150
06980-056
0.2
Figure 58. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 170 MSPS
2.0
0.8
1.8
0.7
1.6
IAVDD
0.6
1.4
0.5
1.2
POWER
1.0
0.4
0.8
0.3
0.6
RMS CLOCK JITTER REQUIREMENT
0.2
0.4
120
IDRVDD
0.2
110
100
16 BITS
90
14 BITS
80
0
50
70
90
110
130
150
ENCODE (MSPS)
0.1
170
190
0
210
06980-057
130
Figure 59. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 210 MSPS
12 BITS
2.0
0.8
70
1.8
10 BITS
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
30
1
10
100
ANALOG INPUT FREQUENCY (MHz)
0.6
1.4
1000
Figure 57. Ideal SNR vs. Input Frequency and Jitter
0.5
POWER
1.2
1.0
0.4
0.8
0.3
CURRENT (mA)
40
0.7
0.6
Power Dissipation
0.2
0.4
As shown in Figure 58 to Figure 60, the power dissipated by the
AD9239 is proportional to its clock rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the digital
output drivers.
IDRVDD
0.1
0.2
0
50
70
90
110
130 150 170
ENCODE (MSPS)
190
210
230
0
250
06980-058
50
IAVDD
1.6
POWER (W)
60
06980-024
SNR (dB)
IAVDD
CURRENT (mA)
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9239.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
0.6
1.4
POWER (W)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
0.7
1.6
POWER (W)
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
0.8
Figure 60. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 250 MSPS
Rev. 0 | Page 22 of 40
AD9239
The output digital data from the AD9239 is coded and packetized,
which requires the device to have a certain start-up sequence.
The following steps should be initialized by the user to capture
coherent data at the receiving logic.
3.
4.
5.
6.
Initialize a soft reset via Bit 5 of Register 0 (see Table 14).
All PGMx pins are automatically initialized as sync pins by
default. These pins can be used to lock the FPGA timing
and data capture during initial startup. These pins are
respective to each channel (PGM3 = Channel A).
Each sync pin is held low until its respective PGMx pin
receives a high signal input from the receiver, during which
time the ADC outputs a training pattern.
The training pattern defaults to the values implemented by
the user in Register 19 through Register 20.
When the receiver finds the frame boundary, the sync
identification is deasserted high via the sync pin or via a
SPI write. The ADC outputs the valid data on the next packet
boundary. The time necessary for sync establishment is highly
dependent on the receiver logic processing. Refer to the
Switching Specifications section; the switching timing is
directly related to the ADC channel.
Once steady state operation for the device has occurred,
these pins can each be assigned to be a standby option by
using Register 53 (see Table 14). All other pins act as
universal sync pins.
The AD9239 digital outputs can interface with custom applicationspecific integrated circuits (ASICs) and field-programmable gate
array (FPGA) receivers, providing superior switching performance
in noisy environments. Single point-to-point net topologies are
recommended with a single differential 100 Ω termination resistor
placed as close to the receiver logic as possible. The common mode
of the digital output automatically biases itself to half the supply
of the receiver (that is, the common-mode voltage is 0.9 V for a
receiver supply of 1.8 V) if dc-coupled connecting is used. For
receiver logic that is not within the bounds of the DRVDD supply,
an ac-coupled connection should be used. Simply place a 0.1 μF
capacitor on each output pin and derive a 100 Ω differential
termination close to the receiver side.
If there is no far-end receiver termination or there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than 6 inches and that the differential output traces be close
together and at equal lengths.
To minimize skew and time misalignment between each
channel of the digital outputs, the following actions should be
taken to ensure that each channel data packet is within ±1 clock
cycle of its specified switching time. For some receiver logic,
this is not required.
1.
2.
3.
100Ω
DIFFERENTIAL
TRACE PAIR
DRVDD
DOUT + x
RECEIVER
100Ω
DOUT – x
VCM = DRVDD/2
OUTPUT SWING = 400mV p-p
Figure 61. DC-Coupled Digital Output Termination Example
Full power-down through external PDWN pin.
Chip reset via external RESET pin.
Power back up by releasing external PDWN pin.
VRXCM
DRVDD
Digital Outputs and Timing
The AD9239 has differential digital outputs that power up on
default. The driver current is derived on chip and sets the output
current at each output equal to a nominal 8 mA. Each output
presents a 100 Ω dynamic internal termination to reduce unwanted
reflections
100Ω
DIFFERENTIAL
0.1µF TRACE PAIR
DOUT + x
100Ω
DOUT – x
OR
RECEIVER
0.1µF
OUTPUT SWING = 400mV p-p
VCM = Rx VCM
Figure 62. AC-Coupled Digital Output Termination Example
Rev. 0 | Page 23 of 40
06980-093
1.
2.
A 100 Ω differential termination resistor should be placed at each
receiver input to result in a nominal 800 mV p-p swing at the
receiver. Alternatively, single-ended 50 Ω termination can be
used. When single-ended termination is used, the termination
voltage should be DRVDD/2; otherwise, ac coupling capacitors
can be used to terminate to any single-ended voltage.
06980-092
Digital Start-Up Sequence
AD9239
HEIGHT1: EYE DIAGRAM
600
TIE1: HISTOGRAM
(y1) –375.023m
(y2) +409.847m
(Δy) +784.671m
600
1
1
2
+
+
3
+
0.01
500
400
[email protected]: BATHTUB
–200
200
–400
–600
1E–6
300
1E–10
100
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL: 12000: 80091
–200
–100
0
100
TIME (ps)
0
200
1E–8
1E–12
–30
–10
10
TIME (ps)
1E–14
–0.5
30
0
ULS
06980-094
0
BER
HITS
VOLTAGE (mV)
0.0001
400
200
0.5
Figure 63. Digital Outputs Data Eye with Trace Lengths Less than 6 Inches on Standard FR-4, External 100 Ω Terminations at Receiver
HEIGHT1: EYE DIAGRAM
600
TIE1: HISTOGRAM
(y1) –402.016m
(y2) +398.373m
(Δy) +800.389m
300
1
1
2
+
+
3
+
0.01
250
400
[email protected]: BATHTUB
–200
100
–400
–600
1E–6
150
1E–10
50
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL 8000: 40044
–200
–100
0
100
TIME (ps)
200
0
1E–8
1E–12
–50
0
TIME (ps)
50
1E–14
–0.5
0
ULS
0.5
06980-095
0
BER
HITS
VOLTAGE (mV)
0.0001
200
200
Figure 64. Digital Outputs Data Eye with Trace Lengths Greater than 12 Inches on Standard FR-4, External 100 Ω Terminations at Receiver
An example of the digital output (default) data eye and a time
interval error (TIE) jitter histogram with trace lengths less than
6 inches on standard FR-4 material is shown in Figure 63. Figure 64
shows an example of trace lengths exceeding 12 inches on standard
FR-4 material. Notice that the TIE jitter histogram reflects the
decrease of the data eye opening as the edge deviates from the
ideal position. It is the user’s responsibility to determine if the
waveforms meet the timing budget of the design when the trace
lengths exceed 6 inches.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs in order to drive
longer trace lengths (see Register 15 in Table 14). Even though
this produces sharper rise and fall times on the data edges and is
less prone to bit errors, the power dissipation of the DRVDD
supply increases when this option is used. See the Memory Map
section for more details.
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement or gray
code, see the Memory Map section.
Table 8. Digital Output Coding
Code
4095
2048
2047
0
(VIN + x) − (VIN − x),
Input Span = 1.25 V p-p (V)
+0.625
0.00
−0.000305
−0.625
Digital Output Offset Binary
(D11 ... D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to N bits
times the sample clock rate times, in addition to some amount
of overhead to account for the 8-bit header and error correction,
for a maximum of 3.15 Gbps (that is, 12 bits × 210 MSPS × 25%
= 3.15 Gbps). The lowest typical clock rate is 100 MSPS. For
clock rates slower than 100 MSPS, refer to Register 21 in the SPI
Memory Map. This option allows the user to adjust the PLL
loop bandwidth in order to use clock rates as low as 50 MSPS.
Rev. 0 | Page 24 of 40
AD9239
Table 9. Flexible Output Test Modes
Output Test Mode
Bit Sequence
0000
0001
0010
Pattern Name
Off (default)
Midscale short
+Full-scale short
Digital Output Word 1
N/A
1000 0000 0000
1111 1111 1111
Digital Output Word 2
N/A
Same
Same
Subject to Data
Format Select
Yes
Yes
Yes
0011
0100
0101
0110
0111
−Full-scale short
Checkerboard
PN sequence long 1
PN sequence short1
One-/zero-word toggle
0000 0000 0000
1010 1010 1010
N/A
N/A
1111 1111 1111
Same
0101 0101 0101
N/A
N/A
0000 0000 0000
Yes
No
Yes
Yes
No
1
All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
Register 14 allows the user to invert the digital outputs from
their nominal state. This is not to be confused with inverting
the serial stream to an LSB-first mode. In default mode, as
shown in Figure 2, the MSB is first in the data output serial
stream. However, this can be inverted so that the LSB is first in
the data output serial stream.
There are eight digital output test pattern options available that
can be initiated through the SPI. This feature is useful when
validating receiver capture and timing. Refer to Table 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. It should be noted
that some patterns do not adhere to the data format select
option. In addition, custom user-defined test patterns can be
assigned in the 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, and
0x20 register addresses.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 or 511 bits. A description
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The only
difference is that the starting value must be a specific value
instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 − 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 10 for the initial values) and the
AD9239 inverts the bit stream with relation to the ITU standard.
Digital Output Scrambler and Error Code Correction
The data from the AD9239 is sent serially in packets of 64 bits.
These numbers are derived from the necessity to have the output
data streaming at 16× the encode clock. The data packets consist
of a header, data, and error correction code (that is, 8 Bits of
Header + 48 Bits of Data (4 Conv.) + 8 Bits of ECC = 64 Bits).
The 12-bit protocol is shown in Figure 2 and Table 1.
Error Correction Code
The error correction code (ECC) is a Hamming code due to the
ease of implementation. Seven bits are used for the ECC to
correct one error or detect one or two errors during transmission.
The MSB of the ECC is always 0 and is not used to detect an
error. The six LSBs of the ECC are the result of the XORs of the
given bits (see Figure 68 to Figure 75). These bits allow for a
parity check for any bit in the header and data field.
The seventh parity bit is applied to the entire packet after the
Hamming parity bits are calculated. This parity check allows
correction of an error in the data or in the ECC bits.
In the general implementation, the parity bits are located in the
power of 2 positions, but are pulled from these locations and
placed together at the end of the packet. Figure 68 to Figure 75
show which header and data bits are associated with the parity bits.
In the receiver, these parity checks are performed and the
receiver parity bits are calculated. The difference between the
received parity bits and the calculated parity bits indicate which
bit was in error.
Table 10. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
Initial
Value
0x0df
0x29b80a
First Three Output Samples
(MSB First)
0xdf9, 0x353, 0x301
0x591, 0xfd7, 0x0a3
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
Rev. 0 | Page 25 of 40
AD9239
Scramblers
There are three scramblers on the AD9239. The scramblers are
an Ethernet scrambler (x58 + x39 + 1), a SONET scrambler (x7 +
x6 + 1), and a static inverter scrambler (inverts bits at set locations
in the packet). The scramblers are used to help balance the number
of 1s and 0s in the packet.
The Ethernet and SONET scramblers work on scrambling the
whole packet (64 bits), the header and the data (56 bits), or just
the data (48 bits). The scrambler is self-synchronizing on the
descramble end or receive end and does not require an additional
sync bit. For a copy of either the Ethernet or SONET scrambler
code, send an email to [email protected]
Figure 65 and Figure 66 show the serial implementation of the
Ethernet and SONET scramblers. The parallel implementation
allows the scrambler and descrambler to run at a slower clock
rate and can be implemented in the fabric of a receiver.
The serial implementations of the Ethernet and SONET scramblers
more easily show what is being done. The parallel implementation
must be derived from the serial implementation. The end product
depends on how many bits need to be processed in parallel. For
the scrambler, 64 bits are processed even in the 56- and 48-bit
cases. To achieve this for 56 bits and 48 bits, a portion of two
samples is used to fill the rest of the input word.
Inverter Balance Example
The inverter implementation uses predetermined bit positions
to balance the packet in an overrange condition (all 1s or all 0s)
in the converter. The inversions are present in all conditions,
not just the overrange condition.
is balanced based on an overranged condition. If each packet is
balanced, the bit stream should be balanced. Instead of a random
sequence that changes from packet to packet, certain inverts are
set at predetermined bit positions within the packet. This allows
the decoding to be done in the receiver end. Figure 67 shows the
inverters in the packet for the 12-bit data case and the inverter
order in the header.
Table 11 shows the average value of the packet for various
conditions.
Table 11. Average of 1s and 0s in Overrange Conditions
Assuming Header Bits are All 0
No Scramble (Data = 0)
No Scramble (Data = 1)
Average of Negative and Positive
Overrange
Scramble Only Data (Data = 0)
Scramble Only Data (Data = 1)
Average of Negative and Positive
Overrange
Scramble Data and Header (Data = 0)
Scramble Data and Header (Data = 1)
Average of Negative and Positive
Overrange
12-Bit
0
0.844
0.422
ECC
00000000
00111111
0.375
0.469
0.422
00000000
00111111
0.437
0.531
0.484
00000000
00111111
If the analog signal is out of range, there should be about the same
number of out-of-range positive and out-of-range negative values.
The average for no scrambling and for scrambling just the data
is about the same. If the header is used to indicate out of range,
the balance improves for the 12-bit case.
The descrambler can be based off any number of bits the user
chooses to process. In the inverter-based scrambler, the packet
Rev. 0 | Page 26 of 40
AD9239
POLYNOMIAL = 1 + x39 + x58
D58
S57
S56
S19
S18
S1
S0
S57
S56
S19
S18
S1
S0
S58
06980-025
S58
D58
Figure 65. Serial Implementation of Ethernet Scrambler
POLYNOMIAL = 1 + x6 + x7
D7
S6
S5
S4
S3
S2
S1
S0
S6
S5
S4
S3
S2
S1
S0
S7
06980-026
S7
D7
Figure 66. Serial Implementation of SONET Scrambler
h7
h6
h5
h4
h1
h0
D1
D1
D1
<11> <10> <9>
D1
<8>
D1
<7>
D1
<6>
D1
<5>
D1
<4>
D1
<3>
D1
<2>
D1
<1>
D1
D2
D2
D2
<0> <11> <10> <9>
D2
<8>
D2
<7>
D2
<6>
D2
<5>
D2
<4>
D2
<3>
D2
<2>
D2
<1>
D2
<0>
D3
D3
D3
<11> <10> <9>
D3
<8>
D3
<7>
D3
<6>
D3
<5>
D3
<4>
D3
<3>
D3
<2>
D3
<1>
D3
D4
D4
D4
<0> <11> <10> <9>
D4
<8>
D4
<7>
D4
<4>
D4
<3>
D4
<2>
D4
<1>
D4
<0>
0
p7
p6
p5
p1
D4
<5>
h2
p4
p3
p2
06980-105
D4
<6>
h3
= INVERTED BIT
Figure 67. Scrambler Inverters for 64-Bit Packet: 12-Bit Case
Rev. 0 | Page 27 of 40
AD9239
Calculating the Parity Bits for the Hamming Code
is just the inversion. A separate document will show the proper
way to correct an error in the transmission.
The Hamming bits are defined as follows. The definition is
shown in the charts for a 12-bit example. The Hamming parity
bits are shown interleaved in the data. This makes it easier to
see the numeric relationship. The decoding on the receive side
h7
h6
h5
h4
h1
h0
D1
D1
D1
<11> <10> <9>
D1
<8>
D1
<7>
D1
<6>
D1
<5>
D1
<4>
D1
<3>
D1
<2>
D1
<1>
D1
D2
D2
D2
<0> <11> <10> <9>
D2
<8>
D2
<7>
D2
<6>
D2
<5>
D2
<4>
D2
<3>
D2
<2>
D2
<1>
D2
<0>
D3
D3
D3
<11> <10> <9>
D3
<8>
D3
<7>
D3
<6>
D3
<5>
D3
<4>
D3
<3>
D3
<2>
D3
<1>
D3
D4
D4
D4
<0> <11> <10> <9>
D4
<8>
D4
<7>
D4
<4>
D4
<3>
D4
<2>
D4
<1>
D4
<0>
0
p7
p6
p5
D4
<6>
D4
<5>
h3
h2
p4
p3
p2
p1
06980-096
The p8 bit (MSB of the parity bits) will always be 0. The p7 bit is
a parity bit for the entire packet after the other parity bits are
calculated.
h1
h0
D1
D1
D1
<11> <10> <9>
D1
<8>
D1
<7>
D1
<6>
D1
<5>
D1
D2
D2
D2
<0> <11> <10> <9>
D2
<8>
D2
<7>
D2
<6>
D2
<5>
D2
<4>
D2
<3>
D2
<2>
D2
<1>
D3
<6>
D3
<5>
D3
<4>
D3
<3>
D3
<2>
D3
<1>
D3
D4
D4
<0> <11> <10>
D4
<3>
p4
D4
<2>
D4
<1>
D4
<0>
p3
p7
h7
h6
h5
D1
<4>
D1
<3>
D1
<2>
D1
<1>
p6
D2
D3
D3
D3
<0> <11> <10> <9>
D3
<8>
D3
<7>
p5
D4
<9>
D4
<5>
D4
<4>
D4
<8>
D4
<7>
h4
D4
<6>
h3
h2
0
p2
p1
06980-097
Figure 68. 64-Bit Packet: 12-Bit Case
h7
h5
h3
h1
D1
<11>
D1
<9>
D1
<7>
D1
<5>
D1
<3>
D1
<1>
D2
<11>
D2
<9>
D2
<7>
D2
<5>
D2
<3>
D2
<1>
D2
<0>
D3
<10>
D3
<8>
D3
<6>
D3
<4>
D3
<2>
D3
<0>
D4
<10>
D4
<9>
D4
<7>
D4
<5>
D4
<3>
D4
<2>
D4
<0>
0
p1
p1 = h7^h5^h3^h1^d1<11>^d1<9>^d1<7>^d1<5>^d1<3>^d1<1>^d2<11>^d2<9>^d2<7>^d2<5>^d2<3>^d2<1>^d2<0>
^d3<10>^d3<8>^d3<6>^d3<4>^d3<2>^d3<0>^d4<10>^d4<9>^d4<7>^d4<5>^d4<3>^d4<2>^d4<0>^0
06980-098
Figure 69. 64-Bit Packet Hamming Template for 12-Bit Case
Figure 70. p1 Bit for 64-Bit Packet: 12-Bit Case
D1
D1
<11> <10>
D1
<7>
D1
<6>
D2
D2
<11> <10>
D2
<7>
D2
<6>
D2
<3>
D2
<2>
D2
D3
<0> <11>
D3
<8>
D3
<7>
D3
<4>
D3
<3>
D3
D4
<0> <11>
D4
<9>
D4
<5>
D4
<4>
D4
<2>
D4
<1>
h6
D1
<3>
D1
<2>
D4
<8>
h3
h2
0
p2
p2 = h7^h6^h3^h2^d1<11>^d1<10>^d1<7>^d1<6>^d1<3>^d1<2>^d2<11>^d2<10>^d2<7>^d2<6>^d2<3>^d2<2>^
d2<0>^d3<11>^d3<8>^d3<7>^d3<4>^d3<3>^d3<0>^d4<11>^d4<9>^d4<8>^d4<5>^d4<4>^d4<2>^d4<1>^0
Figure 71. p2 Bit for 64-Bit Packet: 12-Bit Case
Rev. 0 | Page 28 of 40
06980-099
h7
D1
D1
D1
<11> <10> <9>
D1
<8>
D1
<0>
D2
<7>
D2
<6>
D2
<5>
D2
<4>
D2
D3
D3
D3
<0> <11> <10> <9>
D3
<4>
D3
<3>
D3
<2>
D3
<1>
D4
<9>
D4
<2>
D4
<1>
D4
<0>
p3
h7
h6
h5
h4
D1
<3>
D1
<2>
D1
<1>
D4
<8>
D4
<7>
D4
<6>
p3 = h7^h6^h5^h4^d1<11>^d1<10>^d1<9>^d1<8>^d1<3>^d1<2>^d1<1>^d1<0>^d2<7>^d2<6>^d2<5>^d2<4>^d2<0>^
d3<11>^d3<10>^d3<9>^d3<4>^d3<3>^d3<2>^d3<1>^d4<9>^d4<8>^d4<7>^d4<6>^d4<2>^d4<1>^d4<0>
06980-100
AD9239
h7
h6
h5
D1
<3>
D1
<2>
D1
<1>
h4
h3
h2
h1
h0
D1
D2
D2
D2
<0> <11> <10> <9>
D2
<8>
D2
D3
D3
D3
<0> <11> <10> <9>
D3
<8>
D3
<7>
D3
<6>
D3
<5>
D4
<9>
D4
<5>
D4
<4>
D4
<3>
p4
D4
<8>
D4
<7>
D4
<6>
p4 = h7^h6^h5^h4^h3^h2^h1^h0^d1<3>^d1<2>^d1<1>^d1<0>^d2<11>^d2<10>^d2<9>^d2<8>^d2<0>^d3<11>^
d3<10>^d3<9>^d3<8>^d3<7>^d3<6>^d3<5>^d4<9>^d4<8>^d4<7>^d4<6>^d4<5>^d4<4>^d4<3>
06980-101
Figure 72. p3 Bit for 64-Bit Packet: 12-Bit Case
Figure 73. p4 Bit for 64-Bit Packet: 12-Bit Case
h4
h3
h2
h1
h0
D1
D1
D1
<11> <10> <9>
D1
<8>
D1
<7>
D2
D3
D3
D3
<0> <11> <10> <9>
D3
<8>
D3
<7>
D3
<6>
D3
<5>
D3
<4>
D3
<1>
D3
D4
D4
<0> <11> <10>
h7
h6
h5
D1
<6>
D1
<5>
D1
<4>
D3
<3>
D3
<2>
06980-102
p5
p5 = h7^h6^h5^h4^h3^h2^h1^h0^d1<11>^d1<10>^d1<9>^d1<8>^d1<7>^d1<6>^d1<5>^d1<4>^d2<0>^d3<11>^
d3<10>^d3<9>^d3<8>^d3<7>^d3<6>^d3<5>^d3<4>^d3<3>^d3<2>^d3<1>^d3<0>^d4<11>^d4<10>
Figure 74. p5 Bit for 64-Bit Packet: 12-Bit Case
D1
<4>
h7
h6
h5
D1
<3>
D1
<2>
D1
<1>
h1
h0
D1
D1
D1
<11> <10> <9>
D1
<8>
D1
<7>
D1
<6>
D1
<5>
D1
D2
D2
D2
<0> <11> <10> <9>
D2
<8>
D2
<7>
D2
<4>
D2
<3>
D2
<2>
D2
<1>
h4
h3
h2
D2
<6>
D2
<5>
p6 = h7^h6^h5^h4^h3^h2^h1^h0^d1<11>^d1<10>^d1<9>^d1<8>^d1<7>^d1<6>^d1<5>^d1<4>^d1<3>^d1<2>^d1<1>^
d1<0>^d2<11>^d2<10>^d2<9>^d2<8>^d2<7>^d2<6>^d2<5>^d2<4>^d2<3>^d2<2>^d2<1>
Figure 75. p6 Bit for 64-Bit Packet: 12-Bit Case
Rev. 0 | Page 29 of 40
06980-103
p6
AD9239
TEMPOUT Pin
The TEMPOUT pin can be used as a course temperature sensor
to monitor the internal die temperature of the device. This pin
typical has a 734 mV output with a clock rate of 250 MSPS and
a negative temperature going coefficient of −1.12 mV/C. The
voltage response of this pin is characterized in Figure 76.
SDO Pin
0.79
The SDO pin is for use in applications that require a 4-wire SPI
mode operation. For normal operation, it should be tied low to
AGND through a 10 kΩ resistor. Alternatively, the device pin
can be left open, and the 345 Ω internal pull-down resistor pulls
this pin low. This pin adheres to only 1.8 V logic.
0.77
SDI/SDIO Pin
0.85
0.83
TEMPOUT PIN VOLTAGE (V)
the power-down feature is enabled, the chip continues to function
after PDWN is pulled low without requiring a reset. The AD9239
returns to normal operating mode when the PDWN pin is pulled
low. This pin is only 1.8 V tolerant.
0.81
The SDI/SDIO pin is for use in applications that require either a
4- or 3-wire SPI mode operation. For normal operation, it should
be tied low to AGND through a 10 kΩ resistor. Alternatively,
the device pin can be left open, and the 30 kΩ internal pulldown resistor pulls this pin low. This pin is only 1.8 V tolerant.
0.75
0.73
0.71
0.69
0.67
SCLK Pin
0
10 20 30 40
TEMPERATURE (°C)
50
60
70
80
06980-055
0.65
–40 –30 –20 –10
For normal operation, the SCLK pin should be tied to AGND
through a 10 kΩ resistor. Alternatively, the device pin can be left
open, and the 30 kΩ internal pull-down resistor pulls this pin low.
This pin is only 1.8 V tolerant.
Figure 76. TEMPOUT Pin Voltage vs. Temperature
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) between ground and the RBIAS pin.
The resistor current is derived on chip and sets the AVDD current
of the ADC to a nominal 725 mA at 250 MSPS. Therefore, it is
imperative that a 1% or less tolerance on this resistor be used to
achieve consistent performance.
VCMx Pins
The common-mode output pins can be enabled through the SPI
to provide an external reference bias voltage of 1.4 V for driving the
VIN + x/VIN − x analog inputs. These pins may be required when
connecting external devices, such as an amplifier or transformer,
to interface to the analog inputs.
RESET Pin
The RESET pin sets all SPI registers to their default values and
the datapath. Using this pin requires the user to resync the
digital outputs. This pin is only 1.8 V tolerant.
PDWN Pin
When asserted high, the PDWN pin turns off all the ADC
channels, including the output drivers. This function can be
changed to a standby function. See Register 8 in Table 14. Using
this feature allows the user to put all channels into standby mode.
The output drivers transmit pseudorandom data until the outputs
are disabled using Register 14.
By asserting the PDWN pin high, the AD9239 is placed into
power-down mode, shutting down the reference, reference buffer,
PLL, and biasing networks. In this state, the ADC typically
dissipates 3 mW. If any of the SPI features are changed before
CSB Pin
For normal operation, the CSB pin should be tied high to
AVDD through a 10 kΩ resistor. Alternatively, the device pin
can be left open, and the 26 kΩ internal pull-up resistor pulls
this pin high. By tying the CSB pin to AVDD, all SCLK and
SDI/SDIO information is ignored. In comparison, by tying the
CSB pin low, all information on the SDO and SDI/SDIO pins
are written to the device. This feature allows the user to reduce
the number of traces to the device if necessary. This pin is only
1.8 V tolerant.
PGMx Pins
All PGMx pins are automatically initialized as a sync pin by
default. These pins are used to lock the FPGA timing and data
capture during initial startup. These pins are respective to each
channel (PGM3 = Channel A). The sync pin should be pulled
low until this pin receives a high signal input from the receiver,
during which time the ADC outputs a training word. The training
word defaults to the values implemented by the user in Register 19
through Register 20. When the receiver finds the frame boundary,
the sync identification is deasserted high and the ADC outputs
the valid data on the next packet boundary.
Once steady state operation for the device has occurred, these
pins can be assigned as a standby option using Register 53 in
Table 14. All other pins change to a global sync pin.
This pin is only 1.8 V tolerant.
Rev. 0 | Page 30 of 40
AD9239
SERIAL PORT INTERFACE (SPI)
The AD9239 serial port interface allows the user to configure the
converter for specific functions or operations through a structured
register space provided in the ADC. This may provide the user
with additional flexibility and customization, depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, as documented
in the Memory Map section. Detailed operational information
can be found in the Analog Devices, Inc., AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Four pins define the SPI: SCLK, SDI/SDIO, SDO, and CSB (see
Table 12). The SCLK pin is used to synchronize the read and
write data presented to the ADC. The SDI/SDIO pin is a dualpurpose pin that allows data to be sent to and read from the
internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 12. Serial Port Pins
Pin
SCLK
SDI/SDIO
SDO
CSB
Function
Serial Clock. The serial shift clock input. SCLK is used
to synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or output, depending on
the SPI wire mode and instruction sent and the
relative position in the timing frame.
Serial Data Output is used only in 4-wire SPI mode.
When set, the SDO pin becomes active. When cleared,
the SDO pin remains in tristate, and all read data is
routed to the SDI/SDIO pin.
Chip Select Bar (Active Low). This control gates the
read and write cycles.
The falling edge of the CSB in conjunction with the rising edge of
the SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted, followed by
one or more data bytes, which is determined by Bit Field W0 and
Bit Field W1. An example of the serial timing and its definitions
can be found in Figure 78 and Table 13.
During normal operation, CSB is used to signal to the device
that SPI commands are to be received and processed. When
CSB is brought low, the device processes SCLK and SDI/SDIO
to execute instructions. Normally, CSB remains low until the
communication cycle is complete. However, if connected to a
slow device, CSB can be brought high between bytes, allowing
older microcontrollers enough time to transfer data into shift
registers. CSB can be stalled when transferring one, two, or three
bytes of data. When W0 and W1 are set to 11, the device enters
streaming mode and continues to process data, either reading
or writing, until CSB is taken high to end the communication
cycle. This allows complete memory transfers without requiring
additional instructions. Regardless of the mode, if CSB is taken
high in the middle of a byte transfer, the SPI state machine is
reset and the device waits for a new instruction.
In addition to the operation modes, the SPI port configuration
influences how the AD9239 operates. For applications that do
not require a control port, the CSB line can be tied and held
high. This places the SDI/SDIO pin into its secondary mode, as
defined in the SDI/SDIO Pin section. CSB can also be tied low to
enable 2-wire mode. When CSB is tied low, SCLK and SDI/SDIO
are the only pins required for communication. Although the
device is synchronized during power-up, the user should ensure
that the serial port remains synchronized with the CSB line
when using this mode. When operating in 2-wire mode, it is
recommended to use a 1-, 2-, or 3-byte transfer exclusively.
Without an active CSB line, streaming mode can be entered but
not exited.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the SDI/SDIO pin to change from
an input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 12 constitute the physical interface
between the user’s programming device and the serial port of
the AD9239. The SDO, SCLK and CSB pins function as inputs
when using the SPI. The SDI/SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
If multiple SDI/SDIO pins share a common connection, care
should be taken to ensure that proper VOH levels are met. Assuming
the same load for each AD9239, Figure 77 shows the number of
SDI/SDIO pins that can be connected together and the resulting
VOH level. This interface is flexible enough to be controlled by
either serial PROMS or PIC mirocontrollers, providing the
user with an alternative method, other than a full SPI controller,
to program the ADC (see the AN-812 Application Note).
For users who wish to operate the ADC without using the
SPI, remove any connections from the CSB, SCLK, SDO, and
SDI/SDIO pins. By disconnecting these pins from the control bus,
the ADC can function in its most basic operation. Each of these
pins has an internal termination that floats to its respective level.
Rev. 0 | Page 31 of 40
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715
0
10
20
30
40
50
60
70
80
90
100
NUMBER OF SDI/SDIO PINS CONNECTED TOGETHER
06980-104
VOH (V)
AD9239
Figure 77. SDI/SDIO Pin Loading
tDS
tS
tHI
tCLK
tDH
tH
tLO
CSB
DON’T CARE
SDIO
DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
06980-028
SCLK
Figure 78. Serial Timing Details
Table 13. Serial Timing Definitions
Parameter
tDS
tDH
tCLK
tS
tH
tHI
tLO
tEN_SDI/SDIO
Timing (Minimum, ns)
5
2
40
5
2
16
16
10
tDIS_SDI/SDIO
10
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDI/SDIO pin to switch from an input to an output relative to the
SCLK falling edge (not shown in Figure 78)
Minimum time for the SDI/SDIO pin to switch from an output to an input relative to the
SCLK rising edge (not shown in Figure 78)
Rev. 0 | Page 32 of 40
AD9239
MEMORY MAP
READING THE MEMORY MAP TABLE
RESERVED LOCATIONS
Each row in the memory map register table (Table 14) has eight
bit locations. The memory map is divided into three sections: the
chip configuration registers (Address 0x00 to Address 0x02), the
device index and transfer registers (Address 0x05 and
Address 0xFF), and the ADC functions registers (Address 0x08 to
Address 0x53).
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The Bit 7 column is the start of the default
hexadecimal value given. For example, Address 0x09, the clock
register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6
= 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and
Bit 0 = 1, or 0000 0001 in binary. This setting is the default for
the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0
of this address, followed by a 0x01 in Register 0xFF (transfer bit),
the duty cycle stabilizer turns off. It is important to follow each
writing sequence with a transfer bit to update the SPI registers. For
more information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
DEFAULT VALUES
When the AD9239 comes out of a reset, critical registers are
preloaded with default values. These values are indicated in
Table 14, where an X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Rev. 0 | Page 33 of 40
AD9239
Table 14. Memory Map Register
Addr. Register
(MSB)
(Hex) Name
Bit 7
Chip Configuration Registers
00
chip_port_
SDO active
(not
config (local,
master)
required,
ignored if
not used)
01
chip_id
(global)
02
chip_grade
(global)
Bit 6
Bit 5
LSB
first
Soft
reset
Bit 4
Bit 2
Bit 1
ADC B
ADC C
ADC D
0x0F
SW
transfer
1 = on
0 = off
(default)
0x00
00 = chip run
(default)
01 = full power-down
10 = standby
11 = reset
0x00
Determines
various generic modes
of chip
operation.
Duty
cycle
stabilize
1 = on
(default)
0 = off
0x01
Turns the
internal
duty cycle
stabilizer
on and off.
0x00
When set,
the test data
is placed on
the output
pins in place
of normal
data.
0x00
When Bit 0
is set, the
built-in selftest function
is initiated.
device_
update (local,
master)
ADC Functions Registers
08
modes
(local)
09
Clock
(global)
0D
test_io
(local)
0E
test_bist
(local)
External
PDWN
pin
function
00 = full
PDWN
(default)
01 =
standby
Reset PN
long gen
1 = on
0 = off
(default)
Reset PN
short gen
1 = on
0 = off
(default)
Flex output test mode
0000 = off (normal operation)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
BIST init
1 = on
0 = off
(default)
Rev. 0 | Page 34 of 40
Default
Notes/
Comments
Read
only
Read
only
Speed grade
010 = 170
100 = 210
101 = 250
ADC A
Default
Value
(Hex)
0x18
16 bit
address
(default
mode for
ADCs)
8-bit Chip ID Bits[2:0]
0x0B – AD9239 – 12-bit quad
Device Index and Transfer Registers
05
device_
index_A
(global)
FF
Bit 3
(LSB)
Bit 0
BIST
enable
1 = on
0 = off
(default)
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Synchronously
transfers
data from
the master
shift register
to the slave.
AD9239
Addr.
(Hex)
0F
Register
Name
adc_input
(local)
10
offset
(local)
14
output_mode
(local/global)
15
output_adjust
(global)
18
vref
(global)
19
user_
patt1_lsb
(local)
user_
patt1_msb
(local)
user_
patt2_lsb
(local)
user_
patt2_msb
(local)
user_
patt3_lsb
(local)
user_
patt3_msb
(local)
1A
1B
1C
1D
1E
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
6-bit Device Offset Adjustment[5:0]
011111 = +31 LSB
011110 = +30 LSB
011101 = +29 LSB
…
000010 = +2 LSB
000001 = +1 LSB
000000 = 0 LSB
111111 = −1 LSB
111110 = −2 LSB
111101 = −3 LSB
…
100001 = −31 LSB
100000 = −32 LSB
Output
enable bar
(local)
1 = off
0 = on
(default)
Bit 2
Analog
disconnect
enable
1 = on
0 = off
(default)
Output
invert
(global)
enable
1 = on
0 = off
(default)
Bit 1
VCM
enable
1 = on
0 = off
(default)
(LSB)
Bit 0
Data format select
(global)
00 = offset binary
(default)
01 = twos
complement
10 = gray code
Output Drive
Current[1:0]
00 = 400 mV
(default)
01 = 500 mV
10 = 440 mV
11 = 320 mV
Default
Value
(Hex)
0x00
Default
Notes/
Comments
0x00
Device
offset
trim.
0x00
Configures
the outputs
and the
format of
the data.
0x00
VCM output
adjustments.
00h
Select
adjustments
for VREF.
User-defined
pattern,
1 LSB.
User-defined
pattern,
1 MSB
User-defined
pattern,
2 LSB
User-defined
pattern,
2 MSB
User-defined
pattern,
3 LSB
User-defined
pattern,
3 MSB
B7
B6
B5
Ref_Vfs[4:0]
Reference full-scale adjust
10000 = 1.14 V p-p FS
10001 = 1.1575 V p-p FS
10010 = 1.175 V p-p FS
10011 = 1.1925 V p-p FS
…
11111 = 1.4025 V p-p FS
00000 = 1.42 V p-p FS
00001 = 1.4375 V p-p FS
…
01110 = 1.6825 V p-p FS
01111 = 1.7 V p-p FS
B4
B3
B2
B15
B14
B13
B12
B11
B10
B9
B8
0xAA
B7
B6
B5
B4
B3
B2
B1
B0
0xAA
B15
B14
B13
B12
B11
B10
B9
B8
0xAA
B7
B6
B5
B4
B3
B2
B1
B0
0xAA
B15
B14
B13
B12
B11
B10
B9
B8
0xAA
Rev. 0 | Page 35 of 40
B1
B0
0xAA
AD9239
Addr.
(Hex)
1F
Bit 1
B1
(LSB)
Bit 0
B0
Default
Value
(Hex)
0xAA
B9
B8
0xCC
Register
Name
user_
patt4_lsb
(local)
user_
patt4_msb
(local)
serial_control
(global)
(MSB)
Bit 7
B7
Bit 6
B6
Bit 5
B5
Bit 4
B4
Bit 3
B3
Bit 2
B2
B15
B14
B13
B12
B11
B10
24
misr_lsb
(local)
B7
B6
B5
B4
PLL
high
encode
rate
mode
(global)
0 = low
rate
1 = high
rate
(default)
B3
B2
B1
B0
0x00
25
misr_msb
(local)
B15
B14
B13
B12
B11
B10
B9
B8
0x00
32
adi_link_
options
(global)
34
Channel ID
(local)
coarse_
gain_adj
(local)
20
21
50
51
fine_
gain_adj
(local)
52
gain_cal_ctl
53
Dynamic
pgm pins
(global)
Scramble
Scramble options
OverData flow
enable
range in 00 = inverted
order
1 = on
01 = SONET (default)
header
0=
(default)
10 = Ethernet
1 = on
ECC last
0 = off
(default)
(default)
0 = off
1=
Scrambler
last
(Override
0x032[5])
Channel ID
(Only Bits[3:0] used if overrange is included in header)
Coarse Gain Adjust[5:0] = Output[63:0]
000000 = 0000…0001
000001 = 0000…0011
000010 = 0000…0111
…
111101 = 0011…1111
111110 = 0111…1111
111111 = 1111…1111
Fine Gain Adjust[3:0] = Output[15:0]
0000 = 0000000000000001
0001 = 0000000000000010
0010 = 0000000000000100
…
1101 = 0010000000000000
1110 = 0100000000000000
1111 = 1000000000000000
Gain cal
Gain cal
Gain quarenable
resetb
ter LSB
1 = on
1 = on
1 = on
0 = off
(default)
0 = off
(default)
0 = off
(default)
pgm_0
pgm_1
pgm_2
00 = sync
00 = sync
00 = sync
01 = standby D
01 = standby C
01 = standby B
10 = standby D and A
10 = standby C and B
10 = standby B and C
11 = standby D and C
11 = standby C and D
11 = standby B and A
Hamming
enable
1 = on
(default)
0 = off
Gain adjust
enable
1 = on
0 = off
(default)
Temp. sensor
enable
1 = on
0 = off
(default)
pgm_3
00 = sync
01 = standby A
10 = standby A and D
11 = standby A and B
0x08
Scramble
data only
0=
scramble
header
and data
(default)
1=
scramble
data only
Rev. 0 | Page 36 of 40
0x4B
Default
Notes/
Comments
User-defined
pattern,
4 LSB.
User defined
pattern
4 MSB.
Serial stream
control.
Least
significant
byte of
MISR.
Read only.
Most
significant
byte of
MISR.
Read only.
Default is
56-bit
SONET
scrambler
with over
range in the
header bits.
0x00
0x00
00h
0x02
0x00
Standby =
ADC core
off, PN23
enabled,
serial channel
enabled.
AD9239
Power and Ground Recommendations
Exposed Paddle Thermal Heat Slug Recommendations
When connecting power to the AD9239, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the printed circuit board (PCB) level and close to the
parts, with minimal trace lengths.
It is required that the exposed paddle on the underside of the
ADC is connected to analog ground (AGND) to achieve the best
electrical and thermal performance of the AD9239. An exposed
continuous copper plane on the PCB should mate to the AD9239
exposed paddle, Pin 0. The copper plane should have several vias
to achieve the lowest possible resistive thermal path for heat
dissipation to flow through the bottom of the PCB. These vias
should be solder-filled or plugged with nonconductive epoxy.
A single PCB ground plane should be sufficient when using the
AD9239. With proper decoupling and smart partitioning of the
analog, digital, and clock sections of the PCB, optimum
performance can easily be achieved.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
guarantees only one tie point. See Figure 79 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP), at www.analog.com.
06980-029
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 79. Typical PCB Layout
Rev. 0 | Page 37 of 40
AD9239
OUTLINE DIMENSIONS
10.00
BSC SQ
0.60
0.42
0.24
0.60
0.42
0.24
55
54
72 1
PIN 1
INDICATOR
PIN 1
INDICATOR
9.75
BSC SQ
8.35
8.20 SQ
8.05
EXPOSEDPAD
(BOTTOM VIEW)
0.50
0.40
0.30
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
SEATING
PLANE
37
36
0.30
0.23
0.18
19
18
8.50 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
030408-A
TOP VIEW
0.50
BSC
Figure 80. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(CP-72-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9239BCPZ-170 1
AD9239BCPZ-2101
AD9239BCPZ-2501
AD9239-250KITZ1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 38 of 40
Package Option
CP-72-3
CP-72-3
CP-72-3
AD9239
NOTES
Rev. 0 | Page 39 of 40
AD9239
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06980-0-10/08(0)
Rev. 0 | Page 40 of 40